<div dir="ltr"><div>I reverted this patch at r338214 because it broke several bots like this:</div><div><a href="http://lab.llvm.org:8011/builders/clang-cmake-armv8-quick/builds/5107/steps/ninja%20check%201/logs/FAIL%3A%20LLVM%3A%3Ainline-asm-operand-implicit-cast.ll">http://lab.llvm.org:8011/builders/clang-cmake-armv8-quick/builds/5107/steps/ninja%20check%201/logs/FAIL%3A%20LLVM%3A%3Ainline-asm-operand-implicit-cast.ll</a><br></div><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Sat, Jul 28, 2018 at 3:33 PM, Thomas Preud'homme via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: thopre<br>
Date: Sat Jul 28 14:33:39 2018<br>
New Revision: 338206<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=338206&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=338206&view=rev</a><br>
Log:<br>
Fix crash on inline asm with 64bit matching input in 32bit GPR<br>
<br>
Add support for inline assembly with matching input operand that do not<br>
naturally go in the register class it is constrained to (eg. double in a<br>
32-bit GPR). Note that regular input is already handled by existing<br>
code.<br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/<wbr>SelectionDAGBuilder.cpp<br>
llvm/trunk/test/CodeGen/ARM/<wbr>inline-asm-operand-implicit-<wbr>cast.ll<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/<wbr>SelectionDAGBuilder.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=338206&r1=338205&r2=338206&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/SelectionDAG/<wbr>SelectionDAGBuilder.cpp?rev=<wbr>338206&r1=338205&r2=338206&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/<wbr>SelectionDAGBuilder.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/<wbr>SelectionDAGBuilder.cpp Sat Jul 28 14:33:39 2018<br>
@@ -7198,10 +7198,11 @@ static SDValue getAddressForMemoryInput(<br>
/// uses features that we can't model on machineinstrs, we have SDISel do the<br>
/// allocation. This produces generally horrible, but correct, code.<br>
///<br>
-/// OpInfo describes the operand.<br>
+/// OpInfo describes the operand<br>
+/// RefOpInfo describes the matching operand if any, the operand otherwise<br>
static void GetRegistersForValue(<wbr>SelectionDAG &DAG, const TargetLowering &TLI,<br>
- const SDLoc &DL,<br>
- SDISelAsmOperandInfo &OpInfo) {<br>
+ const SDLoc &DL, SDISelAsmOperandInfo &OpInfo,<br>
+ SDISelAsmOperandInfo &RefOpInfo) {<br>
LLVMContext &Context = *DAG.getContext();<br>
<br>
MachineFunction &MF = DAG.getMachineFunction();<br>
@@ -7211,8 +7212,8 @@ static void GetRegistersForValue(Selecti<br>
// If this is a constraint for a single physreg, or a constraint for a<br>
// register class, find it.<br>
std::pair<unsigned, const TargetRegisterClass *> PhysReg =<br>
- TLI.<wbr>getRegForInlineAsmConstraint(&<wbr>TRI, OpInfo.ConstraintCode,<br>
- OpInfo.ConstraintVT);<br>
+ TLI.<wbr>getRegForInlineAsmConstraint(&<wbr>TRI, RefOpInfo.ConstraintCode,<br>
+ RefOpInfo.ConstraintVT);<br>
<br>
unsigned NumRegs = 1;<br>
if (OpInfo.ConstraintVT != MVT::Other) {<br>
@@ -7254,6 +7255,11 @@ static void GetRegistersForValue(Selecti<br>
NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);<br>
}<br>
<br>
+ // No need to allocate a matching input constraint since the constraint it's<br>
+ // matching to has already been allocated.<br>
+ if (OpInfo.<wbr>isMatchingInputConstraint())<br>
+ return;<br>
+<br>
MVT RegVT;<br>
EVT ValueVT = OpInfo.ConstraintVT;<br>
<br>
@@ -7502,19 +7508,27 @@ void SelectionDAGBuilder::<wbr>visitInlineAsm<br>
<br>
// If this constraint is for a specific register, allocate it before<br>
// anything else.<br>
- if (OpInfo.ConstraintType == TargetLowering::C_Register)<br>
- GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);<br>
+ SDISelAsmOperandInfo &RefOpInfo =<br>
+ OpInfo.<wbr>isMatchingInputConstraint()<br>
+ ? ConstraintOperands[OpInfo.<wbr>getMatchedOperand()]<br>
+ : ConstraintOperands[i];<br>
+ if (RefOpInfo.ConstraintType == TargetLowering::C_Register)<br>
+ GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo, RefOpInfo);<br>
}<br>
<br>
// Third pass - Loop over all of the operands, assigning virtual or physregs<br>
// to register class operands.<br>
for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {<br>
SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];<br>
+ SDISelAsmOperandInfo &RefOpInfo =<br>
+ OpInfo.<wbr>isMatchingInputConstraint()<br>
+ ? ConstraintOperands[OpInfo.<wbr>getMatchedOperand()]<br>
+ : ConstraintOperands[i];<br>
<br>
// C_Register operands have already been allocated, Other/Memory don't need<br>
// to be.<br>
- if (OpInfo.ConstraintType == TargetLowering::C_<wbr>RegisterClass)<br>
- GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);<br>
+ if (RefOpInfo.ConstraintType == TargetLowering::C_<wbr>RegisterClass)<br>
+ GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo, RefOpInfo);<br>
}<br>
<br>
// AsmNodeOperands - The operands for the ISD::INLINEASM node.<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>inline-asm-operand-implicit-<wbr>cast.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inline-asm-operand-implicit-cast.ll?rev=338206&r1=338205&r2=338206&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/inline-asm-<wbr>operand-implicit-cast.ll?rev=<wbr>338206&r1=338205&r2=338206&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>inline-asm-operand-implicit-<wbr>cast.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>inline-asm-operand-implicit-<wbr>cast.ll Sat Jul 28 14:33:39 2018<br>
@@ -17,6 +17,42 @@ define arm_aapcscc double @zerobits_doub<br>
ret double %1<br>
}<br>
<br>
+; Check support for returning a float in GPR with matching float input with<br>
+; soft float ABI<br>
+define arm_aapcscc float @flt_gpr_matching_in_op_soft(<wbr>float %f) #0 {<br>
+; CHECK-LABEL: flt_gpr_matching_in_op_soft<br>
+; CHECK: mov r0, r0<br>
+ %1 = call float asm "mov $0, $1", "=&r,0"(float %f)<br>
+ ret float %1<br>
+}<br>
+<br>
+; Check support for returning a double in GPR with matching double input with<br>
+; soft float ABI<br>
+define arm_aapcscc double @dbl_gpr_matching_in_op_soft(<wbr>double %d) #0 {<br>
+; CHECK-LABEL: dbl_gpr_matching_in_op_soft<br>
+; CHECK: mov r1, r0<br>
+ %1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)<br>
+ ret double %1<br>
+}<br>
+<br>
+; Check support for returning a float in specific GPR with matching float input<br>
+; with soft float ABI<br>
+define arm_aapcscc float @flt_gpr_matching_spec_reg_in_<wbr>op_soft(float %f) #0 {<br>
+; CHECK-LABEL: flt_gpr_matching_spec_reg_in_<wbr>op_soft<br>
+; CHECK: mov r3, r3<br>
+ %1 = call float asm "mov $0, $1", "=&{r3},0"(float %f)<br>
+ ret float %1<br>
+}<br>
+<br>
+; Check support for returning a double in specific GPR with matching double<br>
+; input with soft float ABI<br>
+define arm_aapcscc double @dbl_gpr_matching_spec_reg_in_<wbr>op_soft(double %d) #0 {<br>
+; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_<wbr>op_soft<br>
+; CHECK: mov r3, r2<br>
+ %1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d)<br>
+ ret double %1<br>
+}<br>
+<br>
attributes #0 = { nounwind "target-features"="+d16,+vfp2,<wbr>+vfp3,-fp-only-sp" "use-soft-float"="true" }<br>
<br>
<br>
@@ -39,4 +75,48 @@ define double @zerobits_double_hard() #1<br>
ret double %1<br>
}<br>
<br>
+; Check support for returning a float in GPR with matching float input with<br>
+; hard float ABI<br>
+define float @flt_gpr_matching_in_op_hard(<wbr>float %f) #1 {<br>
+; CHECK-LABEL: flt_gpr_matching_in_op_hard<br>
+; CHECK: vmov r0, s0<br>
+; CHECK: mov r0, r0<br>
+; CHECK: vmov s0, r0<br>
+ %1 = call float asm "mov $0, $1", "=&r,0"(float %f)<br>
+ ret float %1<br>
+}<br>
+<br>
+; Check support for returning a double in GPR with matching double input with<br>
+; hard float ABI<br>
+define double @dbl_gpr_matching_in_op_hard(<wbr>double %d) #1 {<br>
+; CHECK-LABEL: dbl_gpr_matching_in_op_hard<br>
+; CHECK: vmov r0, r1, d0<br>
+; CHECK: mov r1, r0<br>
+; CHECK: vmov d0, r0, r1<br>
+ %1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)<br>
+ ret double %1<br>
+}<br>
+<br>
+; Check support for returning a float in specific GPR with matching float<br>
+; input with hard float ABI<br>
+define float @flt_gpr_matching_spec_reg_in_<wbr>op_hard(float %f) #1 {<br>
+; CHECK-LABEL: flt_gpr_matching_spec_reg_in_<wbr>op_hard<br>
+; CHECK: vmov r3, s0<br>
+; CHECK: mov r3, r3<br>
+; CHECK: vmov s0, r3<br>
+ %1 = call float asm "mov $0, $1", "=&{r3},0"(float %f)<br>
+ ret float %1<br>
+}<br>
+<br>
+; Check support for returning a double in specific GPR with matching double<br>
+; input with hard float ABI<br>
+define double @dbl_gpr_matching_spec_reg_in_<wbr>op_hard(double %d) #1 {<br>
+; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_<wbr>op_hard<br>
+; CHECK: vmov r2, r3, d0<br>
+; CHECK: mov r3, r2<br>
+; CHECK: vmov d0, r2, r3<br>
+ %1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d)<br>
+ ret double %1<br>
+}<br>
+<br>
attributes #1 = { nounwind "target-features"="+d16,+vfp2,<wbr>+vfp3,-fp-only-sp" "use-soft-float"="false" }<br>
<br>
<br>
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</blockquote></div><br></div>