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    <p>Please can somebody revert for me? I'm going to be away from
      email for the next few days. I'll investigate and apply a fix when
      I get back late next week.<br>
    </p>
    Sorry, Simon.<br>
    <br>
    <div class="moz-cite-prefix">On 20/07/2018 20:43, Benjamin Kramer
      wrote:<br>
    </div>
    <blockquote type="cite"
cite="mid:CAL3drCojEvBZE0MvyM_U1vbv541w16uHtNHn9nrsXLTqVQ85kg@mail.gmail.com">
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      <div dir="ltr">This hangs llc on the attached test case.</div>
      <br>
      <div class="gmail_quote">
        <div dir="ltr">On Fri, Jul 20, 2018 at 3:31 PM Simon Pilgrim via
          llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org"
            moz-do-not-send="true">llvm-commits@lists.llvm.org</a>>
          wrote:<br>
        </div>
        <blockquote class="gmail_quote" style="margin:0 0 0
          .8ex;border-left:1px #ccc solid;padding-left:1ex">Author:
          rksimon<br>
          Date: Fri Jul 20 06:26:51 2018<br>
          New Revision: 337547<br>
          <br>
          URL: <a
            href="http://llvm.org/viewvc/llvm-project?rev=337547&view=rev"
            rel="noreferrer" target="_blank" moz-do-not-send="true">http://llvm.org/viewvc/llvm-project?rev=337547&view=rev</a><br>
          Log:<br>
          [X86][AVX] Convert X86ISD::VBROADCAST demanded elts combine to
          use SimplifyDemandedVectorElts<br>
          <br>
          This is an early step towards using SimplifyDemandedVectorElts
          for target shuffle combining - this merely moves the existing
          X86ISD::VBROADCAST simplification code to use the
          SimplifyDemandedVectorElts mechanism.<br>
          <br>
          Adds
          X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode to
          handle X86ISD::VBROADCAST - in time we can support all target
          shuffles (and other ops) here.<br>
          <br>
          Modified:<br>
              llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
              llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
          <br>
          Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
          URL: <a
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=337547&r1=337546&r2=337547&view=diff"
            rel="noreferrer" target="_blank" moz-do-not-send="true">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=337547&r1=337546&r2=337547&view=diff</a><br>
==============================================================================<br>
          --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
          +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jul 20
          06:26:51 2018<br>
          @@ -30635,24 +30635,13 @@ static SDValue
          combineTargetShuffle(SDVa<br>
          <br>
             switch (Opcode) {<br>
             case X86ISD::VBROADCAST: {<br>
          -    // If broadcasting from another shuffle, attempt to
          simplify it.<br>
               // TODO - we really need a general
          SimplifyDemandedVectorElts mechanism.<br>
          -    SDValue Src = N.getOperand(0);<br>
          -    SDValue BC = peekThroughBitcasts(Src);<br>
          -    EVT SrcVT = Src.getValueType();<br>
          -    EVT BCVT = BC.getValueType();<br>
          -    if (isTargetShuffle(BC.getOpcode()) &&<br>
          -        VT.getScalarSizeInBits() % BCVT.getScalarSizeInBits()
          == 0) {<br>
          -      unsigned Scale = VT.getScalarSizeInBits() /
          BCVT.getScalarSizeInBits();<br>
          -      SmallVector<int, 16>
          DemandedMask(BCVT.getVectorNumElements(),<br>
          -                                        SM_SentinelUndef);<br>
          -      for (unsigned i = 0; i != Scale; ++i)<br>
          -        DemandedMask[i] = i;<br>
          -      if (SDValue Res = combineX86ShufflesRecursively(<br>
          -              {BC}, 0, BC, DemandedMask, {}, /*Depth*/ 1,<br>
          -              /*HasVarMask*/ false, DAG, Subtarget))<br>
          -        return DAG.getNode(X86ISD::VBROADCAST, DL, VT,<br>
          -                           DAG.getBitcast(SrcVT, Res));<br>
          +    APInt KnownUndef, KnownZero;<br>
          +    APInt
          DemandedMask(APInt::getAllOnesValue(VT.getVectorNumElements()));<br>
          +    const TargetLowering &TLI =
          DAG.getTargetLoweringInfo();<br>
          +    if (TLI.SimplifyDemandedVectorElts(N, DemandedMask,
          KnownUndef, KnownZero,<br>
          +                                       DCI)) {<br>
          +      return SDValue(N.getNode(), 0);<br>
               }<br>
               return SDValue();<br>
             }<br>
          @@ -31298,6 +31287,41 @@ static SDValue combineShuffle(SDNode
          *N,<br>
             return SDValue();<br>
           }<br>
          <br>
          +bool
          X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(<br>
          +    SDValue Op, const APInt &DemandedElts, APInt
          &KnownUndef, APInt &KnownZero,<br>
          +    TargetLoweringOpt &TLO, unsigned Depth) const {<br>
          +<br>
          +  if (X86ISD::VBROADCAST != Op.getOpcode())<br>
          +    return false;<br>
          +<br>
          +  EVT VT = Op.getValueType();<br>
          +  SDValue Src = Op.getOperand(0);<br>
          +  SDValue BC = peekThroughBitcasts(Src);<br>
          +  EVT SrcVT = Src.getValueType();<br>
          +  EVT BCVT = BC.getValueType();<br>
          +<br>
          +  if (!isTargetShuffle(BC.getOpcode()) ||<br>
          +      (VT.getScalarSizeInBits() % BCVT.getScalarSizeInBits())
          != 0)<br>
          +    return false;<br>
          +<br>
          +  unsigned Scale = VT.getScalarSizeInBits() /
          BCVT.getScalarSizeInBits();<br>
          +  SmallVector<int, 16>
          DemandedMask(BCVT.getVectorNumElements(),<br>
          +                                    SM_SentinelUndef);<br>
          +  for (unsigned i = 0; i != Scale; ++i)<br>
          +    DemandedMask[i] = i;<br>
          +<br>
          +  if (SDValue Res = combineX86ShufflesRecursively(<br>
          +          {BC}, 0, BC, DemandedMask, {}, Depth + 1,
          /*HasVarMask*/ false,<br>
          +          TLO.DAG, Subtarget)) {<br>
          +    SDLoc DL(Op);<br>
          +    Res = TLO.DAG.getNode(X86ISD::VBROADCAST, DL, VT,<br>
          +                          TLO.DAG.getBitcast(SrcVT, Res));<br>
          +    return TLO.CombineTo(Op, Res);<br>
          +  }<br>
          +<br>
          +  return false;<br>
          +}<br>
          +<br>
           /// Check if a vector extract from a target-specific shuffle
          of a load can be<br>
           /// folded into a single element load.<br>
           /// Similar handling for VECTOR_SHUFFLE is performed by
          DAGCombiner, but<br>
          <br>
          Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
          URL: <a
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=337547&r1=337546&r2=337547&view=diff"
            rel="noreferrer" target="_blank" moz-do-not-send="true">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=337547&r1=337546&r2=337547&view=diff</a><br>
==============================================================================<br>
          --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)<br>
          +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Fri Jul 20
          06:26:51 2018<br>
          @@ -866,6 +866,13 @@ namespace llvm {<br>
                                                        const
          SelectionDAG &DAG,<br>
                                                        unsigned Depth)
          const override;<br>
          <br>
          +    bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op,<br>
          +                                                 const APInt
          &DemandedElts,<br>
          +                                                 APInt
          &KnownUndef,<br>
          +                                                 APInt
          &KnownZero,<br>
          +                                               
           TargetLoweringOpt &TLO,<br>
          +                                                 unsigned
          Depth) const override;<br>
          +<br>
               SDValue unwrapAddress(SDValue N) const override;<br>
          <br>
               bool isGAPlusOffset(SDNode *N, const GlobalValue*
          &GA,<br>
          <br>
          <br>
          _______________________________________________<br>
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            rel="noreferrer" target="_blank" moz-do-not-send="true">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
        </blockquote>
      </div>
    </blockquote>
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