<div dir="ltr"><div>I have just uploaded the full patch for review here: <a href="https://reviews.llvm.org/D49182">https://reviews.llvm.org/D49182</a></div><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jul 11, 2018 at 1:19 PM, Mikael Holmén <span dir="ltr"><<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsson.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi,<br>
<br>
Indeed, with that patch "my" case doesn't hit the assertion anymore either.<br>
<br>
Thanks,<br>
Mikael<div><div class="h5"><br>
<br>
On 07/11/2018 02:03 PM, Andrea Di Biagio wrote:<br>
</div></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div class="h5">
For the record.<br>
The instructions affected by the missing `mayLoad` flag are:<br>
MOVLPSrm<br>
VMOVLPSrm<br>
VMOVLPSZ128rm<br>
<br>
The diff below would fix the issue with the (V)MOVLPSrm.<br>
<br>
Index: lib/Target/X86/X86InstrSSE.td<br>
==============================<wbr>==============================<wbr>=======<br>
--- lib/Target/X86/X86InstrSSE.td <wbr> (revision 336790)<br>
+++ lib/Target/X86/X86InstrSSE.td <wbr> (working copy)<br>
@@ -650,14 +650,17 @@<br>
<br>
multiclass sse12_mov_hilo_packed<bits<8>o<wbr>pc, SDPatternOperator psnode,<br>
<wbr> SDPatternOperator pdnode, string base_opc> {<br>
- let Predicates = [UseAVX] in<br>
+<br>
+ let mayLoad = 1 in {<br>
+ let Predicates = [UseAVX] in<br>
defm V#NAME : sse12_mov_hilo_packed_base<opc<wbr>, psnode, pdnode, base_opc,<br>
<wbr> "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,<br>
<wbr> VEX_4V, VEX_WIG;<br>
<br>
- let Constraints = "$src1 = $dst" in<br>
+ let Constraints = "$src1 = $dst" in<br>
defm NAME : sse12_mov_hilo_packed_base<opc<wbr>, psnode, pdnode, base_opc,<br>
<wbr> "\t{$src2, $dst|$dst, $src2}">;<br>
+ }<br>
}<br>
<br>
defm MOVL : sse12_mov_hilo_packed<0x12, null_frag, null_frag, "movlp">;<br>
<br></div></div><span class="">
On Wed, Jul 11, 2018 at 12:34 PM, Andrea Di Biagio <<a href="mailto:andrea.dibiagio@gmail.com" target="_blank">andrea.dibiagio@gmail.com</a> <mailto:<a href="mailto:andrea.dibiagio@gmail.com" target="_blank">andrea.dibiagio@gmail.<wbr>com</a>>> wrote:<br>
<br>
I found a similar issue.<br>
<br>
<br>
Before 336728, the "mayLoad" flag for the (V)MOVLPSrm was<br>
automatically inferred (in utils/Tablegen/CodeGenDAGPatte<wbr>rns.cpp)<br>
directly from the default pattern associated with the instruction<br>
definition.<br>
<br>
With 336728, `X86Movlps` is gone. However, the instruction<br>
definition in tablegen leaves the "mayLoad" flag unset for the<br>
(V)MOVLPSrm.<br>
Later on, CodeGenDAGPatterns::InferInstr<wbr>uctionFlags() sees that<br>
(V)MOVLPSrm has undefined flags and no pattern. So, it<br>
conservatively sets the "hasSideEffects" flag to true.<br>
<br>
The assert is probably a consequence of all of this:<br>
<br>
there is no 'mayLoad' associated with (V)MOVLPSrm, however,<br>
VMOVLPSrm is used as the variant to use with a folded memory operand.<br>
<br>
<br>
On Wed, Jul 11, 2018 at 12:04 PM, Mikael Holmén via llvm-commits<br></span>
<<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a> <mailto:<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llv<wbr>m.org</a>>><div><div class="h5"><br>
wrote:<br>
<br>
Hi Craig,<br>
<br>
The following (llvm-stress generated and bugpoint reduced) case<br>
starts to crash the register allocator with this patch:<br>
<br>
llc -march=x86-64 -mcpu=corei7 -o /dev/null fold.ll<br>
<br>
gives<br>
<br>
llc: ../lib/CodeGen/TargetInstrInfo<wbr>.cpp:594: llvm::MachineInstr<br>
*llvm::TargetInstrInfo::foldMe<wbr>moryOperand(llvm::MachineInstr &,<br>
ArrayRef<unsigned int>, int, llvm::LiveIntervals *) const:<br>
Assertion `(!(Flags & MachineMemOperand::MOLoad) ||<br>
NewMI->mayLoad()) && "Folded a use to a non-load!"' failed.<br>
Stack dump:<br>
0. Program arguments: build-all/bin/llc -march=x86-64<br>
-mcpu=corei7 -o /dev/null fold.ll<br>
1. Running pass 'Function Pass Manager' on module 'fold.ll'.<br>
2. Running pass 'Greedy Register Allocator' on function<br>
'@autogen_SD17302'<br>
#0 0x0000000001ff28f4 PrintStackTraceSignalHandler(v<wbr>oid*)<br>
(build-all/bin/llc+0x1ff28f4)<br>
#1 0x0000000001ff0b60 llvm::sys::RunSignalHandlers()<br>
(build-all/bin/llc+0x1ff0b60)<br>
#2 0x0000000001ff2c58 SignalHandler(int)<br>
(build-all/bin/llc+0x1ff2c58)<br>
#3 0x00007f7b62559330 __restore_rt<br>
(/lib/x86_64-linux-gnu/libpthr<wbr>ead.so.0+0x10330)<br>
#4 0x00007f7b61148c37 gsignal<br>
/build/eglibc-ripdx6/eglibc-2.<wbr>19/signal/../nptl/sysdeps/unix<wbr>/sysv/linux/raise.c:56:0<br>
#5 0x00007f7b6114c028 abort<br>
/build/eglibc-ripdx6/eglibc-2.<wbr>19/stdlib/abort.c:91:0<br>
#6 0x00007f7b61141bf6 __assert_fail_base<br>
/build/eglibc-ripdx6/eglibc-2.<wbr>19/assert/assert.c:92:0<br>
#7 0x00007f7b61141ca2 (/lib/x86_64-linux-gnu/libc.so<wbr>.6+0x2fca2)<br>
#8 0x000000000188be0d<br>
llvm::TargetInstrInfo::foldMem<wbr>oryOperand(llvm::MachineInstr&<wbr>,<br>
llvm::ArrayRef<unsigned int>, int, llvm::LiveIntervals*) const<br>
(build-all/bin/llc+0x188be0d)<br>
#9 0x00000000018e6607 (anonymous<br>
namespace)::InlineSpiller::fol<wbr>dMemoryOperand(llvm::ArrayRef<<wbr>std::pair<llvm::MachineInstr*,<br>
unsigned int> >, llvm::MachineInstr*) (build-all/bin/llc+0x18e6607)<br>
#10 0x00000000018decc5 (anonymous<br>
namespace)::InlineSpiller::spi<wbr>ll(llvm::LiveRangeEdit&)<br>
(build-all/bin/llc+0x18decc5)<br>
#11 0x00000000017eb5d9 (anonymous<br>
namespace)::RAGreedy::selectOr<wbr>SplitImpl(llvm::LiveInterval&,<br>
llvm::SmallVectorImpl<unsigned int>&, llvm::SmallSet<unsigned<br>
int, 16u, std::less<unsigned int> >&, unsigned int)<br>
(build-all/bin/llc+0x17eb5d9)<br>
#12 0x00000000017ea1aa (anonymous<br>
namespace)::RAGreedy::selectOr<wbr>Split(llvm::LiveInterval&,<br>
llvm::SmallVectorImpl<unsigned int>&) (build-all/bin/llc+0x17ea1aa)<br>
#13 0x000000000190ab1a llvm::RegAllocBase::allocatePh<wbr>ysRegs()<br>
(build-all/bin/llc+0x190ab1a)<br>
#14 0x00000000017e8ed1 (anonymous<br>
namespace)::RAGreedy::runOnMac<wbr>hineFunction(llvm::MachineFunc<wbr>tion&)<br>
(build-all/bin/llc+0x17e8ed1)<br>
#15 0x0000000001713749<br>
llvm::MachineFunctionPass::run<wbr>OnFunction(llvm::Function&)<br>
(build-all/bin/llc+0x1713749)<br>
#16 0x0000000001a3cc7a<br>
llvm::FPPassManager::runOnFunc<wbr>tion(llvm::Function&)<br>
(build-all/bin/llc+0x1a3cc7a)<br>
#17 0x0000000001a3ced8<br>
llvm::FPPassManager::runOnModu<wbr>le(llvm::Module&)<br>
(build-all/bin/llc+0x1a3ced8)<br>
#18 0x0000000001a3d40d<br>
llvm::legacy::PassManagerImpl:<wbr>:run(llvm::Module&)<br>
(build-all/bin/llc+0x1a3d40d)<br>
#19 0x00000000006fccb9 compileModule(char**, llvm::LLVMContext&)<br>
(build-all/bin/llc+0x6fccb9)<br>
#20 0x00000000006fa2b0 main (build-all/bin/llc+0x6fa2b0)<br>
#21 0x00007f7b61133f45 __libc_start_main<br>
/build/eglibc-ripdx6/eglibc-2.<wbr>19/csu/libc-start.c:321:0<br>
#22 0x00000000006f7b0a _start (build-all/bin/llc+0x6f7b0a)<br>
Abort<br>
<br>
NewMI is<br>
<br>
%26:vr128 = MOVLPSrm %26:vr128, %stack.1, 1, $noreg, 8, $noreg<br>
<br>
when it crashes.<br>
<br>
Regards,<br>
Mikael<br>
<br>
<br>
On 07/10/2018 11:00 PM, Craig Topper via llvm-commits wrote:<br>
<br>
Author: ctopper<br>
Date: Tue Jul 10 14:00:22 2018<br>
New Revision: 336728<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=336728&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=336728&view=rev</a><br>
<<a href="http://llvm.org/viewvc/llvm-project?rev=336728&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject?rev=336728&view=rev</a>><br>
Log:<br>
[X86] Remove X86ISD::MOVLPS and X86ISD::MOVLPD. NFCI<br>
<br>
These ISD nodes try to select the MOVLPS and MOVLPD<br>
instructions which are special load only instructions. They<br>
load data and merge it into the lower 64-bits of an XMM<br>
register. They are logically equivalent to our MOVSD node<br>
plus a load.<br>
<br>
There was only one place in X86ISelLowering that used MOVLPD<br>
and no places that selected MOVLPS. The one place that<br>
selected MOVLPD had to choose between it and MOVSD based on<br>
whether there was a load. But lowering is too early to tell<br>
if the load can really be folded. So in isel we have<br>
patterns that use MOVSD for MOVLPD if we can't find a load.<br>
<br>
We also had patterns that select the MOVLPD instruction for<br>
a MOVSD if we can find a load, but didn't choose the MOVLPD<br>
ISD opcode for some reason.<br>
<br>
So it seems better to just standardize on MOVSD ISD opcode<br>
and manage MOVSD vs MOVLPD instruction with isel patterns.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86<wbr>ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86<wbr>ISelLowering.h<br>
llvm/trunk/lib/Target/X86/X86<wbr>InstrAVX512.td<br>
llvm/trunk/lib/Target/X86/X86<wbr>InstrFragmentsSIMD.td<br>
llvm/trunk/lib/Target/X86/X86<wbr>InstrSSE.td<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86I<wbr>SelLowering.cpp<br>
URL:<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=336728&r1=336727&r2=336728&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86ISelLowering.cpp?rev=3367<wbr>28&r1=336727&r2=336728&view=<wbr>diff</a><br>
<<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=336728&r1=336727&r2=336728&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/lib/Target/X<wbr>86/X86ISelLowering.cpp?rev=336<wbr>728&r1=336727&r2=336728&view=<wbr>diff</a>><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86I<wbr>SelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86I<wbr>SelLowering.cpp Tue Jul 10<br>
14:00:22 2018<br>
@@ -4369,8 +4369,6 @@ static bool isTargetShuffle(unsigned Opc<br>
case X86ISD::VSRLDQ:<br>
case X86ISD::MOVLHPS:<br>
case X86ISD::MOVHLPS:<br>
- case X86ISD::MOVLPS:<br>
- case X86ISD::MOVLPD:<br>
case X86ISD::MOVSHDUP:<br>
case X86ISD::MOVSLDUP:<br>
case X86ISD::MOVDDUP:<br>
@@ -5951,10 +5949,6 @@ static bool getTargetShuffleMask(SDNode<br>
DecodeMOVDDUPMask(NumElems, Mask);<br>
IsUnary = true;<br>
break;<br>
- case X86ISD::MOVLPD:<br>
- case X86ISD::MOVLPS:<br>
- // Not yet implemented<br>
- return false;<br>
case X86ISD::VPERMIL2: {<br>
assert(N->getOperand(0).getVal<wbr>ueType() == VT &&<br>
"Unexpected value type");<br>
assert(N->getOperand(1).getVal<wbr>ueType() == VT &&<br>
"Unexpected value type");<br>
@@ -11363,8 +11357,7 @@ static SDValue lowerV2F64VectorShuffle(c<br>
// We can either use a special instruction to load<br>
over the low double or<br>
// to move just the low double.<br>
return DAG.getNode(<br>
- isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD :<br>
X86ISD::MOVSD,<br>
- DL, MVT::v2f64, V2,<br>
+ X86ISD::MOVSD, DL, MVT::v2f64, V2,<br>
DAG.getNode(ISD::SCALAR_TO_VEC<wbr>TOR, DL,<br>
MVT::v2f64, V1S));<br>
if (Subtarget.hasSSE41())<br>
@@ -26041,8 +26034,6 @@ const char *X86TargetLowering::getTarget<br>
case X86ISD::SHUF128: return "X86ISD::SHUF128";<br>
case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";<br>
case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";<br>
- case X86ISD::MOVLPS: return "X86ISD::MOVLPS";<br>
- case X86ISD::MOVLPD: return "X86ISD::MOVLPD";<br>
case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";<br>
case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";<br>
case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86I<wbr>SelLowering.h<br>
URL:<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=336728&r1=336727&r2=336728&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86ISelLowering.h?rev=336728<wbr>&r1=336727&r2=336728&view=diff</a><br>
<<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=336728&r1=336727&r2=336728&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/lib/Target/X<wbr>86/X86ISelLowering.h?rev=33672<wbr>8&r1=336727&r2=336728&view=<wbr>diff</a>><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86I<wbr>SelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86I<wbr>SelLowering.h Tue Jul 10<br>
14:00:22 2018<br>
@@ -408,8 +408,6 @@ namespace llvm {<br>
MOVSLDUP,<br>
MOVLHPS,<br>
MOVHLPS,<br>
- MOVLPS,<br>
- MOVLPD,<br>
MOVSD,<br>
MOVSS,<br>
UNPCKL,<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86I<wbr>nstrAVX512.td<br>
URL:<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=336728&r1=336727&r2=336728&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86InstrAVX512.td?rev=336728<wbr>&r1=336727&r2=336728&view=diff</a><br>
<<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=336728&r1=336727&r2=336728&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/lib/Target/X<wbr>86/X86InstrAVX512.td?rev=33672<wbr>8&r1=336727&r2=336728&view=<wbr>diff</a>><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86I<wbr>nstrAVX512.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86I<wbr>nstrAVX512.td Tue Jul 10<br>
14:00:22 2018<br>
@@ -4439,11 +4439,6 @@ let Predicates = [HasAVX512] in {<br>
def : Pat<(v2f64 (X86Movsd VR128X:$src1,<br>
(scalar_to_vector FR64X:$src2))),<br>
(VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS<br>
FR64X:$src2, VR128X))>;<br>
-<br>
- def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),<br>
- (VMOVSDZrr VR128X:$src1, VR128X:$src2)>;<br>
- def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),<br>
- (VMOVSDZrr VR128X:$src1, VR128X:$src2)>;<br>
}<br>
let ExeDomain = SSEPackedInt, SchedRW =<br>
[SchedWriteVecLogic.XMM] in {<br>
@@ -6405,7 +6400,8 @@ def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrc<br>
// All patterns was taken from SSS implementation.<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
-multiclass avx512_mov_hilo_packed<bits<8> opc, string<br>
OpcodeStr, SDNode OpNode,<br>
+multiclass avx512_mov_hilo_packed<bits<8> opc, string<br>
OpcodeStr,<br>
+ SDPatternOperator OpNode,<br>
X86VectorVTInfo _> {<br>
let ExeDomain = _.ExeDomain in<br>
def rm : AVX512<opc, MRMSrcMem, (outs _.RC:$dst),<br>
@@ -6423,9 +6419,9 @@ defm VMOVHPSZ128 : avx512_mov_hilo_packe<br>
v4f32x_info>,<br>
EVEX_CD8<32, CD8VT2>, PS;<br>
defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16,<br>
"vmovhpd", X86Unpckl,<br>
v2f64x_info>,<br>
EVEX_CD8<64, CD8VT1>, PD, VEX_W;<br>
-defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps",<br>
X86Movlps,<br>
+defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps",<br>
null_frag,<br>
v4f32x_info>,<br>
EVEX_CD8<32, CD8VT2>, PS;<br>
-defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd",<br>
X86Movlpd,<br>
+defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd",<br>
null_frag,<br>
v2f64x_info>,<br>
EVEX_CD8<64, CD8VT1>, PD, VEX_W;<br>
let Predicates = [HasAVX512] in {<br>
@@ -6440,12 +6436,7 @@ let Predicates = [HasAVX512] in {<br>
def : Pat<(v2f64 (X86Unpckl VR128X:$src1,<br>
(bc_v2f64 (v2i64 (scalar_to_vector<br>
(loadi64 addr:$src2)))))),<br>
(VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;<br>
- // VMOVLPS patterns<br>
- def : Pat<(v4f32 (X86Movlps VR128X:$src1, (load<br>
addr:$src2))),<br>
- (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;<br>
// VMOVLPD patterns<br>
- def : Pat<(v2f64 (X86Movlpd VR128X:$src1, (load<br>
addr:$src2))),<br>
- (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;<br>
def : Pat<(v2f64 (X86Movsd VR128X:$src1,<br>
(v2f64 (scalar_to_vector<br>
(loadf64 addr:$src2))))),<br>
(VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;<br>
@@ -6487,14 +6478,6 @@ let Predicates = [HasAVX512] in {<br>
(v2f64 (X86VPermilpi<br>
VR128X:$src, (i8 1))),<br>
(iPTR 0))), addr:$dst),<br>
(VMOVHPDZ128mr addr:$dst, VR128X:$src)>;<br>
- // VMOVLPS patterns<br>
- def : Pat<(store (v4f32 (X86Movlps (load addr:$src1),<br>
VR128X:$src2)),<br>
- addr:$src1),<br>
- (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;<br>
- // VMOVLPD patterns<br>
- def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1),<br>
VR128X:$src2)),<br>
- addr:$src1),<br>
- (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;<br>
}<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
// FMA - Fused Multiply Operations<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86I<wbr>nstrFragmentsSIMD.td<br>
URL:<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=336728&r1=336727&r2=336728&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86InstrFragmentsSIMD.td?rev<wbr>=336728&r1=336727&r2=336728&<wbr>view=diff</a><br>
<<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=336728&r1=336727&r2=336728&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/lib/Target/X<wbr>86/X86InstrFragmentsSIMD.td?re<wbr>v=336728&r1=336727&r2=336728&<wbr>view=diff</a>><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86I<wbr>nstrFragmentsSIMD.td<br>
(original)<br>
+++ llvm/trunk/lib/Target/X86/X86I<wbr>nstrFragmentsSIMD.td Tue<br>
Jul 10 14:00:22 2018<br>
@@ -374,9 +374,6 @@ def X86Movss : SDNode<"X86ISD::MOVSS", S<br>
def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;<br>
def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;<br>
-def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;<br>
-def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;<br>
-<br>
def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>,<br>
SDTCisInt<0>,<br>
SDTCisVec<1>,<br>
SDTCisInt<1>,<br>
SDTCisSameSizeAs<0,1>,<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86I<wbr>nstrSSE.td<br>
URL:<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=336728&r1=336727&r2=336728&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86InstrSSE.td?rev=336728&r1<wbr>=336727&r2=336728&view=diff</a><br>
<<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=336728&r1=336727&r2=336728&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/lib/Target/X<wbr>86/X86InstrSSE.td?rev=336728&r<wbr>1=336727&r2=336728&view=diff</a>><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86I<wbr>nstrSSE.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86I<wbr>nstrSSE.td Tue Jul 10<br>
14:00:22 2018<br>
@@ -305,15 +305,6 @@ let Predicates = [UseAVX] in {<br>
def : Pat<(v2f64 (X86Movsd VR128:$src1,<br>
(scalar_to_vector FR64:$src2))),<br>
(VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS<br>
FR64:$src2, VR128))>;<br>
-<br>
- // FIXME: Instead of a X86Movlps there should be a<br>
X86Movsd here, the problem<br>
- // is during lowering, where it's not possible to<br>
recognize the fold cause<br>
- // it has two uses through a bitcast. One use disappears<br>
at isel time and the<br>
- // fold opportunity reappears.<br>
- def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),<br>
- (VMOVSDrr VR128:$src1, VR128:$src2)>;<br>
- def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),<br>
- (VMOVSDrr VR128:$src1, VR128:$src2)>;<br>
}<br>
let Predicates = [UseSSE1] in {<br>
@@ -372,15 +363,6 @@ let Predicates = [UseSSE2] in {<br>
def : Pat<(v2f64 (X86Movsd VR128:$src1,<br>
(scalar_to_vector FR64:$src2))),<br>
(MOVSDrr VR128:$src1, (COPY_TO_REGCLASS<br>
FR64:$src2, VR128))>;<br>
-<br>
- // FIXME: Instead of a X86Movlps there should be a<br>
X86Movsd here, the problem<br>
- // is during lowering, where it's not possible to<br>
recognize the fold because<br>
- // it has two uses through a bitcast. One use disappears<br>
at isel time and the<br>
- // fold opportunity reappears.<br>
- def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),<br>
- (MOVSDrr VR128:$src1, VR128:$src2)>;<br>
- def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),<br>
- (MOVSDrr VR128:$src1, VR128:$src2)>;<br>
}<br>
// Aliases to help the assembler pick two byte VEX<br>
encodings by swapping the<br>
@@ -692,8 +674,8 @@ multiclass sse12_mov_hilo_packed_base<bi<br>
Sched<[SchedWriteFShuffle.XMM<wbr>.Folded, ReadAfterLd]>;<br>
}<br>
-multiclass sse12_mov_hilo_packed<bits<8>o<wbr>pc, SDNode<br>
psnode, SDNode pdnode,<br>
- string base_opc> {<br>
+multiclass sse12_mov_hilo_packed<bits<8>o<wbr>pc,<br>
SDPatternOperator psnode,<br>
+ SDPatternOperator pdnode,<br>
string base_opc> {<br>
let Predicates = [UseAVX] in<br>
defm V#NAME : sse12_mov_hilo_packed_base<opc<wbr>, psnode,<br>
pdnode, base_opc,<br>
"\t{$src2, $src1,<br>
$dst|$dst, $src1, $src2}">,<br>
@@ -704,7 +686,7 @@ multiclass sse12_mov_hilo_packed<bits<8><br>
"\t{$src2, $dst|$dst,<br>
$src2}">;<br>
}<br>
-defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps,<br>
X86Movlpd, "movlp">;<br>
+defm MOVL : sse12_mov_hilo_packed<0x12, null_frag,<br>
null_frag, "movlp">;<br>
let SchedRW = [WriteFStore] in {<br>
let Predicates = [UseAVX] in {<br>
@@ -730,24 +712,10 @@ def MOVLPDmr : PDI<0x13, MRMDestMem, (ou<br>
} // SchedRW<br>
let Predicates = [UseAVX] in {<br>
- // Shuffle with VMOVLPS<br>
- def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),<br>
- (VMOVLPSrm VR128:$src1, addr:$src2)>;<br>
-<br>
// Shuffle with VMOVLPD<br>
- def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),<br>
- (VMOVLPDrm VR128:$src1, addr:$src2)>;<br>
def : Pat<(v2f64 (X86Movsd VR128:$src1,<br>
(v2f64 (scalar_to_vector<br>
(loadf64 addr:$src2))))),<br>
(VMOVLPDrm VR128:$src1, addr:$src2)>;<br>
-<br>
- // Store patterns<br>
- def : Pat<(store (v4f32 (X86Movlps (load addr:$src1),<br>
VR128:$src2)),<br>
- addr:$src1),<br>
- (VMOVLPSmr addr:$src1, VR128:$src2)>;<br>
- def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1),<br>
VR128:$src2)),<br>
- addr:$src1),<br>
- (VMOVLPDmr addr:$src1, VR128:$src2)>;<br>
}<br>
let Predicates = [UseSSE1] in {<br>
@@ -755,32 +723,13 @@ let Predicates = [UseSSE1] in {<br>
def : Pat<(store (i64 (extractelt (bc_v2i64 (v4f32<br>
VR128:$src2)),<br>
(iPTR 0))), addr:$src1),<br>
(MOVLPSmr addr:$src1, VR128:$src2)>;<br>
-<br>
- // Shuffle with MOVLPS<br>
- def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),<br>
- (MOVLPSrm VR128:$src1, addr:$src2)>;<br>
- def : Pat<(X86Movlps VR128:$src1,<br>
- (bc_v4f32 (v2i64 (scalar_to_vector<br>
(loadi64 addr:$src2))))),<br>
- (MOVLPSrm VR128:$src1, addr:$src2)>;<br>
-<br>
- // Store patterns<br>
- def : Pat<(store (v4f32 (X86Movlps (load addr:$src1),<br>
VR128:$src2)),<br>
- addr:$src1),<br>
- (MOVLPSmr addr:$src1, VR128:$src2)>;<br>
}<br>
let Predicates = [UseSSE2] in {<br>
// Shuffle with MOVLPD<br>
- def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),<br>
- (MOVLPDrm VR128:$src1, addr:$src2)>;<br>
def : Pat<(v2f64 (X86Movsd VR128:$src1,<br>
(v2f64 (scalar_to_vector<br>
(loadf64 addr:$src2))))),<br>
(MOVLPDrm VR128:$src1, addr:$src2)>;<br>
-<br>
- // Store patterns<br>
- def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1),<br>
VR128:$src2)),<br>
- addr:$src1),<br>
- (MOVLPDmr addr:$src1, VR128:$src2)>;<br>
}<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
<br>
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