<div dir="ltr"><div>These look like good fixes (and a strong argument for not writing test assertions by hand), but I'm seeing test failures:</div><div><br></div><div>Failing Tests (3):<br> LLVM :: CodeGen/AArch64/aarch64_tree_tests.ll<br> LLVM :: CodeGen/AArch64/arm64-csel.ll<br> LLVM :: CodeGen/ARM/debug-frame-large-stack.ll<br><br></div><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jul 4, 2018 at 7:28 AM, Gabor Buella via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: gbuella<br>
Date: Wed Jul 4 06:28:39 2018<br>
New Revision: 336268<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=336268&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=336268&view=rev</a><br>
Log:<br>
NFC - Various typo fixes in tests<br>
<br>
Modified:<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/aarch64_tree_tests.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/andandshift.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-addr-mode-<wbr>folding.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-csel.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/cmpwithshort.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/fast-isel-gep.ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>GlobalISel/arm-param-lowering.<wbr>ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>atomic-op.ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>debug-frame-large-stack.ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>float-helpers.s<br>
llvm/trunk/test/CodeGen/ARM/<wbr>fp16.ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>shift-combine.ll<br>
llvm/trunk/test/CodeGen/NVPTX/<wbr>ctlz.ll<br>
llvm/trunk/test/CodeGen/<wbr>PowerPC/vec_rotate_shift.ll<br>
llvm/trunk/test/CodeGen/SPARC/<wbr>soft-float.ll<br>
llvm/trunk/test/CodeGen/<wbr>WebAssembly/address-offsets.ll<br>
llvm/trunk/test/DebugInfo/X86/<wbr>mem2reg_fp80.ll<br>
llvm/trunk/test/MC/<wbr>Disassembler/Hexagon/nv_j.txt<br>
llvm/trunk/test/Transforms/<wbr>Inline/deoptimize-intrinsic.ll<br>
llvm/trunk/test/Transforms/<wbr>LICM/loopsink.ll<br>
llvm/trunk/test/Transforms/<wbr>LoadStoreVectorizer/X86/merge-<wbr>tbaa.ll<br>
llvm/trunk/test/Transforms/<wbr>LoopInterchange/profitability.<wbr>ll<br>
llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/vector_max_<wbr>bandwidth.ll<br>
llvm/trunk/test/Transforms/<wbr>RewriteStatepointsForGC/deopt-<wbr>intrinsic-cconv.ll<br>
llvm/trunk/test/tools/llvm-<wbr>dwarfdump/X86/debug_line_<wbr>offset.test<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/aarch64_tree_tests.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/aarch64_tree_tests.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/aarch64_tree_<wbr>tests.ll?rev=336268&r1=336267&<wbr>r2=336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/aarch64_tree_tests.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/aarch64_tree_tests.ll Wed Jul 4 06:28:39 2018<br>
@@ -4,7 +4,7 @@<br>
target datalayout = "e-m:e-i64:64-i128:128-n32:64-<wbr>S128"<br>
target triple = "arm64--linux-gnu"<br>
<br>
-; CHECK-LABLE: @aarch64_tree_tests_and<br>
+; CHECK-LABEL: @aarch64_tree_tests_and<br>
; CHECK: .hword 32768 <br>
; CHECK: .hword 32767 <br>
; CHECK: .hword 4664 <br>
@@ -22,7 +22,7 @@ entry:<br>
ret <8 x i16> %ret<br>
}<br>
<br>
-; CHECK-LABLE: @aarch64_tree_tests_or<br>
+; CHECK-LABEL: @aarch64_tree_tests_or<br>
; CHECK: .hword 32768 <br>
; CHECK: .hword 32766<br>
; CHECK: .hword 4664 <br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/andandshift.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/andandshift.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/andandshift.<wbr>ll?rev=336268&r1=336267&r2=<wbr>336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/andandshift.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/andandshift.ll Wed Jul 4 06:28:39 2018<br>
@@ -4,7 +4,7 @@ target triple = "arm64--linux-gnu"<br>
<br>
; Function Attrs: nounwind readnone<br>
define i32 @test1(i8 %a) {<br>
-; CHECK-LABLE: @test1<br>
+; CHECK-LABEL: @test1<br>
; CHECK: ubfx {{w[0-9]+}}, w0, #3, #5<br>
entry:<br>
%conv = zext i8 %a to i32<br>
@@ -14,7 +14,7 @@ entry:<br>
<br>
; Function Attrs: nounwind readnone<br>
define i32 @test2(i8 %a) {<br>
-; CHECK-LABLE: @test2<br>
+; CHECK-LABEL: @test2<br>
; CHECK: and {{w[0-9]+}}, w0, #0xff<br>
; CHECK: ubfx {{w[0-9]+}}, w0, #3, #5<br>
entry:<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-addr-mode-<wbr>folding.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-addr-mode-folding.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-addr-<wbr>mode-folding.ll?rev=336268&r1=<wbr>336267&r2=336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-addr-mode-<wbr>folding.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-addr-mode-<wbr>folding.ll Wed Jul 4 06:28:39 2018<br>
@@ -8,7 +8,7 @@ define i32 @fct(i32 %i1, i32 %i2) {<br>
; Sign extension is used more than once, thus it should not be folded.<br>
; CodeGenPrepare is not sharing sext across uses, thus this is folded because<br>
; of that.<br>
-; _CHECK-NOT_: , sxtw]<br>
+; _CHECK-NOT: , sxtw]<br>
entry:<br>
%idxprom = sext i32 %i1 to i64<br>
%0 = load i8*, i8** @block, align 8<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-csel.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-csel.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-csel.ll?<wbr>rev=336268&r1=336267&r2=<wbr>336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-csel.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-csel.ll Wed Jul 4 06:28:39 2018<br>
@@ -79,9 +79,9 @@ define i32 @foo7(i32 %a, i32 %b) nounwin<br>
entry:<br>
; CHECK-LABEL: foo7:<br>
; CHECK: sub<br>
-; CHECK-next: adds<br>
-; CHECK-next: csneg<br>
-; CHECK-next: b<br>
+; CHECK-NEXT: adds<br>
+; CHECK-NEXT: csneg<br>
+; CHECK-NEXT: b<br>
%sub = sub nsw i32 %a, %b<br>
%cmp = icmp sgt i32 %sub, -1<br>
%sub3 = sub nsw i32 0, %sub<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/cmpwithshort.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/cmpwithshort.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/cmpwithshort.<wbr>ll?rev=336268&r1=336267&r2=<wbr>336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/cmpwithshort.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/cmpwithshort.ll Wed Jul 4 06:28:39 2018<br>
@@ -1,7 +1,7 @@<br>
; RUN: llc < %s -O3 -mtriple=aarch64-eabi | FileCheck %s <br>
<br>
define i16 @test_1cmp_signed_1(i16* %ptr1) {<br>
-; CHECK-LABLE: @test_1cmp_signed_1<br>
+; CHECK-LABEL: @test_1cmp_signed_1<br>
; CHECK: ldrsh<br>
; CHECK-NEXT: cmn<br>
entry:<br>
@@ -16,7 +16,7 @@ if.then:<br>
}<br>
<br>
define i16 @test_1cmp_signed_2(i16* %ptr1) {<br>
-; CHECK-LABLE: @test_1cmp_signed_2<br>
+; CHECK-LABEL: @test_1cmp_signed_2<br>
; CHECK: ldrsh<br>
; CHECK-NEXT: cmn<br>
entry:<br>
@@ -31,7 +31,7 @@ if.then:<br>
}<br>
<br>
define i16 @test_1cmp_unsigned_1(i16* %ptr1) {<br>
-; CHECK-LABLE: @test_1cmp_unsigned_1<br>
+; CHECK-LABEL: @test_1cmp_unsigned_1<br>
; CHECK: ldrsh<br>
; CHECK-NEXT: cmn<br>
entry:<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/fast-isel-gep.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-gep.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/fast-isel-gep.<wbr>ll?rev=336268&r1=336267&r2=<wbr>336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/fast-isel-gep.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/fast-isel-gep.ll Wed Jul 4 06:28:39 2018<br>
@@ -34,7 +34,7 @@ define i32* @test_array3(i32* %a) {<br>
define i32* @test_array4(i32* %a) {<br>
; CHECK-LABEL: test_array4<br>
; CHECK: mov [[REG:x[0-9]+]], #4104<br>
-; CHECK-NEXR: add x0, x0, [[REG]]<br>
+; CHECK-NEXT: add x0, x0, [[REG]]<br>
%1 = getelementptr inbounds i32, i32* %a, i64 1026<br>
ret i32* %1<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>GlobalISel/arm-param-lowering.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/GlobalISel/arm-<wbr>param-lowering.ll?rev=336268&<wbr>r1=336267&r2=336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>GlobalISel/arm-param-lowering.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>GlobalISel/arm-param-lowering.<wbr>ll Wed Jul 4 06:28:39 2018<br>
@@ -30,7 +30,7 @@ define arm_aapcscc i32* @test_call_simpl<br>
; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp<br>
; CHECK-DAG: $r0 = COPY [[BVREG]]<br>
; CHECK-DAG: $r1 = COPY [[AVREG]]<br>
-; CHECK-DxAG: $r2 = COPY [[BVREG]]<br>
+; CHECK-DAG: $r2 = COPY [[BVREG]]<br>
; CHECK-DAG: $r3 = COPY [[AVREG]]<br>
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp<br>
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>atomic-op.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/atomic-op.ll?rev=<wbr>336268&r1=336267&r2=336268&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>atomic-op.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>atomic-op.ll Wed Jul 4 06:28:39 2018<br>
@@ -396,9 +396,9 @@ define void @store_store_release(i32* %m<br>
; CHECK-T1-M0: str r3, [r2]<br>
<br>
; CHECK-BAREMETAL-NOT: dmb<br>
-; CHECK-BAREMTEAL: str r1, [r0]<br>
+; CHECK-BAREMETAL: str r1, [r0]<br>
; CHECK-BAREMETAL-NOT: dmb<br>
-; CHECK-BAREMTEAL: str r3, [r2]<br>
+; CHECK-BAREMETAL: str r3, [r2]<br>
<br>
ret void<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>debug-frame-large-stack.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-frame-large-stack.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/debug-frame-large-<wbr>stack.ll?rev=336268&r1=336267&<wbr>r2=336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>debug-frame-large-stack.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>debug-frame-large-stack.ll Wed Jul 4 06:28:39 2018<br>
@@ -35,16 +35,16 @@ define void @test2() {<br>
; CHECK-ARM: sub sp, sp, #4096<br>
; CHECK-ARM: .cfi_endproc<br>
<br>
-; CHECK-ARM-FP_ELIM-LABEL: test2:<br>
-; CHECK-ARM-FP_ELIM: .cfi_startproc<br>
-; CHECK-ARM-FP_ELIM: push {r4, r5}<br>
-; CHECK-ARM-FP_ELIM: .cfi_def_cfa_offset 8<br>
-; CHECK-ARM-FP_ELIM: .cfi_offset 54, -4<br>
-; CHECK-ARM-FP_ELIM: .cfi_offset r4, -8<br>
-; CHECK-ARM-FP_ELIM: sub sp, sp, #72<br>
-; CHECK-ARM-FP_ELIM: sub sp, sp, #4096<br>
-; CHECK-ARM-FP_ELIM: .cfi_def_cfa_offset 4176<br>
-; CHECK-ARM-FP_ELIM: .cfi_endproc<br>
+; CHECK-ARM-FP-ELIM-LABEL: test2:<br>
+; CHECK-ARM-FP-ELIM: .cfi_startproc<br>
+; CHECK-ARM-FP-ELIM: push {r4, r5}<br>
+; CHECK-ARM-FP-ELIM: .cfi_def_cfa_offset 8<br>
+; CHECK-ARM-FP-ELIM: .cfi_offset 54, -4<br>
+; CHECK-ARM-FP-ELIM: .cfi_offset r4, -8<br>
+; CHECK-ARM-FP-ELIM: sub sp, sp, #72<br>
+; CHECK-ARM-FP-ELIM: sub sp, sp, #4096<br>
+; CHECK-ARM-FP-ELIM: .cfi_def_cfa_offset 4176<br>
+; CHECK-ARM-FP-ELIM: .cfi_endproc<br>
<br>
define i32 @test3() {<br>
%retval = alloca i32, align 4<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>float-helpers.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/float-helpers.s?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/float-helpers.s?<wbr>rev=336268&r1=336267&r2=<wbr>336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>float-helpers.s (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>float-helpers.s Wed Jul 4 06:28:39 2018<br>
@@ -20,14 +20,14 @@<br>
; * all functions use base AAPCS<br>
; * floating point instructions permitted, so __aeabi_ helpers only<br>
; expected when there is no available instruction.<br>
-; CHECK-HARD-FP-SP -mfloat-abi=hardfp (single precision instructions)<br>
+; CHECK-HARDFP-SP -mfloat-abi=hardfp (single precision instructions)<br>
; * all non Runtime ABI helper functions use AAPCS VFP<br>
; * floating point instructions permitted, so __aeabi_ helpers only<br>
; expected when there is no available instruction.<br>
-; CHECK-HARD-FP-DP -mfloat-abi=hardfp (double precision instructions)<br>
-; CHECK-HARD_FP_SPONLY -mfloat-abi=hardfp (double precision but single<br>
+; CHECK-HARDFP-DP -mfloat-abi=hardfp (double precision instructions)<br>
+; CHECK-HARDFP-SPONLY -mfloat-abi=hardfp (double precision but single<br>
; precision only FPU)<br>
-; * as CHECK-HARD-FP-SP, but we split up the double precision helper<br>
+; * as CHECK-HARDFP-SP, but we split up the double precision helper<br>
; functions so we can test a single precision only FPU, which has to use<br>
; helper function for all double precision operations.<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>fp16.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/fp16.ll?rev=<wbr>336268&r1=336267&r2=336268&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>fp16.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>fp16.ll Wed Jul 4 06:28:39 2018<br>
@@ -29,7 +29,7 @@ entry:<br>
; CHECK-HARDFLOAT-EABI: __aeabi_h2f<br>
; CHECK-HARDFLOAT-GNU: __gnu_h2f_ieee<br>
; CHECK-FP16: vcvtb.f32.f16<br>
-; CHECK-ARMv8: vcvtb.f32.f16<br>
+; CHECK-ARMV8: vcvtb.f32.f16<br>
; CHECK-SOFTFLOAT-EABI: __aeabi_h2f<br>
; CHECK-SOFTFLOAT-GNU: __gnu_h2f_ieee<br>
%3 = tail call float @llvm.convert.from.fp16.f32(<wbr>i16 %1)<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>shift-combine.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/shift-combine.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/shift-combine.ll?<wbr>rev=336268&r1=336267&r2=<wbr>336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>shift-combine.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>shift-combine.ll Wed Jul 4 06:28:39 2018<br>
@@ -9,7 +9,7 @@<br>
<br>
define i32 @test_lshr_and1(i32 %x) {<br>
entry:<br>
-;CHECK-LABLE: test_lshr_and1:<br>
+;CHECK-LABEL: test_lshr_and1:<br>
;CHECK-COMMON: movw r1, :lower16:array<br>
;CHECK-COMMON-NEXT: and r0, r0, #12<br>
;CHECK-COMMON-NEXT: movt r1, :upper16:array<br>
<br>
Modified: llvm/trunk/test/CodeGen/NVPTX/<wbr>ctlz.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/ctlz.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/NVPTX/ctlz.ll?rev=<wbr>336268&r1=336267&r2=336268&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/NVPTX/<wbr>ctlz.ll (original)<br>
+++ llvm/trunk/test/CodeGen/NVPTX/<wbr>ctlz.ll Wed Jul 4 06:28:39 2018<br>
@@ -108,7 +108,7 @@ define i16 @myctlz_ret16_2(i16 %a) {<br>
define void @myctlz_store16(i16 %a, i16* %b) {<br>
; CHECK: ld.param.<br>
; CHECK-NEXT: cvt.u32.u16<br>
-; CHECK-NET: clz.b32<br>
+; CHECK-NEXT: clz.b32<br>
; CHECK-DAG: cvt.u16.u32<br>
; CHECK-DAG: sub.<br>
; CHECK: st.{{[a-z]}}16<br>
@@ -121,7 +121,7 @@ define void @myctlz_store16(i16 %a, i16*<br>
define void @myctlz_store16_2(i16 %a, i16* %b) {<br>
; CHECK: ld.param.<br>
; CHECK-NEXT: cvt.u32.u16<br>
-; CHECK-NET: clz.b32<br>
+; CHECK-NEXT: clz.b32<br>
; CHECK-DAG: cvt.u16.u32<br>
; CHECK-DAG: sub.<br>
; CHECK: st.{{[a-z]}}16<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>PowerPC/vec_rotate_shift.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_rotate_shift.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/PowerPC/vec_rotate_<wbr>shift.ll?rev=336268&r1=336267&<wbr>r2=336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>PowerPC/vec_rotate_shift.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>PowerPC/vec_rotate_shift.ll Wed Jul 4 06:28:39 2018<br>
@@ -30,7 +30,7 @@ define <2 x i64> @test_vsrd(<2 x i64> %x<br>
define <2 x i64> @test_vsrad(<2 x i64> %x, <2 x i64> %y) nounwind readnone {<br>
%tmp = ashr <2 x i64> %x, %y<br>
ret <2 x i64> %tmp<br>
-; CHECK-LABER: @test_vsrad<br>
+; CHECK-LABEL: @test_vsrad<br>
; CHECK: vsrad 2, 2, 3<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/SPARC/<wbr>soft-float.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/soft-float.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/SPARC/soft-float.ll?<wbr>rev=336268&r1=336267&r2=<wbr>336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/SPARC/<wbr>soft-float.ll (original)<br>
+++ llvm/trunk/test/CodeGen/SPARC/<wbr>soft-float.ll Wed Jul 4 06:28:39 2018<br>
@@ -151,21 +151,21 @@ define i1 @test_netf2(fp128 %a, fp128 %b<br>
}<br>
<br>
define i1 @test_gesf2(float %a, float %b) #0 {<br>
- ; CHECK-LABLE: test_gesf2:<br>
+ ; CHECK-LABEL: test_gesf2:<br>
; CHECK: call __gesf2<br>
%cmp = fcmp oge float %a, %b<br>
ret i1 %cmp<br>
}<br>
<br>
define i1 @test_gedf2(double %a, double %b) #0 {<br>
- ; CHECK-LABLE: test_gedf2:<br>
+ ; CHECK-LABEL: test_gedf2:<br>
; CHECK: call __gedf2<br>
%cmp = fcmp oge double %a, %b<br>
ret i1 %cmp<br>
}<br>
<br>
define i1 @test_getf2(fp128 %a, fp128 %b) #0 {<br>
- ; CHECK-LABLE: test_getf2:<br>
+ ; CHECK-LABEL: test_getf2:<br>
; CHECK: call __getf2<br>
%cmp = fcmp oge fp128 %a, %b<br>
ret i1 %cmp<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>WebAssembly/address-offsets.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/address-offsets.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/WebAssembly/address-<wbr>offsets.ll?rev=336268&r1=<wbr>336267&r2=336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>WebAssembly/address-offsets.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>WebAssembly/address-offsets.ll Wed Jul 4 06:28:39 2018<br>
@@ -36,9 +36,9 @@ define i32 @load_test0_noinbounds() {<br>
; CHECK-NEXT: param i32{{$}}<br>
; CHECK-NEXT: result i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
-; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}}<br>
-; CHECK-NEX T: return $pop2{{$}}<br>
+; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
+; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}}<br>
+; CHECK-NEXT: return $pop2{{$}}<br>
define i32 @load_test1(i32 %n) {<br>
%add = add nsw i32 %n, 10<br>
%arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add<br>
@@ -50,9 +50,9 @@ define i32 @load_test1(i32 %n) {<br>
; CHECK-NEXT: param i32{{$}}<br>
; CHECK-NEXT: result i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
-; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}}<br>
-; CHECK-NEX T: return $pop2{{$}}<br>
+; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
+; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}}<br>
+; CHECK-NEXT: return $pop2{{$}}<br>
define i32 @load_test2(i32 %n) {<br>
%add = add nsw i32 10, %n<br>
%arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add<br>
@@ -64,9 +64,9 @@ define i32 @load_test2(i32 %n) {<br>
; CHECK-NEXT: param i32{{$}}<br>
; CHECK-NEXT: result i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
-; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}}<br>
-; CHECK-NEX T: return $pop2{{$}}<br>
+; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
+; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}}<br>
+; CHECK-NEXT: return $pop2{{$}}<br>
define i32 @load_test3(i32 %n) {<br>
%add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %n<br>
%add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10<br>
@@ -78,9 +78,9 @@ define i32 @load_test3(i32 %n) {<br>
; CHECK-NEXT: param i32{{$}}<br>
; CHECK-NEXT: result i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
-; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}}<br>
-; CHECK-NEX T: return $pop2{{$}}<br>
+; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
+; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}}<br>
+; CHECK-NEXT: return $pop2{{$}}<br>
define i32 @load_test4(i32 %n) {<br>
%add.ptr = getelementptr inbounds i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), i32 %n<br>
%t = load i32, i32* %add.ptr, align 4<br>
@@ -91,9 +91,9 @@ define i32 @load_test4(i32 %n) {<br>
; CHECK-NEXT: param i32{{$}}<br>
; CHECK-NEXT: result i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
-; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}}<br>
-; CHECK-NEX T: return $pop2{{$}}<br>
+; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
+; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}}<br>
+; CHECK-NEXT: return $pop2{{$}}<br>
define i32 @load_test5(i32 %n) {<br>
%add.ptr = getelementptr inbounds i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), i32 %n<br>
%t = load i32, i32* %add.ptr, align 4<br>
@@ -104,9 +104,9 @@ define i32 @load_test5(i32 %n) {<br>
; CHECK-NEXT: param i32{{$}}<br>
; CHECK-NEXT: result i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
-; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}}<br>
-; CHECK-NEX T: return $pop2{{$}}<br>
+; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
+; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}}<br>
+; CHECK-NEXT: return $pop2{{$}}<br>
define i32 @load_test6(i32 %n) {<br>
%add = add nsw i32 %n, 10<br>
%add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add<br>
@@ -118,9 +118,9 @@ define i32 @load_test6(i32 %n) {<br>
; CHECK-NEXT: param i32{{$}}<br>
; CHECK-NEXT: result i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
-; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}}<br>
-; CHECK-NEX T: return $pop2{{$}}<br>
+; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
+; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}}<br>
+; CHECK-NEXT: return $pop2{{$}}<br>
define i32 @load_test7(i32 %n) {<br>
%add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %n<br>
%add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10<br>
@@ -132,9 +132,9 @@ define i32 @load_test7(i32 %n) {<br>
; CHECK-NEXT: param i32{{$}}<br>
; CHECK-NEXT: result i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
-; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}}<br>
-; CHECK-NEX T: return $pop2{{$}}<br>
+; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
+; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}}<br>
+; CHECK-NEXT: return $pop2{{$}}<br>
define i32 @load_test8(i32 %n) {<br>
%add = add nsw i32 10, %n<br>
%add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add<br>
@@ -378,8 +378,8 @@ define void @store_test0_noinbounds(i32<br>
; CHECK-NEXT: param i32, i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}<br>
-; CHECK-NEX T: return{{$}}<br>
+; CHECK-NEXT: i32.store g+40($pop1), $1{{$}}<br>
+; CHECK-NEXT: return{{$}}<br>
define void @store_test1(i32 %n, i32 %i) {<br>
%add = add nsw i32 %n, 10<br>
%arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add<br>
@@ -391,8 +391,8 @@ define void @store_test1(i32 %n, i32 %i)<br>
; CHECK-NEXT: param i32, i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}<br>
-; CHECK-NEX T: return{{$}}<br>
+; CHECK-NEXT: i32.store g+40($pop1), $1{{$}}<br>
+; CHECK-NEXT: return{{$}}<br>
define void @store_test2(i32 %n, i32 %i) {<br>
%add = add nsw i32 10, %n<br>
%arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add<br>
@@ -404,8 +404,8 @@ define void @store_test2(i32 %n, i32 %i)<br>
; CHECK-NEXT: param i32, i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}<br>
-; CHECK-NEX T: return{{$}}<br>
+; CHECK-NEXT: i32.store g+40($pop1), $1{{$}}<br>
+; CHECK-NEXT: return{{$}}<br>
define void @store_test3(i32 %n, i32 %i) {<br>
%add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %n<br>
%add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10<br>
@@ -417,8 +417,8 @@ define void @store_test3(i32 %n, i32 %i)<br>
; CHECK-NEXT: param i32, i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}<br>
-; CHECK-NEX T: return{{$}}<br>
+; CHECK-NEXT: i32.store g+40($pop1), $1{{$}}<br>
+; CHECK-NEXT: return{{$}}<br>
define void @store_test4(i32 %n, i32 %i) {<br>
%add.ptr = getelementptr inbounds i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), i32 %n<br>
store i32 %i, i32* %add.ptr, align 4<br>
@@ -429,8 +429,8 @@ define void @store_test4(i32 %n, i32 %i)<br>
; CHECK-NEXT: param i32, i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}<br>
-; CHECK-NEX T: return{{$}}<br>
+; CHECK-NEXT: i32.store g+40($pop1), $1{{$}}<br>
+; CHECK-NEXT: return{{$}}<br>
define void @store_test5(i32 %n, i32 %i) {<br>
%add.ptr = getelementptr inbounds i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), i32 %n<br>
store i32 %i, i32* %add.ptr, align 4<br>
@@ -441,8 +441,8 @@ define void @store_test5(i32 %n, i32 %i)<br>
; CHECK-NEXT: param i32, i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}<br>
-; CHECK-NEX T: return{{$}}<br>
+; CHECK-NEXT: i32.store g+40($pop1), $1{{$}}<br>
+; CHECK-NEXT: return{{$}}<br>
define void @store_test6(i32 %n, i32 %i) {<br>
%add = add nsw i32 %n, 10<br>
%add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add<br>
@@ -454,8 +454,8 @@ define void @store_test6(i32 %n, i32 %i)<br>
; CHECK-NEXT: param i32, i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}<br>
-; CHECK-NEX T: return{{$}}<br>
+; CHECK-NEXT: i32.store g+40($pop1), $1{{$}}<br>
+; CHECK-NEXT: return{{$}}<br>
define void @store_test7(i32 %n, i32 %i) {<br>
%add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %n<br>
%add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10<br>
@@ -467,8 +467,8 @@ define void @store_test7(i32 %n, i32 %i)<br>
; CHECK-NEXT: param i32, i32{{$}}<br>
; CHECK-NEXT: i32.const $push0=, 2{{$}}<br>
; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}}<br>
-; CHECK-NEX T: i32.store g+40($pop1), $1{{$}}<br>
-; CHECK-NEX T: return{{$}}<br>
+; CHECK-NEXT: i32.store g+40($pop1), $1{{$}}<br>
+; CHECK-NEXT: return{{$}}<br>
define void @store_test8(i32 %n, i32 %i) {<br>
%add = add nsw i32 10, %n<br>
%add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add<br>
<br>
Modified: llvm/trunk/test/DebugInfo/X86/<wbr>mem2reg_fp80.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/mem2reg_fp80.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>DebugInfo/X86/mem2reg_fp80.ll?<wbr>rev=336268&r1=336267&r2=<wbr>336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/DebugInfo/X86/<wbr>mem2reg_fp80.ll (original)<br>
+++ llvm/trunk/test/DebugInfo/X86/<wbr>mem2reg_fp80.ll Wed Jul 4 06:28:39 2018<br>
@@ -10,7 +10,7 @@ entry:<br>
br i1 undef, label %if.then, label %if.end, !dbg !16<br>
<br>
if.then: ; preds = %entry<br>
-; CHECK-label: if.then:<br>
+; CHECK-LABEL: if.then:<br>
; CHECK: %mul = fmul x86_fp80<br>
; CHECK: call void @llvm.dbg.value(metadata x86_fp80 %mul, metadata {{.*}}, metadata !DIExpression())<br>
%mul = fmul x86_fp80 undef, undef, !dbg !18<br>
@@ -18,7 +18,7 @@ if.then:<br>
br label %if.end, !dbg !20<br>
<br>
if.end: ; preds = %if.then, %entry<br>
-; CHECK-label: if.end:<br>
+; CHECK-LABEL: if.end:<br>
; CHECK: %r.0 = phi x86_fp80<br>
; CHECK: call void @llvm.dbg.value(metadata x86_fp80 %r.0, metadata {{.*}}, metadata !DIExpression())<br>
%out = load x86_fp80, x86_fp80* %r, align 16, !dbg !21<br>
<br>
Modified: llvm/trunk/test/MC/<wbr>Disassembler/Hexagon/nv_j.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/nv_j.txt?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>Disassembler/Hexagon/nv_j.txt?<wbr>rev=336268&r1=336267&r2=<wbr>336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/<wbr>Disassembler/Hexagon/nv_j.txt (original)<br>
+++ llvm/trunk/test/MC/<wbr>Disassembler/Hexagon/nv_j.txt Wed Jul 4 06:28:39 2018<br>
@@ -67,7 +67,7 @@<br>
# CHECK-NEXT: if (cmp.eq(r17.new,#21)) jump:nt<br>
0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x24<br>
# CHECK: r17 = r17<br>
-# CHECK-NETX: if (cmp.eq(r17.new,#21)) jump:t<br>
+# CHECK-NEXT: if (cmp.eq(r17.new,#21)) jump:t<br>
0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x24<br>
# CHECK: r17 = r17<br>
# CHECK-NEXT: if (!cmp.eq(r17.new,#21)) jump:nt<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>Inline/deoptimize-intrinsic.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/deoptimize-intrinsic.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/Inline/deoptimize-<wbr>intrinsic.ll?rev=336268&r1=<wbr>336267&r2=336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>Inline/deoptimize-intrinsic.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>Inline/deoptimize-intrinsic.ll Wed Jul 4 06:28:39 2018<br>
@@ -97,7 +97,7 @@ define i8 @callee_with_alloca() alwaysin<br>
}<br>
<br>
define void @caller_with_lifetime() {<br>
-; CHECK-LABLE: @caller_with_lifetime(<br>
+; CHECK-LABEL: @caller_with_lifetime(<br>
; CHECK: call void (...) @llvm.experimental.deoptimize.<wbr>isVoid(i32 1) [ "deopt"(i8* %t.i) ]<br>
; CHECK-NEXT: ret void<br>
<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LICM/loopsink.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/loopsink.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LICM/loopsink.ll?<wbr>rev=336268&r1=336267&r2=<wbr>336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LICM/loopsink.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LICM/loopsink.ll Wed Jul 4 06:28:39 2018<br>
@@ -198,7 +198,7 @@ define i32 @t3(i32, i32) #0 !prof !0 {<br>
; For single-BB loop with <=1 avg trip count, sink load to b1<br>
; CHECK: t4<br>
; CHECK: .preheader:<br>
-; CHECK-not: load i32, i32* @g<br>
+; CHECK-NOT: load i32, i32* @g<br>
; CHECK: .b1:<br>
; CHECK: load i32, i32* @g<br>
; CHECK: .exit:<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoadStoreVectorizer/X86/merge-<wbr>tbaa.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoadStoreVectorizer/X86/merge-tbaa.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/<wbr>LoadStoreVectorizer/X86/merge-<wbr>tbaa.ll?rev=336268&r1=336267&<wbr>r2=336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoadStoreVectorizer/X86/merge-<wbr>tbaa.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoadStoreVectorizer/X86/merge-<wbr>tbaa.ll Wed Jul 4 06:28:39 2018<br>
@@ -43,4 +43,4 @@ entry:<br>
!8 = !{!3, !7, i64 4}<br>
<br>
; CHECK-DAG: [[TYPE_char:!.*]] = !{!"omnipotent char", {{.*}}, i64 0}<br>
-; CHECK-FAG: [[TAG_char]] = !{[[TYPE_char]], [[TYPE_char]], i64 0}<br>
+; CHECK-DAG: [[TAG_char]] = !{[[TYPE_char]], [[TYPE_char]], i64 0}<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoopInterchange/profitability.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopInterchange/profitability.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LoopInterchange/<wbr>profitability.ll?rev=336268&<wbr>r1=336267&r2=336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoopInterchange/profitability.<wbr>ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoopInterchange/profitability.<wbr>ll Wed Jul 4 06:28:39 2018<br>
@@ -98,7 +98,7 @@ for.end21:<br>
;; A[i-1][j-1] = A[i - 1][j-1] + B[i][j];<br>
<br>
; CHECK: Name: InterchangeNotProfitable<br>
-; CHECK-ENXT: Function: interchange_03<br>
+; CHECK-NEXT: Function: interchange_03<br>
define void @interchange_03(){<br>
entry:<br>
br label %for1.header<br>
@@ -136,7 +136,7 @@ for.end19:<br>
;; A[i][j] = A[i][j]+k;<br>
<br>
; CHECK: Name: InterchangeNotProfitable<br>
-; CHECK-ENXT: Function: interchange_04<br>
+; CHECK-NEXT: Function: interchange_04<br>
define void @interchange_04(i32 %k) {<br>
entry:<br>
br label %for.cond1.preheader<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/vector_max_<wbr>bandwidth.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/vector_max_bandwidth.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LoopVectorize/X86/<wbr>vector_max_bandwidth.ll?rev=<wbr>336268&r1=336267&r2=336268&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/vector_max_<wbr>bandwidth.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/vector_max_<wbr>bandwidth.ll Wed Jul 4 06:28:39 2018<br>
@@ -16,7 +16,7 @@ target triple = "x86_64-unknown-linux-gn<br>
; widest type in the loop for maximum bandwidth when<br>
; -vectorizer-maximize-bandwidth is indicated.<br>
;<br>
-; CHECK-label: foo<br>
+; CHECK-LABEL: foo<br>
; CHECK-AVX1: LV: Selecting VF: 16.<br>
; CHECK-AVX2: LV: Selecting VF: 32.<br>
define void @foo() {<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>RewriteStatepointsForGC/deopt-<wbr>intrinsic-cconv.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/RewriteStatepointsForGC/deopt-intrinsic-cconv.ll?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/<wbr>RewriteStatepointsForGC/deopt-<wbr>intrinsic-cconv.ll?rev=336268&<wbr>r1=336267&r2=336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>RewriteStatepointsForGC/deopt-<wbr>intrinsic-cconv.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>RewriteStatepointsForGC/deopt-<wbr>intrinsic-cconv.ll Wed Jul 4 06:28:39 2018<br>
@@ -7,7 +7,7 @@ target triple = "x86_64-apple-macosx10.1<br>
declare cc42 double @llvm.experimental.deoptimize.<wbr>f64(...)<br>
<br>
define double @caller_3() gc "statepoint-example" {<br>
-; CHECK-LABELL @caller_3(<br>
+; CHECK-LABEL: @caller_3(<br>
; CHECK: call cc42 token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.<wbr>statepoint<br>
; CHECK: unreachable<br>
<br>
<br>
Modified: llvm/trunk/test/tools/llvm-<wbr>dwarfdump/X86/debug_line_<wbr>offset.test<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-dwarfdump/X86/debug_line_offset.test?rev=336268&r1=336267&r2=336268&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/tools/<wbr>llvm-dwarfdump/X86/debug_line_<wbr>offset.test?rev=336268&r1=<wbr>336267&r2=336268&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/tools/llvm-<wbr>dwarfdump/X86/debug_line_<wbr>offset.test (original)<br>
+++ llvm/trunk/test/tools/llvm-<wbr>dwarfdump/X86/debug_line_<wbr>offset.test Wed Jul 4 06:28:39 2018<br>
@@ -3,11 +3,11 @@ RUN: -debug-line=0x0 | FileCheck %s --c<br>
<br>
CHECK-A: debug_line[0x00000000]<br>
CHECK-A: Address Line Column File ISA Discriminator Flags<br>
-CHECK-A-NET: ------------------ ------ ------ ------ --- ------------- -------------<br>
-CHECK-A-NET: 0x0000000000000000 26 0 1 0 0 is_stmt<br>
-CHECK-A-NET: 0x0000000000000004 27 10 1 0 0 is_stmt prologue_end<br>
-CHECK-A-NET: 0x0000000000000009 27 3 1 0 0<br>
-CHECK-A-NET: 0x0000000000000074 27 3 1 0 0 end_sequence<br>
+CHECK-A-NEXT: ------------------ ------ ------ ------ --- ------------- -------------<br>
+CHECK-A-NEXT: 0x0000000000000000 26 0 1 0 0 is_stmt<br>
+CHECK-A-NEXT: 0x0000000000000004 27 10 1 0 0 is_stmt prologue_end<br>
+CHECK-A-NEXT: 0x0000000000000009 27 3 1 0 0<br>
+CHECK-A-NEXT: 0x0000000000000074 27 3 1 0 0 end_sequence<br>
CHECK-A-NOT: debug_line[0x0000009a]<br>
<br>
RUN: llvm-dwarfdump %S/../../dsymutil/Inputs/<wbr>basic-lto-dw4.macho.x86_64.o \<br>
<br>
<br>
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</blockquote></div><br></div>