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Yes, we already found the fix.
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<div class="">When I glanced through the recent changes I didn’t spot a revert or anything which looks obviously related.
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<div class="">Artur</div>
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<div><br class="">
<blockquote type="cite" class="">
<div class="">On 27 Jun 2018, at 18:25, Craig Topper <<a href="mailto:craig.topper@gmail.com" class="">craig.topper@gmail.com</a>> wrote:</div>
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<div class="">
<div dir="auto" class="">I think this is PR37879 which was already fixed. Are you on the an earlier revision?</div>
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<div class="gmail_quote">
<div dir="ltr" class="">On Wed, Jun 27, 2018 at 5:21 AM Artur Pilipenko via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class="">
</div>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
This change is causing failures in our downstream testing. We see something like:<br class="">
LLVM ERROR: Cannot select: 0x8f7cd0: v1i1 = scalar_to_vector 0x8f7c00<br class="">
0x8f7c00: i64,ch = CopyFromReg 0x85acf8, Register:i64 %11<br class="">
0x8f7e70: i64 = Register %11<br class="">
<br class="">
Any ideas on what this might be? <br class="">
<br class="">
I’ll try to come up with a smaller reproducer, but we might need to revert the change for the time being.<br class="">
<br class="">
Artur<br class="">
<br class="">
> On 19 Jun 2018, at 13:37, Mikhail Dvoretckii via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class="">
> <br class="">
> Author: mike.dvoretsky<br class="">
> Date: Tue Jun 19 03:37:52 2018<br class="">
> New Revision: 335037<br class="">
> <br class="">
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=335037&view=rev" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-project?rev=335037&view=rev</a><br class="">
> Log:<br class="">
> [X86] VRNDSCALE* folding from masked and scalar ffloor and fceil patterns<br class="">
> <br class="">
> This patch handles back-end folding of generic patterns created by lowering the<br class="">
> X86 rounding intrinsics to native IR in cases where the instruction isn't a<br class="">
> straightforward packed values rounding operation, but a masked operation or a<br class="">
> scalar operation.<br class="">
> <br class="">
> Differential Revision: <a href="https://reviews.llvm.org/D45203" rel="noreferrer" target="_blank" class="">
https://reviews.llvm.org/D45203</a><br class="">
> <br class="">
> Modified:<br class="">
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br class="">
> llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br class="">
> llvm/trunk/lib/Target/X86/X86InstrSSE.td<br class="">
> llvm/trunk/test/CodeGen/X86/vec_floor.ll<br class="">
> <br class="">
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br class="">
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=335037&r1=335036&r2=335037&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=335037&r1=335036&r2=335037&view=diff</a><br class="">
> ==============================================================================<br class="">
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br class="">
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jun 19 03:37:52 2018<br class="">
> @@ -39121,9 +39121,31 @@ static SDValue combineScalarToVector(SDN<br class="">
> // TODO: SimplifyDemandedBits instead?<br class="">
> if (VT == MVT::v1i1 && Src.getOpcode() == ISD::AND && Src.hasOneUse())<br class="">
> if (auto *C = dyn_cast<ConstantSDNode>(Src.getOperand(1)))<br class="">
> - if (C->getAPIntValue().isOneValue())<br class="">
> - return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), MVT::v1i1,<br class="">
> - Src.getOperand(0));<br class="">
> + if (C->getAPIntValue().isOneValue()) {<br class="">
> + SDValue Mask = Src.getOperand(0);<br class="">
> + if (Mask.getOpcode() == ISD::TRUNCATE &&<br class="">
> + Mask.getOperand(0).getValueType() != MVT::i16)<br class="">
> + Mask = Mask.getOperand(0);<br class="">
> + return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), MVT::v1i1, Mask);<br class="">
> + }<br class="">
> +<br class="">
> + // The result of AND may also be truncated. This occurs in code for lowered<br class="">
> + // masked scalar intrinsics.<br class="">
> + if (VT == MVT::v1i1 && Src.getOpcode() == ISD::TRUNCATE && Src.hasOneUse() &&<br class="">
> + Src.getOperand(0).getOpcode() == ISD::AND &&<br class="">
> + Src.getOperand(0).hasOneUse())<br class="">
> + if (auto *C = dyn_cast<ConstantSDNode>(Src.getOperand(0).getOperand(1)))<br class="">
> + if (C->getAPIntValue().isOneValue()) {<br class="">
> + SDValue Mask = Src.getOperand(0).getOperand(0);<br class="">
> + if (Mask.getOpcode() == ISD::TRUNCATE &&<br class="">
> + Mask.getOperand(0).getValueType() != MVT::i16)<br class="">
> + Mask = Mask.getOperand(0);<br class="">
> + // Check if the initial value is an i16. scalar_to_vector fails to<br class="">
> + // select for that type, so the combine should be aborted.<br class="">
> + if (Mask.getValueType() == MVT::i16)<br class="">
> + return SDValue();<br class="">
> + return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), MVT::v1i1, Mask);<br class="">
> + }<br class="">
> <br class="">
> return SDValue();<br class="">
> }<br class="">
> <br class="">
> Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br class="">
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=335037&r1=335036&r2=335037&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=335037&r1=335036&r2=335037&view=diff</a><br class="">
> ==============================================================================<br class="">
> --- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)<br class="">
> +++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue Jun 19 03:37:52 2018<br class="">
> @@ -8781,16 +8781,50 @@ multiclass avx512_masked_scalar_imm<SDNo<br class="">
> def : Pat<(Move _.VT:$src1, (scalar_to_vector (X86selects Mask,<br class="">
> (OpNode (extractelt _.VT:$src2, (iPTR 0))),<br class="">
> (extractelt _.VT:$dst, (iPTR 0))))),<br class="">
> - (!cast<Instruction>("V"#OpcPrefix#r_Intk)<br class="">
> + (!cast<Instruction>("V"#OpcPrefix#Zr_Intk)<br class="">
> _.VT:$dst, OutMask, _.VT:$src1, _.VT:$src2, (i32 ImmV))>;<br class="">
> <br class="">
> def : Pat<(Move _.VT:$src1, (scalar_to_vector (X86selects Mask,<br class="">
> (OpNode (extractelt _.VT:$src2, (iPTR 0))), ZeroFP))),<br class="">
> - (!cast<Instruction>("V"#OpcPrefix#r_Intkz)<br class="">
> + (!cast<Instruction>("V"#OpcPrefix#Zr_Intkz)<br class="">
> OutMask, _.VT:$src1, _.VT:$src2, (i32 ImmV))>;<br class="">
> }<br class="">
> }<br class="">
> <br class="">
> +defm : avx512_masked_scalar_imm<ffloor, "RNDSCALESS", X86Movss,<br class="">
> + (v1i1 (scalar_to_vector GR32:$mask)),<br class="">
> + v4f32x_info, fp32imm0, 0x01,<br class="">
> + (COPY_TO_REGCLASS $mask, VK1WM), HasAVX512>;<br class="">
> +defm : avx512_masked_scalar_imm<ffloor, "RNDSCALESS", X86Movss,<br class="">
> + (v1i1 (scalar_to_vector GR8:$mask)),<br class="">
> + v4f32x_info, fp32imm0, 0x01,<br class="">
> + (COPY_TO_REGCLASS $mask, VK1WM), HasAVX512>;<br class="">
> +defm : avx512_masked_scalar_imm<fceil, "RNDSCALESS", X86Movss,<br class="">
> + (v1i1 (scalar_to_vector GR32:$mask)),<br class="">
> + v4f32x_info, fp32imm0, 0x02,<br class="">
> + (COPY_TO_REGCLASS $mask, VK1WM), HasAVX512>;<br class="">
> +defm : avx512_masked_scalar_imm<fceil, "RNDSCALESS", X86Movss,<br class="">
> + (v1i1 (scalar_to_vector GR8:$mask)),<br class="">
> + v4f32x_info, fp32imm0, 0x02,<br class="">
> + (COPY_TO_REGCLASS $mask, VK1WM), HasAVX512>;<br class="">
> +defm : avx512_masked_scalar_imm<ffloor, "RNDSCALESD", X86Movsd,<br class="">
> + (v1i1 (scalar_to_vector GR32:$mask)),<br class="">
> + v2f64x_info, fp64imm0, 0x01,<br class="">
> + (COPY_TO_REGCLASS $mask, VK1WM), HasAVX512>;<br class="">
> +defm : avx512_masked_scalar_imm<ffloor, "RNDSCALESD", X86Movsd,<br class="">
> + (v1i1 (scalar_to_vector GR8:$mask)),<br class="">
> + v2f64x_info, fp64imm0, 0x01,<br class="">
> + (COPY_TO_REGCLASS $mask, VK1WM), HasAVX512>;<br class="">
> +defm : avx512_masked_scalar_imm<fceil, "RNDSCALESD", X86Movsd,<br class="">
> + (v1i1 (scalar_to_vector GR32:$mask)),<br class="">
> + v2f64x_info, fp64imm0, 0x02,<br class="">
> + (COPY_TO_REGCLASS $mask, VK1WM), HasAVX512>;<br class="">
> +defm : avx512_masked_scalar_imm<fceil, "RNDSCALESD", X86Movsd,<br class="">
> + (v1i1 (scalar_to_vector GR8:$mask)),<br class="">
> + v2f64x_info, fp64imm0, 0x02,<br class="">
> + (COPY_TO_REGCLASS $mask, VK1WM), HasAVX512>;<br class="">
> +<br class="">
> +<br class="">
> //-------------------------------------------------<br class="">
> // Integer truncate and extend operations<br class="">
> //-------------------------------------------------<br class="">
> @@ -9936,10 +9970,18 @@ defm VGETMANTSS: avx512_common_fp_sae_sc<br class="">
> let Predicates = [HasAVX512] in {<br class="">
> def : Pat<(v16f32 (ffloor VR512:$src)),<br class="">
> (VRNDSCALEPSZrri VR512:$src, (i32 0x9))>;<br class="">
> +def : Pat<(v16f32 (vselect VK16WM:$mask, (ffloor VR512:$src), VR512:$dst)),<br class="">
> + (VRNDSCALEPSZrrik VR512:$dst, VK16WM:$mask, VR512:$src, (i32 0x9))>;<br class="">
> +def : Pat<(v16f32 (vselect VK16WM:$mask, (ffloor VR512:$src), v16f32_info.ImmAllZerosV)),<br class="">
> + (VRNDSCALEPSZrrikz VK16WM:$mask, VR512:$src, (i32 0x9))>;<br class="">
> def : Pat<(v16f32 (fnearbyint VR512:$src)),<br class="">
> (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;<br class="">
> def : Pat<(v16f32 (fceil VR512:$src)),<br class="">
> (VRNDSCALEPSZrri VR512:$src, (i32 0xA))>;<br class="">
> +def : Pat<(v16f32 (vselect VK16WM:$mask, (fceil VR512:$src), VR512:$dst)),<br class="">
> + (VRNDSCALEPSZrrik VR512:$dst, VK16WM:$mask, VR512:$src, (i32 0xA))>;<br class="">
> +def : Pat<(v16f32 (vselect VK16WM:$mask, (fceil VR512:$src), v16f32_info.ImmAllZerosV)),<br class="">
> + (VRNDSCALEPSZrrikz VK16WM:$mask, VR512:$src, (i32 0xA))>;<br class="">
> def : Pat<(v16f32 (frint VR512:$src)),<br class="">
> (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;<br class="">
> def : Pat<(v16f32 (ftrunc VR512:$src)),<br class="">
> @@ -9958,10 +10000,18 @@ def : Pat<(v16f32 (ftrunc (loadv16f32 ad<br class="">
> <br class="">
> def : Pat<(v8f64 (ffloor VR512:$src)),<br class="">
> (VRNDSCALEPDZrri VR512:$src, (i32 0x9))>;<br class="">
> +def : Pat<(v8f64 (vselect VK8WM:$mask, (ffloor VR512:$src), VR512:$dst)),<br class="">
> + (VRNDSCALEPDZrrik VR512:$dst, VK8WM:$mask, VR512:$src, (i32 0x9))>;<br class="">
> +def : Pat<(v8f64 (vselect VK8WM:$mask, (ffloor VR512:$src), v8f64_info.ImmAllZerosV)),<br class="">
> + (VRNDSCALEPDZrrikz VK8WM:$mask, VR512:$src, (i32 0x9))>;<br class="">
> def : Pat<(v8f64 (fnearbyint VR512:$src)),<br class="">
> (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;<br class="">
> def : Pat<(v8f64 (fceil VR512:$src)),<br class="">
> (VRNDSCALEPDZrri VR512:$src, (i32 0xA))>;<br class="">
> +def : Pat<(v8f64 (vselect VK8WM:$mask, (fceil VR512:$src), VR512:$dst)),<br class="">
> + (VRNDSCALEPDZrrik VR512:$dst, VK8WM:$mask, VR512:$src, (i32 0xA))>;<br class="">
> +def : Pat<(v8f64 (vselect VK8WM:$mask, (fceil VR512:$src), v8f64_info.ImmAllZerosV)),<br class="">
> + (VRNDSCALEPDZrrikz VK8WM:$mask, VR512:$src, (i32 0xA))>;<br class="">
> def : Pat<(v8f64 (frint VR512:$src)),<br class="">
> (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;<br class="">
> def : Pat<(v8f64 (ftrunc VR512:$src)),<br class="">
> @@ -9982,10 +10032,18 @@ def : Pat<(v8f64 (ftrunc (loadv8f64 addr<br class="">
> let Predicates = [HasVLX] in {<br class="">
> def : Pat<(v4f32 (ffloor VR128X:$src)),<br class="">
> (VRNDSCALEPSZ128rri VR128X:$src, (i32 0x9))>;<br class="">
> +def : Pat<(v4f32 (vselect VK4WM:$mask, (ffloor VR128X:$src), VR128X:$dst)),<br class="">
> + (VRNDSCALEPSZ128rrik VR128X:$dst, VK4WM:$mask, VR128X:$src, (i32 0x9))>;<br class="">
> +def : Pat<(v4f32 (vselect VK4WM:$mask, (ffloor VR128X:$src), v4f32x_info.ImmAllZerosV)),<br class="">
> + (VRNDSCALEPSZ128rrikz VK4WM:$mask, VR128X:$src, (i32 0x9))>;<br class="">
> def : Pat<(v4f32 (fnearbyint VR128X:$src)),<br class="">
> (VRNDSCALEPSZ128rri VR128X:$src, (i32 0xC))>;<br class="">
> def : Pat<(v4f32 (fceil VR128X:$src)),<br class="">
> (VRNDSCALEPSZ128rri VR128X:$src, (i32 0xA))>;<br class="">
> +def : Pat<(v4f32 (vselect VK4WM:$mask, (fceil VR128X:$src), VR128X:$dst)),<br class="">
> + (VRNDSCALEPSZ128rrik VR128X:$dst, VK4WM:$mask, VR128X:$src, (i32 0xA))>;<br class="">
> +def : Pat<(v4f32 (vselect VK4WM:$mask, (fceil VR128X:$src), v4f32x_info.ImmAllZerosV)),<br class="">
> + (VRNDSCALEPSZ128rrikz VK4WM:$mask, VR128X:$src, (i32 0xA))>;<br class="">
> def : Pat<(v4f32 (frint VR128X:$src)),<br class="">
> (VRNDSCALEPSZ128rri VR128X:$src, (i32 0x4))>;<br class="">
> def : Pat<(v4f32 (ftrunc VR128X:$src)),<br class="">
> @@ -10004,10 +10062,18 @@ def : Pat<(v4f32 (ftrunc (loadv4f32 addr<br class="">
> <br class="">
> def : Pat<(v2f64 (ffloor VR128X:$src)),<br class="">
> (VRNDSCALEPDZ128rri VR128X:$src, (i32 0x9))>;<br class="">
> +def : Pat<(v2f64 (vselect VK2WM:$mask, (ffloor VR128X:$src), VR128X:$dst)),<br class="">
> + (VRNDSCALEPDZ128rrik VR128X:$dst, VK2WM:$mask, VR128X:$src, (i32 0x9))>;<br class="">
> +def : Pat<(v2f64 (vselect VK2WM:$mask, (ffloor VR128X:$src), v2f64x_info.ImmAllZerosV)),<br class="">
> + (VRNDSCALEPDZ128rrikz VK2WM:$mask, VR128X:$src, (i32 0x9))>;<br class="">
> def : Pat<(v2f64 (fnearbyint VR128X:$src)),<br class="">
> (VRNDSCALEPDZ128rri VR128X:$src, (i32 0xC))>;<br class="">
> def : Pat<(v2f64 (fceil VR128X:$src)),<br class="">
> (VRNDSCALEPDZ128rri VR128X:$src, (i32 0xA))>;<br class="">
> +def : Pat<(v2f64 (vselect VK2WM:$mask, (fceil VR128X:$src), VR128X:$dst)),<br class="">
> + (VRNDSCALEPDZ128rrik VR128X:$dst, VK2WM:$mask, VR128X:$src, (i32 0xA))>;<br class="">
> +def : Pat<(v2f64 (vselect VK2WM:$mask, (fceil VR128X:$src), v2f64x_info.ImmAllZerosV)),<br class="">
> + (VRNDSCALEPDZ128rrikz VK2WM:$mask, VR128X:$src, (i32 0xA))>;<br class="">
> def : Pat<(v2f64 (frint VR128X:$src)),<br class="">
> (VRNDSCALEPDZ128rri VR128X:$src, (i32 0x4))>;<br class="">
> def : Pat<(v2f64 (ftrunc VR128X:$src)),<br class="">
> @@ -10026,10 +10092,18 @@ def : Pat<(v2f64 (ftrunc (loadv2f64 addr<br class="">
> <br class="">
> def : Pat<(v8f32 (ffloor VR256X:$src)),<br class="">
> (VRNDSCALEPSZ256rri VR256X:$src, (i32 0x9))>;<br class="">
> +def : Pat<(v8f32 (vselect VK8WM:$mask, (ffloor VR256X:$src), VR256X:$dst)),<br class="">
> + (VRNDSCALEPSZ256rrik VR256X:$dst, VK8WM:$mask, VR256X:$src, (i32 0x9))>;<br class="">
> +def : Pat<(v8f32 (vselect VK8WM:$mask, (ffloor VR256X:$src), v8f32x_info.ImmAllZerosV)),<br class="">
> + (VRNDSCALEPSZ256rrikz VK8WM:$mask, VR256X:$src, (i32 0x9))>;<br class="">
> def : Pat<(v8f32 (fnearbyint VR256X:$src)),<br class="">
> (VRNDSCALEPSZ256rri VR256X:$src, (i32 0xC))>;<br class="">
> def : Pat<(v8f32 (fceil VR256X:$src)),<br class="">
> (VRNDSCALEPSZ256rri VR256X:$src, (i32 0xA))>;<br class="">
> +def : Pat<(v8f32 (vselect VK8WM:$mask, (fceil VR256X:$src), VR256X:$dst)),<br class="">
> + (VRNDSCALEPSZ256rrik VR256X:$dst, VK8WM:$mask, VR256X:$src, (i32 0xA))>;<br class="">
> +def : Pat<(v8f32 (vselect VK8WM:$mask, (fceil VR256X:$src), v8f32x_info.ImmAllZerosV)),<br class="">
> + (VRNDSCALEPSZ256rrikz VK8WM:$mask, VR256X:$src, (i32 0xA))>;<br class="">
> def : Pat<(v8f32 (frint VR256X:$src)),<br class="">
> (VRNDSCALEPSZ256rri VR256X:$src, (i32 0x4))>;<br class="">
> def : Pat<(v8f32 (ftrunc VR256X:$src)),<br class="">
> @@ -10048,10 +10122,18 @@ def : Pat<(v8f32 (ftrunc (loadv8f32 addr<br class="">
> <br class="">
> def : Pat<(v4f64 (ffloor VR256X:$src)),<br class="">
> (VRNDSCALEPDZ256rri VR256X:$src, (i32 0x9))>;<br class="">
> +def : Pat<(v4f64 (vselect VK4WM:$mask, (ffloor VR256X:$src), VR256X:$dst)),<br class="">
> + (VRNDSCALEPDZ256rrik VR256X:$dst, VK4WM:$mask, VR256X:$src, (i32 0x9))>;<br class="">
> +def : Pat<(v4f64 (vselect VK4WM:$mask, (ffloor VR256X:$src), v4f64x_info.ImmAllZerosV)),<br class="">
> + (VRNDSCALEPDZ256rrikz VK4WM:$mask, VR256X:$src, (i32 0x9))>;<br class="">
> def : Pat<(v4f64 (fnearbyint VR256X:$src)),<br class="">
> (VRNDSCALEPDZ256rri VR256X:$src, (i32 0xC))>;<br class="">
> def : Pat<(v4f64 (fceil VR256X:$src)),<br class="">
> (VRNDSCALEPDZ256rri VR256X:$src, (i32 0xA))>;<br class="">
> +def : Pat<(v4f64 (vselect VK4WM:$mask, (fceil VR256X:$src), VR256X:$dst)),<br class="">
> + (VRNDSCALEPDZ256rrik VR256X:$dst, VK4WM:$mask, VR256X:$src, (i32 0xA))>;<br class="">
> +def : Pat<(v4f64 (vselect VK4WM:$mask, (fceil VR256X:$src), v4f64x_info.ImmAllZerosV)),<br class="">
> + (VRNDSCALEPDZ256rrikz VK4WM:$mask, VR256X:$src, (i32 0xA))>;<br class="">
> def : Pat<(v4f64 (frint VR256X:$src)),<br class="">
> (VRNDSCALEPDZ256rri VR256X:$src, (i32 0x4))>;<br class="">
> def : Pat<(v4f64 (ftrunc VR256X:$src)),<br class="">
> <br class="">
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br class="">
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=335037&r1=335036&r2=335037&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=335037&r1=335036&r2=335037&view=diff</a><br class="">
> ==============================================================================<br class="">
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br class="">
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 19 03:37:52 2018<br class="">
> @@ -5944,6 +5944,15 @@ let Predicates = [UseSSE41] in {<br class="">
> (ROUNDPDm addr:$src, (i32 0xB))>;<br class="">
> }<br class="">
> <br class="">
> +defm : scalar_unary_math_imm_patterns<ffloor, "ROUNDSS", X86Movss,<br class="">
> + v4f32, 0x01, UseSSE41>;<br class="">
> +defm : scalar_unary_math_imm_patterns<fceil, "ROUNDSS", X86Movss,<br class="">
> + v4f32, 0x02, UseSSE41>;<br class="">
> +defm : scalar_unary_math_imm_patterns<ffloor, "ROUNDSD", X86Movsd,<br class="">
> + v2f64, 0x01, UseSSE41>;<br class="">
> +defm : scalar_unary_math_imm_patterns<fceil, "ROUNDSD", X86Movsd,<br class="">
> + v2f64, 0x02, UseSSE41>;<br class="">
> +<br class="">
> //===----------------------------------------------------------------------===//<br class="">
> // SSE4.1 - Packed Bit Test<br class="">
> //===----------------------------------------------------------------------===//<br class="">
> <br class="">
> Modified: llvm/trunk/test/CodeGen/X86/vec_floor.ll<br class="">
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_floor.ll?rev=335037&r1=335036&r2=335037&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_floor.ll?rev=335037&r1=335036&r2=335037&view=diff</a><br class="">
> ==============================================================================<br class="">
> --- llvm/trunk/test/CodeGen/X86/vec_floor.ll (original)<br class="">
> +++ llvm/trunk/test/CodeGen/X86/vec_floor.ll Tue Jun 19 03:37:52 2018<br class="">
> @@ -1,7 +1,8 @@<br class="">
> ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br class="">
> ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41<br class="">
> ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s --check-prefix=AVX<br class="">
> -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512vl | FileCheck %s --check-prefix=AVX512<br class="">
> +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f | FileCheck %s --check-prefix=AVX512 --check-prefix=AVX512F<br class="">
> +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512vl | FileCheck %s --check-prefix=AVX512 --check-prefix=AVX512VL<br class="">
> <br class="">
> define <2 x double> @floor_v2f64(<2 x double> %p) {<br class="">
> ; SSE41-LABEL: floor_v2f64:<br class="">
> @@ -770,3 +771,2135 @@ define <4 x float> @const_trunc_v4f32()<br class="">
> %t = call <4 x float> @llvm.trunc.v4f32(<4 x float> <float -3.5, float 6.0, float -9.0, float 2.5>)<br class="">
> ret <4 x float> %t<br class="">
> }<br class="">
> +<br class="">
> +;<br class="">
> +; Scalar and masked instructions<br class="">
> +;<br class="">
> +<br class="">
> +define <4 x float> @floor_ss(<4 x float> %x, <4 x float> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_ss:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundss $1, %xmm0, %xmm1<br class="">
> +; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_ss:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vroundss $1, %xmm0, %xmm1, %xmm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_ss:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: vroundss $1, %xmm0, %xmm1, %xmm0<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %s = extractelement <4 x float> %x, i32 0<br class="">
> + %call = call float @llvm.floor.f32(float %s)<br class="">
> + %res = insertelement <4 x float> %y, float %call, i32 0<br class="">
> + ret <4 x float> %res<br class="">
> +}<br class="">
> +declare float @llvm.floor.f32(float %s)<br class="">
> +<br class="">
> +define <2 x double> @floor_sd(<2 x double> %x, <2 x double> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_sd:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundsd $1, %xmm0, %xmm1<br class="">
> +; SSE41-NEXT: movapd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_sd:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vroundsd $1, %xmm0, %xmm1, %xmm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_sd:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: vroundsd $1, %xmm0, %xmm1, %xmm0<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %s = extractelement <2 x double> %x, i32 0<br class="">
> + %call = call double @llvm.floor.f64(double %s)<br class="">
> + %res = insertelement <2 x double> %y, double %call, i32 0<br class="">
> + ret <2 x double> %res<br class="">
> +}<br class="">
> +declare double @llvm.floor.f64(double %s)<br class="">
> +<br class="">
> +define <4 x float> @floor_mask_128_ps(<4 x float> %x, <4 x float> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_mask_128_ps:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundps $9, %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: cmpeqps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm1<br class="">
> +; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_mask_128_ps:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: vroundps $9, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: floor_mask_128_ps:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqps %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundps $9, %xmm0, %xmm0<br class="">
> +; AVX512F-NEXT: vblendmps %zmm0, %zmm1, %zmm0 {%k1}<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: vzeroupper<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: floor_mask_128_ps:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqps %xmm1, %xmm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscaleps $9, %xmm0, %xmm1 {%k1}<br class="">
> +; AVX512VL-NEXT: vmovaps %xmm1, %xmm0<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <4 x float> %x, %y<br class="">
> + %call = call <4 x float> @llvm.floor.v4f32(<4 x float> %x)<br class="">
> + %res = select <4 x i1> %k, <4 x float> %call, <4 x float> %y<br class="">
> + ret <4 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <4 x float> @floor_maskz_128_ps(<4 x float> %x, <4 x float> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_maskz_128_ps:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: cmpeqps %xmm0, %xmm1<br class="">
> +; SSE41-NEXT: roundps $9, %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: andps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_maskz_128_ps:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm1<br class="">
> +; AVX-NEXT: vroundps $9, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vandps %xmm0, %xmm1, %xmm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: floor_maskz_128_ps:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqps %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundps $9, %xmm0, %xmm0<br class="">
> +; AVX512F-NEXT: vmovaps %zmm0, %zmm0 {%k1} {z}<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: vzeroupper<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: floor_maskz_128_ps:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqps %xmm1, %xmm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscaleps $9, %xmm0, %xmm0 {%k1} {z}<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <4 x float> %x, %y<br class="">
> + %call = call <4 x float> @llvm.floor.v4f32(<4 x float> %x)<br class="">
> + %res = select <4 x i1> %k, <4 x float> %call, <4 x float> zeroinitializer<br class="">
> + ret <4 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <2 x double> @floor_mask_128_pd(<2 x double> %x, <2 x double> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_mask_128_pd:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1<br class="">
> +; SSE41-NEXT: movapd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_mask_128_pd:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: vroundpd $9, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: floor_mask_128_pd:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqpd %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundpd $9, %xmm0, %xmm0<br class="">
> +; AVX512F-NEXT: vblendmpd %zmm0, %zmm1, %zmm0 {%k1}<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: vzeroupper<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: floor_mask_128_pd:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqpd %xmm1, %xmm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscalepd $9, %xmm0, %xmm1 {%k1}<br class="">
> +; AVX512VL-NEXT: vmovapd %xmm1, %xmm0<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <2 x double> %x, %y<br class="">
> + %call = call <2 x double> @llvm.floor.v2f64(<2 x double> %x)<br class="">
> + %res = select <2 x i1> %k, <2 x double> %call, <2 x double> %y<br class="">
> + ret <2 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <2 x double> @floor_maskz_128_pd(<2 x double> %x, <2 x double> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_maskz_128_pd:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm0, %xmm1<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: andpd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_maskz_128_pd:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm1<br class="">
> +; AVX-NEXT: vroundpd $9, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vandpd %xmm0, %xmm1, %xmm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: floor_maskz_128_pd:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqpd %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundpd $9, %xmm0, %xmm0<br class="">
> +; AVX512F-NEXT: vmovapd %zmm0, %zmm0 {%k1} {z}<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: vzeroupper<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: floor_maskz_128_pd:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqpd %xmm1, %xmm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscalepd $9, %xmm0, %xmm0 {%k1} {z}<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <2 x double> %x, %y<br class="">
> + %call = call <2 x double> @llvm.floor.v2f64(<2 x double> %x)<br class="">
> + %res = select <2 x i1> %k, <2 x double> %call, <2 x double> zeroinitializer<br class="">
> + ret <2 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <8 x float> @floor_mask_256_ps(<8 x float> %x, <8 x float> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_mask_256_ps:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundps $9, %xmm1, %xmm4<br class="">
> +; SSE41-NEXT: cmpeqps %xmm3, %xmm1<br class="">
> +; SSE41-NEXT: roundps $9, %xmm0, %xmm5<br class="">
> +; SSE41-NEXT: cmpeqps %xmm2, %xmm0<br class="">
> +; SSE41-NEXT: blendvps %xmm0, %xmm5, %xmm2<br class="">
> +; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm3<br class="">
> +; SSE41-NEXT: movaps %xmm2, %xmm0<br class="">
> +; SSE41-NEXT: movaps %xmm3, %xmm1<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_mask_256_ps:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqps %ymm1, %ymm0, %ymm2<br class="">
> +; AVX-NEXT: vroundps $9, %ymm0, %ymm0<br class="">
> +; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: floor_mask_256_ps:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm1 killed $ymm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqps %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundps $9, %ymm0, %ymm0<br class="">
> +; AVX512F-NEXT: vblendmps %zmm0, %zmm1, %zmm0 {%k1}<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: floor_mask_256_ps:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqps %ymm1, %ymm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscaleps $9, %ymm0, %ymm1 {%k1}<br class="">
> +; AVX512VL-NEXT: vmovaps %ymm1, %ymm0<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <8 x float> %x, %y<br class="">
> + %call = call <8 x float> @llvm.floor.v8f32(<8 x float> %x)<br class="">
> + %res = select <8 x i1> %k, <8 x float> %call, <8 x float> %y<br class="">
> + ret <8 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <8 x float> @floor_maskz_256_ps(<8 x float> %x, <8 x float> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_maskz_256_ps:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: cmpeqps %xmm1, %xmm3<br class="">
> +; SSE41-NEXT: cmpeqps %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: roundps $9, %xmm1, %xmm1<br class="">
> +; SSE41-NEXT: andps %xmm3, %xmm1<br class="">
> +; SSE41-NEXT: roundps $9, %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: andps %xmm2, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_maskz_256_ps:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqps %ymm1, %ymm0, %ymm1<br class="">
> +; AVX-NEXT: vroundps $9, %ymm0, %ymm0<br class="">
> +; AVX-NEXT: vandps %ymm0, %ymm1, %ymm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: floor_maskz_256_ps:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm1 killed $ymm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqps %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundps $9, %ymm0, %ymm0<br class="">
> +; AVX512F-NEXT: vmovaps %zmm0, %zmm0 {%k1} {z}<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: floor_maskz_256_ps:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqps %ymm1, %ymm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscaleps $9, %ymm0, %ymm0 {%k1} {z}<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <8 x float> %x, %y<br class="">
> + %call = call <8 x float> @llvm.floor.v8f32(<8 x float> %x)<br class="">
> + %res = select <8 x i1> %k, <8 x float> %call, <8 x float> zeroinitializer<br class="">
> + ret <8 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <4 x double> @floor_mask_256_pd(<4 x double> %x, <4 x double> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_mask_256_pd:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm1, %xmm4<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm3, %xmm1<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm0, %xmm5<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm2, %xmm0<br class="">
> +; SSE41-NEXT: blendvpd %xmm0, %xmm5, %xmm2<br class="">
> +; SSE41-NEXT: movapd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm3<br class="">
> +; SSE41-NEXT: movapd %xmm2, %xmm0<br class="">
> +; SSE41-NEXT: movapd %xmm3, %xmm1<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_mask_256_pd:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm2<br class="">
> +; AVX-NEXT: vroundpd $9, %ymm0, %ymm0<br class="">
> +; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: floor_mask_256_pd:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm1 killed $ymm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqpd %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundpd $9, %ymm0, %ymm0<br class="">
> +; AVX512F-NEXT: vblendmpd %zmm0, %zmm1, %zmm0 {%k1}<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: floor_mask_256_pd:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqpd %ymm1, %ymm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscalepd $9, %ymm0, %ymm1 {%k1}<br class="">
> +; AVX512VL-NEXT: vmovapd %ymm1, %ymm0<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <4 x double> %x, %y<br class="">
> + %call = call <4 x double> @llvm.floor.v4f64(<4 x double> %x)<br class="">
> + %res = select <4 x i1> %k, <4 x double> %call, <4 x double> %y<br class="">
> + ret <4 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <4 x double> @floor_maskz_256_pd(<4 x double> %x, <4 x double> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_maskz_256_pd:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm1, %xmm3<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm1, %xmm1<br class="">
> +; SSE41-NEXT: andpd %xmm3, %xmm1<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: andpd %xmm2, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_maskz_256_pd:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm1<br class="">
> +; AVX-NEXT: vroundpd $9, %ymm0, %ymm0<br class="">
> +; AVX-NEXT: vandpd %ymm0, %ymm1, %ymm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: floor_maskz_256_pd:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm1 killed $ymm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqpd %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundpd $9, %ymm0, %ymm0<br class="">
> +; AVX512F-NEXT: vmovapd %zmm0, %zmm0 {%k1} {z}<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: floor_maskz_256_pd:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqpd %ymm1, %ymm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscalepd $9, %ymm0, %ymm0 {%k1} {z}<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <4 x double> %x, %y<br class="">
> + %call = call <4 x double> @llvm.floor.v4f64(<4 x double> %x)<br class="">
> + %res = select <4 x i1> %k, <4 x double> %call, <4 x double> zeroinitializer<br class="">
> + ret <4 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <16 x float> @floor_mask_512_ps(<16 x float> %x, <16 x float> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_mask_512_ps:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundps $9, %xmm3, %xmm8<br class="">
> +; SSE41-NEXT: cmpeqps %xmm7, %xmm3<br class="">
> +; SSE41-NEXT: roundps $9, %xmm2, %xmm9<br class="">
> +; SSE41-NEXT: cmpeqps %xmm6, %xmm2<br class="">
> +; SSE41-NEXT: roundps $9, %xmm1, %xmm10<br class="">
> +; SSE41-NEXT: cmpeqps %xmm5, %xmm1<br class="">
> +; SSE41-NEXT: roundps $9, %xmm0, %xmm11<br class="">
> +; SSE41-NEXT: cmpeqps %xmm4, %xmm0<br class="">
> +; SSE41-NEXT: blendvps %xmm0, %xmm11, %xmm4<br class="">
> +; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: blendvps %xmm0, %xmm10, %xmm5<br class="">
> +; SSE41-NEXT: movaps %xmm2, %xmm0<br class="">
> +; SSE41-NEXT: blendvps %xmm0, %xmm9, %xmm6<br class="">
> +; SSE41-NEXT: movaps %xmm3, %xmm0<br class="">
> +; SSE41-NEXT: blendvps %xmm0, %xmm8, %xmm7<br class="">
> +; SSE41-NEXT: movaps %xmm4, %xmm0<br class="">
> +; SSE41-NEXT: movaps %xmm5, %xmm1<br class="">
> +; SSE41-NEXT: movaps %xmm6, %xmm2<br class="">
> +; SSE41-NEXT: movaps %xmm7, %xmm3<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_mask_512_ps:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqps %ymm3, %ymm1, %ymm4<br class="">
> +; AVX-NEXT: vcmpeqps %ymm2, %ymm0, %ymm5<br class="">
> +; AVX-NEXT: vroundps $9, %ymm1, %ymm1<br class="">
> +; AVX-NEXT: vroundps $9, %ymm0, %ymm0<br class="">
> +; AVX-NEXT: vblendvps %ymm5, %ymm0, %ymm2, %ymm0<br class="">
> +; AVX-NEXT: vblendvps %ymm4, %ymm1, %ymm3, %ymm1<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_mask_512_ps:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: vcmpeqps %zmm1, %zmm0, %k1<br class="">
> +; AVX512-NEXT: vrndscaleps $9, %zmm0, %zmm1 {%k1}<br class="">
> +; AVX512-NEXT: vmovaps %zmm1, %zmm0<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %k = fcmp oeq <16 x float> %x, %y<br class="">
> + %call = call <16 x float> @llvm.floor.v16f32(<16 x float> %x)<br class="">
> + %res = select <16 x i1> %k, <16 x float> %call, <16 x float> %y<br class="">
> + ret <16 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <16 x float> @floor_maskz_512_ps(<16 x float> %x, <16 x float> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_maskz_512_ps:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: cmpeqps %xmm3, %xmm7<br class="">
> +; SSE41-NEXT: cmpeqps %xmm2, %xmm6<br class="">
> +; SSE41-NEXT: cmpeqps %xmm1, %xmm5<br class="">
> +; SSE41-NEXT: cmpeqps %xmm0, %xmm4<br class="">
> +; SSE41-NEXT: roundps $9, %xmm3, %xmm3<br class="">
> +; SSE41-NEXT: andps %xmm7, %xmm3<br class="">
> +; SSE41-NEXT: roundps $9, %xmm2, %xmm2<br class="">
> +; SSE41-NEXT: andps %xmm6, %xmm2<br class="">
> +; SSE41-NEXT: roundps $9, %xmm1, %xmm1<br class="">
> +; SSE41-NEXT: andps %xmm5, %xmm1<br class="">
> +; SSE41-NEXT: roundps $9, %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: andps %xmm4, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_maskz_512_ps:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqps %ymm3, %ymm1, %ymm3<br class="">
> +; AVX-NEXT: vcmpeqps %ymm2, %ymm0, %ymm2<br class="">
> +; AVX-NEXT: vroundps $9, %ymm1, %ymm1<br class="">
> +; AVX-NEXT: vandps %ymm1, %ymm3, %ymm1<br class="">
> +; AVX-NEXT: vroundps $9, %ymm0, %ymm0<br class="">
> +; AVX-NEXT: vandps %ymm0, %ymm2, %ymm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_maskz_512_ps:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: vcmpeqps %zmm1, %zmm0, %k1<br class="">
> +; AVX512-NEXT: vrndscaleps $9, %zmm0, %zmm0 {%k1} {z}<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %k = fcmp oeq <16 x float> %x, %y<br class="">
> + %call = call <16 x float> @llvm.floor.v16f32(<16 x float> %x)<br class="">
> + %res = select <16 x i1> %k, <16 x float> %call, <16 x float> zeroinitializer<br class="">
> + ret <16 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <8 x double> @floor_mask_512_pd(<8 x double> %x, <8 x double> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_mask_512_pd:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm3, %xmm8<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm7, %xmm3<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm2, %xmm9<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm6, %xmm2<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm1, %xmm10<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm5, %xmm1<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm0, %xmm11<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm4, %xmm0<br class="">
> +; SSE41-NEXT: blendvpd %xmm0, %xmm11, %xmm4<br class="">
> +; SSE41-NEXT: movapd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: blendvpd %xmm0, %xmm10, %xmm5<br class="">
> +; SSE41-NEXT: movapd %xmm2, %xmm0<br class="">
> +; SSE41-NEXT: blendvpd %xmm0, %xmm9, %xmm6<br class="">
> +; SSE41-NEXT: movapd %xmm3, %xmm0<br class="">
> +; SSE41-NEXT: blendvpd %xmm0, %xmm8, %xmm7<br class="">
> +; SSE41-NEXT: movapd %xmm4, %xmm0<br class="">
> +; SSE41-NEXT: movapd %xmm5, %xmm1<br class="">
> +; SSE41-NEXT: movapd %xmm6, %xmm2<br class="">
> +; SSE41-NEXT: movapd %xmm7, %xmm3<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_mask_512_pd:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqpd %ymm3, %ymm1, %ymm4<br class="">
> +; AVX-NEXT: vcmpeqpd %ymm2, %ymm0, %ymm5<br class="">
> +; AVX-NEXT: vroundpd $9, %ymm1, %ymm1<br class="">
> +; AVX-NEXT: vroundpd $9, %ymm0, %ymm0<br class="">
> +; AVX-NEXT: vblendvpd %ymm5, %ymm0, %ymm2, %ymm0<br class="">
> +; AVX-NEXT: vblendvpd %ymm4, %ymm1, %ymm3, %ymm1<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_mask_512_pd:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: vcmpeqpd %zmm1, %zmm0, %k1<br class="">
> +; AVX512-NEXT: vrndscalepd $9, %zmm0, %zmm1 {%k1}<br class="">
> +; AVX512-NEXT: vmovapd %zmm1, %zmm0<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %k = fcmp oeq <8 x double> %x, %y<br class="">
> + %call = call <8 x double> @llvm.floor.v8f64(<8 x double> %x)<br class="">
> + %res = select <8 x i1> %k, <8 x double> %call, <8 x double> %y<br class="">
> + ret <8 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <8 x double> @floor_maskz_512_pd(<8 x double> %x, <8 x double> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_maskz_512_pd:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm3, %xmm7<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm2, %xmm6<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm1, %xmm5<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm0, %xmm4<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm3, %xmm3<br class="">
> +; SSE41-NEXT: andpd %xmm7, %xmm3<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm2, %xmm2<br class="">
> +; SSE41-NEXT: andpd %xmm6, %xmm2<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm1, %xmm1<br class="">
> +; SSE41-NEXT: andpd %xmm5, %xmm1<br class="">
> +; SSE41-NEXT: roundpd $9, %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: andpd %xmm4, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_maskz_512_pd:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqpd %ymm3, %ymm1, %ymm3<br class="">
> +; AVX-NEXT: vcmpeqpd %ymm2, %ymm0, %ymm2<br class="">
> +; AVX-NEXT: vroundpd $9, %ymm1, %ymm1<br class="">
> +; AVX-NEXT: vandpd %ymm1, %ymm3, %ymm1<br class="">
> +; AVX-NEXT: vroundpd $9, %ymm0, %ymm0<br class="">
> +; AVX-NEXT: vandpd %ymm0, %ymm2, %ymm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_maskz_512_pd:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: vcmpeqpd %zmm1, %zmm0, %k1<br class="">
> +; AVX512-NEXT: vrndscalepd $9, %zmm0, %zmm0 {%k1} {z}<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %k = fcmp oeq <8 x double> %x, %y<br class="">
> + %call = call <8 x double> @llvm.floor.v8f64(<8 x double> %x)<br class="">
> + %res = select <8 x i1> %k, <8 x double> %call, <8 x double> zeroinitializer<br class="">
> + ret <8 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <4 x float> @floor_mask_ss(<4 x float> %x, <4 x float> %y, <4 x float> %w, i8 %k) nounwind {<br class="">
> +; SSE41-LABEL: floor_mask_ss:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: testb $1, %dil<br class="">
> +; SSE41-NEXT: je LBB50_2<br class="">
> +; SSE41-NEXT: ## %bb.1:<br class="">
> +; SSE41-NEXT: xorps %xmm2, %xmm2<br class="">
> +; SSE41-NEXT: roundss $9, %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: LBB50_2:<br class="">
> +; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]<br class="">
> +; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_mask_ss:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: testb $1, %dil<br class="">
> +; AVX-NEXT: je LBB50_2<br class="">
> +; AVX-NEXT: ## %bb.1:<br class="">
> +; AVX-NEXT: vroundss $9, %xmm0, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: LBB50_2:<br class="">
> +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0],xmm1[1,2,3]<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_mask_ss:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: kmovw %edi, %k1<br class="">
> +; AVX512-NEXT: vrndscaless $1, %xmm0, %xmm1, %xmm2 {%k1}<br class="">
> +; AVX512-NEXT: vmovaps %xmm2, %xmm0<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %mask = and i8 %k, 1<br class="">
> + %nmask = icmp eq i8 %mask, 0<br class="">
> + %s = extractelement <4 x float> %x, i64 0<br class="">
> + %call = tail call float @llvm.floor.f32(float %s)<br class="">
> + %dst = extractelement <4 x float> %w, i64 0<br class="">
> + %low = select i1 %nmask, float %dst, float %call<br class="">
> + %res = insertelement <4 x float> %y, float %low, i64 0<br class="">
> + ret <4 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <4 x float> @floor_maskz_ss(<4 x float> %x, <4 x float> %y, i8 %k) nounwind {<br class="">
> +; SSE41-LABEL: floor_maskz_ss:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: testb $1, %dil<br class="">
> +; SSE41-NEXT: xorps %xmm2, %xmm2<br class="">
> +; SSE41-NEXT: je LBB51_2<br class="">
> +; SSE41-NEXT: ## %bb.1:<br class="">
> +; SSE41-NEXT: xorps %xmm2, %xmm2<br class="">
> +; SSE41-NEXT: roundss $9, %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: LBB51_2:<br class="">
> +; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]<br class="">
> +; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_maskz_ss:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: testb $1, %dil<br class="">
> +; AVX-NEXT: vxorps %xmm2, %xmm2, %xmm2<br class="">
> +; AVX-NEXT: je LBB51_2<br class="">
> +; AVX-NEXT: ## %bb.1:<br class="">
> +; AVX-NEXT: vroundss $9, %xmm0, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: LBB51_2:<br class="">
> +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0],xmm1[1,2,3]<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_maskz_ss:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: kmovw %edi, %k1<br class="">
> +; AVX512-NEXT: vrndscaless $1, %xmm0, %xmm1, %xmm0 {%k1} {z}<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %mask = and i8 %k, 1<br class="">
> + %nmask = icmp eq i8 %mask, 0<br class="">
> + %s = extractelement <4 x float> %x, i64 0<br class="">
> + %call = tail call float @llvm.floor.f32(float %s)<br class="">
> + %low = select i1 %nmask, float zeroinitializer, float %call<br class="">
> + %res = insertelement <4 x float> %y, float %low, i64 0<br class="">
> + ret <4 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <2 x double> @floor_mask_sd(<2 x double> %x, <2 x double> %y, <2 x double> %w, i8 %k) nounwind {<br class="">
> +; SSE41-LABEL: floor_mask_sd:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: testb $1, %dil<br class="">
> +; SSE41-NEXT: je LBB52_2<br class="">
> +; SSE41-NEXT: ## %bb.1:<br class="">
> +; SSE41-NEXT: xorps %xmm2, %xmm2<br class="">
> +; SSE41-NEXT: roundsd $9, %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: LBB52_2:<br class="">
> +; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm2[0],xmm1[1]<br class="">
> +; SSE41-NEXT: movapd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_mask_sd:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: testb $1, %dil<br class="">
> +; AVX-NEXT: je LBB52_2<br class="">
> +; AVX-NEXT: ## %bb.1:<br class="">
> +; AVX-NEXT: vroundsd $9, %xmm0, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: LBB52_2:<br class="">
> +; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm2[0],xmm1[1]<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_mask_sd:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: kmovw %edi, %k1<br class="">
> +; AVX512-NEXT: vrndscalesd $1, %xmm0, %xmm1, %xmm2 {%k1}<br class="">
> +; AVX512-NEXT: vmovapd %xmm2, %xmm0<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %mask = and i8 %k, 1<br class="">
> + %nmask = icmp eq i8 %mask, 0<br class="">
> + %s = extractelement <2 x double> %x, i64 0<br class="">
> + %call = tail call double @llvm.floor.f64(double %s)<br class="">
> + %dst = extractelement <2 x double> %w, i64 0<br class="">
> + %low = select i1 %nmask, double %dst, double %call<br class="">
> + %res = insertelement <2 x double> %y, double %low, i64 0<br class="">
> + ret <2 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <2 x double> @floor_maskz_sd(<2 x double> %x, <2 x double> %y, i8 %k) nounwind {<br class="">
> +; SSE41-LABEL: floor_maskz_sd:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: testb $1, %dil<br class="">
> +; SSE41-NEXT: xorpd %xmm2, %xmm2<br class="">
> +; SSE41-NEXT: je LBB53_2<br class="">
> +; SSE41-NEXT: ## %bb.1:<br class="">
> +; SSE41-NEXT: xorps %xmm2, %xmm2<br class="">
> +; SSE41-NEXT: roundsd $9, %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: LBB53_2:<br class="">
> +; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm2[0],xmm1[1]<br class="">
> +; SSE41-NEXT: movapd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_maskz_sd:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: testb $1, %dil<br class="">
> +; AVX-NEXT: vxorpd %xmm2, %xmm2, %xmm2<br class="">
> +; AVX-NEXT: je LBB53_2<br class="">
> +; AVX-NEXT: ## %bb.1:<br class="">
> +; AVX-NEXT: vroundsd $9, %xmm0, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: LBB53_2:<br class="">
> +; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm2[0],xmm1[1]<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_maskz_sd:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: kmovw %edi, %k1<br class="">
> +; AVX512-NEXT: vrndscalesd $1, %xmm0, %xmm1, %xmm0 {%k1} {z}<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %mask = and i8 %k, 1<br class="">
> + %nmask = icmp eq i8 %mask, 0<br class="">
> + %s = extractelement <2 x double> %x, i64 0<br class="">
> + %call = tail call double @llvm.floor.f64(double %s)<br class="">
> + %low = select i1 %nmask, double zeroinitializer, double %call<br class="">
> + %res = insertelement <2 x double> %y, double %low, i64 0<br class="">
> + ret <2 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <4 x float> @floor_mask_ss_trunc(<4 x float> %x, <4 x float> %y, <4 x float> %w, i16 %k) nounwind {<br class="">
> +; SSE41-LABEL: floor_mask_ss_trunc:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: testb $1, %dil<br class="">
> +; SSE41-NEXT: je LBB54_2<br class="">
> +; SSE41-NEXT: ## %bb.1:<br class="">
> +; SSE41-NEXT: xorps %xmm2, %xmm2<br class="">
> +; SSE41-NEXT: roundss $9, %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: LBB54_2:<br class="">
> +; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]<br class="">
> +; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_mask_ss_trunc:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: testb $1, %dil<br class="">
> +; AVX-NEXT: je LBB54_2<br class="">
> +; AVX-NEXT: ## %bb.1:<br class="">
> +; AVX-NEXT: vroundss $9, %xmm0, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: LBB54_2:<br class="">
> +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0],xmm1[1,2,3]<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_mask_ss_trunc:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: kmovw %edi, %k1<br class="">
> +; AVX512-NEXT: vrndscaless $1, %xmm0, %xmm1, %xmm2 {%k1}<br class="">
> +; AVX512-NEXT: vmovaps %xmm2, %xmm0<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %mask = trunc i16 %k to i1<br class="">
> + %s = extractelement <4 x float> %x, i64 0<br class="">
> + %call = tail call float @llvm.floor.f32(float %s)<br class="">
> + %dst = extractelement <4 x float> %w, i64 0<br class="">
> + %low = select i1 %mask, float %call, float %dst<br class="">
> + %res = insertelement <4 x float> %y, float %low, i64 0<br class="">
> + ret <4 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <4 x float> @floor_maskz_ss_trunc(<4 x float> %x, <4 x float> %y, i16 %k) nounwind {<br class="">
> +; SSE41-LABEL: floor_maskz_ss_trunc:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: testb $1, %dil<br class="">
> +; SSE41-NEXT: jne LBB55_1<br class="">
> +; SSE41-NEXT: ## %bb.2:<br class="">
> +; SSE41-NEXT: xorps %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: jmp LBB55_3<br class="">
> +; SSE41-NEXT: LBB55_1:<br class="">
> +; SSE41-NEXT: roundss $9, %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: LBB55_3:<br class="">
> +; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]<br class="">
> +; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_maskz_ss_trunc:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: testb $1, %dil<br class="">
> +; AVX-NEXT: jne LBB55_1<br class="">
> +; AVX-NEXT: ## %bb.2:<br class="">
> +; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]<br class="">
> +; AVX-NEXT: retq<br class="">
> +; AVX-NEXT: LBB55_1:<br class="">
> +; AVX-NEXT: vroundss $9, %xmm0, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_maskz_ss_trunc:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: kmovw %edi, %k1<br class="">
> +; AVX512-NEXT: vrndscaless $1, %xmm0, %xmm1, %xmm0 {%k1} {z}<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %mask = trunc i16 %k to i1<br class="">
> + %s = extractelement <4 x float> %x, i64 0<br class="">
> + %call = tail call float @llvm.floor.f32(float %s)<br class="">
> + %low = select i1 %mask, float %call, float zeroinitializer<br class="">
> + %res = insertelement <4 x float> %y, float %low, i64 0<br class="">
> + ret <4 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <2 x double> @floor_mask_sd_trunc(<2 x double> %x, <2 x double> %y, <2 x double> %w, i16 %k) nounwind {<br class="">
> +; SSE41-LABEL: floor_mask_sd_trunc:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: testb $1, %dil<br class="">
> +; SSE41-NEXT: je LBB56_2<br class="">
> +; SSE41-NEXT: ## %bb.1:<br class="">
> +; SSE41-NEXT: xorps %xmm2, %xmm2<br class="">
> +; SSE41-NEXT: roundsd $9, %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: LBB56_2:<br class="">
> +; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm2[0],xmm1[1]<br class="">
> +; SSE41-NEXT: movapd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_mask_sd_trunc:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: testb $1, %dil<br class="">
> +; AVX-NEXT: je LBB56_2<br class="">
> +; AVX-NEXT: ## %bb.1:<br class="">
> +; AVX-NEXT: vroundsd $9, %xmm0, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: LBB56_2:<br class="">
> +; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm2[0],xmm1[1]<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_mask_sd_trunc:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: kmovw %edi, %k1<br class="">
> +; AVX512-NEXT: vrndscalesd $1, %xmm0, %xmm1, %xmm2 {%k1}<br class="">
> +; AVX512-NEXT: vmovapd %xmm2, %xmm0<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %mask = trunc i16 %k to i1<br class="">
> + %s = extractelement <2 x double> %x, i64 0<br class="">
> + %call = tail call double @llvm.floor.f64(double %s)<br class="">
> + %dst = extractelement <2 x double> %w, i64 0<br class="">
> + %low = select i1 %mask, double %call, double %dst<br class="">
> + %res = insertelement <2 x double> %y, double %low, i64 0<br class="">
> + ret <2 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <2 x double> @floor_maskz_sd_trunc(<2 x double> %x, <2 x double> %y, i16 %k) nounwind {<br class="">
> +; SSE41-LABEL: floor_maskz_sd_trunc:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: testb $1, %dil<br class="">
> +; SSE41-NEXT: jne LBB57_1<br class="">
> +; SSE41-NEXT: ## %bb.2:<br class="">
> +; SSE41-NEXT: xorpd %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: jmp LBB57_3<br class="">
> +; SSE41-NEXT: LBB57_1:<br class="">
> +; SSE41-NEXT: roundsd $9, %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: LBB57_3:<br class="">
> +; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm0[0],xmm1[1]<br class="">
> +; SSE41-NEXT: movapd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_maskz_sd_trunc:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: testb $1, %dil<br class="">
> +; AVX-NEXT: jne LBB57_1<br class="">
> +; AVX-NEXT: ## %bb.2:<br class="">
> +; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]<br class="">
> +; AVX-NEXT: retq<br class="">
> +; AVX-NEXT: LBB57_1:<br class="">
> +; AVX-NEXT: vroundsd $9, %xmm0, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: floor_maskz_sd_trunc:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: kmovw %edi, %k1<br class="">
> +; AVX512-NEXT: vrndscalesd $1, %xmm0, %xmm1, %xmm0 {%k1} {z}<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %mask = trunc i16 %k to i1<br class="">
> + %s = extractelement <2 x double> %x, i64 0<br class="">
> + %call = tail call double @llvm.floor.f64(double %s)<br class="">
> + %low = select i1 %mask, double %call, double zeroinitializer<br class="">
> + %res = insertelement <2 x double> %y, double %low, i64 0<br class="">
> + ret <2 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <4 x float> @floor_mask_ss_mask8(<4 x float> %x, <4 x float> %y, <4 x float> %w) nounwind {<br class="">
> +; SSE41-LABEL: floor_mask_ss_mask8:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: movaps %xmm0, %xmm3<br class="">
> +; SSE41-NEXT: cmpeqps %xmm1, %xmm3<br class="">
> +; SSE41-NEXT: pextrb $0, %xmm3, %eax<br class="">
> +; SSE41-NEXT: testb $1, %al<br class="">
> +; SSE41-NEXT: je LBB58_2<br class="">
> +; SSE41-NEXT: ## %bb.1:<br class="">
> +; SSE41-NEXT: xorps %xmm2, %xmm2<br class="">
> +; SSE41-NEXT: roundss $9, %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: LBB58_2:<br class="">
> +; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]<br class="">
> +; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_mask_ss_mask8:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm3<br class="">
> +; AVX-NEXT: vpextrb $0, %xmm3, %eax<br class="">
> +; AVX-NEXT: testb $1, %al<br class="">
> +; AVX-NEXT: je LBB58_2<br class="">
> +; AVX-NEXT: ## %bb.1:<br class="">
> +; AVX-NEXT: vroundss $9, %xmm0, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: LBB58_2:<br class="">
> +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0],xmm1[1,2,3]<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: floor_mask_ss_mask8:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqps %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vrndscaless $1, %xmm0, %xmm1, %xmm2 {%k1}<br class="">
> +; AVX512F-NEXT: vmovaps %xmm2, %xmm0<br class="">
> +; AVX512F-NEXT: vzeroupper<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: floor_mask_ss_mask8:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqps %xmm1, %xmm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscaless $1, %xmm0, %xmm1, %xmm2 {%k1}<br class="">
> +; AVX512VL-NEXT: vmovaps %xmm2, %xmm0<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %mask1 = fcmp oeq <4 x float> %x, %y<br class="">
> + %mask = extractelement <4 x i1> %mask1, i64 0<br class="">
> + %s = extractelement <4 x float> %x, i64 0<br class="">
> + %call = tail call float @llvm.floor.f32(float %s)<br class="">
> + %dst = extractelement <4 x float> %w, i64 0<br class="">
> + %low = select i1 %mask, float %call, float %dst<br class="">
> + %res = insertelement <4 x float> %y, float %low, i64 0<br class="">
> + ret <4 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <4 x float> @floor_maskz_ss_mask8(<4 x float> %x, <4 x float> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_maskz_ss_mask8:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: movaps %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: cmpeqps %xmm1, %xmm2<br class="">
> +; SSE41-NEXT: pextrb $0, %xmm2, %eax<br class="">
> +; SSE41-NEXT: testb $1, %al<br class="">
> +; SSE41-NEXT: jne LBB59_1<br class="">
> +; SSE41-NEXT: ## %bb.2:<br class="">
> +; SSE41-NEXT: xorps %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: jmp LBB59_3<br class="">
> +; SSE41-NEXT: LBB59_1:<br class="">
> +; SSE41-NEXT: roundss $9, %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: LBB59_3:<br class="">
> +; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]<br class="">
> +; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_maskz_ss_mask8:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: vpextrb $0, %xmm2, %eax<br class="">
> +; AVX-NEXT: testb $1, %al<br class="">
> +; AVX-NEXT: jne LBB59_1<br class="">
> +; AVX-NEXT: ## %bb.2:<br class="">
> +; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]<br class="">
> +; AVX-NEXT: retq<br class="">
> +; AVX-NEXT: LBB59_1:<br class="">
> +; AVX-NEXT: vroundss $9, %xmm0, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: floor_maskz_ss_mask8:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqps %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vrndscaless $1, %xmm0, %xmm1, %xmm0 {%k1} {z}<br class="">
> +; AVX512F-NEXT: vzeroupper<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: floor_maskz_ss_mask8:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqps %xmm1, %xmm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscaless $1, %xmm0, %xmm1, %xmm0 {%k1} {z}<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %mask1 = fcmp oeq <4 x float> %x, %y<br class="">
> + %mask = extractelement <4 x i1> %mask1, i64 0<br class="">
> + %s = extractelement <4 x float> %x, i64 0<br class="">
> + %call = tail call float @llvm.floor.f32(float %s)<br class="">
> + %low = select i1 %mask, float %call, float zeroinitializer<br class="">
> + %res = insertelement <4 x float> %y, float %low, i64 0<br class="">
> + ret <4 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <2 x double> @floor_mask_sd_mask8(<2 x double> %x, <2 x double> %y, <2 x double> %w) nounwind {<br class="">
> +; SSE41-LABEL: floor_mask_sd_mask8:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: movapd %xmm0, %xmm3<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm1, %xmm3<br class="">
> +; SSE41-NEXT: pextrb $0, %xmm3, %eax<br class="">
> +; SSE41-NEXT: testb $1, %al<br class="">
> +; SSE41-NEXT: je LBB60_2<br class="">
> +; SSE41-NEXT: ## %bb.1:<br class="">
> +; SSE41-NEXT: xorps %xmm2, %xmm2<br class="">
> +; SSE41-NEXT: roundsd $9, %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: LBB60_2:<br class="">
> +; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm2[0],xmm1[1]<br class="">
> +; SSE41-NEXT: movapd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_mask_sd_mask8:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm3<br class="">
> +; AVX-NEXT: vpextrb $0, %xmm3, %eax<br class="">
> +; AVX-NEXT: testb $1, %al<br class="">
> +; AVX-NEXT: je LBB60_2<br class="">
> +; AVX-NEXT: ## %bb.1:<br class="">
> +; AVX-NEXT: vroundsd $9, %xmm0, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: LBB60_2:<br class="">
> +; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm2[0],xmm1[1]<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: floor_mask_sd_mask8:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqpd %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vrndscalesd $1, %xmm0, %xmm1, %xmm2 {%k1}<br class="">
> +; AVX512F-NEXT: vmovapd %xmm2, %xmm0<br class="">
> +; AVX512F-NEXT: vzeroupper<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: floor_mask_sd_mask8:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqpd %xmm1, %xmm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscalesd $1, %xmm0, %xmm1, %xmm2 {%k1}<br class="">
> +; AVX512VL-NEXT: vmovapd %xmm2, %xmm0<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %mask1 = fcmp oeq <2 x double> %x, %y<br class="">
> + %mask = extractelement <2 x i1> %mask1, i64 0<br class="">
> + %s = extractelement <2 x double> %x, i64 0<br class="">
> + %call = tail call double @llvm.floor.f64(double %s)<br class="">
> + %dst = extractelement <2 x double> %w, i64 0<br class="">
> + %low = select i1 %mask, double %call, double %dst<br class="">
> + %res = insertelement <2 x double> %y, double %low, i64 0<br class="">
> + ret <2 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <2 x double> @floor_maskz_sd_mask8(<2 x double> %x, <2 x double> %y) nounwind {<br class="">
> +; SSE41-LABEL: floor_maskz_sd_mask8:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: movapd %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm1, %xmm2<br class="">
> +; SSE41-NEXT: pextrb $0, %xmm2, %eax<br class="">
> +; SSE41-NEXT: testb $1, %al<br class="">
> +; SSE41-NEXT: jne LBB61_1<br class="">
> +; SSE41-NEXT: ## %bb.2:<br class="">
> +; SSE41-NEXT: xorpd %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: jmp LBB61_3<br class="">
> +; SSE41-NEXT: LBB61_1:<br class="">
> +; SSE41-NEXT: roundsd $9, %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: LBB61_3:<br class="">
> +; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm0[0],xmm1[1]<br class="">
> +; SSE41-NEXT: movapd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: floor_maskz_sd_mask8:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: vpextrb $0, %xmm2, %eax<br class="">
> +; AVX-NEXT: testb $1, %al<br class="">
> +; AVX-NEXT: jne LBB61_1<br class="">
> +; AVX-NEXT: ## %bb.2:<br class="">
> +; AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]<br class="">
> +; AVX-NEXT: retq<br class="">
> +; AVX-NEXT: LBB61_1:<br class="">
> +; AVX-NEXT: vroundsd $9, %xmm0, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: floor_maskz_sd_mask8:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqpd %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vrndscalesd $1, %xmm0, %xmm1, %xmm0 {%k1} {z}<br class="">
> +; AVX512F-NEXT: vzeroupper<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: floor_maskz_sd_mask8:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqpd %xmm1, %xmm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscalesd $1, %xmm0, %xmm1, %xmm0 {%k1} {z}<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %mask1 = fcmp oeq <2 x double> %x, %y<br class="">
> + %mask = extractelement <2 x i1> %mask1, i64 0<br class="">
> + %s = extractelement <2 x double> %x, i64 0<br class="">
> + %call = tail call double @llvm.floor.f64(double %s)<br class="">
> + %low = select i1 %mask, double %call, double zeroinitializer<br class="">
> + %res = insertelement <2 x double> %y, double %low, i64 0<br class="">
> + ret <2 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <4 x float> @ceil_ss(<4 x float> %x, <4 x float> %y) nounwind {<br class="">
> +; SSE41-LABEL: ceil_ss:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundss $2, %xmm0, %xmm1<br class="">
> +; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: ceil_ss:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vroundss $2, %xmm0, %xmm1, %xmm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: ceil_ss:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: vroundss $2, %xmm0, %xmm1, %xmm0<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %s = extractelement <4 x float> %x, i32 0<br class="">
> + %call = call float @llvm.ceil.f32(float %s)<br class="">
> + %res = insertelement <4 x float> %y, float %call, i32 0<br class="">
> + ret <4 x float> %res<br class="">
> +}<br class="">
> +declare float @llvm.ceil.f32(float %s)<br class="">
> +<br class="">
> +define <2 x double> @ceil_sd(<2 x double> %x, <2 x double> %y) nounwind {<br class="">
> +; SSE41-LABEL: ceil_sd:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundsd $2, %xmm0, %xmm1<br class="">
> +; SSE41-NEXT: movapd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: ceil_sd:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vroundsd $2, %xmm0, %xmm1, %xmm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512-LABEL: ceil_sd:<br class="">
> +; AVX512: ## %bb.0:<br class="">
> +; AVX512-NEXT: vroundsd $2, %xmm0, %xmm1, %xmm0<br class="">
> +; AVX512-NEXT: retq<br class="">
> + %s = extractelement <2 x double> %x, i32 0<br class="">
> + %call = call double @llvm.ceil.f64(double %s)<br class="">
> + %res = insertelement <2 x double> %y, double %call, i32 0<br class="">
> + ret <2 x double> %res<br class="">
> +}<br class="">
> +declare double @llvm.ceil.f64(double %s)<br class="">
> +<br class="">
> +define <4 x float> @ceil_mask_128_ps(<4 x float> %x, <4 x float> %y) nounwind {<br class="">
> +; SSE41-LABEL: ceil_mask_128_ps:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundps $10, %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: cmpeqps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm1<br class="">
> +; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: ceil_mask_128_ps:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: vroundps $10, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: ceil_mask_128_ps:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqps %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundps $10, %xmm0, %xmm0<br class="">
> +; AVX512F-NEXT: vblendmps %zmm0, %zmm1, %zmm0 {%k1}<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: vzeroupper<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: ceil_mask_128_ps:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqps %xmm1, %xmm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscaleps $10, %xmm0, %xmm1 {%k1}<br class="">
> +; AVX512VL-NEXT: vmovaps %xmm1, %xmm0<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <4 x float> %x, %y<br class="">
> + %call = call <4 x float> @llvm.ceil.v4f32(<4 x float> %x)<br class="">
> + %res = select <4 x i1> %k, <4 x float> %call, <4 x float> %y<br class="">
> + ret <4 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <4 x float> @ceil_maskz_128_ps(<4 x float> %x, <4 x float> %y) nounwind {<br class="">
> +; SSE41-LABEL: ceil_maskz_128_ps:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: cmpeqps %xmm0, %xmm1<br class="">
> +; SSE41-NEXT: roundps $10, %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: andps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: ceil_maskz_128_ps:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm1<br class="">
> +; AVX-NEXT: vroundps $10, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vandps %xmm0, %xmm1, %xmm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: ceil_maskz_128_ps:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqps %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundps $10, %xmm0, %xmm0<br class="">
> +; AVX512F-NEXT: vmovaps %zmm0, %zmm0 {%k1} {z}<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: vzeroupper<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: ceil_maskz_128_ps:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqps %xmm1, %xmm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscaleps $10, %xmm0, %xmm0 {%k1} {z}<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <4 x float> %x, %y<br class="">
> + %call = call <4 x float> @llvm.ceil.v4f32(<4 x float> %x)<br class="">
> + %res = select <4 x i1> %k, <4 x float> %call, <4 x float> zeroinitializer<br class="">
> + ret <4 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <2 x double> @ceil_mask_128_pd(<2 x double> %x, <2 x double> %y) nounwind {<br class="">
> +; SSE41-LABEL: ceil_mask_128_pd:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundpd $10, %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1<br class="">
> +; SSE41-NEXT: movapd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: ceil_mask_128_pd:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm2<br class="">
> +; AVX-NEXT: vroundpd $10, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: ceil_mask_128_pd:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqpd %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundpd $10, %xmm0, %xmm0<br class="">
> +; AVX512F-NEXT: vblendmpd %zmm0, %zmm1, %zmm0 {%k1}<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: vzeroupper<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: ceil_mask_128_pd:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqpd %xmm1, %xmm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscalepd $10, %xmm0, %xmm1 {%k1}<br class="">
> +; AVX512VL-NEXT: vmovapd %xmm1, %xmm0<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <2 x double> %x, %y<br class="">
> + %call = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x)<br class="">
> + %res = select <2 x i1> %k, <2 x double> %call, <2 x double> %y<br class="">
> + ret <2 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <2 x double> @ceil_maskz_128_pd(<2 x double> %x, <2 x double> %y) nounwind {<br class="">
> +; SSE41-LABEL: ceil_maskz_128_pd:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm0, %xmm1<br class="">
> +; SSE41-NEXT: roundpd $10, %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: andpd %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: ceil_maskz_128_pd:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm1<br class="">
> +; AVX-NEXT: vroundpd $10, %xmm0, %xmm0<br class="">
> +; AVX-NEXT: vandpd %xmm0, %xmm1, %xmm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: ceil_maskz_128_pd:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqpd %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundpd $10, %xmm0, %xmm0<br class="">
> +; AVX512F-NEXT: vmovapd %zmm0, %zmm0 {%k1} {z}<br class="">
> +; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: vzeroupper<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: ceil_maskz_128_pd:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqpd %xmm1, %xmm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscalepd $10, %xmm0, %xmm0 {%k1} {z}<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <2 x double> %x, %y<br class="">
> + %call = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x)<br class="">
> + %res = select <2 x i1> %k, <2 x double> %call, <2 x double> zeroinitializer<br class="">
> + ret <2 x double> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <8 x float> @ceil_mask_256_ps(<8 x float> %x, <8 x float> %y) nounwind {<br class="">
> +; SSE41-LABEL: ceil_mask_256_ps:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundps $10, %xmm1, %xmm4<br class="">
> +; SSE41-NEXT: cmpeqps %xmm3, %xmm1<br class="">
> +; SSE41-NEXT: roundps $10, %xmm0, %xmm5<br class="">
> +; SSE41-NEXT: cmpeqps %xmm2, %xmm0<br class="">
> +; SSE41-NEXT: blendvps %xmm0, %xmm5, %xmm2<br class="">
> +; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
> +; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm3<br class="">
> +; SSE41-NEXT: movaps %xmm2, %xmm0<br class="">
> +; SSE41-NEXT: movaps %xmm3, %xmm1<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: ceil_mask_256_ps:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqps %ymm1, %ymm0, %ymm2<br class="">
> +; AVX-NEXT: vroundps $10, %ymm0, %ymm0<br class="">
> +; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: ceil_mask_256_ps:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm1 killed $ymm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqps %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundps $10, %ymm0, %ymm0<br class="">
> +; AVX512F-NEXT: vblendmps %zmm0, %zmm1, %zmm0 {%k1}<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: ceil_mask_256_ps:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqps %ymm1, %ymm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscaleps $10, %ymm0, %ymm1 {%k1}<br class="">
> +; AVX512VL-NEXT: vmovaps %ymm1, %ymm0<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <8 x float> %x, %y<br class="">
> + %call = call <8 x float> @llvm.ceil.v8f32(<8 x float> %x)<br class="">
> + %res = select <8 x i1> %k, <8 x float> %call, <8 x float> %y<br class="">
> + ret <8 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <8 x float> @ceil_maskz_256_ps(<8 x float> %x, <8 x float> %y) nounwind {<br class="">
> +; SSE41-LABEL: ceil_maskz_256_ps:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: cmpeqps %xmm1, %xmm3<br class="">
> +; SSE41-NEXT: cmpeqps %xmm0, %xmm2<br class="">
> +; SSE41-NEXT: roundps $10, %xmm1, %xmm1<br class="">
> +; SSE41-NEXT: andps %xmm3, %xmm1<br class="">
> +; SSE41-NEXT: roundps $10, %xmm0, %xmm0<br class="">
> +; SSE41-NEXT: andps %xmm2, %xmm0<br class="">
> +; SSE41-NEXT: retq<br class="">
> +;<br class="">
> +; AVX-LABEL: ceil_maskz_256_ps:<br class="">
> +; AVX: ## %bb.0:<br class="">
> +; AVX-NEXT: vcmpeqps %ymm1, %ymm0, %ymm1<br class="">
> +; AVX-NEXT: vroundps $10, %ymm0, %ymm0<br class="">
> +; AVX-NEXT: vandps %ymm0, %ymm1, %ymm0<br class="">
> +; AVX-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512F-LABEL: ceil_maskz_256_ps:<br class="">
> +; AVX512F: ## %bb.0:<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm1 killed $ymm1 def $zmm1<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 def $zmm0<br class="">
> +; AVX512F-NEXT: vcmpeqps %zmm1, %zmm0, %k1<br class="">
> +; AVX512F-NEXT: vroundps $10, %ymm0, %ymm0<br class="">
> +; AVX512F-NEXT: vmovaps %zmm0, %zmm0 {%k1} {z}<br class="">
> +; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 killed $zmm0<br class="">
> +; AVX512F-NEXT: retq<br class="">
> +;<br class="">
> +; AVX512VL-LABEL: ceil_maskz_256_ps:<br class="">
> +; AVX512VL: ## %bb.0:<br class="">
> +; AVX512VL-NEXT: vcmpeqps %ymm1, %ymm0, %k1<br class="">
> +; AVX512VL-NEXT: vrndscaleps $10, %ymm0, %ymm0 {%k1} {z}<br class="">
> +; AVX512VL-NEXT: retq<br class="">
> + %k = fcmp oeq <8 x float> %x, %y<br class="">
> + %call = call <8 x float> @llvm.ceil.v8f32(<8 x float> %x)<br class="">
> + %res = select <8 x i1> %k, <8 x float> %call, <8 x float> zeroinitializer<br class="">
> + ret <8 x float> %res<br class="">
> +}<br class="">
> +<br class="">
> +define <4 x double> @ceil_mask_256_pd(<4 x double> %x, <4 x double> %y) nounwind {<br class="">
> +; SSE41-LABEL: ceil_mask_256_pd:<br class="">
> +; SSE41: ## %bb.0:<br class="">
> +; SSE41-NEXT: roundpd $10, %xmm1, %xmm4<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm3, %xmm1<br class="">
> +; SSE41-NEXT: roundpd $10, %xmm0, %xmm5<br class="">
> +; SSE41-NEXT: cmpeqpd %xmm2, %xmm0<br class="">
> +; SSE41-NEXT: blendvpd %xmm0, %xmm5, %xmm2<br class="">
> +; SSE41-NEXT: movapd %xmm1, %xmm0<br class="">
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-- <br class="">
<div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature">~Craig</div>
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</blockquote>
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