<div dir="auto"><div><div class="gmail_quote"><div dir="ltr">On Tue, 26 Jun 2018, 11:44 Brendon Cahoon via llvm-commits, <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: bcahoon<br>
Date: Tue Jun 26 11:44:05 2018<br>
New Revision: 335641<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=335641&view=rev" rel="noreferrer noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=335641&view=rev</a><br>
Log:<br>
[Hexagon] Add a "generic" cpu<br>
<br>
Add the generic processor for Hexagon so that it can be used<br>
with 3rd party programs that create a back-end with the<br>
"generic" CPU. This patch also enables the JIT for Hexagon.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D48571" rel="noreferrer noreferrer" target="_blank">https://reviews.llvm.org/D48571</a></blockquote></div></div><div dir="auto"><br></div><div dir="auto">Wrong differential revision?</div><div dir="auto"><br></div><div dir="auto"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
<br>
Added:<br>
    llvm/trunk/test/CodeGen/Hexagon/generic-cpu.ll<br>
Modified:<br>
    llvm/trunk/lib/Target/Hexagon/Hexagon.td<br>
    llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp<br>
    llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp<br>
    llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=335641&r1=335640&r2=335641&view=diff" rel="noreferrer noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=335641&r1=335640&r2=335641&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Tue Jun 26 11:44:05 2018<br>
@@ -322,6 +322,10 @@ class Proc<string Name, SchedMachineMode<br>
            list<SubtargetFeature> Features><br>
  : ProcessorModel<Name, Model, Features>;<br>
<br>
+def : Proc<"generic", HexagonModelV60,<br>
+           [ArchV4, ArchV5, ArchV55, ArchV60,<br>
+            FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,<br>
+            FeaturePackets, FeatureSmallData]>;<br>
 def : Proc<"hexagonv4",  HexagonModelV4,<br>
            [ArchV4,<br>
             FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=335641&r1=335640&r2=335641&view=diff" rel="noreferrer noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=335641&r1=335640&r2=335641&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Tue Jun 26 11:44:05 2018<br>
@@ -92,6 +92,7 @@ HexagonSubtarget::HexagonSubtarget(const<br>
 HexagonSubtarget &<br>
 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {<br>
   static std::map<StringRef, Hexagon::ArchEnum> CpuTable{<br>
+      {"generic", Hexagon::ArchEnum::V60},<br>
       {"hexagonv4", Hexagon::ArchEnum::V4},<br>
       {"hexagonv5", Hexagon::ArchEnum::V5},<br>
       {"hexagonv55", Hexagon::ArchEnum::V55},<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=335641&r1=335640&r2=335641&view=diff" rel="noreferrer noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=335641&r1=335640&r2=335641&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp Tue Jun 26 11:44:05 2018<br>
@@ -309,6 +309,7 @@ static bool isCPUValid(std::string CPU)<br>
 {<br>
   std::vector<std::string> table<br>
   {<br>
+    "generic",<br>
     "hexagonv4",<br>
     "hexagonv5",<br>
     "hexagonv55",<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp?rev=335641&r1=335640&r2=335641&view=diff" rel="noreferrer noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp?rev=335641&r1=335640&r2=335641&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp Tue Jun 26 11:44:05 2018<br>
@@ -18,6 +18,6 @@ Target &llvm::getTheHexagonTarget() {<br>
 }<br>
<br>
 extern "C" void LLVMInitializeHexagonTargetInfo() {<br>
-  RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(<br>
+  RegisterTarget<Triple::hexagon, /*HasJIT=*/true> X(<br>
       getTheHexagonTarget(), "hexagon", "Hexagon", "Hexagon");<br>
 }<br>
<br>
Added: llvm/trunk/test/CodeGen/Hexagon/generic-cpu.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/generic-cpu.ll?rev=335641&view=auto" rel="noreferrer noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/generic-cpu.ll?rev=335641&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/generic-cpu.ll (added)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/generic-cpu.ll Tue Jun 26 11:44:05 2018<br>
@@ -0,0 +1,7 @@<br>
+; RUN: llc -mtriple=hexagon-unknown-elf -mcpu=generic < %s | FileCheck %s<br>
+<br>
+; CHECK-NOT: invalid CPU<br>
+<br>
+define i32 @test(i32 %a) {<br>
+  ret i32 0<br>
+}<br>
<br>
<br>
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</blockquote></div></div></div>