<div dir="ltr">I've filed <a href="https://bugs.llvm.org/show_bug.cgi?id=37929">https://bugs.llvm.org/show_bug.cgi?id=37929</a> for the JumpThreading compile slowness and merged <a href="https://reviews.llvm.org/D48566">https://reviews.llvm.org/D48566</a> to inhibit UBSan instrumentation of these functions for now. The compile seems to be well under the timeout duration now.</div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jun 25, 2018 at 10:43 AM, Vlad Tsyrklevich <span dir="ltr"><<a href="mailto:vlad@tsyrklevich.net" target="_blank">vlad@tsyrklevich.net</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">I took a look at this again since we're still seeing occasional build timeouts on the UBSan bot. I recorded the # of basic blocks on entry to the jump threading pass for printAliasInstr() with different build settings:<div>-O1: ~5.5k BBs</div><div>-O2: ~25k BBs</div><div>-O3: ~25k BBs</div><div>-O3 + sanitizers: ~54k BBs</div><div><br></div><div>The blow-up between -O1 and -O2 is due to the inliner inlining MCInst::getOperand() and MCRegisterInfo::getRegClass() many times. By adding a CFGSimplificationPass before the JumpThreadingPass runs, the number of BBs is brought down to:</div><div>-O2 : ~15k BBs</div><div>-O3 -fsanitize: ~42k BBs</div><div><br></div><div>This corresponds with ~30s/2m local build runtimes, approximately a ~4x improvement. Not sure if this change is worth pursuing given that it may only benefit compile times for huge functions.</div><div><div class="h5"><div><br></div><div class="gmail_quote"><div dir="ltr">On Tue, Jun 19, 2018 at 5:09 PM Vlad Tsyrklevich <<a href="mailto:vlad@tsyrklevich.net" target="_blank">vlad@tsyrklevich.net</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hi Sander, this change has started causing intermittent build timeouts on the ubsan builder: <a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-ubsan" target="_blank">http://lab.llvm.org:<wbr>8011/builders/sanitizer-x86_<wbr>64-linux-bootstrap-ubsan</a><div><br></div><div>I've tracked it down to this change, before this change AArch64InstPrinter.cpp takes ~95s to build with -O3 locally, with this change it takes 120s. With sanitizers enabled, this increase is multiplied by 5-15x, and the builder in the cloud is even slower. Taking a brief look at what's happening in the compiler, it looks like most of the time is spent recomputing dominator trees in the JumpThreading pass for llvm::<wbr>AArch64AppleInstPrinter::<wbr>printAliasInstr(). Looking at the IR for printAliasInstr(), it contains a switch statement with many targets and every statement in the switch is inlining multiple functions (like MCInst::getOperand and MCRegisterInfo::getRegClass) multiple times significantly multiplying the number of basic blocks in the function.</div><div><br></div><div>I've reverted this change and r334983 for now in r335085.</div></div><div dir="ltr"><div><br></div><div class="gmail_quote"><div dir="ltr">On Mon, Jun 18, 2018 at 1:54 PM Sander de Smalen via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: s.desmalen<br>
Date: Mon Jun 18 13:50:33 2018<br>
New Revision: 334980<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=334980&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=334980&view=rev</a><br>
Log:<br>
[AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions.<br>
<br>
The variants added by this patch are:<br>
- SQINC     signed increment, e.g. sqinc x0, w0, all, mul #4<br>
- SQDEC     signed decrement, e.g. sqdec x0, w0, all, mul #4<br>
- UQINC   unsigned increment, e.g. uqinc w0, all, mul #4<br>
- UQDEC   unsigned decrement, e.g. uqdec w0, all, mul #4<br>
<br>
This patch includes asmparser changes to parse a GPR64 as a GPR32 in<br>
order to satisfy the constraint check:<br>
  x0 == GPR64(w0)<br>
in:<br>
  sqinc x0, w0, all, mul #4<br>
         ^___^ (must match)<br>
<br>
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar<br>
<br>
Reviewed By: fhahn<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D47716" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D47716</a><br>
<br>
<br>
Modified:<br>
    llvm/trunk/lib/Target/AArch64/<wbr>AArch64InstrFormats.td<br>
    llvm/trunk/lib/Target/AArch64/<wbr>AArch64SVEInstrInfo.td<br>
    llvm/trunk/lib/Target/AArch64/<wbr>AsmParser/AArch64AsmParser.cpp<br>
    llvm/trunk/lib/Target/AArch64/<wbr>InstPrinter/<wbr>AArch64InstPrinter.cpp<br>
    llvm/trunk/lib/Target/AArch64/<wbr>InstPrinter/<wbr>AArch64InstPrinter.h<br>
    llvm/trunk/lib/Target/AArch64/<wbr>SVEInstrFormats.td<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecb-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecb.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecd-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecd.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdech-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdech.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecw-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecw.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincb-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincb.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincd-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincd.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqinch-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqinch.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincw-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincw.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecb-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecb.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecd-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecd.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdech-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdech.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecw-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecw.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincb-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincb.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincd-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincd.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqinch-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqinch.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincw-diagnostics.s<br>
    llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincw.s<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AArch64InstrFormats.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/AArch64InstrFormats.<wbr>td?rev=334980&r1=334979&r2=<wbr>334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64InstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64InstrFormats.td Mon Jun 18 13:50:33 2018<br>
@@ -179,11 +179,23 @@ def CondCode : AsmOperandClass {<br>
 // A 32-bit register pasrsed as 64-bit<br>
 def GPR32as64Operand : AsmOperandClass {<br>
   let Name = "GPR32as64";<br>
+  let ParserMethod =<br>
+      "tryParseGPROperand<false, RegConstraintEqualityTy::<wbr>EqualsSubReg>";<br>
 }<br>
 def GPR32as64 : RegisterOperand<GPR32> {<br>
   let ParserMatchClass = GPR32as64Operand;<br>
 }<br>
<br>
+// A 64-bit register pasrsed as 32-bit<br>
+def GPR64as32Operand : AsmOperandClass {<br>
+  let Name = "GPR64as32";<br>
+  let ParserMethod =<br>
+      "tryParseGPROperand<false, RegConstraintEqualityTy::<wbr>EqualsSuperReg>";<br>
+}<br>
+def GPR64as32 : RegisterOperand<GPR64, "printGPR64as32"> {<br>
+  let ParserMatchClass = GPR64as32Operand;<br>
+}<br>
+<br>
 // 8-bit immediate for AdvSIMD where 64-bit values of the form:<br>
 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh<br>
 // are encoded as the eight bit value 'abcdefgh'.<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AArch64SVEInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/AArch64SVEInstrInfo.<wbr>td?rev=334980&r1=334979&r2=<wbr>334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64SVEInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64SVEInstrInfo.td Mon Jun 18 13:50:33 2018<br>
@@ -527,21 +527,37 @@ let Predicates = [HasSVE] in {<br>
   defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo">;<br>
   defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls">;<br>
<br>
+  defm SQINCB_XPiWdI : sve_int_pred_pattern_b_s32<<wbr>0b00000, "sqincb">;<br>
+  defm UQINCB_WPiI   : sve_int_pred_pattern_b_u32<<wbr>0b00001, "uqincb">;<br>
+  defm SQDECB_XPiWdI : sve_int_pred_pattern_b_s32<<wbr>0b00010, "sqdecb">;<br>
+  defm UQDECB_WPiI   : sve_int_pred_pattern_b_u32<<wbr>0b00011, "uqdecb">;<br>
   defm SQINCB_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b00100, "sqincb">;<br>
   defm UQINCB_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b00101, "uqincb">;<br>
   defm SQDECB_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b00110, "sqdecb">;<br>
   defm UQDECB_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b00111, "uqdecb">;<br>
<br>
+  defm SQINCH_XPiWdI : sve_int_pred_pattern_b_s32<<wbr>0b01000, "sqinch">;<br>
+  defm UQINCH_WPiI   : sve_int_pred_pattern_b_u32<<wbr>0b01001, "uqinch">;<br>
+  defm SQDECH_XPiWdI : sve_int_pred_pattern_b_s32<<wbr>0b01010, "sqdech">;<br>
+  defm UQDECH_WPiI   : sve_int_pred_pattern_b_u32<<wbr>0b01011, "uqdech">;<br>
   defm SQINCH_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b01100, "sqinch">;<br>
   defm UQINCH_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b01101, "uqinch">;<br>
   defm SQDECH_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b01110, "sqdech">;<br>
   defm UQDECH_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b01111, "uqdech">;<br>
<br>
+  defm SQINCW_XPiWdI : sve_int_pred_pattern_b_s32<<wbr>0b10000, "sqincw">;<br>
+  defm UQINCW_WPiI   : sve_int_pred_pattern_b_u32<<wbr>0b10001, "uqincw">;<br>
+  defm SQDECW_XPiWdI : sve_int_pred_pattern_b_s32<<wbr>0b10010, "sqdecw">;<br>
+  defm UQDECW_WPiI   : sve_int_pred_pattern_b_u32<<wbr>0b10011, "uqdecw">;<br>
   defm SQINCW_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b10100, "sqincw">;<br>
   defm UQINCW_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b10101, "uqincw">;<br>
   defm SQDECW_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b10110, "sqdecw">;<br>
   defm UQDECW_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b10111, "uqdecw">;<br>
<br>
+  defm SQINCD_XPiWdI : sve_int_pred_pattern_b_s32<<wbr>0b11000, "sqincd">;<br>
+  defm UQINCD_WPiI   : sve_int_pred_pattern_b_u32<<wbr>0b11001, "uqincd">;<br>
+  defm SQDECD_XPiWdI : sve_int_pred_pattern_b_s32<<wbr>0b11010, "sqdecd">;<br>
+  defm UQDECD_WPiI   : sve_int_pred_pattern_b_u32<<wbr>0b11011, "uqdecd">;<br>
   defm SQINCD_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b11100, "sqincd">;<br>
   defm UQINCD_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b11101, "uqincd">;<br>
   defm SQDECD_XPiI   : sve_int_pred_pattern_b_x64<<wbr>0b11110, "sqdecd">;<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AsmParser/AArch64AsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/AsmParser/<wbr>AArch64AsmParser.cpp?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AsmParser/AArch64AsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AsmParser/AArch64AsmParser.cpp Mon Jun 18 13:50:33 2018<br>
@@ -66,6 +66,12 @@ enum class RegKind {<br>
   SVEPredicateVector<br>
 };<br>
<br>
+enum RegConstraintEqualityTy {<br>
+  EqualsReg,<br>
+  EqualsSuperReg,<br>
+  EqualsSubReg<br>
+};<br>
+<br>
 class AArch64AsmParser : public MCTargetAsmParser {<br>
 private:<br>
   StringRef Mnemonic; ///< Instruction mnemonic.<br>
@@ -92,7 +98,8 @@ private:<br>
   bool parseOperand(OperandVector &Operands, bool isCondCode,<br>
                     bool invertCondCode);<br>
<br>
-  bool showMatchError(SMLoc Loc, unsigned ErrCode, OperandVector &Operands);<br>
+  bool showMatchError(SMLoc Loc, unsigned ErrCode, uint64_t ErrorInfo,<br>
+                      OperandVector &Operands);<br>
<br>
   bool parseDirectiveArch(SMLoc L);<br>
   bool parseDirectiveCPU(SMLoc L);<br>
@@ -139,7 +146,8 @@ private:<br>
   bool tryParseNeonVectorRegister(<wbr>OperandVector &Operands);<br>
   OperandMatchResultTy tryParseVectorIndex(<wbr>OperandVector &Operands);<br>
   OperandMatchResultTy tryParseGPRSeqPair(<wbr>OperandVector &Operands);<br>
-  template <bool ParseShiftExtend><br>
+  template <bool ParseShiftExtend,<br>
+            RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::<wbr>EqualsReg><br>
   OperandMatchResultTy tryParseGPROperand(<wbr>OperandVector &Operands);<br>
   template <bool ParseShiftExtend, bool ParseSuffix><br>
   OperandMatchResultTy tryParseSVEDataVector(<wbr>OperandVector &Operands);<br>
@@ -177,6 +185,8 @@ public:<br>
     setAvailableFeatures(<wbr>ComputeAvailableFeatures(<wbr>getSTI().getFeatureBits()));<br>
   }<br>
<br>
+  bool regsEqual(const MCParsedAsmOperand &Op1,<br>
+                 const MCParsedAsmOperand &Op2) const override;<br>
   bool ParseInstruction(<wbr>ParseInstructionInfo &Info, StringRef Name,<br>
                         SMLoc NameLoc, OperandVector &Operands) override;<br>
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;<br>
@@ -231,6 +241,10 @@ private:<br>
     RegKind Kind;<br>
     int ElementWidth;<br>
<br>
+    // The register may be allowed as a different register class,<br>
+    // e.g. for GPR64as32 or GPR32as64.<br>
+    RegConstraintEqualityTy EqualityTy;<br>
+<br>
     // In some cases the shift/extend needs to be explicitly parsed together<br>
     // with the register, rather than as a separate operand. This is needed<br>
     // for addressing modes where the instruction as a whole dictates the<br>
@@ -446,6 +460,11 @@ public:<br>
     return Reg.RegNum;<br>
   }<br>
<br>
+  RegConstraintEqualityTy getRegEqualityTy() const {<br>
+    assert(Kind == k_Register && "Invalid access!");<br>
+    return Reg.EqualityTy;<br>
+  }<br>
+<br>
   unsigned getVectorListStart() const {<br>
     assert(Kind == k_VectorList && "Invalid access!");<br>
     return VectorList.RegNum;<br>
@@ -1002,6 +1021,11 @@ public:<br>
       AArch64MCRegisterClasses[<wbr>AArch64::GPR64RegClassID].<wbr>contains(Reg.RegNum);<br>
   }<br>
<br>
+  bool isGPR64as32() const {<br>
+    return Kind == k_Register && Reg.Kind == RegKind::Scalar &&<br>
+      AArch64MCRegisterClasses[<wbr>AArch64::GPR32RegClassID].<wbr>contains(Reg.RegNum);<br>
+  }<br>
+<br>
   bool isWSeqPair() const {<br>
     return Kind == k_Register && Reg.Kind == RegKind::Scalar &&<br>
            AArch64MCRegisterClasses[<wbr>AArch64::<wbr>WSeqPairsClassRegClassID].<wbr>contains(<br>
@@ -1318,6 +1342,18 @@ public:<br>
     Inst.addOperand(MCOperand::<wbr>createReg(Reg));<br>
   }<br>
<br>
+  void addGPR64as32Operands(MCInst &Inst, unsigned N) const {<br>
+    assert(N == 1 && "Invalid number of operands!");<br>
+    assert(<br>
+        AArch64MCRegisterClasses[<wbr>AArch64::GPR32RegClassID].<wbr>contains(getReg()));<br>
+<br>
+    const MCRegisterInfo *RI = Ctx.getRegisterInfo();<br>
+    uint32_t Reg = RI->getRegClass(AArch64::<wbr>GPR64RegClassID).getRegister(<br>
+        RI->getEncodingValue(getReg())<wbr>);<br>
+<br>
+    Inst.addOperand(MCOperand::<wbr>createReg(Reg));<br>
+  }<br>
+<br>
   template <int Width><br>
   void addFPRasZPRRegOperands(MCInst &Inst, unsigned N) const {<br>
     unsigned Base;<br>
@@ -1668,6 +1704,7 @@ public:<br>
<br>
   static std::unique_ptr<<wbr>AArch64Operand><br>
   CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx,<br>
+            RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::<wbr>EqualsReg,<br>
             AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL,<br>
             unsigned ShiftAmount = 0,<br>
             unsigned HasExplicitAmount = false) {<br>
@@ -1675,6 +1712,7 @@ public:<br>
     Op->Reg.RegNum = RegNum;<br>
     Op->Reg.Kind = Kind;<br>
     Op->Reg.ElementWidth = 0;<br>
+    Op->Reg.EqualityTy = EqTy;<br>
     Op->Reg.ShiftExtend.Type = ExtTy;<br>
     Op->Reg.ShiftExtend.Amount = ShiftAmount;<br>
     Op->Reg.ShiftExtend.<wbr>HasExplicitAmount = HasExplicitAmount;<br>
@@ -1692,7 +1730,7 @@ public:<br>
     assert((Kind == RegKind::NeonVector || Kind == RegKind::SVEDataVector ||<br>
             Kind == RegKind::SVEPredicateVector) &&<br>
            "Invalid vector kind");<br>
-    auto Op = CreateReg(RegNum, Kind, S, E, Ctx, ExtTy, ShiftAmount,<br>
+    auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount,<br>
                         HasExplicitAmount);<br>
     Op->Reg.ElementWidth = ElementWidth;<br>
     return Op;<br>
@@ -3164,7 +3202,7 @@ AArch64AsmParser::<wbr>tryParseGPR64sp0Operan<br>
   return MatchOperand_Success;<br>
 }<br>
<br>
-template <bool ParseShiftExtend><br>
+template <bool ParseShiftExtend, RegConstraintEqualityTy EqTy><br>
 OperandMatchResultTy<br>
 AArch64AsmParser::<wbr>tryParseGPROperand(<wbr>OperandVector &Operands) {<br>
   SMLoc StartLoc = getLoc();<br>
@@ -3177,7 +3215,7 @@ AArch64AsmParser::<wbr>tryParseGPROperand(Ope<br>
   // No shift/extend is the default.<br>
   if (!ParseShiftExtend || getParser().getTok().isNot(<wbr>AsmToken::Comma)) {<br>
     Operands.push_back(<wbr>AArch64Operand::CreateReg(<br>
-        RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext()));<br>
+        RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext(), EqTy));<br>
     return MatchOperand_Success;<br>
   }<br>
<br>
@@ -3191,10 +3229,10 @@ AArch64AsmParser::<wbr>tryParseGPROperand(Ope<br>
     return Res;<br>
<br>
   auto Ext = static_cast<AArch64Operand*>(<wbr>ExtOpnd.back().get());<br>
-  Operands.push_back(<wbr>AArch64Operand::CreateReg(<wbr>RegNum, RegKind::Scalar,<br>
-                     StartLoc, Ext->getEndLoc(), getContext(),<br>
-                     Ext->getShiftExtendType(), Ext->getShiftExtendAmount(),<br>
-                     Ext->hasShiftExtendAmount()))<wbr>;<br>
+  Operands.push_back(<wbr>AArch64Operand::CreateReg(<br>
+      RegNum, RegKind::Scalar, StartLoc, Ext->getEndLoc(), getContext(), EqTy,<br>
+      Ext->getShiftExtendType(), Ext->getShiftExtendAmount(),<br>
+      Ext->hasShiftExtendAmount()));<br>
<br>
   return MatchOperand_Success;<br>
 }<br>
@@ -3412,6 +3450,30 @@ bool AArch64AsmParser::<wbr>parseOperand(Oper<br>
   }<br>
 }<br>
<br>
+bool AArch64AsmParser::regsEqual(<wbr>const MCParsedAsmOperand &Op1,<br>
+                                 const MCParsedAsmOperand &Op2) const {<br>
+  auto &AOp1 = static_cast<const AArch64Operand&>(Op1);<br>
+  auto &AOp2 = static_cast<const AArch64Operand&>(Op2);<br>
+  if (AOp1.getRegEqualityTy() == RegConstraintEqualityTy::<wbr>EqualsReg &&<br>
+      AOp2.getRegEqualityTy() == RegConstraintEqualityTy::<wbr>EqualsReg)<br>
+    return MCTargetAsmParser::regsEqual(<wbr>Op1, Op2);<br>
+<br>
+  assert(AOp1.isScalarReg() && AOp2.isScalarReg() &&<br>
+         "Testing equality of non-scalar registers not supported");<br>
+<br>
+  // Check if a registers match their sub/super register classes.<br>
+  if (AOp1.getRegEqualityTy() == EqualsSuperReg)<br>
+    return getXRegFromWReg(Op1.getReg()) == Op2.getReg();<br>
+  if (AOp1.getRegEqualityTy() == EqualsSubReg)<br>
+    return getWRegFromXReg(Op1.getReg()) == Op2.getReg();<br>
+  if (AOp2.getRegEqualityTy() == EqualsSuperReg)<br>
+    return getXRegFromWReg(Op2.getReg()) == Op1.getReg();<br>
+  if (AOp2.getRegEqualityTy() == EqualsSubReg)<br>
+    return getWRegFromXReg(Op2.getReg()) == Op1.getReg();<br>
+<br>
+  return false;<br>
+}<br>
+<br>
 /// ParseInstruction - Parse an AArch64 instruction mnemonic followed by its<br>
 /// operands.<br>
 bool AArch64AsmParser::<wbr>ParseInstruction(<wbr>ParseInstructionInfo &Info,<br>
@@ -3765,10 +3827,22 @@ static std::string AArch64MnemonicSpellC<br>
                                              unsigned VariantID = 0);<br>
<br>
 bool AArch64AsmParser::<wbr>showMatchError(SMLoc Loc, unsigned ErrCode,<br>
+                                      uint64_t ErrorInfo,<br>
                                       OperandVector &Operands) {<br>
   switch (ErrCode) {<br>
-  case Match_InvalidTiedOperand:<br>
-    return Error(Loc, "operand must match destination register");<br>
+  case Match_InvalidTiedOperand: {<br>
+    RegConstraintEqualityTy EqTy =<br>
+        static_cast<const AArch64Operand &>(*Operands[ErrorInfo])<br>
+            .getRegEqualityTy();<br>
+    switch (EqTy) {<br>
+    case RegConstraintEqualityTy::<wbr>EqualsSubReg:<br>
+      return Error(Loc, "operand must be 64-bit form of destination register");<br>
+    case RegConstraintEqualityTy::<wbr>EqualsSuperReg:<br>
+      return Error(Loc, "operand must be 32-bit form of destination register");<br>
+    case RegConstraintEqualityTy::<wbr>EqualsReg:<br>
+      return Error(Loc, "operand must match destination register");<br>
+    }<br>
+  }<br>
   case Match_MissingFeature:<br>
     return Error(Loc,<br>
                  "instruction requires a CPU feature not currently enabled");<br>
@@ -4389,7 +4463,7 @@ bool AArch64AsmParser::<wbr>MatchAndEmitInstr<br>
     return Error(IDLoc, Msg);<br>
   }<br>
   case Match_MnemonicFail:<br>
-    return showMatchError(IDLoc, MatchResult, Operands);<br>
+    return showMatchError(IDLoc, MatchResult, ErrorInfo, Operands);<br>
   case Match_InvalidOperand: {<br>
     SMLoc ErrorLoc = IDLoc;<br>
<br>
@@ -4408,7 +4482,7 @@ bool AArch64AsmParser::<wbr>MatchAndEmitInstr<br>
         ((AArch64Operand &)*Operands[ErrorInfo]).<wbr>isTokenSuffix())<br>
       MatchResult = Match_InvalidSuffix;<br>
<br>
-    return showMatchError(ErrorLoc, MatchResult, Operands);<br>
+    return showMatchError(ErrorLoc, MatchResult, ErrorInfo, Operands);<br>
   }<br>
   case Match_InvalidTiedOperand:<br>
   case Match_InvalidMemoryIndexed1:<br>
@@ -4546,7 +4620,7 @@ bool AArch64AsmParser::<wbr>MatchAndEmitInstr<br>
     SMLoc ErrorLoc = ((AArch64Operand &)*Operands[ErrorInfo]).<wbr>getStartLoc();<br>
     if (ErrorLoc == SMLoc())<br>
       ErrorLoc = IDLoc;<br>
-    return showMatchError(ErrorLoc, MatchResult, Operands);<br>
+    return showMatchError(ErrorLoc, MatchResult, ErrorInfo, Operands);<br>
   }<br>
   }<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>InstPrinter/<wbr>AArch64InstPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/InstPrinter/<wbr>AArch64InstPrinter.cpp?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>InstPrinter/<wbr>AArch64InstPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>InstPrinter/<wbr>AArch64InstPrinter.cpp Mon Jun 18 13:50:33 2018<br>
@@ -1527,3 +1527,10 @@ void AArch64InstPrinter::<wbr>printExactFPImm<br>
   unsigned Val = MI->getOperand(OpNum).getImm()<wbr>;<br>
   O << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);<br>
 }<br>
+<br>
+void AArch64InstPrinter::<wbr>printGPR64as32(const MCInst *MI, unsigned OpNum,<br>
+                                        const MCSubtargetInfo &STI,<br>
+                                        raw_ostream &O) {<br>
+  unsigned Reg = MI->getOperand(OpNum).getReg()<wbr>;<br>
+  O << getRegisterName(<wbr>getWRegFromXReg(Reg));<br>
+}<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>InstPrinter/<wbr>AArch64InstPrinter.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/InstPrinter/<wbr>AArch64InstPrinter.h?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>InstPrinter/<wbr>AArch64InstPrinter.h (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>InstPrinter/<wbr>AArch64InstPrinter.h Mon Jun 18 13:50:33 2018<br>
@@ -180,6 +180,8 @@ protected:<br>
   template <char = 0><br>
   void printSVERegOp(const MCInst *MI, unsigned OpNum,<br>
                     const MCSubtargetInfo &STI, raw_ostream &O);<br>
+  void printGPR64as32(const MCInst *MI, unsigned OpNum,<br>
+                      const MCSubtargetInfo &STI, raw_ostream &O);<br>
   template <int Width><br>
   void printZPRasFPR(const MCInst *MI, unsigned OpNum,<br>
                      const MCSubtargetInfo &STI, raw_ostream &O);<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>SVEInstrFormats.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/SVEInstrFormats.td?<wbr>rev=334980&r1=334979&r2=<wbr>334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>SVEInstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>SVEInstrFormats.td Mon Jun 18 13:50:33 2018<br>
@@ -333,9 +333,32 @@ class sve_int_pred_pattern_b<bits<5> opc<br>
   let Inst{9-5}   = pattern;<br>
   let Inst{4-0}   = Rdn;<br>
<br>
+  // Signed 32bit forms require their GPR operand printed.<br>
+  let AsmString = !if(!eq(opc{2,0}, 0b00),<br>
+                      !strconcat(asm, "\t$Rdn, $_Rdn, $pattern, mul $imm4"),<br>
+                      !strconcat(asm, "\t$Rdn, $pattern, mul $imm4"));<br>
+<br>
   let Constraints = "$Rdn = $_Rdn";<br>
 }<br>
<br>
+multiclass sve_int_pred_pattern_b_s32<<wbr>bits<5> opc, string asm> {<br>
+  def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64as32>;<br>
+<br>
+  def : InstAlias<asm # "\t$Rd, $Rn, $pattern",<br>
+                  (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1), 1>;<br>
+  def : InstAlias<asm # "\t$Rd, $Rn",<br>
+                  (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, 0b11111, 1), 2>;<br>
+}<br>
+<br>
+multiclass sve_int_pred_pattern_b_u32<<wbr>bits<5> opc, string asm> {<br>
+  def NAME : sve_int_pred_pattern_b<opc, asm, GPR32z, GPR32z>;<br>
+<br>
+  def : InstAlias<asm # "\t$Rdn, $pattern",<br>
+                  (!cast<Instruction>(NAME) GPR32z:$Rdn, sve_pred_enum:$pattern, 1), 1>;<br>
+  def : InstAlias<asm # "\t$Rdn",<br>
+                  (!cast<Instruction>(NAME) GPR32z:$Rdn, 0b11111, 1), 2>;<br>
+}<br>
+<br>
 multiclass sve_int_pred_pattern_b_x64<<wbr>bits<5> opc, string asm> {<br>
   def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>;<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecb-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqdecb-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecb-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecb-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -20,6 +20,20 @@ sqdecb sp<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up<br>
+<br>
+sqdecb x0, w1<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register<br>
+// CHECK-NEXT: sqdecb x0, w1<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+sqdecb x0, x1<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: sqdecb x0, x1<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
 sqdecb x0, all, mul #-1<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecb.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecb.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqdecb.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecb.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecb.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ sqdecb  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (x0, w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+sqdecb  x0, w0<br>
+// CHECK-INST: sqdecb  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb 20 04 <unknown><br>
+<br>
+sqdecb  x0, w0, all<br>
+// CHECK-INST: sqdecb  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb 20 04 <unknown><br>
+<br>
+sqdecb  x0, w0, all, mul #1<br>
+// CHECK-INST: sqdecb  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb 20 04 <unknown><br>
+<br>
+sqdecb  x0, w0, all, mul #16<br>
+// CHECK-INST: sqdecb  x0, w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xfb,0x2f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb 2f 04 <unknown><br>
+<br>
+sqdecb  x0, w0, pow2<br>
+// CHECK-INST: sqdecb  x0, w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xf8,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f8 20 04 <unknown><br>
+<br>
+sqdecb  x0, w0, pow2, mul #16<br>
+// CHECK-INST: sqdecb  x0, w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xf8,0x2f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f8 2f 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecd-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqdecd-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecd-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecd-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -20,6 +20,20 @@ sqdecd sp<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up<br>
+<br>
+sqdecd x0, w1<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register<br>
+// CHECK-NEXT: sqdecd x0, w1<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+sqdecd x0, x1<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: sqdecd x0, x1<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
 sqdecd x0, all, mul #-1<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecd.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecd.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqdecd.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecd.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecd.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ sqdecd  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (x0, w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+sqdecd  x0, w0<br>
+// CHECK-INST: sqdecd  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb e0 04 <unknown><br>
+<br>
+sqdecd  x0, w0, all<br>
+// CHECK-INST: sqdecd  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb e0 04 <unknown><br>
+<br>
+sqdecd  x0, w0, all, mul #1<br>
+// CHECK-INST: sqdecd  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb e0 04 <unknown><br>
+<br>
+sqdecd  x0, w0, all, mul #16<br>
+// CHECK-INST: sqdecd  x0, w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xfb,0xef,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb ef 04 <unknown><br>
+<br>
+sqdecd  x0, w0, pow2<br>
+// CHECK-INST: sqdecd  x0, w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xf8,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f8 e0 04 <unknown><br>
+<br>
+sqdecd  x0, w0, pow2, mul #16<br>
+// CHECK-INST: sqdecd  x0, w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xf8,0xef,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f8 ef 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdech-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqdech-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdech-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdech-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -20,6 +20,20 @@ sqdech sp<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up<br>
+<br>
+sqdech x0, w1<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register<br>
+// CHECK-NEXT: sqdech x0, w1<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+sqdech x0, x1<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: sqdech x0, x1<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
 sqdech x0, all, mul #-1<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdech.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdech.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqdech.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdech.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdech.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ sqdech  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (x0, w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+sqdech  x0, w0<br>
+// CHECK-INST: sqdech  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb 60 04 <unknown><br>
+<br>
+sqdech  x0, w0, all<br>
+// CHECK-INST: sqdech  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb 60 04 <unknown><br>
+<br>
+sqdech  x0, w0, all, mul #1<br>
+// CHECK-INST: sqdech  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb 60 04 <unknown><br>
+<br>
+sqdech  x0, w0, all, mul #16<br>
+// CHECK-INST: sqdech  x0, w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xfb,0x6f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb 6f 04 <unknown><br>
+<br>
+sqdech  x0, w0, pow2<br>
+// CHECK-INST: sqdech  x0, w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xf8,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f8 60 04 <unknown><br>
+<br>
+sqdech  x0, w0, pow2, mul #16<br>
+// CHECK-INST: sqdech  x0, w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xf8,0x6f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f8 6f 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecw-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqdecw-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecw-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecw-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -20,6 +20,20 @@ sqdecw sp<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up<br>
+<br>
+sqdecw x0, w1<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register<br>
+// CHECK-NEXT: sqdecw x0, w1<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+sqdecw x0, x1<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: sqdecw x0, x1<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
 sqdecw x0, all, mul #-1<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecw.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecw.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqdecw.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecw.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqdecw.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ sqdecw  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (x0, w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+sqdecw  x0, w0<br>
+// CHECK-INST: sqdecw  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb a0 04 <unknown><br>
+<br>
+sqdecw  x0, w0, all<br>
+// CHECK-INST: sqdecw  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb a0 04 <unknown><br>
+<br>
+sqdecw  x0, w0, all, mul #1<br>
+// CHECK-INST: sqdecw  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb a0 04 <unknown><br>
+<br>
+sqdecw  x0, w0, all, mul #16<br>
+// CHECK-INST: sqdecw  x0, w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xfb,0xaf,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 fb af 04 <unknown><br>
+<br>
+sqdecw  x0, w0, pow2<br>
+// CHECK-INST: sqdecw  x0, w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xf8,0xa0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f8 a0 04 <unknown><br>
+<br>
+sqdecw  x0, w0, pow2, mul #16<br>
+// CHECK-INST: sqdecw  x0, w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xf8,0xaf,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f8 af 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincb-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqincb-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincb-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincb-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -20,6 +20,20 @@ sqincb sp<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up<br>
+<br>
+sqincb x0, w1<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register<br>
+// CHECK-NEXT: sqincb x0, w1<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+sqincb x0, x0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: sqincb x0, x0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
 sqincb x0, all, mul #-1<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincb.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincb.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqincb.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincb.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincb.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ sqincb  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (x0, w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+sqincb  x0, w0<br>
+// CHECK-INST: sqincb  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 20 04 <unknown><br>
+<br>
+sqincb  x0, w0, all<br>
+// CHECK-INST: sqincb  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 20 04 <unknown><br>
+<br>
+sqincb  x0, w0, all, mul #1<br>
+// CHECK-INST: sqincb  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 20 04 <unknown><br>
+<br>
+sqincb  x0, w0, all, mul #16<br>
+// CHECK-INST: sqincb  x0, w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xf3,0x2f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 2f 04 <unknown><br>
+<br>
+sqincb  x0, w0, pow2<br>
+// CHECK-INST: sqincb  x0, w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xf0,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f0 20 04 <unknown><br>
+<br>
+sqincb  x0, w0, pow2, mul #16<br>
+// CHECK-INST: sqincb  x0, w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xf0,0x2f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f0 2f 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincd-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqincd-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincd-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincd-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -20,6 +20,20 @@ sqincd sp<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up<br>
+<br>
+sqincd x0, w1<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register<br>
+// CHECK-NEXT: sqincd x0, w1<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+sqincd x0, x0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: sqincd x0, x0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
 sqincd x0, all, mul #-1<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincd.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincd.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqincd.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincd.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincd.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ sqincd  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (x0, w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+sqincd  x0, w0<br>
+// CHECK-INST: sqincd  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 e0 04 <unknown><br>
+<br>
+sqincd  x0, w0, all<br>
+// CHECK-INST: sqincd  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 e0 04 <unknown><br>
+<br>
+sqincd  x0, w0, all, mul #1<br>
+// CHECK-INST: sqincd  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 e0 04 <unknown><br>
+<br>
+sqincd  x0, w0, all, mul #16<br>
+// CHECK-INST: sqincd  x0, w0, all<br>
+// CHECK-ENCODING: [0xe0,0xf3,0xef,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 ef 04 <unknown><br>
+<br>
+sqincd  x0, w0, pow2<br>
+// CHECK-INST: sqincd  x0, w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xf0,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f0 e0 04 <unknown><br>
+<br>
+sqincd  x0, w0, pow2, mul #16<br>
+// CHECK-INST: sqincd  x0, w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xf0,0xef,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f0 ef 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqinch-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqinch-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqinch-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqinch-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -20,6 +20,20 @@ sqinch sp<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up<br>
+<br>
+sqinch x0, w1<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register<br>
+// CHECK-NEXT: sqinch x0, w1<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+sqinch x0, x0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: sqinch x0, x0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
 sqinch x0, all, mul #-1<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqinch.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqinch.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqinch.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqinch.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqinch.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ sqinch  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (x0, w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+sqinch  x0, w0<br>
+// CHECK-INST: sqinch  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 60 04 <unknown><br>
+<br>
+sqinch  x0, w0, all<br>
+// CHECK-INST: sqinch  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 60 04 <unknown><br>
+<br>
+sqinch  x0, w0, all, mul #1<br>
+// CHECK-INST: sqinch  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 60 04 <unknown><br>
+<br>
+sqinch  x0, w0, all, mul #16<br>
+// CHECK-INST: sqinch  x0, w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xf3,0x6f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 6f 04 <unknown><br>
+<br>
+sqinch  x0, w0, pow2<br>
+// CHECK-INST: sqinch  x0, w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xf0,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f0 60 04 <unknown><br>
+<br>
+sqinch  x0, w0, pow2, mul #16<br>
+// CHECK-INST: sqinch  x0, w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xf0,0x6f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f0 6f 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincw-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqincw-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincw-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincw-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -20,6 +20,20 @@ sqincw sp<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up<br>
+<br>
+sqincw x0, w1<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register<br>
+// CHECK-NEXT: sqincw x0, w1<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+sqincw x0, x0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: sqincw x0, x0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
 sqincw x0, all, mul #-1<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincw.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincw.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/sqincw.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincw.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/sqincw.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ sqincw  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (x0, w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+sqincw  x0, w0<br>
+// CHECK-INST: sqincw  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 a0 04 <unknown><br>
+<br>
+sqincw  x0, w0, all<br>
+// CHECK-INST: sqincw  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 a0 04 <unknown><br>
+<br>
+sqincw  x0, w0, all, mul #1<br>
+// CHECK-INST: sqincw  x0, w0<br>
+// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 a0 04 <unknown><br>
+<br>
+sqincw  x0, w0, all, mul #16<br>
+// CHECK-INST: sqincw  x0, w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xf3,0xaf,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f3 af 04 <unknown><br>
+<br>
+sqincw  x0, w0, pow2<br>
+// CHECK-INST: sqincw  x0, w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xf0,0xa0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f0 a0 04 <unknown><br>
+<br>
+sqincw  x0, w0, pow2, mul #16<br>
+// CHECK-INST: sqincw  x0, w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xf0,0xaf,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f0 af 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecb-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqdecb-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecb-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecb-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -3,11 +3,6 @@<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Invalid result register<br>
<br>
-uqdecb w0<br>
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
-// CHECK-NEXT: uqdecb w0<br>
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
-<br>
 uqdecb wsp<br>
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
 // CHECK-NEXT: uqdecb wsp<br>
@@ -19,6 +14,25 @@ uqdecb sp<br>
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
<br>
<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up (unsigned dec only has one register operand)<br>
+<br>
+uqdecb x0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqdecb x0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqdecb w0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqdecb w0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqdecb x0, x0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqdecb x0, x0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecb.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecb.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqdecb.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecb.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecb.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ uqdecb  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+uqdecb  w0<br>
+// CHECK-INST: uqdecb  w0<br>
+// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff 20 04 <unknown><br>
+<br>
+uqdecb  w0, all<br>
+// CHECK-INST: uqdecb  w0<br>
+// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff 20 04 <unknown><br>
+<br>
+uqdecb  w0, all, mul #1<br>
+// CHECK-INST: uqdecb  w0<br>
+// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff 20 04 <unknown><br>
+<br>
+uqdecb  w0, all, mul #16<br>
+// CHECK-INST: uqdecb  w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xff,0x2f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff 2f 04 <unknown><br>
+<br>
+uqdecb  w0, pow2<br>
+// CHECK-INST: uqdecb  w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xfc,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 fc 20 04 <unknown><br>
+<br>
+uqdecb  w0, pow2, mul #16<br>
+// CHECK-INST: uqdecb  w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xfc,0x2f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 fc 2f 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecd-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqdecd-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecd-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecd-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -3,11 +3,6 @@<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Invalid result register<br>
<br>
-uqdecd w0<br>
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
-// CHECK-NEXT: uqdecd w0<br>
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
-<br>
 uqdecd wsp<br>
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
 // CHECK-NEXT: uqdecd wsp<br>
@@ -19,6 +14,25 @@ uqdecd sp<br>
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
<br>
<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up (unsigned dec only has one register operand)<br>
+<br>
+uqdecd x0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqdecd x0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqdecd w0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqdecd w0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqdecd x0, x0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqdecd x0, x0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecd.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecd.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqdecd.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecd.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecd.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ uqdecd  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+uqdecd  w0<br>
+// CHECK-INST: uqdecd  w0<br>
+// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff e0 04 <unknown><br>
+<br>
+uqdecd  w0, all<br>
+// CHECK-INST: uqdecd  w0<br>
+// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff e0 04 <unknown><br>
+<br>
+uqdecd  w0, all, mul #1<br>
+// CHECK-INST: uqdecd  w0<br>
+// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff e0 04 <unknown><br>
+<br>
+uqdecd  w0, all, mul #16<br>
+// CHECK-INST: uqdecd  w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xff,0xef,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff ef 04 <unknown><br>
+<br>
+uqdecd  w0, pow2<br>
+// CHECK-INST: uqdecd  w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xfc,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 fc e0 04 <unknown><br>
+<br>
+uqdecd  w0, pow2, mul #16<br>
+// CHECK-INST: uqdecd  w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xfc,0xef,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 fc ef 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdech-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqdech-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdech-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdech-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -3,11 +3,6 @@<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Invalid result register<br>
<br>
-uqdech w0<br>
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
-// CHECK-NEXT: uqdech w0<br>
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
-<br>
 uqdech wsp<br>
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
 // CHECK-NEXT: uqdech wsp<br>
@@ -19,6 +14,25 @@ uqdech sp<br>
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
<br>
<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up (unsigned dec only has one register operand)<br>
+<br>
+uqdech x0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqdech x0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqdech w0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqdech w0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqdech x0, x0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqdech x0, x0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdech.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdech.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqdech.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdech.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdech.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ uqdech  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+uqdech  w0<br>
+// CHECK-INST: uqdech  w0<br>
+// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff 60 04 <unknown><br>
+<br>
+uqdech  w0, all<br>
+// CHECK-INST: uqdech  w0<br>
+// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff 60 04 <unknown><br>
+<br>
+uqdech  w0, all, mul #1<br>
+// CHECK-INST: uqdech  w0<br>
+// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff 60 04 <unknown><br>
+<br>
+uqdech  w0, all, mul #16<br>
+// CHECK-INST: uqdech  w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xff,0x6f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff 6f 04 <unknown><br>
+<br>
+uqdech  w0, pow2<br>
+// CHECK-INST: uqdech  w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xfc,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 fc 60 04 <unknown><br>
+<br>
+uqdech  w0, pow2, mul #16<br>
+// CHECK-INST: uqdech  w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xfc,0x6f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 fc 6f 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecw-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqdecw-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecw-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecw-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -3,11 +3,6 @@<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Invalid result register<br>
<br>
-uqdecw w0<br>
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
-// CHECK-NEXT: uqdecw w0<br>
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
-<br>
 uqdecw wsp<br>
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
 // CHECK-NEXT: uqdecw wsp<br>
@@ -19,6 +14,25 @@ uqdecw sp<br>
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
<br>
<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up (unsigned dec only has one register operand)<br>
+<br>
+uqdecw x0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqdecw x0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqdecw w0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqdecw w0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqdecw x0, x0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqdecw x0, x0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecw.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecw.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqdecw.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecw.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqdecw.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ uqdecw  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+uqdecw  w0<br>
+// CHECK-INST: uqdecw  w0<br>
+// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff a0 04 <unknown><br>
+<br>
+uqdecw  w0, all<br>
+// CHECK-INST: uqdecw  w0<br>
+// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff a0 04 <unknown><br>
+<br>
+uqdecw  w0, all, mul #1<br>
+// CHECK-INST: uqdecw  w0<br>
+// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff a0 04 <unknown><br>
+<br>
+uqdecw  w0, all, mul #16<br>
+// CHECK-INST: uqdecw  w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xff,0xaf,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 ff af 04 <unknown><br>
+<br>
+uqdecw  w0, pow2<br>
+// CHECK-INST: uqdecw  w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xfc,0xa0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 fc a0 04 <unknown><br>
+<br>
+uqdecw  w0, pow2, mul #16<br>
+// CHECK-INST: uqdecw  w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xfc,0xaf,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 fc af 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincb-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqincb-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincb-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincb-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -3,11 +3,6 @@<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Invalid result register<br>
<br>
-uqincb w0<br>
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
-// CHECK-NEXT: uqincb w0<br>
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
-<br>
 uqincb wsp<br>
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
 // CHECK-NEXT: uqincb wsp<br>
@@ -19,6 +14,25 @@ uqincb sp<br>
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
<br>
<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up (unsigned inc only has one register operand)<br>
+<br>
+uqincb x0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqincb x0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqincb w0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqincb w0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqincb x0, x0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqincb x0, x0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincb.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincb.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqincb.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincb.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincb.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ uqincb  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+uqincb  w0<br>
+// CHECK-INST: uqincb  w0<br>
+// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f7 20 04 <unknown><br>
+<br>
+uqincb  w0, all<br>
+// CHECK-INST: uqincb  w0<br>
+// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f7 20 04 <unknown><br>
+<br>
+uqincb  w0, all, mul #1<br>
+// CHECK-INST: uqincb  w0<br>
+// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f7 20 04 <unknown><br>
+<br>
+uqincb  w0, all, mul #16<br>
+// CHECK-INST: uqincb  w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xf7,0x2f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f7 2f 04 <unknown><br>
+<br>
+uqincb  w0, pow2<br>
+// CHECK-INST: uqincb  w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xf4,0x20,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f4 20 04 <unknown><br>
+<br>
+uqincb  w0, pow2, mul #16<br>
+// CHECK-INST: uqincb  w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xf4,0x2f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f4 2f 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincd-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqincd-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincd-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincd-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -3,11 +3,6 @@<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Invalid result register<br>
<br>
-uqincd w0<br>
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
-// CHECK-NEXT: uqincd w0<br>
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
-<br>
 uqincd wsp<br>
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
 // CHECK-NEXT: uqincd wsp<br>
@@ -19,6 +14,25 @@ uqincd sp<br>
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
<br>
<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up (unsigned inc only has one register operand)<br>
+<br>
+uqincd x0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqincd x0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqincd w0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqincd w0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqincd x0, x0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqincd x0, x0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincd.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincd.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqincd.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincd.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincd.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ uqincd  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+uqincd  w0<br>
+// CHECK-INST: uqincd  w0<br>
+// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f7 e0 04 <unknown><br>
+<br>
+uqincd  w0, all<br>
+// CHECK-INST: uqincd  w0<br>
+// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f7 e0 04 <unknown><br>
+<br>
+uqincd  w0, all, mul #1<br>
+// CHECK-INST: uqincd  w0<br>
+// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f7 e0 04 <unknown><br>
+<br>
+uqincd  w0, all, mul #16<br>
+// CHECK-INST: uqincd  w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xf7,0xef,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f7 ef 04 <unknown><br>
+<br>
+uqincd  w0, pow2<br>
+// CHECK-INST: uqincd  w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xf4,0xe0,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f4 e0 04 <unknown><br>
+<br>
+uqincd  w0, pow2, mul #16<br>
+// CHECK-INST: uqincd  w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xf4,0xef,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f4 ef 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqinch-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqinch-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqinch-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqinch-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -3,11 +3,6 @@<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Invalid result register<br>
<br>
-uqinch w0<br>
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
-// CHECK-NEXT: uqinch w0<br>
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
-<br>
 uqinch wsp<br>
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
 // CHECK-NEXT: uqinch wsp<br>
@@ -19,6 +14,25 @@ uqinch sp<br>
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
<br>
<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up (unsigned inc only has one register operand)<br>
+<br>
+uqinch x0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqinch x0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqinch w0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqinch w0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqinch x0, x0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqinch x0, x0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Immediate not compatible with encode/decode function.<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqinch.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqinch.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqinch.s?rev=<wbr>334980&r1=334979&r2=334980&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqinch.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqinch.s Mon Jun 18 13:50:33 2018<br>
@@ -37,6 +37,47 @@ uqinch  x0, all, mul #16<br>
<br>
<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+// Test 32-bit form (w0) and its aliases<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
+<br>
+uqinch  w0<br>
+// CHECK-INST: uqinch  w0<br>
+// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f7 60 04 <unknown><br>
+<br>
+uqinch  w0, all<br>
+// CHECK-INST: uqinch  w0<br>
+// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f7 60 04 <unknown><br>
+<br>
+uqinch  w0, all, mul #1<br>
+// CHECK-INST: uqinch  w0<br>
+// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f7 60 04 <unknown><br>
+<br>
+uqinch  w0, all, mul #16<br>
+// CHECK-INST: uqinch  w0, all, mul #16<br>
+// CHECK-ENCODING: [0xe0,0xf7,0x6f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: e0 f7 6f 04 <unknown><br>
+<br>
+uqinch  w0, pow2<br>
+// CHECK-INST: uqinch  w0, pow2<br>
+// CHECK-ENCODING: [0x00,0xf4,0x60,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f4 60 04 <unknown><br>
+<br>
+uqinch  w0, pow2, mul #16<br>
+// CHECK-INST: uqinch  w0, pow2, mul #16<br>
+// CHECK-ENCODING: [0x00,0xf4,0x6f,0x04]<br>
+// CHECK-ERROR: instruction requires: sve<br>
+// CHECK-UNKNOWN: 00 f4 6f 04 <unknown><br>
+<br>
+<br>
+// ------------------------------<wbr>------------------------------<wbr>---------------//<br>
 // Test all patterns for 64-bit form<br>
 // ------------------------------<wbr>------------------------------<wbr>---------------//<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincw-diagnostics.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/SVE/uqincw-<wbr>diagnostics.s?rev=334980&r1=<wbr>334979&r2=334980&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincw-diagnostics.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>SVE/uqincw-diagnostics.s Mon Jun 18 13:50:33 2018<br>
@@ -3,11 +3,6 @@<br>
 // ------------------------------<wbr>------------------------------<wbr>------------- //<br>
 // Invalid result register<br>
<br>
-uqincw w0<br>
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
-// CHECK-NEXT: uqincw w0<br>
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
-<br>
 uqincw wsp<br>
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand<br>
 // CHECK-NEXT: uqincw wsp<br>
@@ -19,6 +14,25 @@ uqincw sp<br>
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
<br>
<br>
+// ------------------------------<wbr>------------------------------<wbr>------------- //<br>
+// Operands not matching up (unsigned inc only has one register operand)<br>
+<br>
+uqincw x0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern<br>
+// CHECK-NEXT: uqincw x0, w0<br>
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:<br>
+<br>
+uqincw w0, w0<br>
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pa</blockquote></div></div></blockquote></div></div></div></div>
</blockquote></div><br></div>