<div dir="ltr">This patch breaks libFuzzer tests<div><a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fuzzer/builds/15589/steps/check-fuzzer/logs/stdio">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fuzzer/builds/15589/steps/check-fuzzer/logs/stdio</a><br></div></div><br><div class="gmail_quote"><div dir="ltr">On Thu, May 24, 2018 at 2:26 PM Craig Topper via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ctopper<br>
Date: Thu May 24 14:22:51 2018<br>
New Revision: 333226<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=333226&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=333226&view=rev</a><br>
Log:<br>
[ValueTracking] Teach computeKnownBits that the result of an absolute value pattern that uses nsw flag is always positive.<br>
<br>
If the nsw flag is used in the absolute value then it is undefined for INT_MIN. For all other value it will produce a positive number. So we can assume the result is positive.<br>
<br>
This breaks some InstCombine abs/nabs combining tests because we simplify the second compare from known bits rather than as the whole pattern. Looks like we can probably fix it by adding a neg+abs/nabs combine to just swap the select operands. Need to check alive to make sure there are no corner cases.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D47041" rel="noreferrer" target="_blank">https://reviews.llvm.org/D47041</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Analysis/ValueTracking.cpp<br>
llvm/trunk/test/Transforms/InstCombine/abs-1.ll<br>
llvm/trunk/test/Transforms/InstCombine/abs_abs.ll<br>
<br>
Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=333226&r1=333225&r2=333226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=333226&r1=333225&r2=333226&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)<br>
+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Thu May 24 14:22:51 2018<br>
@@ -1078,6 +1078,12 @@ static void computeKnownBitsFromOperator<br>
// leading zero bits.<br>
MaxHighZeros =<br>
std::max(Known.countMinLeadingZeros(), Known2.countMinLeadingZeros());<br>
+ } else if (SPF == SPF_ABS) {<br>
+ // RHS from matchSelectPattern returns the negation part of abs pattern.<br>
+ // If the negate has an NSW flag we can assume the sign bit of the result<br>
+ // will be 0 because that makes abs(INT_MIN) undefined.<br>
+ if (cast<Instruction>(RHS)->hasNoSignedWrap())<br>
+ MaxHighZeros = 1;<br>
}<br>
<br>
// Only known if known in both the LHS and RHS.<br>
<br>
Modified: llvm/trunk/test/Transforms/InstCombine/abs-1.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/abs-1.ll?rev=333226&r1=333225&r2=333226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/abs-1.ll?rev=333226&r1=333225&r2=333226&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/Transforms/InstCombine/abs-1.ll (original)<br>
+++ llvm/trunk/test/Transforms/InstCombine/abs-1.ll Thu May 24 14:22:51 2018<br>
@@ -293,3 +293,14 @@ define <2 x i8> @negate_nabs(<2 x i8> %x<br>
%r = sub <2 x i8> zeroinitializer, %s<br>
ret <2 x i8> %r<br>
}<br>
+<br>
+define i1 @abs_must_be_positive(i32 %x) {<br>
+; CHECK-LABEL: @abs_must_be_positive(<br>
+; CHECK-NEXT: ret i1 true<br>
+;<br>
+ %negx = sub nsw i32 0, %x<br>
+ %c = icmp sge i32 %x, 0<br>
+ %sel = select i1 %c, i32 %x, i32 %negx<br>
+ %c2 = icmp sge i32 %sel, 0<br>
+ ret i1 %c2<br>
+}<br>
<br>
Modified: llvm/trunk/test/Transforms/InstCombine/abs_abs.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/abs_abs.ll?rev=333226&r1=333225&r2=333226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/abs_abs.ll?rev=333226&r1=333225&r2=333226&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/Transforms/InstCombine/abs_abs.ll (original)<br>
+++ llvm/trunk/test/Transforms/InstCombine/abs_abs.ll Thu May 24 14:22:51 2018<br>
@@ -933,8 +933,8 @@ define i32 @nabs_abs_x09(i32 %x) {<br>
; CHECK-LABEL: @nabs_abs_x09(<br>
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0<br>
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[X]]<br>
-; CHECK-NEXT: [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]<br>
-; CHECK-NEXT: ret i32 [[COND1]]<br>
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]<br>
+; CHECK-NEXT: ret i32 [[COND]]<br>
;<br>
%cmp = icmp sgt i32 %x, -1<br>
%sub = sub nsw i32 0, %x<br>
@@ -949,8 +949,8 @@ define i32 @nabs_abs_x10(i32 %x) {<br>
; CHECK-LABEL: @nabs_abs_x10(<br>
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0<br>
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[X]]<br>
-; CHECK-NEXT: [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]<br>
-; CHECK-NEXT: ret i32 [[COND1]]<br>
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]<br>
+; CHECK-NEXT: ret i32 [[COND]]<br>
;<br>
%cmp = icmp sgt i32 %x, 0<br>
%sub = sub nsw i32 0, %x<br>
@@ -965,8 +965,8 @@ define i32 @nabs_abs_x11(i32 %x) {<br>
; CHECK-LABEL: @nabs_abs_x11(<br>
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0<br>
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[X]]<br>
-; CHECK-NEXT: [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]<br>
-; CHECK-NEXT: ret i32 [[COND1]]<br>
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]<br>
+; CHECK-NEXT: ret i32 [[COND]]<br>
;<br>
%cmp = icmp slt i32 %x, 0<br>
%sub = sub nsw i32 0, %x<br>
@@ -981,8 +981,8 @@ define i32 @nabs_abs_x12(i32 %x) {<br>
; CHECK-LABEL: @nabs_abs_x12(<br>
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0<br>
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[X]]<br>
-; CHECK-NEXT: [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]<br>
-; CHECK-NEXT: ret i32 [[COND1]]<br>
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]<br>
+; CHECK-NEXT: ret i32 [[COND]]<br>
;<br>
%cmp = icmp slt i32 %x, 1<br>
%sub = sub nsw i32 0, %x<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
</blockquote></div>