<div dir="ltr"><div>Patch up for review: <a href="https://reviews.llvm.org/D46404">https://reviews.llvm.org/D46404</a></div><div><br></div>-Nirav</div><br><div class="gmail_quote"><div dir="ltr">On Thu, May 3, 2018 at 10:52 AM Nirav Davé <<a href="mailto:niravd@google.com">niravd@google.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">This looks like a we're finding an equivalence in the DAG and but keeping a stale reference. I'll take a little bit of time today and see if I can work this out. But I don't think this was so important a change <div>to merit keeping it. Let's plan on reverting this if we don't have something today.</div><div><br></div><div>-Nirav </div></div><br><div class="gmail_quote"><div dir="ltr">On Thu, May 3, 2018 at 10:03 AM Jesper Antonsson <<a href="mailto:jesper.antonsson@ericsson.com" target="_blank">jesper.antonsson@ericsson.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi all,<br>
<br>
We keep running into variations of this bug in our automated testing at Ericsson. Zhendong has registered 36602. Quentin has also<br>
registered a PR about this patch not doing what's intended in some case and giving him performance regressions. And Amaury doesn't<br>
seem to get back to us. Nirav, as you were one of the reviewers, do you have an idea about what to do about these issues? (I tried<br>
to look at it, but I'm too unfamiliar with the machinery.) Is it time to revert?<br>
<br>
BR, Jesper<br>
<br>
<br>
<br>
On mån, 2018-03-19 at 12:32 +0100, Mikael Holmén via llvm-commits wrote:<br>
> Hi Amaury,<br>
> <br>
> It seems like<br>
> <br>
> <a href="https://bugs.llvm.org/show_bug.cgi?id=36602" rel="noreferrer" target="_blank">https://bugs.llvm.org/show_bug.cgi?id=36602</a><br>
> <br>
> describes the same thing I found.<br>
> <br>
> Did you take a look at the problem?<br>
> <br>
> Regards,<br>
> Mikael<br>
> <br>
> On 03/14/2018 12:51 PM, Mikael Holmén wrote:<br>
> > <br>
> > Hi Amaury,<br>
> > <br>
> > llc crashes on the attached ll file crashes with your patch:<br>
> > <br>
> > llc -o - fail.ll -disable-cgp-branch-opts<br>
> > <br>
> > yields<br>
> > <br>
> > .text<br>
> > .file "fail.ll"<br>
> > Operand not processed?<br>
> > t13: ch = br t15, BasicBlock:ch<bb1 0x4250b98><br>
> > <br>
> > UNREACHABLE executed at ../lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:476!<br>
> > #0 0x0000000001e8a874 PrintStackTraceSignalHandler(void*) <br>
> > (build-all/bin/llc+0x1e8a874)<br>
> > #1 0x0000000001e8afe6 SignalHandler(int) (build-all/bin/llc+0x1e8afe6)<br>
> > #2 0x00007f950fde2330 __restore_rt <br>
> > (/lib/x86_64-linux-gnu/libpthread.so.0+0x10330)<br>
> > #3 0x00007f950e9d1c37 gsignal <br>
> > /build/eglibc-ripdx6/eglibc-2.19/signal/../nptl/sysdeps/unix/sysv/linux/raise.c:56:0 <br>
> > <br>
> > #4 0x00007f950e9d5028 abort <br>
> > /build/eglibc-ripdx6/eglibc-2.19/stdlib/abort.c:91:0<br>
> > #5 0x0000000001e41b5d llvm::llvm_unreachable_internal(char const*, char <br>
> > const*, unsigned int) (build-all/bin/llc+0x1e41b5d)<br>
> > #6 0x0000000001d9cbaf llvm::DAGTypeLegalizer::run() <br>
> > (build-all/bin/llc+0x1d9cbaf)<br>
> > #7 0x0000000001da29d5 llvm::SelectionDAG::LegalizeTypes() <br>
> > (build-all/bin/llc+0x1da29d5)<br>
> > #8 0x0000000001d567c9 llvm::SelectionDAGISel::CodeGenAndEmitDAG() <br>
> > (build-all/bin/llc+0x1d567c9)<br>
> > #9 0x0000000001d549e1 <br>
> > llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) <br>
> > (build-all/bin/llc+0x1d549e1)<br>
> > #10 0x0000000001d50ca9 <br>
> > llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) <br>
> > (build-all/bin/llc+0x1d50ca9)<br>
> > #11 0x000000000112b2a1 (anonymous <br>
> > namespace)::X86DAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&) (build-all/bin/llc+0x112b2a1) <br>
> > <br>
> > #12 0x00000000015fec79 <br>
> > llvm::MachineFunctionPass::runOnFunction(llvm::Function&) <br>
> > (build-all/bin/llc+0x15fec79)<br>
> > #13 0x0000000001904ce8 <br>
> > llvm::FPPassManager::runOnFunction(llvm::Function&) <br>
> > (build-all/bin/llc+0x1904ce8)<br>
> > #14 0x0000000001904f28 llvm::FPPassManager::runOnModule(llvm::Module&) <br>
> > (build-all/bin/llc+0x1904f28)<br>
> > #15 0x0000000001905405 llvm::legacy::PassManagerImpl::run(llvm::Module&) <br>
> > (build-all/bin/llc+0x1905405)<br>
> > #16 0x00000000006db358 compileModule(char**, llvm::LLVMContext&) <br>
> > (build-all/bin/llc+0x6db358)<br>
> > #17 0x00000000006d8acb main (build-all/bin/llc+0x6d8acb)<br>
> > #18 0x00007f950e9bcf45 __libc_start_main <br>
> > /build/eglibc-ripdx6/eglibc-2.19/csu/libc-start.c:321:0<br>
> > #19 0x00000000006d62ca _start (build-all/bin/llc+0x6d62ca)<br>
> > Stack dump:<br>
> > 0. Program arguments: build-all/bin/llc -o - fail.ll <br>
> > -disable-cgp-branch-opts<br>
> > 1. Running pass 'Function Pass Manager' on module 'fail.ll'.<br>
> > 2. Running pass 'X86 DAG->DAG Instruction Selection' on function <br>
> > '@fn2'<br>
> > Abort<br>
> > <br>
> > <br>
> > I just took a quick look in the debugger and saw that in <br>
> > DAGCombiner::rebuildSetCC() we end up at<br>
> > <br>
> > // Avoid missing important xor optimizations.<br>
> > while (SDValue Tmp = visitXOR(TheXor)) {<br>
> > // We don't have a XOR anymore, bail.<br>
> > if (Tmp.getOpcode() != ISD::XOR)<br>
> > return Tmp;<br>
> > <br>
> > And when we do the above<br>
> > <br>
> > return Tmp;<br>
> > <br>
> > Tmp is:<br>
> > <br>
> > (gdb) p Tmp->dump()<br>
> > t10: i1 = <<Deleted Node!>><br>
> > <br>
> > and this "Deleted Node" is then used to create a new brcond in <br>
> > DAGCombiner::visitBRCOND:<br>
> > <br>
> > if (SDValue NewN1 = rebuildSetCC(N1))<br>
> > return DAG.getNode(ISD::BRCOND, SDLoc(N), MVT::Other, Chain, <br>
> > NewN1, N2);<br>
> > <br>
> > <br>
> > We noticed this when we ran tests on csmith-generated code so it's not a <br>
> > huge issue for us but it's still a regression I thought you'd be <br>
> > interested in.<br>
> > <br>
> > Regards,<br>
> > Mikael<br>
> > <br>
> > On 02/23/2018 12:50 PM, Amaury Sechet via llvm-commits wrote:<br>
> > > <br>
> > > Author: deadalnix<br>
> > > Date: Fri Feb 23 03:50:42 2018<br>
> > > New Revision: 325892<br>
> > > <br>
> > > URL: <a href="http://llvm.org/viewvc/llvm-project?rev=325892&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=325892&view=rev</a><br>
> > > Log:<br>
> > > [DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a <br>
> > > canonical manner.<br>
> > > <br>
> > > Summary:<br>
> > > There are transformation that change setcc into other constructs, and <br>
> > > transform that try to reconstruct a setcc from the brcond condition. <br>
> > > Depending on what order these transform are done, the end result differs.<br>
> > > <br>
> > > Most of the time, it is preferable to get a setcc as a brcond argument <br>
> > > (and this is why brcond try to recreate the setcc in the first place) <br>
> > > so we ensure this is done every time by also doing it at the setcc <br>
> > > level when the only user is a brcond.<br>
> > > <br>
> > > Reviewers: spatel, hfinkel, niravd, craig.topper<br>
> > > <br>
> > > Subscribers: nhaehnle, llvm-commits<br>
> > > <br>
> > > Differential Revision: <a href="https://reviews.llvm.org/D41235" rel="noreferrer" target="_blank">https://reviews.llvm.org/D41235</a><br>
> > > <br>
> > > Modified:<br>
> > > llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
> > > llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td<br>
> > > llvm/trunk/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll<br>
> > > llvm/trunk/test/CodeGen/AMDGPU/setcc.ll<br>
> > > llvm/trunk/test/CodeGen/X86/and-sink.ll<br>
> > > llvm/trunk/test/CodeGen/X86/fold-rmw-ops.ll<br>
> > > llvm/trunk/test/CodeGen/X86/or-branch.ll<br>
> > > <br>
> > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
> > > URL: <br>
> > > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=325892&r1=325891&r2=325892&view=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=325892&r1=325891&r2=325892&view=</a><br>
> > > diff <br>
> > > <br>
> > > ============================================================================== <br>
> > > <br>
> > > --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
> > > +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Feb 23 <br>
> > > 03:50:42 2018<br>
> > > @@ -415,7 +415,8 @@ namespace {<br>
> > > SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,<br>
> > > const SDLoc &DL);<br>
> > > SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, <br>
> > > ISD::CondCode Cond,<br>
> > > - const SDLoc &DL, bool foldBooleans = true);<br>
> > > + const SDLoc &DL, bool foldBooleans);<br>
> > > + SDValue rebuildSetCC(SDValue N);<br>
> > > bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,<br>
> > > SDValue &CC) const;<br>
> > > @@ -7157,9 +7158,33 @@ SDValue DAGCombiner::visitSELECT_CC(SDNo<br>
> > > }<br>
> > > SDValue DAGCombiner::visitSETCC(SDNode *N) {<br>
> > > - return SimplifySetCC(N->getValueType(0), N->getOperand(0), <br>
> > > N->getOperand(1),<br>
> > > - cast<CondCodeSDNode>(N->getOperand(2))->get(),<br>
> > > - SDLoc(N));<br>
> > > + // setcc is very commonly used as an argument to brcond. This pattern<br>
> > > + // also lend itself to numerous combines and, as a result, it is <br>
> > > desired<br>
> > > + // we keep the argument to a brcond as a setcc as much as possible.<br>
> > > + bool PreferSetCC =<br>
> > > + N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND;<br>
> > > +<br>
> > > + SDValue Combined = SimplifySetCC(<br>
> > > + N->getValueType(0), N->getOperand(0), N->getOperand(1),<br>
> > > + cast<CondCodeSDNode>(N->getOperand(2))->get(), SDLoc(N), <br>
> > > !PreferSetCC);<br>
> > > +<br>
> > > + if (!Combined)<br>
> > > + return SDValue();<br>
> > > +<br>
> > > + // If we prefer to have a setcc, and we don't, we'll try our best to<br>
> > > + // recreate one using rebuildSetCC.<br>
> > > + if (PreferSetCC && Combined.getOpcode() != ISD::SETCC) {<br>
> > > + SDValue NewSetCC = rebuildSetCC(Combined);<br>
> > > +<br>
> > > + // We don't have anything interesting to combine to.<br>
> > > + if (NewSetCC.getNode() == N)<br>
> > > + return SDValue();<br>
> > > +<br>
> > > + if (NewSetCC)<br>
> > > + return NewSetCC;<br>
> > > + }<br>
> > > +<br>
> > > + return Combined;<br>
> > > }<br>
> > > SDValue DAGCombiner::visitSETCCE(SDNode *N) {<br>
> > > @@ -11151,16 +11176,22 @@ SDValue DAGCombiner::visitBRCOND(SDNode<br>
> > > N1.getOperand(0), N1.getOperand(1), N2);<br>
> > > }<br>
> > > - if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||<br>
> > > - ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&<br>
> > > - (N1.getOperand(0).hasOneUse() &&<br>
> > > - N1.getOperand(0).getOpcode() == ISD::SRL))) {<br>
> > > - SDNode *Trunc = nullptr;<br>
> > > - if (N1.getOpcode() == ISD::TRUNCATE) {<br>
> > > - // Look pass the truncate.<br>
> > > - Trunc = N1.getNode();<br>
> > > - N1 = N1.getOperand(0);<br>
> > > - }<br>
> > > + if (N1.hasOneUse()) {<br>
> > > + if (SDValue NewN1 = rebuildSetCC(N1))<br>
> > > + return DAG.getNode(ISD::BRCOND, SDLoc(N), MVT::Other, Chain, <br>
> > > NewN1, N2);<br>
> > > + }<br>
> > > +<br>
> > > + return SDValue();<br>
> > > +}<br>
> > > +<br>
> > > +SDValue DAGCombiner::rebuildSetCC(SDValue N) {<br>
> > > + if (N.getOpcode() == ISD::SRL ||<br>
> > > + (N.getOpcode() == ISD::TRUNCATE &&<br>
> > > + (N.getOperand(0).hasOneUse() &&<br>
> > > + N.getOperand(0).getOpcode() == ISD::SRL))) {<br>
> > > + // Look pass the truncate.<br>
> > > + if (N.getOpcode() == ISD::TRUNCATE)<br>
> > > + N = N.getOperand(0);<br>
> > > // Match this pattern so that we can generate simpler code:<br>
> > > //<br>
> > > @@ -11179,75 +11210,43 @@ SDValue DAGCombiner::visitBRCOND(SDNode<br>
> > > // This applies only when the AND constant value has one bit set <br>
> > > and the<br>
> > > // SRL constant is equal to the log2 of the AND constant. The <br>
> > > back-end is<br>
> > > // smart enough to convert the result into a TEST/JMP sequence.<br>
> > > - SDValue Op0 = N1.getOperand(0);<br>
> > > - SDValue Op1 = N1.getOperand(1);<br>
> > > + SDValue Op0 = N.getOperand(0);<br>
> > > + SDValue Op1 = N.getOperand(1);<br>
> > > - if (Op0.getOpcode() == ISD::AND &&<br>
> > > - Op1.getOpcode() == ISD::Constant) {<br>
> > > + if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == <br>
> > > ISD::Constant) {<br>
> > > SDValue AndOp1 = Op0.getOperand(1);<br>
> > > if (AndOp1.getOpcode() == ISD::Constant) {<br>
> > > const APInt &AndConst = <br>
> > > cast<ConstantSDNode>(AndOp1)->getAPIntValue();<br>
> > > if (AndConst.isPowerOf2() &&<br>
> > > - <br>
> > > cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {<br>
> > > + cast<ConstantSDNode>(Op1)->getAPIntValue() == <br>
> > > AndConst.logBase2()) {<br>
> > > SDLoc DL(N);<br>
> > > - SDValue SetCC =<br>
> > > - DAG.getSetCC(DL,<br>
> > > - getSetCCResultType(Op0.getValueType()),<br>
> > > - Op0, DAG.getConstant(0, DL, <br>
> > > Op0.getValueType()),<br>
> > > - ISD::SETNE);<br>
> > > -<br>
> > > - SDValue NewBRCond = DAG.getNode(ISD::BRCOND, DL,<br>
> > > - MVT::Other, Chain, SetCC, N2);<br>
> > > - // Don't add the new BRCond into the worklist or else <br>
> > > SimplifySelectCC<br>
> > > - // will convert it back to (X & C1) >> C2.<br>
> > > - CombineTo(N, NewBRCond, false);<br>
> > > - // Truncate is dead.<br>
> > > - if (Trunc)<br>
> > > - deleteAndRecombine(Trunc);<br>
> > > - // Replace the uses of SRL with SETCC<br>
> > > - WorklistRemover DeadNodes(*this);<br>
> > > - DAG.ReplaceAllUsesOfValueWith(N1, SetCC);<br>
> > > - deleteAndRecombine(N1.getNode());<br>
> > > - return SDValue(N, 0); // Return N so it doesn't get <br>
> > > rechecked!<br>
> > > + return DAG.getSetCC(DL, <br>
> > > getSetCCResultType(Op0.getValueType()),<br>
> > > + Op0, DAG.getConstant(0, DL, <br>
> > > Op0.getValueType()),<br>
> > > + ISD::SETNE);<br>
> > > }<br>
> > > }<br>
> > > }<br>
> > > -<br>
> > > - if (Trunc)<br>
> > > - // Restore N1 if the above transformation doesn't match.<br>
> > > - N1 = N->getOperand(1);<br>
> > > }<br>
> > > // Transform br(xor(x, y)) -> br(x != y)<br>
> > > // Transform br(xor(xor(x,y), 1)) -> br (x == y)<br>
> > > - if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {<br>
> > > - SDNode *TheXor = N1.getNode();<br>
> > > - SDValue Op0 = TheXor->getOperand(0);<br>
> > > - SDValue Op1 = TheXor->getOperand(1);<br>
> > > - if (Op0.getOpcode() == Op1.getOpcode()) {<br>
> > > - // Avoid missing important xor optimizations.<br>
> > > - if (SDValue Tmp = visitXOR(TheXor)) {<br>
> > > - if (Tmp.getNode() != TheXor) {<br>
> > > - DEBUG(dbgs() << "\nReplacing.8 ";<br>
> > > - TheXor->dump(&DAG);<br>
> > > - dbgs() << "\nWith: ";<br>
> > > - Tmp.getNode()->dump(&DAG);<br>
> > > - dbgs() << '\n');<br>
> > > - WorklistRemover DeadNodes(*this);<br>
> > > - DAG.ReplaceAllUsesOfValueWith(N1, Tmp);<br>
> > > - deleteAndRecombine(TheXor);<br>
> > > - return DAG.getNode(ISD::BRCOND, SDLoc(N),<br>
> > > - MVT::Other, Chain, Tmp, N2);<br>
> > > - }<br>
> > > + if (N.getOpcode() == ISD::XOR) {<br>
> > > + SDNode *TheXor = N.getNode();<br>
> > > - // visitXOR has changed XOR's operands or replaced the XOR <br>
> > > completely,<br>
> > > - // bail out.<br>
> > > - return SDValue(N, 0);<br>
> > > - }<br>
> > > + // Avoid missing important xor optimizations.<br>
> > > + while (SDValue Tmp = visitXOR(TheXor)) {<br>
> > > + // We don't have a XOR anymore, bail.<br>
> > > + if (Tmp.getOpcode() != ISD::XOR)<br>
> > > + return Tmp;<br>
> > > +<br>
> > > + TheXor = Tmp.getNode();<br>
> > > }<br>
> > > + SDValue Op0 = TheXor->getOperand(0);<br>
> > > + SDValue Op1 = TheXor->getOperand(1);<br>
> > > +<br>
> > > if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != <br>
> > > ISD::SETCC) {<br>
> > > bool Equal = false;<br>
> > > if (isOneConstant(Op0) && Op0.hasOneUse() &&<br>
> > > @@ -11256,19 +11255,12 @@ SDValue DAGCombiner::visitBRCOND(SDNode<br>
> > > Equal = true;<br>
> > > }<br>
> > > - EVT SetCCVT = N1.getValueType();<br>
> > > + EVT SetCCVT = N.getValueType();<br>
> > > if (LegalTypes)<br>
> > > SetCCVT = getSetCCResultType(SetCCVT);<br>
> > > - SDValue SetCC = DAG.getSetCC(SDLoc(TheXor),<br>
> > > - SetCCVT,<br>
> > > - Op0, Op1,<br>
> > > - Equal ? ISD::SETEQ : ISD::SETNE);<br>
> > > // Replace the uses of XOR with SETCC<br>
> > > - WorklistRemover DeadNodes(*this);<br>
> > > - DAG.ReplaceAllUsesOfValueWith(N1, SetCC);<br>
> > > - deleteAndRecombine(N1.getNode());<br>
> > > - return DAG.getNode(ISD::BRCOND, SDLoc(N),<br>
> > > - MVT::Other, Chain, SetCC, N2);<br>
> > > + return DAG.getSetCC(SDLoc(TheXor), SetCCVT, Op0, Op1,<br>
> > > + Equal ? ISD::SETEQ : ISD::SETNE);<br>
> > > }<br>
> > > }<br>
> > > <br>
> > > Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td<br>
> > > URL: <br>
> > > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=325892&r1=325891&r2=325892&view=dif" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=325892&r1=325891&r2=325892&view=dif</a><br>
> > > f <br>
> > > <br>
> > > ============================================================================== <br>
> > > <br>
> > > --- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)<br>
> > > +++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Fri Feb 23 <br>
> > > 03:50:42 2018<br>
> > > @@ -2800,6 +2800,8 @@ def: Pat<(brcond (not I1:$Pu), bb:$dst),<br>
> > > (J2_jumpf I1:$Pu, bb:$dst)>;<br>
> > > def: Pat<(brcond (i1 (setne I1:$Pu, -1)), bb:$dst),<br>
> > > (J2_jumpf I1:$Pu, bb:$dst)>;<br>
> > > +def: Pat<(brcond (i1 (seteq I1:$Pu, 0)), bb:$dst),<br>
> > > + (J2_jumpf I1:$Pu, bb:$dst)>;<br>
> > > def: Pat<(brcond (i1 (setne I1:$Pu, 0)), bb:$dst),<br>
> > > (J2_jumpt I1:$Pu, bb:$dst)>;<br>
> > > <br>
> > > Modified: llvm/trunk/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll<br>
> > > URL: <br>
> > > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll?rev=325892&r1=325891&r2=325892&view" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll?rev=325892&r1=325891&r2=325892&view</a><br>
> > > =diff <br>
> > > <br>
> > > ============================================================================== <br>
> > > <br>
> > > --- llvm/trunk/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll (original)<br>
> > > +++ llvm/trunk/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll Fri Feb 23 <br>
> > > 03:50:42 2018<br>
> > > @@ -7,7 +7,6 @@ declare i1 @llvm.amdgcn.class.f32(float,<br>
> > > ; GCN-LABEL: {{^}}vcc_shrink_vcc_def:<br>
> > > ; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}}<br>
> > > ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc<br>
> > > -; GCN: v_cndmask_b32_e64 v0, 0, 1, s{{\[[0-9]+:[0-9]+\]}}<br>
> > > define amdgpu_kernel void @vcc_shrink_vcc_def(float %arg, i32 %arg1, <br>
> > > float %arg2, i32 %arg3) {<br>
> > > bb0:<br>
> > > %tmp = icmp sgt i32 %arg1, 4<br>
> > > @@ -34,7 +33,6 @@ bb2:<br>
> > > ; GCN-LABEL: {{^}}preserve_condition_undef_flag:<br>
> > > ; GCN-NOT: vcc<br>
> > > ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc<br>
> > > -; GCN: v_cndmask_b32_e64 v0, 0, 1, s{{\[[0-9]+:[0-9]+\]}}<br>
> > > define amdgpu_kernel void @preserve_condition_undef_flag(float %arg, <br>
> > > i32 %arg1, float %arg2) {<br>
> > > bb0:<br>
> > > %tmp = icmp sgt i32 %arg1, 4<br>
> > > <br>
> > > Modified: llvm/trunk/test/CodeGen/AMDGPU/setcc.ll<br>
> > > URL: <br>
> > > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/setcc.ll?rev=325892&r1=325891&r2=325892&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/setcc.ll?rev=325892&r1=325891&r2=325892&view=diff</a> <br>
> > > <br>
> > > ============================================================================== <br>
> > > <br>
> > > --- llvm/trunk/test/CodeGen/AMDGPU/setcc.ll (original)<br>
> > > +++ llvm/trunk/test/CodeGen/AMDGPU/setcc.ll Fri Feb 23 03:50:42 2018<br>
> > > @@ -397,9 +397,9 @@ endif:<br>
> > > }<br>
> > > ; FUNC-LABEL: setcc-i1-and-xor<br>
> > > -; GCN-DAG: v_cmp_ge_f32_e64 [[A:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, <br>
> > > 0{{$}}<br>
> > > -; GCN-DAG: v_cmp_le_f32_e64 [[B:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 1.0<br>
> > > -; GCN: s_and_b64 s[2:3], [[A]], [[B]]<br>
> > > +; GCN-DAG: v_cmp_nge_f32_e64 [[A:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, <br>
> > > 0{{$}}<br>
> > > +; GCN-DAG: v_cmp_nle_f32_e64 [[B:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 1.0<br>
> > > +; GCN: s_or_b64 s[2:3], [[A]], [[B]]<br>
> > > define amdgpu_kernel void @setcc-i1-and-xor(i32 addrspace(1)* %out, <br>
> > > float %cond) #0 {<br>
> > > bb0:<br>
> > > %tmp5 = fcmp oge float %cond, 0.000000e+00<br>
> > > <br>
> > > Modified: llvm/trunk/test/CodeGen/X86/and-sink.ll<br>
> > > URL: <br>
> > > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/and-sink.ll?rev=325892&r1=325891&r2=325892&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/and-sink.ll?rev=325892&r1=325891&r2=325892&view=diff</a> <br>
> > > <br>
> > > ============================================================================== <br>
> > > <br>
> > > --- llvm/trunk/test/CodeGen/X86/and-sink.ll (original)<br>
> > > +++ llvm/trunk/test/CodeGen/X86/and-sink.ll Fri Feb 23 03:50:42 2018<br>
> > > @@ -14,8 +14,8 @@ define i32 @and_sink1(i32 %a, i1 %c) {<br>
> > > ; CHECK-NEXT: je .LBB0_3<br>
> > > ; CHECK-NEXT: # %bb.1: # %bb0<br>
> > > ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
> > > -; CHECK-NEXT: movl $0, A<br>
> > > ; CHECK-NEXT: testb $4, %al<br>
> > > +; CHECK-NEXT: movl $0, A<br>
> > > ; CHECK-NEXT: jne .LBB0_3<br>
> > > ; CHECK-NEXT: # %bb.2: # %bb1<br>
> > > ; CHECK-NEXT: movl $1, %eax<br>
> > > @@ -61,8 +61,8 @@ define i32 @and_sink2(i32 %a, i1 %c, i1<br>
> > > ; CHECK-NEXT: je .LBB1_5<br>
> > > ; CHECK-NEXT: # %bb.3: # %bb1<br>
> > > ; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1<br>
> > > -; CHECK-NEXT: movl $0, C<br>
> > > ; CHECK-NEXT: testb $4, %cl<br>
> > > +; CHECK-NEXT: movl $0, C<br>
> > > ; CHECK-NEXT: jne .LBB1_2<br>
> > > ; CHECK-NEXT: # %bb.4: # %bb2<br>
> > > ; CHECK-NEXT: movl $1, %eax<br>
> > > <br>
> > > Modified: llvm/trunk/test/CodeGen/X86/fold-rmw-ops.ll<br>
> > > URL: <br>
> > > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-rmw-ops.ll?rev=325892&r1=325891&r2=325892&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-rmw-ops.ll?rev=325892&r1=325891&r2=325892&view=diff</a> <br>
> > > <br>
> > > ============================================================================== <br>
> > > <br>
> > > --- llvm/trunk/test/CodeGen/X86/fold-rmw-ops.ll (original)<br>
> > > +++ llvm/trunk/test/CodeGen/X86/fold-rmw-ops.ll Fri Feb 23 03:50:42 2018<br>
> > > @@ -1146,12 +1146,9 @@ b:<br>
> > > define void @and32_imm_br() nounwind {<br>
> > > ; CHECK-LABEL: and32_imm_br:<br>
> > > ; CHECK: # %bb.0: # %entry<br>
> > > -; CHECK-NEXT: movl $-2147483648, %eax # encoding: <br>
> > > [0xb8,0x00,0x00,0x00,0x80]<br>
> > > +; CHECK-NEXT: andl $-2147483648, {{.*}}(%rip) # encoding: <br>
> > > [0x81,0x25,A,A,A,A,0x00,0x00,0x00,0x80]<br>
> > > +; CHECK-NEXT: # fixup A - offset: 2, value: g32-8, kind: <br>
> > > reloc_riprel_4byte<br>
> > > ; CHECK-NEXT: # imm = 0x80000000<br>
> > > -; CHECK-NEXT: andl {{.*}}(%rip), %eax # encoding: [0x23,0x05,A,A,A,A]<br>
> > > -; CHECK-NEXT: # fixup A - offset: 2, value: g32-4, kind: <br>
> > > reloc_riprel_4byte<br>
> > > -; CHECK-NEXT: movl %eax, {{.*}}(%rip) # encoding: [0x89,0x05,A,A,A,A]<br>
> > > -; CHECK-NEXT: # fixup A - offset: 2, value: g32-4, kind: <br>
> > > reloc_riprel_4byte<br>
> > > ; CHECK-NEXT: jne .LBB35_2 # encoding: [0x75,A]<br>
> > > ; CHECK-NEXT: # fixup A - offset: 1, value: .LBB35_2-1, kind: <br>
> > > FK_PCRel_1<br>
> > > ; CHECK-NEXT: # %bb.1: # %a<br>
> > > @@ -1244,13 +1241,9 @@ b:<br>
> > > define void @and16_imm_br() nounwind {<br>
> > > ; CHECK-LABEL: and16_imm_br:<br>
> > > ; CHECK: # %bb.0: # %entry<br>
> > > -; CHECK-NEXT: movzwl {{.*}}(%rip), %eax # encoding: <br>
> > > [0x0f,0xb7,0x05,A,A,A,A]<br>
> > > -; CHECK-NEXT: # fixup A - offset: 3, value: g16-4, kind: <br>
> > > reloc_riprel_4byte<br>
> > > -; CHECK-NEXT: andl $32768, %eax # encoding: <br>
> > > [0x25,0x00,0x80,0x00,0x00]<br>
> > > +; CHECK-NEXT: andw $-32768, {{.*}}(%rip) # encoding: <br>
> > > [0x66,0x81,0x25,A,A,A,A,0x00,0x80]<br>
> > > +; CHECK-NEXT: # fixup A - offset: 3, value: g16-6, kind: <br>
> > > reloc_riprel_4byte<br>
> > > ; CHECK-NEXT: # imm = 0x8000<br>
> > > -; CHECK-NEXT: movw %ax, {{.*}}(%rip) # encoding: <br>
> > > [0x66,0x89,0x05,A,A,A,A]<br>
> > > -; CHECK-NEXT: # fixup A - offset: 3, value: g16-4, kind: <br>
> > > reloc_riprel_4byte<br>
> > > -; CHECK-NEXT: testw %ax, %ax # encoding: [0x66,0x85,0xc0]<br>
> > > ; CHECK-NEXT: jne .LBB38_2 # encoding: [0x75,A]<br>
> > > ; CHECK-NEXT: # fixup A - offset: 1, value: .LBB38_2-1, kind: <br>
> > > FK_PCRel_1<br>
> > > ; CHECK-NEXT: # %bb.1: # %a<br>
> > > <br>
> > > Modified: llvm/trunk/test/CodeGen/X86/or-branch.ll<br>
> > > URL: <br>
> > > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/or-branch.ll?rev=325892&r1=325891&r2=325892&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/or-branch.ll?rev=325892&r1=325891&r2=325892&view=diff</a> <br>
> > > <br>
> > > ============================================================================== <br>
> > > <br>
> > > --- llvm/trunk/test/CodeGen/X86/or-branch.ll (original)<br>
> > > +++ llvm/trunk/test/CodeGen/X86/or-branch.ll Fri Feb 23 03:50:42 2018<br>
> > > @@ -19,11 +19,10 @@ define void @foo(i32 %X, i32 %Y, i32 %Z)<br>
> > > ; JUMP1-LABEL: foo:<br>
> > > ; JUMP1: # %bb.0: # %entry<br>
> > > ; JUMP1-NEXT: cmpl $0, {{[0-9]+}}(%esp)<br>
> > > -; JUMP1-NEXT: sete %al<br>
> > > -; JUMP1-NEXT: cmpl $5, {{[0-9]+}}(%esp)<br>
> > > -; JUMP1-NEXT: setl %cl<br>
> > > -; JUMP1-NEXT: orb %al, %cl<br>
> > > -; JUMP1-NEXT: cmpb $1, %cl<br>
> > > +; JUMP1-NEXT: setne %al<br>
> > > +; JUMP1-NEXT: cmpl $4, {{[0-9]+}}(%esp)<br>
> > > +; JUMP1-NEXT: setg %cl<br>
> > > +; JUMP1-NEXT: testb %al, %cl<br>
> > > ; JUMP1-NEXT: jne .LBB0_1<br>
> > > ; JUMP1-NEXT: # %bb.2: # %cond_true<br>
> > > ; JUMP1-NEXT: jmp bar # TAILCALL<br>
> > > @@ -50,11 +49,10 @@ define void @unpredictable(i32 %X, i32 %<br>
> > > ; JUMP2-LABEL: unpredictable:<br>
> > > ; JUMP2: # %bb.0: # %entry<br>
> > > ; JUMP2-NEXT: cmpl $0, {{[0-9]+}}(%esp)<br>
> > > -; JUMP2-NEXT: sete %al<br>
> > > -; JUMP2-NEXT: cmpl $5, {{[0-9]+}}(%esp)<br>
> > > -; JUMP2-NEXT: setl %cl<br>
> > > -; JUMP2-NEXT: orb %al, %cl<br>
> > > -; JUMP2-NEXT: cmpb $1, %cl<br>
> > > +; JUMP2-NEXT: setne %al<br>
> > > +; JUMP2-NEXT: cmpl $4, {{[0-9]+}}(%esp)<br>
> > > +; JUMP2-NEXT: setg %cl<br>
> > > +; JUMP2-NEXT: testb %al, %cl<br>
> > > ; JUMP2-NEXT: jne .LBB1_1<br>
> > > ; JUMP2-NEXT: # %bb.2: # %cond_true<br>
> > > ; JUMP2-NEXT: jmp bar # TAILCALL<br>
> > > @@ -64,11 +62,10 @@ define void @unpredictable(i32 %X, i32 %<br>
> > > ; JUMP1-LABEL: unpredictable:<br>
> > > ; JUMP1: # %bb.0: # %entry<br>
> > > ; JUMP1-NEXT: cmpl $0, {{[0-9]+}}(%esp)<br>
> > > -; JUMP1-NEXT: sete %al<br>
> > > -; JUMP1-NEXT: cmpl $5, {{[0-9]+}}(%esp)<br>
> > > -; JUMP1-NEXT: setl %cl<br>
> > > -; JUMP1-NEXT: orb %al, %cl<br>
> > > -; JUMP1-NEXT: cmpb $1, %cl<br>
> > > +; JUMP1-NEXT: setne %al<br>
> > > +; JUMP1-NEXT: cmpl $4, {{[0-9]+}}(%esp)<br>
> > > +; JUMP1-NEXT: setg %cl<br>
> > > +; JUMP1-NEXT: testb %al, %cl<br>
> > > ; JUMP1-NEXT: jne .LBB1_1<br>
> > > ; JUMP1-NEXT: # %bb.2: # %cond_true<br>
> > > ; JUMP1-NEXT: jmp bar # TAILCALL<br>
> > > <br>
> > > <br>
> > > _______________________________________________<br>
> > > llvm-commits mailing list<br>
> > > <a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
> > > <a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
> > > <br>
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