<div dir="ltr"><div>We're seeing a similar error I've reduced to this IR. You just need to run with "llc -O0"</div><div><br></div><div><div>; ModuleID = 'bugpoint-reduced-simplified.ll'</div><div>target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"<br></div><div>target triple = "x86_64-unknown-linux-gnu"</div><div><br></div><div>; Function Attrs: cold noinline nounwind optnone uwtable</div><div>define hidden void @foo() #0 {</div><div>bb:</div><div> br label %bb1</div><div><br></div><div>bb1: ; preds = %bb3, %bb</div><div> %tmp = icmp ne i32 0, 0</div><div> br i1 %tmp, label %bb2, label %bb3</div><div><br></div><div>bb2: ; preds = %bb1</div><div> br label %bb3</div><div><br></div><div>bb3: ; preds = %bb2, %bb1</div><div> br label %bb1</div><div>}</div><div><br></div><div>attributes #0 = { noinline nounwind optnone uwtable "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" }</div></div><div><br></div><br clear="all"><div><div dir="ltr" class="gmail_signature">~Craig</div></div><br></div><br><div class="gmail_quote"><div dir="ltr">On Tue, May 1, 2018 at 1:35 PM Vlad Tsyrklevich via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hello, this change is causing a build failure during a Chromium build with a particular build configuration. The build fails with:<div><div>*** Inconsistent CFA register and/or offset between pred and succ ***</div><div>Pred: outgoing CFA Reg:6</div><div>Pred: outgoing CFA Offset:16</div><div>Succ: incoming CFA Reg:7</div><div>Succ: incoming CFA Offset:8</div></div><div><br></div><div>A minimized test case is included below that fails to compile with clang++ -fuse-ld=lld -fsanitize=cfi -fwhole-program-vtables -flto -fvisibility=hidden -g -O2 -fno-omit-frame-pointer<div><br></div><div>I'm not very familiar with how debug information is handled in LLVM; however, it appears that call frame information might not be correctly preserved when calls to TRAP instructions are inlined.</div><div><br></div><div>The test case:</div><div><div>#include <stdio.h></div><div> </div><div>class A {</div><div> public:</div><div> virtual void f() { printf("A\n"); }</div><div>};</div><div>class B {</div><div> public:</div><div> virtual void f() { printf("B\n"); }</div><div>};</div><div><br></div><div>void c(void) {</div><div> volatile void *b = (void*)new A;</div><div> // Unsatisfiable with cfi-vcall, hence always results in a call to llvm.trap()</div><div> ((B*)b)->f();</div><div>}</div><div><br></div><div>int main(int argc, char *argv[]) {</div><div> if (argv) {</div><div> char foo[8];</div><div> printf("a");</div><div> c();</div><div> } else {</div><div> c();</div><div> }</div><div>}</div><div><br></div><div>The failing MIR:</div><div><div># Machine code for function main: NoPHIs, TracksLiveness, NoVRegs</div><div>Frame Objects:</div><div> fi#-1: size=8, align=16, fixed, at location [SP-8]</div><div>Function Live Ins: $rsi</div><div><br></div><div>bb.0 (%ir-block.2):</div><div> successors: %bb.2(0x40000000), %bb.1(0x40000000); %bb.2(50.00%), %bb.1(50.00%)</div><div> liveins: $rsi</div><div> DBG_VALUE debug-use $edi, debug-use $noreg, !"argc", !DIExpression(), debug-location !29; line no:18</div><div> DBG_VALUE debug-use $rsi, debug-use $noreg, !"argv", !DIExpression(), debug-location !30; line no:18</div><div> DBG_VALUE debug-use $rsi, debug-use $noreg, !"argv", !DIExpression(), debug-location !30; line no:18</div><div> TEST64rr killed renamable $rsi, renamable $rsi, implicit-def $eflags, debug-location !31</div><div> JE_1 %bb.2, implicit $eflags, debug-location !32</div><div><br></div><div>bb.1 (%ir-block.4):</div><div>; predecessors: %bb.0</div><div> successors: %bb.2(0x80000000); %bb.2(200.00%)</div><div><br></div><div> DBG_VALUE debug-use $rsi, debug-use $noreg, !"argv", !DIExpression(), debug-location !30; line no:18</div><div> DBG_VALUE debug-use $edi, debug-use $noreg, !"argc", !DIExpression(), debug-location !29; line no:18</div><div> frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp</div><div> CFI_INSTRUCTION def_cfa_offset 16</div><div> CFI_INSTRUCTION offset $rbp, -16</div><div> $rbp = frame-setup MOV64rr $rsp</div><div> CFI_INSTRUCTION def_cfa_register $rbp</div><div> $edi = MOV32ri 97, debug-location !33</div><div> CALL64pcrel32 @putchar, <regmask $bh $bl $bp $bpl $bx $ebp $ebx $hbp $hbx $rbp $rbx $r12 $r13 $r14 $r15 $r12b $r13b $r14b $r15b $r12d $r13d $r14d $r15d $r12w $r13w $r14w $r15w>, implicit $rsp, implicit $ssp, implicit killed $edi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eax, debug-location !33</div><div><br></div><div>bb.2 (%ir-block.6):</div><div>; predecessors: %bb.0, %bb.1</div><div><br></div><div> TRAP debug-location !43</div><div><br></div><div># End machine code for function main.</div></div><div><br></div><div class="gmail_quote"><div dir="ltr">On Tue, Apr 24, 2018 at 3:35 AM Petar Jovanovic via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: petarj<br>
Date: Tue Apr 24 03:32:08 2018<br>
New Revision: 330706<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=330706&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=330706&view=rev</a><br>
Log:<br>
Correct dwarf unwind information in function epilogue<br>
<br>
This patch aims to provide correct dwarf unwind information in function<br>
epilogue for X86.<br>
It consists of two parts. The first part inserts CFI instructions that set<br>
appropriate cfa offset and cfa register in emitEpilogue() in<br>
X86FrameLowering. This part is X86 specific.<br>
<br>
The second part is platform independent and ensures that:<br>
<br>
* CFI instructions do not affect code generation (they are not counted as<br>
instructions when tail duplicating or tail merging)<br>
* Unwind information remains correct when a function is modified by<br>
different passes. This is done in a late pass by analyzing information<br>
about cfa offset and cfa register in BBs and inserting additional CFI<br>
directives where necessary.<br>
<br>
Added CFIInstrInserter pass:<br>
<br>
* analyzes each basic block to determine cfa offset and register are valid<br>
at its entry and exit<br>
* verifies that outgoing cfa offset and register of predecessor blocks match<br>
incoming values of their successors<br>
* inserts additional CFI directives at basic block beginning to correct the<br>
rule for calculating CFA<br>
<br>
Having CFI instructions in function epilogue can cause incorrect CFA<br>
calculation rule for some basic blocks. This can happen if, due to basic<br>
block reordering, or the existence of multiple epilogue blocks, some of the<br>
blocks have wrong cfa offset and register values set by the epilogue block<br>
above them.<br>
CFIInstrInserter is currently run only on X86, but can be used by any target<br>
that implements support for adding CFI instructions in epilogue.<br>
<br>
Patch by Violeta Vukobrat.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D42848" rel="noreferrer" target="_blank">https://reviews.llvm.org/D42848</a><br>
<br>
Added:<br>
llvm/trunk/lib/CodeGen/CFIInstrInserter.cpp<br>
llvm/trunk/test/CodeGen/X86/cfi-inserter-check-order.ll<br>
llvm/trunk/test/CodeGen/X86/epilogue-cfi-fp.ll<br>
llvm/trunk/test/CodeGen/X86/epilogue-cfi-no-fp.ll<br>
llvm/trunk/test/CodeGen/X86/merge-sp-updates-cfi.ll<br>
llvm/trunk/test/CodeGen/X86/throws-cfi-fp.ll<br>
llvm/trunk/test/CodeGen/X86/throws-cfi-no-fp.ll<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/Passes.h<br>
llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h<br>
llvm/trunk/include/llvm/InitializePasses.h<br>
llvm/trunk/lib/CodeGen/BranchFolding.cpp<br>
llvm/trunk/lib/CodeGen/CMakeLists.txt<br>
llvm/trunk/lib/CodeGen/CodeGen.cpp<br>
llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp<br>
llvm/trunk/lib/Target/X86/X86FrameLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86FrameLowering.h<br>
llvm/trunk/lib/Target/X86/X86TargetMachine.cpp<br>
llvm/trunk/test/CodeGen/AArch64/taildup-cfi.ll<br>
llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll<br>
llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll<br>
llvm/trunk/test/CodeGen/X86/GlobalISel/brcond.ll<br>
llvm/trunk/test/CodeGen/X86/GlobalISel/callingconv.ll<br>
llvm/trunk/test/CodeGen/X86/GlobalISel/frameIndex.ll<br>
llvm/trunk/test/CodeGen/X86/O0-pipeline.ll<br>
llvm/trunk/test/CodeGen/X86/O3-pipeline.ll<br>
llvm/trunk/test/CodeGen/X86/TruncAssertZext.ll<br>
llvm/trunk/test/CodeGen/X86/avoid-sfb.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-regcall-Mask.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-select.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll<br>
llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-fast-isel.ll<br>
llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll<br>
llvm/trunk/test/CodeGen/X86/avx512vl-vbroadcast.ll<br>
llvm/trunk/test/CodeGen/X86/bool-vector.ll<br>
llvm/trunk/test/CodeGen/X86/cmp.ll<br>
llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll<br>
llvm/trunk/test/CodeGen/X86/emutls-pie.ll<br>
llvm/trunk/test/CodeGen/X86/emutls.ll<br>
llvm/trunk/test/CodeGen/X86/fast-isel-int-float-conversion.ll<br>
llvm/trunk/test/CodeGen/X86/fast-isel-store.ll<br>
llvm/trunk/test/CodeGen/X86/fmaxnum.ll<br>
llvm/trunk/test/CodeGen/X86/fminnum.ll<br>
llvm/trunk/test/CodeGen/X86/fp-arith.ll<br>
llvm/trunk/test/CodeGen/X86/frame-lowering-debug-intrinsic-2.ll<br>
llvm/trunk/test/CodeGen/X86/frame-lowering-debug-intrinsic.ll<br>
llvm/trunk/test/CodeGen/X86/h-registers-1.ll<br>
llvm/trunk/test/CodeGen/X86/haddsub-2.ll<br>
llvm/trunk/test/CodeGen/X86/hipe-cc64.ll<br>
llvm/trunk/test/CodeGen/X86/illegal-bitfield-loadstore.ll<br>
llvm/trunk/test/CodeGen/X86/imul.ll<br>
llvm/trunk/test/CodeGen/X86/lea-opt-cse1.ll<br>
llvm/trunk/test/CodeGen/X86/lea-opt-cse2.ll<br>
llvm/trunk/test/CodeGen/X86/lea-opt-cse3.ll<br>
llvm/trunk/test/CodeGen/X86/lea-opt-cse4.ll<br>
llvm/trunk/test/CodeGen/X86/legalize-shift-64.ll<br>
llvm/trunk/test/CodeGen/X86/legalize-shl-vec.ll<br>
llvm/trunk/test/CodeGen/X86/live-out-reg-info.ll<br>
llvm/trunk/test/CodeGen/X86/load-combine.ll<br>
llvm/trunk/test/CodeGen/X86/masked_gather_scatter.ll<br>
llvm/trunk/test/CodeGen/X86/memset-nonzero.ll<br>
llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll<br>
llvm/trunk/test/CodeGen/X86/mmx-arith.ll<br>
llvm/trunk/test/CodeGen/X86/movtopush.ll<br>
llvm/trunk/test/CodeGen/X86/mul-constant-result.ll<br>
llvm/trunk/test/CodeGen/X86/mul-i256.ll<br>
llvm/trunk/test/CodeGen/X86/mul128.ll<br>
llvm/trunk/test/CodeGen/X86/musttail-varargs.ll<br>
llvm/trunk/test/CodeGen/X86/pr21792.ll<br>
llvm/trunk/test/CodeGen/X86/pr29061.ll<br>
llvm/trunk/test/CodeGen/X86/pr29112.ll<br>
llvm/trunk/test/CodeGen/X86/pr30430.ll<br>
llvm/trunk/test/CodeGen/X86/pr32241.ll<br>
llvm/trunk/test/CodeGen/X86/pr32256.ll<br>
llvm/trunk/test/CodeGen/X86/pr32282.ll<br>
llvm/trunk/test/CodeGen/X86/pr32284.ll<br>
llvm/trunk/test/CodeGen/X86/pr32329.ll<br>
llvm/trunk/test/CodeGen/X86/pr32345.ll<br>
llvm/trunk/test/CodeGen/X86/pr32451.ll<br>
llvm/trunk/test/CodeGen/X86/pr34088.ll<br>
llvm/trunk/test/CodeGen/X86/pr34592.ll<br>
llvm/trunk/test/CodeGen/X86/pr34653.ll<br>
llvm/trunk/test/CodeGen/X86/pr9743.ll<br>
llvm/trunk/test/CodeGen/X86/push-cfi-debug.ll<br>
llvm/trunk/test/CodeGen/X86/push-cfi-obj.ll<br>
llvm/trunk/test/CodeGen/X86/push-cfi.ll<br>
llvm/trunk/test/CodeGen/X86/rdtsc.ll<br>
llvm/trunk/test/CodeGen/X86/return-ext.ll<br>
llvm/trunk/test/CodeGen/X86/rtm.ll<br>
llvm/trunk/test/CodeGen/X86/schedule-x86_32.ll<br>
llvm/trunk/test/CodeGen/X86/select-mmx.ll<br>
llvm/trunk/test/CodeGen/X86/setcc-lowering.ll<br>
llvm/trunk/test/CodeGen/X86/shrink_vmul.ll<br>
llvm/trunk/test/CodeGen/X86/stack-probe-red-zone.ll<br>
llvm/trunk/test/CodeGen/X86/statepoint-call-lowering.ll<br>
llvm/trunk/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll<br>
llvm/trunk/test/CodeGen/X86/statepoint-invoke.ll<br>
llvm/trunk/test/CodeGen/X86/statepoint-vector.ll<br>
llvm/trunk/test/CodeGen/X86/swift-return.ll<br>
llvm/trunk/test/CodeGen/X86/test-shrink-bug.ll<br>
llvm/trunk/test/CodeGen/X86/test-vs-bittest.ll<br>
llvm/trunk/test/CodeGen/X86/vector-arith-sat.ll<br>
llvm/trunk/test/CodeGen/X86/vector-sext.ll<br>
llvm/trunk/test/CodeGen/X86/vector-shuffle-avx512.ll<br>
llvm/trunk/test/CodeGen/X86/wide-integer-cmp.ll<br>
llvm/trunk/test/CodeGen/X86/x86-64-psub.ll<br>
llvm/trunk/test/CodeGen/X86/x86-framelowering-trap.ll<br>
llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll<br>
llvm/trunk/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/Passes.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/Passes.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/Passes.h Tue Apr 24 03:32:08 2018<br>
@@ -434,6 +434,9 @@ namespace llvm {<br>
// This pass expands indirectbr instructions.<br>
FunctionPass *createIndirectBrExpandPass();<br>
<br>
+ /// Creates CFI Instruction Inserter pass. \see CFIInstrInserter.cpp<br>
+ FunctionPass *createCFIInstrInserter();<br>
+<br>
} // End llvm namespace<br>
<br>
#endif<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h Tue Apr 24 03:32:08 2018<br>
@@ -345,6 +345,14 @@ public:<br>
return false;<br>
return true;<br>
}<br>
+<br>
+ /// Return initial CFA offset value i.e. the one valid at the beginning of the<br>
+ /// function (before any stack operations).<br>
+ virtual int getInitialCFAOffset(const MachineFunction &MF) const;<br>
+<br>
+ /// Return initial CFA register value i.e. the one valid at the beginning of<br>
+ /// the function (before any stack operations).<br>
+ virtual unsigned getInitialCFARegister(const MachineFunction &MF) const;<br>
};<br>
<br>
} // End llvm namespace<br>
<br>
Modified: llvm/trunk/include/llvm/InitializePasses.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/InitializePasses.h (original)<br>
+++ llvm/trunk/include/llvm/InitializePasses.h Tue Apr 24 03:32:08 2018<br>
@@ -91,6 +91,7 @@ void initializeCFGOnlyViewerLegacyPassPa<br>
void initializeCFGPrinterLegacyPassPass(PassRegistry&);<br>
void initializeCFGSimplifyPassPass(PassRegistry&);<br>
void initializeCFGViewerLegacyPassPass(PassRegistry&);<br>
+void initializeCFIInstrInserterPass(PassRegistry&);<br>
void initializeCFLAndersAAWrapperPassPass(PassRegistry&);<br>
void initializeCFLSteensAAWrapperPassPass(PassRegistry&);<br>
void initializeCallGraphDOTPrinterPass(PassRegistry&);<br>
<br>
Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Apr 24 03:32:08 2018<br>
@@ -296,6 +296,11 @@ static unsigned HashEndOfMBB(const Machi<br>
return HashMachineInstr(*I);<br>
}<br>
<br>
+/// Whether MI should be counted as an instruction when calculating common tail.<br>
+static bool countsAsInstruction(const MachineInstr &MI) {<br>
+ return !(MI.isDebugValue() || MI.isCFIInstruction());<br>
+}<br>
+<br>
/// ComputeCommonTailLength - Given two machine basic blocks, compute the number<br>
/// of instructions they actually have in common together at their end. Return<br>
/// iterators for the first shared instruction in each block.<br>
@@ -310,26 +315,27 @@ static unsigned ComputeCommonTailLength(<br>
while (I1 != MBB1->begin() && I2 != MBB2->begin()) {<br>
--I1; --I2;<br>
// Skip debugging pseudos; necessary to avoid changing the code.<br>
- while (I1->isDebugValue()) {<br>
+ while (!countsAsInstruction(*I1)) {<br>
if (I1==MBB1->begin()) {<br>
- while (I2->isDebugValue()) {<br>
- if (I2==MBB2->begin())<br>
+ while (!countsAsInstruction(*I2)) {<br>
+ if (I2==MBB2->begin()) {<br>
// I1==DBG at begin; I2==DBG at begin<br>
- return TailLen;<br>
+ goto SkipTopCFIAndReturn;<br>
+ }<br>
--I2;<br>
}<br>
++I2;<br>
// I1==DBG at begin; I2==non-DBG, or first of DBGs not at begin<br>
- return TailLen;<br>
+ goto SkipTopCFIAndReturn;<br>
}<br>
--I1;<br>
}<br>
// I1==first (untested) non-DBG preceding known match<br>
- while (I2->isDebugValue()) {<br>
+ while (!countsAsInstruction(*I2)) {<br>
if (I2==MBB2->begin()) {<br>
++I1;<br>
// I1==non-DBG, or first of DBGs not at begin; I2==DBG at begin<br>
- return TailLen;<br>
+ goto SkipTopCFIAndReturn;<br>
}<br>
--I2;<br>
}<br>
@@ -368,6 +374,37 @@ static unsigned ComputeCommonTailLength(<br>
}<br>
++I1;<br>
}<br>
+<br>
+SkipTopCFIAndReturn:<br>
+ // Ensure that I1 and I2 do not point to a CFI_INSTRUCTION. This can happen if<br>
+ // I1 and I2 are non-identical when compared and then one or both of them ends<br>
+ // up pointing to a CFI instruction after being incremented. For example:<br>
+ /*<br>
+ BB1:<br>
+ ...<br>
+ INSTRUCTION_A<br>
+ ADD32ri8 <- last common instruction<br>
+ ...<br>
+ BB2:<br>
+ ...<br>
+ INSTRUCTION_B<br>
+ CFI_INSTRUCTION<br>
+ ADD32ri8 <- last common instruction<br>
+ ...<br>
+ */<br>
+ // When INSTRUCTION_A and INSTRUCTION_B are compared as not equal, after<br>
+ // incrementing the iterators, I1 will point to ADD, however I2 will point to<br>
+ // the CFI instruction. Later on, this leads to BB2 being 'hacked off' at the<br>
+ // wrong place (in ReplaceTailWithBranchTo()) which results in losing this CFI<br>
+ // instruction.<br>
+ while (I1 != MBB1->end() && I1->isCFIInstruction()) {<br>
+ ++I1;<br>
+ }<br>
+<br>
+ while (I2 != MBB2->end() && I2->isCFIInstruction()) {<br>
+ ++I2;<br>
+ }<br>
+<br>
return TailLen;<br>
}<br>
<br>
@@ -454,7 +491,7 @@ static unsigned EstimateRuntime(MachineB<br>
MachineBasicBlock::iterator E) {<br>
unsigned Time = 0;<br>
for (; I != E; ++I) {<br>
- if (I->isDebugValue())<br>
+ if (!countsAsInstruction(*I))<br>
continue;<br>
if (I->isCall())<br>
Time += 10;<br>
@@ -814,12 +851,12 @@ mergeOperations(MachineBasicBlock::itera<br>
assert(MBBI != MBBIE && "Reached BB end within common tail length!");<br>
(void)MBBIE;<br>
<br>
- if (MBBI->isDebugValue()) {<br>
+ if (!countsAsInstruction(*MBBI)) {<br>
++MBBI;<br>
continue;<br>
}<br>
<br>
- while ((MBBICommon != MBBIECommon) && MBBICommon->isDebugValue())<br>
+ while ((MBBICommon != MBBIECommon) && !countsAsInstruction(*MBBICommon))<br>
++MBBICommon;<br>
<br>
assert(MBBICommon != MBBIECommon &&<br>
@@ -859,7 +896,7 @@ void BranchFolder::mergeCommonTails(unsi<br>
}<br>
<br>
for (auto &MI : *MBB) {<br>
- if (MI.isDebugValue())<br>
+ if (!countsAsInstruction(MI))<br>
continue;<br>
DebugLoc DL = MI.getDebugLoc();<br>
for (unsigned int i = 0 ; i < NextCommonInsts.size() ; i++) {<br>
@@ -869,7 +906,7 @@ void BranchFolder::mergeCommonTails(unsi<br>
auto &Pos = NextCommonInsts[i];<br>
assert(Pos != SameTails[i].getBlock()->end() &&<br>
"Reached BB end within common tail");<br>
- while (Pos->isDebugValue()) {<br>
+ while (!countsAsInstruction(*Pos)) {<br>
++Pos;<br>
assert(Pos != SameTails[i].getBlock()->end() &&<br>
"Reached BB end within common tail");<br>
<br>
Added: llvm/trunk/lib/CodeGen/CFIInstrInserter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CFIInstrInserter.cpp?rev=330706&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CFIInstrInserter.cpp?rev=330706&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/CFIInstrInserter.cpp (added)<br>
+++ llvm/trunk/lib/CodeGen/CFIInstrInserter.cpp Tue Apr 24 03:32:08 2018<br>
@@ -0,0 +1,308 @@<br>
+//===------ CFIInstrInserter.cpp - Insert additional CFI instructions -----===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file This pass verifies incoming and outgoing CFA information of basic<br>
+/// blocks. CFA information is information about offset and register set by CFI<br>
+/// directives, valid at the start and end of a basic block. This pass checks<br>
+/// that outgoing information of predecessors matches incoming information of<br>
+/// their successors. Then it checks if blocks have correct CFA calculation rule<br>
+/// set and inserts additional CFI instruction at their beginnings if they<br>
+/// don't. CFI instructions are inserted if basic blocks have incorrect offset<br>
+/// or register set by previous blocks, as a result of a non-linear layout of<br>
+/// blocks in a function.<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "llvm/CodeGen/MachineFunctionPass.h"<br>
+#include "llvm/CodeGen/MachineInstrBuilder.h"<br>
+#include "llvm/CodeGen/MachineModuleInfo.h"<br>
+#include "llvm/CodeGen/Passes.h"<br>
+#include "llvm/CodeGen/TargetFrameLowering.h"<br>
+#include "llvm/CodeGen/TargetInstrInfo.h"<br>
+#include "llvm/CodeGen/TargetSubtargetInfo.h"<br>
+#include "llvm/Target/TargetMachine.h"<br>
+using namespace llvm;<br>
+<br>
+namespace {<br>
+class CFIInstrInserter : public MachineFunctionPass {<br>
+ public:<br>
+ static char ID;<br>
+<br>
+ CFIInstrInserter() : MachineFunctionPass(ID) {<br>
+ initializeCFIInstrInserterPass(*PassRegistry::getPassRegistry());<br>
+ }<br>
+<br>
+ void getAnalysisUsage(AnalysisUsage &AU) const override {<br>
+ AU.setPreservesAll();<br>
+ MachineFunctionPass::getAnalysisUsage(AU);<br>
+ }<br>
+<br>
+ bool runOnMachineFunction(MachineFunction &MF) override {<br>
+ if (!MF.getMMI().hasDebugInfo() &&<br>
+ !MF.getFunction().needsUnwindTableEntry())<br>
+ return false;<br>
+<br>
+ MBBVector.resize(MF.getNumBlockIDs());<br>
+ calculateCFAInfo(MF);<br>
+#ifndef NDEBUG<br>
+ if (unsigned ErrorNum = verify(MF))<br>
+ report_fatal_error("Found " + Twine(ErrorNum) +<br>
+ " in/out CFI information errors.");<br>
+#endif<br>
+ bool insertedCFI = insertCFIInstrs(MF);<br>
+ MBBVector.clear();<br>
+ return insertedCFI;<br>
+ }<br>
+<br>
+ private:<br>
+ struct MBBCFAInfo {<br>
+ MachineBasicBlock *MBB;<br>
+ /// Value of cfa offset valid at basic block entry.<br>
+ int IncomingCFAOffset = -1;<br>
+ /// Value of cfa offset valid at basic block exit.<br>
+ int OutgoingCFAOffset = -1;<br>
+ /// Value of cfa register valid at basic block entry.<br>
+ unsigned IncomingCFARegister = 0;<br>
+ /// Value of cfa register valid at basic block exit.<br>
+ unsigned OutgoingCFARegister = 0;<br>
+ /// If in/out cfa offset and register values for this block have already<br>
+ /// been set or not.<br>
+ bool Processed = false;<br>
+ };<br>
+<br>
+ /// Contains cfa offset and register values valid at entry and exit of basic<br>
+ /// blocks.<br>
+ std::vector<MBBCFAInfo> MBBVector;<br>
+<br>
+ /// Calculate cfa offset and register values valid at entry and exit for all<br>
+ /// basic blocks in a function.<br>
+ void calculateCFAInfo(MachineFunction &MF);<br>
+ /// Calculate cfa offset and register values valid at basic block exit by<br>
+ /// checking the block for CFI instructions. Block's incoming CFA info remains<br>
+ /// the same.<br>
+ void calculateOutgoingCFAInfo(MBBCFAInfo &MBBInfo);<br>
+ /// Update in/out cfa offset and register values for successors of the basic<br>
+ /// block.<br>
+ void updateSuccCFAInfo(MBBCFAInfo &MBBInfo);<br>
+<br>
+ /// Check if incoming CFA information of a basic block matches outgoing CFA<br>
+ /// information of the previous block. If it doesn't, insert CFI instruction<br>
+ /// at the beginning of the block that corrects the CFA calculation rule for<br>
+ /// that block.<br>
+ bool insertCFIInstrs(MachineFunction &MF);<br>
+ /// Return the cfa offset value that should be set at the beginning of a MBB<br>
+ /// if needed. The negated value is needed when creating CFI instructions that<br>
+ /// set absolute offset.<br>
+ int getCorrectCFAOffset(MachineBasicBlock *MBB) {<br>
+ return -MBBVector[MBB->getNumber()].IncomingCFAOffset;<br>
+ }<br>
+<br>
+ void report(const MBBCFAInfo &Pred, const MBBCFAInfo &Succ);<br>
+ /// Go through each MBB in a function and check that outgoing offset and<br>
+ /// register of its predecessors match incoming offset and register of that<br>
+ /// MBB, as well as that incoming offset and register of its successors match<br>
+ /// outgoing offset and register of the MBB.<br>
+ unsigned verify(MachineFunction &MF);<br>
+};<br>
+} // namespace<br>
+<br>
+char CFIInstrInserter::ID = 0;<br>
+INITIALIZE_PASS(CFIInstrInserter, "cfi-instr-inserter",<br>
+ "Check CFA info and insert CFI instructions if needed", false,<br>
+ false)<br>
+FunctionPass *llvm::createCFIInstrInserter() { return new CFIInstrInserter(); }<br>
+<br>
+void CFIInstrInserter::calculateCFAInfo(MachineFunction &MF) {<br>
+ // Initial CFA offset value i.e. the one valid at the beginning of the<br>
+ // function.<br>
+ int InitialOffset =<br>
+ MF.getSubtarget().getFrameLowering()->getInitialCFAOffset(MF);<br>
+ // Initial CFA register value i.e. the one valid at the beginning of the<br>
+ // function.<br>
+ unsigned InitialRegister =<br>
+ MF.getSubtarget().getFrameLowering()->getInitialCFARegister(MF);<br>
+<br>
+ // Initialize MBBMap.<br>
+ for (MachineBasicBlock &MBB : MF) {<br>
+ MBBCFAInfo MBBInfo;<br>
+ MBBInfo.MBB = &MBB;<br>
+ MBBInfo.IncomingCFAOffset = InitialOffset;<br>
+ MBBInfo.OutgoingCFAOffset = InitialOffset;<br>
+ MBBInfo.IncomingCFARegister = InitialRegister;<br>
+ MBBInfo.OutgoingCFARegister = InitialRegister;<br>
+ MBBVector[MBB.getNumber()] = MBBInfo;<br>
+ }<br>
+<br>
+ // Set in/out cfa info for all blocks in the function. This traversal is based<br>
+ // on the assumption that the first block in the function is the entry block<br>
+ // i.e. that it has initial cfa offset and register values as incoming CFA<br>
+ // information.<br>
+ for (MachineBasicBlock &MBB : MF) {<br>
+ if (MBBVector[MBB.getNumber()].Processed) continue;<br>
+ calculateOutgoingCFAInfo(MBBVector[MBB.getNumber()]);<br>
+ updateSuccCFAInfo(MBBVector[MBB.getNumber()]);<br>
+ }<br>
+}<br>
+<br>
+void CFIInstrInserter::calculateOutgoingCFAInfo(MBBCFAInfo &MBBInfo) {<br>
+ // Outgoing cfa offset set by the block.<br>
+ int SetOffset = MBBInfo.IncomingCFAOffset;<br>
+ // Outgoing cfa register set by the block.<br>
+ unsigned SetRegister = MBBInfo.IncomingCFARegister;<br>
+ const std::vector<MCCFIInstruction> &Instrs =<br>
+ MBBInfo.MBB->getParent()->getFrameInstructions();<br>
+<br>
+ // Determine cfa offset and register set by the block.<br>
+ for (MachineInstr &MI : *MBBInfo.MBB) {<br>
+ if (MI.isCFIInstruction()) {<br>
+ unsigned CFIIndex = MI.getOperand(0).getCFIIndex();<br>
+ const MCCFIInstruction &CFI = Instrs[CFIIndex];<br>
+ switch (CFI.getOperation()) {<br>
+ case MCCFIInstruction::OpDefCfaRegister:<br>
+ SetRegister = CFI.getRegister();<br>
+ break;<br>
+ case MCCFIInstruction::OpDefCfaOffset:<br>
+ SetOffset = CFI.getOffset();<br>
+ break;<br>
+ case MCCFIInstruction::OpAdjustCfaOffset:<br>
+ SetOffset += CFI.getOffset();<br>
+ break;<br>
+ case MCCFIInstruction::OpDefCfa:<br>
+ SetRegister = CFI.getRegister();<br>
+ SetOffset = CFI.getOffset();<br>
+ break;<br>
+ case MCCFIInstruction::OpRememberState:<br>
+ // TODO: Add support for handling cfi_remember_state.<br>
+#ifndef NDEBUG<br>
+ report_fatal_error(<br>
+ "Support for cfi_remember_state not implemented! Value of CFA "<br>
+ "may be incorrect!\n");<br>
+#endif<br>
+ break;<br>
+ case MCCFIInstruction::OpRestoreState:<br>
+ // TODO: Add support for handling cfi_restore_state.<br>
+#ifndef NDEBUG<br>
+ report_fatal_error(<br>
+ "Support for cfi_restore_state not implemented! Value of CFA may "<br>
+ "be incorrect!\n");<br>
+#endif<br>
+ break;<br>
+ // Other CFI directives do not affect CFA value.<br>
+ case MCCFIInstruction::OpSameValue:<br>
+ case MCCFIInstruction::OpOffset:<br>
+ case MCCFIInstruction::OpRelOffset:<br>
+ case MCCFIInstruction::OpEscape:<br>
+ case MCCFIInstruction::OpRestore:<br>
+ case MCCFIInstruction::OpUndefined:<br>
+ case MCCFIInstruction::OpRegister:<br>
+ case MCCFIInstruction::OpWindowSave:<br>
+ case MCCFIInstruction::OpGnuArgsSize:<br>
+ break;<br>
+ }<br>
+ }<br>
+ }<br>
+<br>
+ MBBInfo.Processed = true;<br>
+<br>
+ // Update outgoing CFA info.<br>
+ MBBInfo.OutgoingCFAOffset = SetOffset;<br>
+ MBBInfo.OutgoingCFARegister = SetRegister;<br>
+}<br>
+<br>
+void CFIInstrInserter::updateSuccCFAInfo(MBBCFAInfo &MBBInfo) {<br>
+ for (MachineBasicBlock *Succ : MBBInfo.MBB->successors()) {<br>
+ MBBCFAInfo &SuccInfo = MBBVector[Succ->getNumber()];<br>
+ if (SuccInfo.Processed) continue;<br>
+ SuccInfo.IncomingCFAOffset = MBBInfo.OutgoingCFAOffset;<br>
+ SuccInfo.IncomingCFARegister = MBBInfo.OutgoingCFARegister;<br>
+ calculateOutgoingCFAInfo(SuccInfo);<br>
+ updateSuccCFAInfo(SuccInfo);<br>
+ }<br>
+}<br>
+<br>
+bool CFIInstrInserter::insertCFIInstrs(MachineFunction &MF) {<br>
+ const MBBCFAInfo *PrevMBBInfo = &MBBVector[MF.front().getNumber()];<br>
+ const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();<br>
+ bool InsertedCFIInstr = false;<br>
+<br>
+ for (MachineBasicBlock &MBB : MF) {<br>
+ // Skip the first MBB in a function<br>
+ if (MBB.getNumber() == MF.front().getNumber()) continue;<br>
+<br>
+ const MBBCFAInfo &MBBInfo = MBBVector[MBB.getNumber()];<br>
+ auto MBBI = MBBInfo.MBB->begin();<br>
+ DebugLoc DL = MBBInfo.MBB->findDebugLoc(MBBI);<br>
+<br>
+ if (PrevMBBInfo->OutgoingCFAOffset != MBBInfo.IncomingCFAOffset) {<br>
+ // If both outgoing offset and register of a previous block don't match<br>
+ // incoming offset and register of this block, add a def_cfa instruction<br>
+ // with the correct offset and register for this block.<br>
+ if (PrevMBBInfo->OutgoingCFARegister != MBBInfo.IncomingCFARegister) {<br>
+ unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(<br>
+ nullptr, MBBInfo.IncomingCFARegister, getCorrectCFAOffset(&MBB)));<br>
+ BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))<br>
+ .addCFIIndex(CFIIndex);<br>
+ // If outgoing offset of a previous block doesn't match incoming offset<br>
+ // of this block, add a def_cfa_offset instruction with the correct<br>
+ // offset for this block.<br>
+ } else {<br>
+ unsigned CFIIndex =<br>
+ MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(<br>
+ nullptr, getCorrectCFAOffset(&MBB)));<br>
+ BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))<br>
+ .addCFIIndex(CFIIndex);<br>
+ }<br>
+ InsertedCFIInstr = true;<br>
+ // If outgoing register of a previous block doesn't match incoming<br>
+ // register of this block, add a def_cfa_register instruction with the<br>
+ // correct register for this block.<br>
+ } else if (PrevMBBInfo->OutgoingCFARegister !=<br>
+ MBBInfo.IncomingCFARegister) {<br>
+ unsigned CFIIndex =<br>
+ MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(<br>
+ nullptr, MBBInfo.IncomingCFARegister));<br>
+ BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))<br>
+ .addCFIIndex(CFIIndex);<br>
+ InsertedCFIInstr = true;<br>
+ }<br>
+ PrevMBBInfo = &MBBInfo;<br>
+ }<br>
+ return InsertedCFIInstr;<br>
+}<br>
+<br>
+void CFIInstrInserter::report(const MBBCFAInfo &Pred,<br>
+ const MBBCFAInfo &Succ) {<br>
+ errs() << "*** Inconsistent CFA register and/or offset between pred and succ "<br>
+ "***\n";<br>
+ errs() << "Pred: " << Pred.MBB->getName()<br>
+ << " outgoing CFA Reg:" << Pred.OutgoingCFARegister << "\n";<br>
+ errs() << "Pred: " << Pred.MBB->getName()<br>
+ << " outgoing CFA Offset:" << Pred.OutgoingCFAOffset << "\n";<br>
+ errs() << "Succ: " << Succ.MBB->getName()<br>
+ << " incoming CFA Reg:" << Succ.IncomingCFARegister << "\n";<br>
+ errs() << "Succ: " << Succ.MBB->getName()<br>
+ << " incoming CFA Offset:" << Succ.IncomingCFAOffset << "\n";<br>
+}<br>
+<br>
+unsigned CFIInstrInserter::verify(MachineFunction &MF) {<br>
+ unsigned ErrorNum = 0;<br>
+ for (MachineBasicBlock &CurrMBB : MF) {<br>
+ const MBBCFAInfo &CurrMBBInfo = MBBVector[CurrMBB.getNumber()];<br>
+ for (MachineBasicBlock *Succ : CurrMBB.successors()) {<br>
+ const MBBCFAInfo &SuccMBBInfo = MBBVector[Succ->getNumber()];<br>
+ // Check that incoming offset and register values of successors match the<br>
+ // outgoing offset and register values of CurrMBB<br>
+ if (SuccMBBInfo.IncomingCFAOffset != CurrMBBInfo.OutgoingCFAOffset ||<br>
+ SuccMBBInfo.IncomingCFARegister != CurrMBBInfo.OutgoingCFARegister) {<br>
+ report(CurrMBBInfo, SuccMBBInfo);<br>
+ ErrorNum++;<br>
+ }<br>
+ }<br>
+ }<br>
+ return ErrorNum;<br>
+}<br>
<br>
Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/CMakeLists.txt (original)<br>
+++ llvm/trunk/lib/CodeGen/CMakeLists.txt Tue Apr 24 03:32:08 2018<br>
@@ -10,6 +10,7 @@ add_llvm_library(LLVMCodeGen<br>
BuiltinGCs.cpp<br>
CalcSpillWeights.cpp<br>
CallingConvLower.cpp<br>
+ CFIInstrInserter.cpp<br>
CodeGen.cpp<br>
CodeGenPrepare.cpp<br>
CriticalAntiDepBreaker.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/CodeGen.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CodeGen.cpp?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CodeGen.cpp?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/CodeGen.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/CodeGen.cpp Tue Apr 24 03:32:08 2018<br>
@@ -23,6 +23,7 @@ void llvm::initializeCodeGen(PassRegistr<br>
initializeAtomicExpandPass(Registry);<br>
initializeBranchFolderPassPass(Registry);<br>
initializeBranchRelaxationPass(Registry);<br>
+ initializeCFIInstrInserterPass(Registry);<br>
initializeCodeGenPreparePass(Registry);<br>
initializeDeadMachineInstructionElimPass(Registry);<br>
initializeDetectDeadLanesPass(Registry);<br>
<br>
Modified: llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp Tue Apr 24 03:32:08 2018<br>
@@ -124,3 +124,12 @@ unsigned TargetFrameLowering::getStackAl<br>
<br>
return 0;<br>
}<br>
+<br>
+int TargetFrameLowering::getInitialCFAOffset(const MachineFunction &MF) const {<br>
+ llvm_unreachable("getInitialCFAOffset() not implemented!");<br>
+}<br>
+<br>
+unsigned TargetFrameLowering::getInitialCFARegister(const MachineFunction &MF)<br>
+ const {<br>
+ llvm_unreachable("getInitialCFARegister() not implemented!");<br>
+}<br>
\ No newline at end of file<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Apr 24 03:32:08 2018<br>
@@ -399,28 +399,30 @@ int X86FrameLowering::mergeSPUpdates(Mac<br>
return 0;<br>
<br>
MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;<br>
- MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr<br>
- : std::next(MBBI);<br>
+<br>
PI = skipDebugInstructionsBackward(PI, MBB.begin());<br>
- if (NI != nullptr)<br>
- NI = skipDebugInstructionsForward(NI, MBB.end());<br>
+ // It is assumed that ADD/SUB/LEA instruction is succeded by one CFI<br>
+ // instruction, and that there are no DBG_VALUE or other instructions between<br>
+ // ADD/SUB/LEA and its corresponding CFI instruction.<br>
+ /* TODO: Add support for the case where there are multiple CFI instructions<br>
+ below the ADD/SUB/LEA, e.g.:<br>
+ ...<br>
+ add<br>
+ cfi_def_cfa_offset<br>
+ cfi_offset<br>
+ ...<br>
+ */<br>
+ if (doMergeWithPrevious && PI != MBB.begin() && PI->isCFIInstruction())<br>
+ PI = std::prev(PI);<br>
<br>
unsigned Opc = PI->getOpcode();<br>
int Offset = 0;<br>
<br>
- if (!doMergeWithPrevious && NI != MBB.end() &&<br>
- NI->getOpcode() == TargetOpcode::CFI_INSTRUCTION) {<br>
- // Don't merge with the next instruction if it has CFI.<br>
- return Offset;<br>
- }<br>
-<br>
if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||<br>
Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&<br>
PI->getOperand(0).getReg() == StackPtr){<br>
assert(PI->getOperand(1).getReg() == StackPtr);<br>
- Offset += PI->getOperand(2).getImm();<br>
- MBB.erase(PI);<br>
- if (!doMergeWithPrevious) MBBI = NI;<br>
+ Offset = PI->getOperand(2).getImm();<br>
} else if ((Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&<br>
PI->getOperand(0).getReg() == StackPtr &&<br>
PI->getOperand(1).getReg() == StackPtr &&<br>
@@ -428,17 +430,19 @@ int X86FrameLowering::mergeSPUpdates(Mac<br>
PI->getOperand(3).getReg() == X86::NoRegister &&<br>
PI->getOperand(5).getReg() == X86::NoRegister) {<br>
// For LEAs we have: def = lea SP, FI, noreg, Offset, noreg.<br>
- Offset += PI->getOperand(4).getImm();<br>
- MBB.erase(PI);<br>
- if (!doMergeWithPrevious) MBBI = NI;<br>
+ Offset = PI->getOperand(4).getImm();<br>
} else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||<br>
Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&<br>
PI->getOperand(0).getReg() == StackPtr) {<br>
assert(PI->getOperand(1).getReg() == StackPtr);<br>
- Offset -= PI->getOperand(2).getImm();<br>
- MBB.erase(PI);<br>
- if (!doMergeWithPrevious) MBBI = NI;<br>
- }<br>
+ Offset = -PI->getOperand(2).getImm();<br>
+ } else<br>
+ return 0;<br>
+<br>
+ PI = MBB.erase(PI);<br>
+ if (PI != MBB.end() && PI->isCFIInstruction()) PI = MBB.erase(PI);<br>
+ if (!doMergeWithPrevious)<br>
+ MBBI = skipDebugInstructionsForward(PI, MBB.end());<br>
<br>
return Offset;<br>
}<br>
@@ -1573,6 +1577,11 @@ void X86FrameLowering::emitEpilogue(Mach<br>
bool HasFP = hasFP(MF);<br>
uint64_t NumBytes = 0;<br>
<br>
+ bool NeedsDwarfCFI =<br>
+ (!MF.getTarget().getTargetTriple().isOSDarwin() &&<br>
+ !MF.getTarget().getTargetTriple().isOSWindows()) &&<br>
+ (MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry());<br>
+<br>
if (IsFunclet) {<br>
assert(HasFP && "EH funclets without FP not yet implemented");<br>
NumBytes = getWinEHFuncletFrameSize(MF);<br>
@@ -1595,6 +1604,13 @@ void X86FrameLowering::emitEpilogue(Mach<br>
BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),<br>
MachineFramePtr)<br>
.setMIFlag(MachineInstr::FrameDestroy);<br>
+ if (NeedsDwarfCFI) {<br>
+ unsigned DwarfStackPtr =<br>
+ TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true);<br>
+ BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfa(<br>
+ nullptr, DwarfStackPtr, -SlotSize));<br>
+ --MBBI;<br>
+ }<br>
}<br>
<br>
MachineBasicBlock::iterator FirstCSPop = MBBI;<br>
@@ -1658,6 +1674,11 @@ void X86FrameLowering::emitEpilogue(Mach<br>
} else if (NumBytes) {<br>
// Adjust stack pointer back: ESP += numbytes.<br>
emitSPUpdate(MBB, MBBI, DL, NumBytes, /*InEpilogue=*/true);<br>
+ if (!hasFP(MF) && NeedsDwarfCFI) {<br>
+ // Define the current CFA rule to use the provided offset.<br>
+ BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(<br>
+ nullptr, -CSSize - SlotSize));<br>
+ }<br>
--MBBI;<br>
}<br>
<br>
@@ -1670,6 +1691,23 @@ void X86FrameLowering::emitEpilogue(Mach<br>
if (NeedsWin64CFI && MF.hasWinCFI())<br>
BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));<br>
<br>
+ if (!hasFP(MF) && NeedsDwarfCFI) {<br>
+ MBBI = FirstCSPop;<br>
+ int64_t Offset = -CSSize - SlotSize;<br>
+ // Mark callee-saved pop instruction.<br>
+ // Define the current CFA rule to use the provided offset.<br>
+ while (MBBI != MBB.end()) {<br>
+ MachineBasicBlock::iterator PI = MBBI;<br>
+ unsigned Opc = PI->getOpcode();<br>
+ ++MBBI;<br>
+ if (Opc == X86::POP32r || Opc == X86::POP64r) {<br>
+ Offset += SlotSize;<br>
+ BuildCFI(MBB, MBBI, DL,<br>
+ MCCFIInstruction::createDefCfaOffset(nullptr, Offset));<br>
+ }<br>
+ }<br>
+ }<br>
+<br>
if (Terminator == MBB.end() || !isTailCallOpcode(Terminator->getOpcode())) {<br>
// Add the return addr area delta back since we are not tail calling.<br>
int Offset = -1 * X86FI->getTCReturnAddrDelta();<br>
@@ -2719,7 +2757,6 @@ eliminateCallFramePseudoInstr(MachineFun<br>
<br>
// Add Amount to SP to destroy a frame, or subtract to setup.<br>
int64_t StackAdjustment = isDestroy ? Amount : -Amount;<br>
- int64_t CfaAdjustment = -StackAdjustment;<br>
<br>
if (StackAdjustment) {<br>
// Merge with any previous or following adjustment instruction. Note: the<br>
@@ -2744,6 +2781,7 @@ eliminateCallFramePseudoInstr(MachineFun<br>
// offset to be correct at each call site, while for debugging we want<br>
// it to be more precise.<br>
<br>
+ int64_t CfaAdjustment = -StackAdjustment;<br>
// TODO: When not using precise CFA, we also need to adjust for the<br>
// InternalAmt here.<br>
if (CfaAdjustment) {<br>
@@ -2874,6 +2912,15 @@ MachineBasicBlock::iterator X86FrameLowe<br>
return MBBI;<br>
}<br>
<br>
+int X86FrameLowering::getInitialCFAOffset(const MachineFunction &MF) const {<br>
+ return TRI->getSlotSize();<br>
+}<br>
+<br>
+unsigned X86FrameLowering::getInitialCFARegister(const MachineFunction &MF)<br>
+ const {<br>
+ return TRI->getDwarfRegNum(StackPtr, true);<br>
+}<br>
+<br>
namespace {<br>
// Struct used by orderFrameObjects to help sort the stack objects.<br>
struct X86FrameSortingObject {<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.h?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.h?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86FrameLowering.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.h Tue Apr 24 03:32:08 2018<br>
@@ -168,6 +168,10 @@ public:<br>
MachineBasicBlock::iterator MBBI,<br>
const DebugLoc &DL, bool RestoreSP = false) const;<br>
<br>
+ int getInitialCFAOffset(const MachineFunction &MF) const override;<br>
+<br>
+ unsigned getInitialCFARegister(const MachineFunction &MF) const override;<br>
+<br>
private:<br>
uint64_t calculateMaxStackAlign(const MachineFunction &MF) const;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Tue Apr 24 03:32:08 2018<br>
@@ -495,4 +495,10 @@ void X86PassConfig::addPreEmitPass() {<br>
<br>
void X86PassConfig::addPreEmitPass2() {<br>
addPass(createX86RetpolineThunksPass());<br>
+ // Verify basic block incoming and outgoing cfa offset and register values and<br>
+ // correct CFA calculation rule where needed by inserting appropriate CFI<br>
+ // instructions.<br>
+ const Triple &TT = TM->getTargetTriple();<br>
+ if (!TT.isOSDarwin() && !TT.isOSWindows())<br>
+ addPass(createCFIInstrInserter());<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/taildup-cfi.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/taildup-cfi.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/taildup-cfi.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/taildup-cfi.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/taildup-cfi.ll Tue Apr 24 03:32:08 2018<br>
@@ -2,8 +2,6 @@<br>
; RUN: llc -mtriple=arm64-unknown-linux-gnu -debug-only=tailduplication %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=LINUX<br>
; RUN: llc -mtriple=arm64-apple-darwin -debug-only=tailduplication %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN<br>
<br>
-; ModuleID = 'taildup-cfi.c'<br>
-source_filename = "taildup-cfi.c"<br>
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"<br>
<br>
@g = common local_unnamed_addr global i32 0, align 4<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll Tue Apr 24 03:32:08 2018<br>
@@ -23,6 +23,7 @@ lpad: ; preds = %cont, %entry<br>
}<br>
<br>
; CHECK: lpad<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 16<br>
; CHECK-NEXT: Ltmp<br>
<br>
declare i32 @__gxx_personality_v0(...)<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll Tue Apr 24 03:32:08 2018<br>
@@ -87,6 +87,7 @@ define void @full_test() {<br>
; X32-NEXT: movss %xmm4, {{[0-9]+}}(%esp)<br>
; X32-NEXT: movss %xmm0, {{[0-9]+}}(%esp)<br>
; X32-NEXT: addl $60, %esp<br>
+; X32-NEXT: .cfi_def_cfa_offset 4<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: full_test:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/brcond.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/brcond.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/brcond.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/GlobalISel/brcond.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/brcond.ll Tue Apr 24 03:32:08 2018<br>
@@ -36,6 +36,7 @@ define i32 @test_1(i32 %a, i32 %b, i32 %<br>
; X32-NEXT: movl %eax, (%esp)<br>
; X32-NEXT: movl (%esp), %eax<br>
; X32-NEXT: popl %ecx<br>
+; X32-NEXT: .cfi_def_cfa_offset 4<br>
; X32-NEXT: retl<br>
entry:<br>
%retval = alloca i32, align 4<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/callingconv.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/callingconv.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/callingconv.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/GlobalISel/callingconv.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/callingconv.ll Tue Apr 24 03:32:08 2018<br>
@@ -117,6 +117,7 @@ define <8 x i32> @test_v8i32_args(<8 x i<br>
; X32-NEXT: movups {{[0-9]+}}(%esp), %xmm1<br>
; X32-NEXT: movaps %xmm2, %xmm0<br>
; X32-NEXT: addl $12, %esp<br>
+; X32-NEXT: .cfi_def_cfa_offset 4<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_v8i32_args:<br>
@@ -135,6 +136,7 @@ define void @test_trivial_call() {<br>
; X32-NEXT: .cfi_def_cfa_offset 16<br>
; X32-NEXT: calll trivial_callee<br>
; X32-NEXT: addl $12, %esp<br>
+; X32-NEXT: .cfi_def_cfa_offset 4<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_trivial_call:<br>
@@ -143,6 +145,7 @@ define void @test_trivial_call() {<br>
; X64-NEXT: .cfi_def_cfa_offset 16<br>
; X64-NEXT: callq trivial_callee<br>
; X64-NEXT: popq %rax<br>
+; X64-NEXT: .cfi_def_cfa_offset 8<br>
; X64-NEXT: retq<br>
call void @trivial_callee()<br>
ret void<br>
@@ -160,6 +163,7 @@ define void @test_simple_arg_call(i32 %i<br>
; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)<br>
; X32-NEXT: calll simple_arg_callee<br>
; X32-NEXT: addl $12, %esp<br>
+; X32-NEXT: .cfi_def_cfa_offset 4<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_simple_arg_call:<br>
@@ -171,6 +175,7 @@ define void @test_simple_arg_call(i32 %i<br>
; X64-NEXT: movl %eax, %esi<br>
; X64-NEXT: callq simple_arg_callee<br>
; X64-NEXT: popq %rax<br>
+; X64-NEXT: .cfi_def_cfa_offset 8<br>
; X64-NEXT: retq<br>
call void @simple_arg_callee(i32 %in1, i32 %in0)<br>
ret void<br>
@@ -193,6 +198,7 @@ define void @test_simple_arg8_call(i32 %<br>
; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)<br>
; X32-NEXT: calll simple_arg8_callee<br>
; X32-NEXT: addl $44, %esp<br>
+; X32-NEXT: .cfi_def_cfa_offset 4<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_simple_arg8_call:<br>
@@ -208,6 +214,7 @@ define void @test_simple_arg8_call(i32 %<br>
; X64-NEXT: movl %edi, %r9d<br>
; X64-NEXT: callq simple_arg8_callee<br>
; X64-NEXT: addq $24, %rsp<br>
+; X64-NEXT: .cfi_def_cfa_offset 8<br>
; X64-NEXT: retq<br>
call void @simple_arg8_callee(i32 %in0, i32 %in0, i32 %in0, i32 %in0,i32 %in0, i32 %in0, i32 %in0, i32 %in0)<br>
ret void<br>
@@ -224,6 +231,7 @@ define i32 @test_simple_return_callee()<br>
; X32-NEXT: calll simple_return_callee<br>
; X32-NEXT: addl %eax, %eax<br>
; X32-NEXT: addl $12, %esp<br>
+; X32-NEXT: .cfi_def_cfa_offset 4<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_simple_return_callee:<br>
@@ -234,6 +242,7 @@ define i32 @test_simple_return_callee()<br>
; X64-NEXT: callq simple_return_callee<br>
; X64-NEXT: addl %eax, %eax<br>
; X64-NEXT: popq %rcx<br>
+; X64-NEXT: .cfi_def_cfa_offset 8<br>
; X64-NEXT: retq<br>
%call = call i32 @simple_return_callee(i32 5)<br>
%r = add i32 %call, %call<br>
@@ -254,6 +263,7 @@ define <8 x i32> @test_split_return_call<br>
; X32-NEXT: paddd (%esp), %xmm0 # 16-byte Folded Reload<br>
; X32-NEXT: paddd {{[0-9]+}}(%esp), %xmm1 # 16-byte Folded Reload<br>
; X32-NEXT: addl $44, %esp<br>
+; X32-NEXT: .cfi_def_cfa_offset 4<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_split_return_callee:<br>
@@ -268,6 +278,7 @@ define <8 x i32> @test_split_return_call<br>
; X64-NEXT: paddd (%rsp), %xmm0 # 16-byte Folded Reload<br>
; X64-NEXT: paddd {{[0-9]+}}(%rsp), %xmm1 # 16-byte Folded Reload<br>
; X64-NEXT: addq $40, %rsp<br>
+; X64-NEXT: .cfi_def_cfa_offset 8<br>
; X64-NEXT: retq<br>
%call = call <8 x i32> @split_return_callee(<8 x i32> %arg2)<br>
%r = add <8 x i32> %arg1, %call<br>
@@ -281,6 +292,7 @@ define void @test_indirect_call(void()*<br>
; X32-NEXT: .cfi_def_cfa_offset 16<br>
; X32-NEXT: calll *{{[0-9]+}}(%esp)<br>
; X32-NEXT: addl $12, %esp<br>
+; X32-NEXT: .cfi_def_cfa_offset 4<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_indirect_call:<br>
@@ -289,6 +301,7 @@ define void @test_indirect_call(void()*<br>
; X64-NEXT: .cfi_def_cfa_offset 16<br>
; X64-NEXT: callq *%rdi<br>
; X64-NEXT: popq %rax<br>
+; X64-NEXT: .cfi_def_cfa_offset 8<br>
; X64-NEXT: retq<br>
call void %func()<br>
ret void<br>
@@ -317,8 +330,11 @@ define void @test_abi_exts_call(i8* %add<br>
; X32-NEXT: movl %esi, (%esp)<br>
; X32-NEXT: calll take_char<br>
; X32-NEXT: addl $4, %esp<br>
+; X32-NEXT: .cfi_def_cfa_offset 12<br>
; X32-NEXT: popl %esi<br>
+; X32-NEXT: .cfi_def_cfa_offset 8<br>
; X32-NEXT: popl %ebx<br>
+; X32-NEXT: .cfi_def_cfa_offset 4<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_abi_exts_call:<br>
@@ -335,6 +351,7 @@ define void @test_abi_exts_call(i8* %add<br>
; X64-NEXT: movl %ebx, %edi<br>
; X64-NEXT: callq take_char<br>
; X64-NEXT: popq %rbx<br>
+; X64-NEXT: .cfi_def_cfa_offset 8<br>
; X64-NEXT: retq<br>
%val = load i8, i8* %addr<br>
call void @take_char(i8 %val)<br>
@@ -357,6 +374,7 @@ define void @test_variadic_call_1(i8** %<br>
; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp)<br>
; X32-NEXT: calll variadic_callee<br>
; X32-NEXT: addl $12, %esp<br>
+; X32-NEXT: .cfi_def_cfa_offset 4<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_variadic_call_1:<br>
@@ -368,6 +386,7 @@ define void @test_variadic_call_1(i8** %<br>
; X64-NEXT: movb $0, %al<br>
; X64-NEXT: callq variadic_callee<br>
; X64-NEXT: popq %rax<br>
+; X64-NEXT: .cfi_def_cfa_offset 8<br>
; X64-NEXT: retq<br>
<br>
%addr = load i8*, i8** %addr_ptr<br>
@@ -393,6 +412,7 @@ define void @test_variadic_call_2(i8** %<br>
; X32-NEXT: movl %ecx, 4(%eax)<br>
; X32-NEXT: calll variadic_callee<br>
; X32-NEXT: addl $12, %esp<br>
+; X32-NEXT: .cfi_def_cfa_offset 4<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_variadic_call_2:<br>
@@ -405,6 +425,7 @@ define void @test_variadic_call_2(i8** %<br>
; X64-NEXT: movb $1, %al<br>
; X64-NEXT: callq variadic_callee<br>
; X64-NEXT: popq %rax<br>
+; X64-NEXT: .cfi_def_cfa_offset 8<br>
; X64-NEXT: retq<br>
<br>
%addr = load i8*, i8** %addr_ptr<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/frameIndex.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/frameIndex.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/frameIndex.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/GlobalISel/frameIndex.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/frameIndex.ll Tue Apr 24 03:32:08 2018<br>
@@ -18,6 +18,7 @@ define i32* @allocai32() {<br>
; X32-NEXT: .cfi_def_cfa_offset 8<br>
; X32-NEXT: movl %esp, %eax<br>
; X32-NEXT: popl %ecx<br>
+; X32-NEXT: .cfi_def_cfa_offset 4<br>
; X32-NEXT: retl<br>
;<br>
; X32ABI-LABEL: allocai32:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/O0-pipeline.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/O0-pipeline.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/O0-pipeline.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/O0-pipeline.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/O0-pipeline.ll Tue Apr 24 03:32:08 2018<br>
@@ -61,6 +61,7 @@<br>
; CHECK-NEXT: Insert XRay ops<br>
; CHECK-NEXT: Implement the 'patchable-function' attribute<br>
; CHECK-NEXT: X86 Retpoline Thunks<br>
+; CHECK-NEXT: Check CFA info and insert CFI instructions if needed<br>
; CHECK-NEXT: Lazy Machine Block Frequency Analysis<br>
; CHECK-NEXT: Machine Optimization Remark Emitter<br>
; CHECK-NEXT: X86 Assembly Printer<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/O3-pipeline.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/O3-pipeline.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/O3-pipeline.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/O3-pipeline.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/O3-pipeline.ll Tue Apr 24 03:32:08 2018<br>
@@ -160,6 +160,7 @@<br>
; CHECK-NEXT: Insert XRay ops<br>
; CHECK-NEXT: Implement the 'patchable-function' attribute<br>
; CHECK-NEXT: X86 Retpoline Thunks<br>
+; CHECK-NEXT: Check CFA info and insert CFI instructions if needed<br>
; CHECK-NEXT: Lazy Machine Block Frequency Analysis<br>
; CHECK-NEXT: Machine Optimization Remark Emitter<br>
; CHECK-NEXT: X86 Assembly Printer<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/TruncAssertZext.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/TruncAssertZext.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/TruncAssertZext.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/TruncAssertZext.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/TruncAssertZext.ll Tue Apr 24 03:32:08 2018<br>
@@ -25,6 +25,7 @@ define i64 @main() {<br>
; CHECK-NEXT: subq %rcx, %rax<br>
; CHECK-NEXT: shrq $32, %rax<br>
; CHECK-NEXT: popq %rcx<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 8<br>
; CHECK-NEXT: retq<br>
%b = call i64 @foo()<br>
%or = and i64 %b, 18446744069414584575 ; this is 0xffffffff000000ff<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avoid-sfb.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avoid-sfb.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avoid-sfb.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avoid-sfb.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avoid-sfb.ll Tue Apr 24 03:32:08 2018<br>
@@ -854,10 +854,15 @@ define void @test_limit_all(%struct.S* n<br>
; CHECK-NEXT: movups (%rbx), %xmm0<br>
; CHECK-NEXT: movups %xmm0, (%r12)<br>
; CHECK-NEXT: popq %rbx<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 40<br>
; CHECK-NEXT: popq %r12<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 32<br>
; CHECK-NEXT: popq %r14<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 24<br>
; CHECK-NEXT: popq %r15<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 16<br>
; CHECK-NEXT: popq %rbp<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 8<br>
; CHECK-NEXT: retq<br>
;<br>
; DISABLED-LABEL: test_limit_all:<br>
@@ -896,10 +901,15 @@ define void @test_limit_all(%struct.S* n<br>
; DISABLED-NEXT: movups (%rbx), %xmm0<br>
; DISABLED-NEXT: movups %xmm0, (%r12)<br>
; DISABLED-NEXT: popq %rbx<br>
+; DISABLED-NEXT: .cfi_def_cfa_offset 40<br>
; DISABLED-NEXT: popq %r12<br>
+; DISABLED-NEXT: .cfi_def_cfa_offset 32<br>
; DISABLED-NEXT: popq %r14<br>
+; DISABLED-NEXT: .cfi_def_cfa_offset 24<br>
; DISABLED-NEXT: popq %r15<br>
+; DISABLED-NEXT: .cfi_def_cfa_offset 16<br>
; DISABLED-NEXT: popq %rbp<br>
+; DISABLED-NEXT: .cfi_def_cfa_offset 8<br>
; DISABLED-NEXT: retq<br>
;<br>
; CHECK-AVX2-LABEL: test_limit_all:<br>
@@ -938,10 +948,15 @@ define void @test_limit_all(%struct.S* n<br>
; CHECK-AVX2-NEXT: vmovups (%rbx), %xmm0<br>
; CHECK-AVX2-NEXT: vmovups %xmm0, (%r12)<br>
; CHECK-AVX2-NEXT: popq %rbx<br>
+; CHECK-AVX2-NEXT: .cfi_def_cfa_offset 40<br>
; CHECK-AVX2-NEXT: popq %r12<br>
+; CHECK-AVX2-NEXT: .cfi_def_cfa_offset 32<br>
; CHECK-AVX2-NEXT: popq %r14<br>
+; CHECK-AVX2-NEXT: .cfi_def_cfa_offset 24<br>
; CHECK-AVX2-NEXT: popq %r15<br>
+; CHECK-AVX2-NEXT: .cfi_def_cfa_offset 16<br>
; CHECK-AVX2-NEXT: popq %rbp<br>
+; CHECK-AVX2-NEXT: .cfi_def_cfa_offset 8<br>
; CHECK-AVX2-NEXT: retq<br>
;<br>
; CHECK-AVX512-LABEL: test_limit_all:<br>
@@ -980,10 +995,15 @@ define void @test_limit_all(%struct.S* n<br>
; CHECK-AVX512-NEXT: vmovups (%rbx), %xmm0<br>
; CHECK-AVX512-NEXT: vmovups %xmm0, (%r12)<br>
; CHECK-AVX512-NEXT: popq %rbx<br>
+; CHECK-AVX512-NEXT: .cfi_def_cfa_offset 40<br>
; CHECK-AVX512-NEXT: popq %r12<br>
+; CHECK-AVX512-NEXT: .cfi_def_cfa_offset 32<br>
; CHECK-AVX512-NEXT: popq %r14<br>
+; CHECK-AVX512-NEXT: .cfi_def_cfa_offset 24<br>
; CHECK-AVX512-NEXT: popq %r15<br>
+; CHECK-AVX512-NEXT: .cfi_def_cfa_offset 16<br>
; CHECK-AVX512-NEXT: popq %rbp<br>
+; CHECK-AVX512-NEXT: .cfi_def_cfa_offset 8<br>
; CHECK-AVX512-NEXT: retq<br>
entry:<br>
%d = getelementptr inbounds %struct.S, %struct.S* %s1, i64 0, i32 3<br>
@@ -1047,10 +1067,15 @@ define void @test_limit_one_pred(%struct<br>
; CHECK-NEXT: movl 12(%rbx), %eax<br>
; CHECK-NEXT: movl %eax, 12(%r14)<br>
; CHECK-NEXT: addq $8, %rsp<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 40<br>
; CHECK-NEXT: popq %rbx<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 32<br>
; CHECK-NEXT: popq %r12<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 24<br>
; CHECK-NEXT: popq %r14<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 16<br>
; CHECK-NEXT: popq %r15<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 8<br>
; CHECK-NEXT: retq<br>
;<br>
; DISABLED-LABEL: test_limit_one_pred:<br>
@@ -1086,10 +1111,15 @@ define void @test_limit_one_pred(%struct<br>
; DISABLED-NEXT: movups (%rbx), %xmm0<br>
; DISABLED-NEXT: movups %xmm0, (%r12)<br>
; DISABLED-NEXT: addq $8, %rsp<br>
+; DISABLED-NEXT: .cfi_def_cfa_offset 40<br>
; DISABLED-NEXT: popq %rbx<br>
+; DISABLED-NEXT: .cfi_def_cfa_offset 32<br>
; DISABLED-NEXT: popq %r12<br>
+; DISABLED-NEXT: .cfi_def_cfa_offset 24<br>
; DISABLED-NEXT: popq %r14<br>
+; DISABLED-NEXT: .cfi_def_cfa_offset 16<br>
; DISABLED-NEXT: popq %r15<br>
+; DISABLED-NEXT: .cfi_def_cfa_offset 8<br>
; DISABLED-NEXT: retq<br>
;<br>
; CHECK-AVX2-LABEL: test_limit_one_pred:<br>
@@ -1129,10 +1159,15 @@ define void @test_limit_one_pred(%struct<br>
; CHECK-AVX2-NEXT: movl 12(%rbx), %eax<br>
; CHECK-AVX2-NEXT: movl %eax, 12(%r14)<br>
; CHECK-AVX2-NEXT: addq $8, %rsp<br>
+; CHECK-AVX2-NEXT: .cfi_def_cfa_offset 40<br>
; CHECK-AVX2-NEXT: popq %rbx<br>
+; CHECK-AVX2-NEXT: .cfi_def_cfa_offset 32<br>
; CHECK-AVX2-NEXT: popq %r12<br>
+; CHECK-AVX2-NEXT: .cfi_def_cfa_offset 24<br>
; CHECK-AVX2-NEXT: popq %r14<br>
+; CHECK-AVX2-NEXT: .cfi_def_cfa_offset 16<br>
; CHECK-AVX2-NEXT: popq %r15<br>
+; CHECK-AVX2-NEXT: .cfi_def_cfa_offset 8<br>
; CHECK-AVX2-NEXT: retq<br>
;<br>
; CHECK-AVX512-LABEL: test_limit_one_pred:<br>
@@ -1172,10 +1207,15 @@ define void @test_limit_one_pred(%struct<br>
; CHECK-AVX512-NEXT: movl 12(%rbx), %eax<br>
; CHECK-AVX512-NEXT: movl %eax, 12(%r14)<br>
; CHECK-AVX512-NEXT: addq $8, %rsp<br>
+; CHECK-AVX512-NEXT: .cfi_def_cfa_offset 40<br>
; CHECK-AVX512-NEXT: popq %rbx<br>
+; CHECK-AVX512-NEXT: .cfi_def_cfa_offset 32<br>
; CHECK-AVX512-NEXT: popq %r12<br>
+; CHECK-AVX512-NEXT: .cfi_def_cfa_offset 24<br>
; CHECK-AVX512-NEXT: popq %r14<br>
+; CHECK-AVX512-NEXT: .cfi_def_cfa_offset 16<br>
; CHECK-AVX512-NEXT: popq %r15<br>
+; CHECK-AVX512-NEXT: .cfi_def_cfa_offset 8<br>
; CHECK-AVX512-NEXT: retq<br>
entry:<br>
%d = getelementptr inbounds %struct.S, %struct.S* %s1, i64 0, i32 3<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll Tue Apr 24 03:32:08 2018<br>
@@ -24,6 +24,7 @@ define zeroext i16 @test_mm512_kunpackb(<br>
; X32-NEXT: movzwl %ax, %eax<br>
; X32-NEXT: movl %ebp, %esp<br>
; X32-NEXT: popl %ebp<br>
+; X32-NEXT: .cfi_def_cfa %esp, 4<br>
; X32-NEXT: vzeroupper<br>
; X32-NEXT: retl<br>
;<br>
@@ -75,6 +76,7 @@ define i32 @test_mm512_kortestc(<8 x i64<br>
; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: movl %ebp, %esp<br>
; X32-NEXT: popl %ebp<br>
+; X32-NEXT: .cfi_def_cfa %esp, 4<br>
; X32-NEXT: vzeroupper<br>
; X32-NEXT: retl<br>
;<br>
@@ -123,6 +125,7 @@ define i32 @test_mm512_kortestz(<8 x i64<br>
; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: movl %ebp, %esp<br>
; X32-NEXT: popl %ebp<br>
+; X32-NEXT: .cfi_def_cfa %esp, 4<br>
; X32-NEXT: vzeroupper<br>
; X32-NEXT: retl<br>
;<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-regcall-Mask.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-regcall-Mask.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-regcall-Mask.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512-regcall-Mask.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-regcall-Mask.ll Tue Apr 24 03:32:08 2018<br>
@@ -194,11 +194,15 @@ define i64 @caller_argv64i1() #0 {<br>
; LINUXOSX64-NEXT: .cfi_adjust_cfa_offset 8<br>
; LINUXOSX64-NEXT: callq test_argv64i1<br>
; LINUXOSX64-NEXT: addq $24, %rsp<br>
-; LINUXOSX64-NEXT: .cfi_adjust_cfa_offset -16<br>
+; LINUXOSX64-NEXT: .cfi_adjust_cfa_offset -24<br>
; LINUXOSX64-NEXT: popq %r12<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 32<br>
; LINUXOSX64-NEXT: popq %r13<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 24<br>
; LINUXOSX64-NEXT: popq %r14<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 16<br>
; LINUXOSX64-NEXT: popq %r15<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
entry:<br>
%v0 = bitcast i64 4294967298 to <64 x i1><br>
@@ -271,6 +275,7 @@ define <64 x i1> @caller_retv64i1() #0 {<br>
; LINUXOSX64-NEXT: kmovq %rax, %k0<br>
; LINUXOSX64-NEXT: vpmovm2b %k0, %zmm0<br>
; LINUXOSX64-NEXT: popq %rax<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
entry:<br>
%call = call x86_regcallcc <64 x i1> @test_retv64i1()<br>
@@ -381,7 +386,9 @@ define x86_regcallcc i32 @test_argv32i1(<br>
; LINUXOSX64-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm14 # 16-byte Reload<br>
; LINUXOSX64-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm15 # 16-byte Reload<br>
; LINUXOSX64-NEXT: addq $128, %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 16<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: vzeroupper<br>
; LINUXOSX64-NEXT: retq<br>
entry:<br>
@@ -435,6 +442,7 @@ define i32 @caller_argv32i1() #0 {<br>
; LINUXOSX64-NEXT: movl $1, %edx<br>
; LINUXOSX64-NEXT: callq test_argv32i1<br>
; LINUXOSX64-NEXT: popq %rcx<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
entry:<br>
%v0 = bitcast i32 1 to <32 x i1><br>
@@ -497,6 +505,7 @@ define i32 @caller_retv32i1() #0 {<br>
; LINUXOSX64-NEXT: callq test_retv32i1<br>
; LINUXOSX64-NEXT: incl %eax<br>
; LINUXOSX64-NEXT: popq %rcx<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
entry:<br>
%call = call x86_regcallcc <32 x i1> @test_retv32i1()<br>
@@ -610,7 +619,9 @@ define x86_regcallcc i16 @test_argv16i1(<br>
; LINUXOSX64-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm14 # 16-byte Reload<br>
; LINUXOSX64-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm15 # 16-byte Reload<br>
; LINUXOSX64-NEXT: addq $128, %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 16<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%res = call i16 @test_argv16i1helper(<16 x i1> %x0, <16 x i1> %x1, <16 x i1> %x2)<br>
ret i16 %res<br>
@@ -662,6 +673,7 @@ define i16 @caller_argv16i1() #0 {<br>
; LINUXOSX64-NEXT: movl $1, %edx<br>
; LINUXOSX64-NEXT: callq test_argv16i1<br>
; LINUXOSX64-NEXT: popq %rcx<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
entry:<br>
%v0 = bitcast i16 1 to <16 x i1><br>
@@ -730,6 +742,7 @@ define i16 @caller_retv16i1() #0 {<br>
; LINUXOSX64-NEXT: incl %eax<br>
; LINUXOSX64-NEXT: # kill: def $ax killed $ax killed $eax<br>
; LINUXOSX64-NEXT: popq %rcx<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
entry:<br>
%call = call x86_regcallcc <16 x i1> @test_retv16i1()<br>
@@ -843,7 +856,9 @@ define x86_regcallcc i8 @test_argv8i1(<8<br>
; LINUXOSX64-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm14 # 16-byte Reload<br>
; LINUXOSX64-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm15 # 16-byte Reload<br>
; LINUXOSX64-NEXT: addq $128, %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 16<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%res = call i8 @test_argv8i1helper(<8 x i1> %x0, <8 x i1> %x1, <8 x i1> %x2)<br>
ret i8 %res<br>
@@ -895,6 +910,7 @@ define i8 @caller_argv8i1() #0 {<br>
; LINUXOSX64-NEXT: movl $1, %edx<br>
; LINUXOSX64-NEXT: callq test_argv8i1<br>
; LINUXOSX64-NEXT: popq %rcx<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
entry:<br>
%v0 = bitcast i8 1 to <8 x i1><br>
@@ -968,9 +984,11 @@ define <8 x i1> @caller_retv8i1() #0 {<br>
; LINUXOSX64-NEXT: vpmovm2w %k0, %zmm0<br>
; LINUXOSX64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0<br>
; LINUXOSX64-NEXT: popq %rax<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: vzeroupper<br>
; LINUXOSX64-NEXT: retq<br>
entry:<br>
%call = call x86_regcallcc <8 x i1> @test_retv8i1()<br>
ret <8 x i1> %call<br>
}<br>
+<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll Tue Apr 24 03:32:08 2018<br>
@@ -63,6 +63,7 @@ define x86_regcallcc i1 @test_CallargRet<br>
; LINUXOSX64-NEXT: callq test_argReti1<br>
; LINUXOSX64-NEXT: incb %al<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%b = add i1 %a, 1<br>
%c = call x86_regcallcc i1 @test_argReti1(i1 %b)<br>
@@ -130,6 +131,7 @@ define x86_regcallcc i8 @test_CallargRet<br>
; LINUXOSX64-NEXT: callq test_argReti8<br>
; LINUXOSX64-NEXT: incb %al<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%b = add i8 %a, 1<br>
%c = call x86_regcallcc i8 @test_argReti8(i8 %b)<br>
@@ -200,6 +202,7 @@ define x86_regcallcc i16 @test_CallargRe<br>
; LINUXOSX64-NEXT: incl %eax<br>
; LINUXOSX64-NEXT: # kill: def $ax killed $ax killed $eax<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%b = add i16 %a, 1<br>
%c = call x86_regcallcc i16 @test_argReti16(i16 %b)<br>
@@ -261,6 +264,7 @@ define x86_regcallcc i32 @test_CallargRe<br>
; LINUXOSX64-NEXT: callq test_argReti32<br>
; LINUXOSX64-NEXT: incl %eax<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%b = add i32 %a, 1<br>
%c = call x86_regcallcc i32 @test_argReti32(i32 %b)<br>
@@ -327,6 +331,7 @@ define x86_regcallcc i64 @test_CallargRe<br>
; LINUXOSX64-NEXT: callq test_argReti64<br>
; LINUXOSX64-NEXT: incq %rax<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%b = add i64 %a, 1<br>
%c = call x86_regcallcc i64 @test_argReti64(i64 %b)<br>
@@ -406,7 +411,9 @@ define x86_regcallcc float @test_Callarg<br>
; LINUXOSX64-NEXT: vaddss %xmm8, %xmm0, %xmm0<br>
; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload<br>
; LINUXOSX64-NEXT: addq $16, %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 16<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%b = fadd float 1.0, %a<br>
%c = call x86_regcallcc float @test_argRetFloat(float %b)<br>
@@ -486,7 +493,9 @@ define x86_regcallcc double @test_Callar<br>
; LINUXOSX64-NEXT: vaddsd %xmm8, %xmm0, %xmm0<br>
; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload<br>
; LINUXOSX64-NEXT: addq $16, %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 16<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%b = fadd double 1.0, %a<br>
%c = call x86_regcallcc double @test_argRetDouble(double %b)<br>
@@ -548,6 +557,7 @@ define x86_regcallcc x86_fp80 @test_Call<br>
; LINUXOSX64-NEXT: callq test_argRetf80<br>
; LINUXOSX64-NEXT: fadd %st(0), %st(0)<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%b = fadd x86_fp80 %a, %a<br>
%c = call x86_regcallcc x86_fp80 @test_argRetf80(x86_fp80 %b)<br>
@@ -611,6 +621,7 @@ define x86_regcallcc [4 x i32]* @test_Ca<br>
; LINUXOSX64-NEXT: callq test_argRetPointer<br>
; LINUXOSX64-NEXT: incl %eax<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%b = ptrtoint [4 x i32]* %a to i32<br>
%c = add i32 %b, 1<br>
@@ -694,7 +705,9 @@ define x86_regcallcc <4 x i32> @test_Cal<br>
; LINUXOSX64-NEXT: vmovdqa32 %xmm8, %xmm0 {%k1}<br>
; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload<br>
; LINUXOSX64-NEXT: addq $16, %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 16<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%b = call x86_regcallcc <4 x i32> @test_argRet128Vector(<4 x i32> %a, <4 x i32> %a)<br>
%c = select <4 x i1> undef , <4 x i32> %a, <4 x i32> %b<br>
@@ -768,7 +781,9 @@ define x86_regcallcc <8 x i32> @test_Cal<br>
; LINUXOSX64-NEXT: vmovdqu (%rsp), %ymm1 # 32-byte Reload<br>
; LINUXOSX64-NEXT: vmovdqa32 %ymm1, %ymm0 {%k1}<br>
; LINUXOSX64-NEXT: addq $48, %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 16<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%b = call x86_regcallcc <8 x i32> @test_argRet256Vector(<8 x i32> %a, <8 x i32> %a)<br>
%c = select <8 x i1> undef , <8 x i32> %a, <8 x i32> %b<br>
@@ -842,7 +857,9 @@ define x86_regcallcc <16 x i32> @test_Ca<br>
; LINUXOSX64-NEXT: vmovdqu64 (%rsp), %zmm1 # 64-byte Reload<br>
; LINUXOSX64-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}<br>
; LINUXOSX64-NEXT: addq $112, %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 16<br>
; LINUXOSX64-NEXT: popq %rsp<br>
+; LINUXOSX64-NEXT: .cfi_def_cfa_offset 8<br>
; LINUXOSX64-NEXT: retq<br>
%b = call x86_regcallcc <16 x i32> @test_argRet512Vector(<16 x i32> %a, <16 x i32> %a)<br>
%c = select <16 x i1> undef , <16 x i32> %a, <16 x i32> %b<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-schedule.ll?rev=330706&r1=330705&r2=330706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-schedule.ll?rev=330706&r1=330705&r2=330706&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-schedule.ll Tue Apr 24 03:32:08 2018<br>
@@ -8702,6 +8702,7 @@ define <16 x float> @broadcast_ss_spill(<br>
; GENERIC-NEXT: callq func_f32<br>
; GENERIC-NEXT: vbroadcastss (%rsp), %zmm0 # 16-byte Folded Reload sched: [6:1.00]<br>
; GENERIC-NEXT: addq $24, %rsp # sched: [1:0.33]<br>
+; GENERIC-NEXT: .cfi_def_cfa_offset 8<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
; SKX-LABEL: broadcast_ss_spill:<br>
@@ -8713,6 +8714,7 @@ define <16 x float> @broadcast_ss_spill(<br>
; SKX-NEXT: callq func_f32<br>
; SKX-NEXT: vbroadcastss (%rsp), %zmm0 # 16-byte Folded Reload sched: [8:0.50]<br>
; SKX-NEXT: addq $24, %rsp # sched: [1:0.25]<br>
+; SKX-NEXT: .cfi_def_cfa_offset 8<br>
; SKX-NEXT: retq # sched: [7:1.00]<br>
%a = fadd float %x, %x<br>
call void @func_f32(float %a)<br>
@@ -8732,6 +8734,7 @@ define <8 x double> @broadcast_sd_spill(<br>
; GENERIC-NEXT: callq func_f64<br>
; GENERIC-NEXT: vbroadcastsd (%rsp), %zmm0 # 16-byte Folded Reload sched: [6:1.00]<br>
; GENERIC-NEXT: addq $24, %rsp # sched: [1:0.33]<br>
+; GENERIC-NEXT: .cfi_def_cfa_offset 8<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
; SKX-LABEL: broadcast_sd_spill:<br>
@@ -8743,6 +8746,7 @@ define <8 x double> @broadcast_sd_spill(<br>
; SKX-NEXT: callq func_f64<br>
; SKX-NEXT: vbroadcastsd (%rsp), %zmm0 # 16-byte Folded Reload sched: [8:0.50]<br>
; SKX-NEXT: addq $24, %rsp # sched: [1:0.25]<br>
+; SKX-NEXT: .cfi_def_cfa_offset 8<br>
; SKX-NEXT: retq # sched: [7:1.00]<br>
%a = fadd double %x,</blockquote></div></div></div></div>
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