<div dir="ltr"><a href="https://reviews.llvm.org/D46135">https://reviews.llvm.org/D46135</a><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Apr 25, 2018 at 7:35 PM, Jorge Gorbe Moya <span dir="ltr"><<a href="mailto:jgorbe@google.com" target="_blank">jgorbe@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Awesome, thanks! :)</div><div class="HOEnZb"><div class="h5"><br><div class="gmail_quote"><div dir="ltr">On Wed, Apr 25, 2018 at 6:31 PM Sanjay Patel <<a href="mailto:spatel@rotateright.com" target="_blank">spatel@rotateright.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div dir="auto">Sure, I’ll post something for review within 24 hours.</div></div><div><br><div class="gmail_quote"><div>On Wed, Apr 25, 2018 at 7:16 PM Jorge Gorbe Moya via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div>Hi Sanjay,<div><br></div><div>Could you give us an approximate ETA for the flag to control the new behavior?</div><div><br></div><div>Cheers,</div><div>Jorge</div></div><br><div class="gmail_quote"><div>On Wed, Apr 25, 2018 at 4:29 PM Chandler Carruth via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div>+1<br><div><br></div><div>I will say, what i want right now is the flag to go back to the old behavior. ;] Our releases will end up blocked on this.</div></div><br><div class="gmail_quote"><div>On Wed, Apr 25, 2018 at 4:00 PM Stephen Canon <<a href="mailto:scanon@apple.com" target="_blank">scanon@apple.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word;line-break:after-white-space">We should also add an intrinsic for fpto[us]I with defined overflow behavior, and have the sanitizer call it to people’s attention. Otherwise people will roll their own clamping and most of them will get it wrong, because INT_MAX isn’t representable as a float.<div><br></div><div>Ideally we should expose this at the clang level as something like bool __builtin_convert_overflow(<wbr>src, &dst) and make the one builtin work across types, as with __builtin_add_overflow and friends.<br><div><br></div><div>– Steve</div></div></div><div style="word-wrap:break-word;line-break:after-white-space"><div><div><br><div><br><blockquote type="cite"><div>On Apr 25, 2018, at 6:11 PM, Chandler Carruth via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="m_-3355316456967321367m_-896781367001454649m_-6245636267813273177m_5921123548073755260m_4712214374593722575Apple-interchange-newline"><div><div><div class="gmail_quote"><div>On Wed, Apr 25, 2018 at 2:58 PM Sanjay Patel <<a href="mailto:spatel@rotateright.com" target="_blank">spatel@rotateright.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div><div>Damn...<br><br></div>1. I've never actually used the sanitizers for anything more than simple experiments. But a look at the docs and simple test says this will do it:<br><a href="https://clang.llvm.org/docs/UndefinedBehaviorSanitizer.html" target="_blank">https://clang.llvm.org/docs/<wbr>UndefinedBehaviorSanitizer.<wbr>html</a><br><code class="m_-3355316456967321367m_-896781367001454649m_-6245636267813273177m_5921123548073755260m_4712214374593722575m_-4827511685014259881gmail-docutils m_-3355316456967321367m_-896781367001454649m_-6245636267813273177m_5921123548073755260m_4712214374593722575m_-4827511685014259881gmail-literal"><span class="m_-3355316456967321367m_-896781367001454649m_-6245636267813273177m_5921123548073755260m_4712214374593722575m_-4827511685014259881gmail-pre">-fsanitize=float-cast-overflow</span></code></div></div></blockquote><div><br></div><div>If this covers everything, great. Maybe document this in the release notes as well? </div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div></div>2. Yes, that's probably wiser. -fjunk-in-trunc ? :)<br></div></blockquote><div><br></div><div>-fstrict-fp-trunc-semantics maybe?</div><div><br></div><div>Or maybe we should phrase it more:</div><div><br></div><div>-ffp-cast-overflow-workaround</div><div><br></div><div>To make it clear that enabling this is a bad idea and something that needs to go away?</div><div><br></div><div>We should be *really* clear around the documentation of the flag that it will not be supported long term and will go away in a future release. (And be really clear about that in the release notes as well.)</div><div><br></div><div>May make sense to make it CC1 only.</div><div><br></div><div>Anyways, all of this is a better clang commits list discussion. =]</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div><br><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Apr 25, 2018 at 3:38 PM, Chandler Carruth <span><<a href="mailto:chandlerc@gmail.com" target="_blank">chandlerc@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div>Hey Sanjay, this is hitting a *lot* of code, even outside of Chrome....<div><br></div><div>I think we need a more nuanced way to handle this.</div><div><br></div><div>1) Is there a specific sanitizer that we can enable that will point out *just* the issues this impacts?</div><div><br></div><div>2) Can we have a flag to control this behavior at least for a temporary period of time? that would make it much easier to roll out when there are very large numbers of issues encountered.</div></div><div class="m_-3355316456967321367m_-896781367001454649m_-6245636267813273177m_5921123548073755260m_4712214374593722575m_-4827511685014259881HOEnZb"><div class="m_-3355316456967321367m_-896781367001454649m_-6245636267813273177m_5921123548073755260m_4712214374593722575m_-4827511685014259881h5"><br><div class="gmail_quote"><div>On Fri, Apr 20, 2018 at 8:11 AM Sanjay Patel via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: spatel<br>
Date: Fri Apr 20 08:07:55 2018<br>
New Revision: 330437<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=330437&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=330437&view=rev</a><br>
Log:<br>
[DAGCombine] (float)((int) f) --> ftrunc (PR36617)<br>
<br>
This was originally committed at rL328921 and reverted at rL329920 to<br>
investigate failures in Chrome. This time I've added to the ReleaseNotes<br>
to warn users of the potential of exposing UB and let me repeat that<br>
here for more exposure:<br>
<br>
Optimization of floating-point casts is improved. This may cause surprising<br>
results for code that is relying on undefined behavior. Code sanitizers can<br>
be used to detect affected patterns such as this:<br>
<br>
int main() {<br>
float x = 4294967296.0f;<br>
x = (float)((int)x);<br>
printf("junk in the ftrunc: %f\n", x);<br>
return 0;<br>
}<br>
<br>
$ clang -O1 ftrunc.c -fsanitize=undefined ; ./a.out<br>
ftrunc.c:5:15: runtime error: 4.29497e+09 is outside the range of <br>
representable values of type 'int'<br>
junk in the ftrunc: 0.000000<br>
<br>
<br>
Original commit message:<br>
<br>
fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC,<br>
so replace a pair of casts with the equivalent node. We don't have to account for<br>
special cases (NaN, INF) because out-of-range casts are undefined.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D44909" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D44909</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/ARM/<wbr>ftrunc.ll<br>
- copied unchanged from r329919, llvm/trunk/test/CodeGen/ARM/<wbr>ftrunc.ll<br>
Modified:<br>
llvm/trunk/docs/ReleaseNotes.<wbr>rst<br>
llvm/trunk/include/llvm/<wbr>CodeGen/ISDOpcodes.h<br>
llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/ftrunc.ll<br>
llvm/trunk/test/CodeGen/<wbr>PowerPC/fp-int128-fp-combine.<wbr>ll<br>
llvm/trunk/test/CodeGen/<wbr>PowerPC/fp-to-int-to-fp.ll<br>
llvm/trunk/test/CodeGen/<wbr>PowerPC/ftrunc-vec.ll<br>
llvm/trunk/test/CodeGen/<wbr>PowerPC/no-extra-fp-conv-ldst.<wbr>ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>2011-10-19-widen_vselect.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>ftrunc.ll<br>
<br>
Modified: llvm/trunk/docs/ReleaseNotes.<wbr>rst<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.rst?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/docs/<wbr>ReleaseNotes.rst?rev=330437&<wbr>r1=330436&r2=330437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/docs/ReleaseNotes.<wbr>rst (original)<br>
+++ llvm/trunk/docs/ReleaseNotes.<wbr>rst Fri Apr 20 08:07:55 2018<br>
@@ -61,6 +61,26 @@ Non-comprehensive list of changes in thi<br>
* The optimization flag to merge constants (-fmerge-all-constants) is no longer<br>
applied by default.<br>
<br>
+* Optimization of floating-point casts is improved. This may cause surprising<br>
+ results for code that is relying on undefined behavior. Code sanitizers can<br>
+ be used to detect affected patterns such as this:<br>
+<br>
+.. code-block:: c<br>
+<br>
+ int main() {<br>
+ float x = 4294967296.0f;<br>
+ x = (float)((int)x);<br>
+ printf("junk in the ftrunc: %f\n", x);<br>
+ return 0;<br>
+ }<br>
+<br>
+.. code-block:: bash<br>
+<br>
+ clang -O1 ftrunc.c -fsanitize=undefined ; ./a.out <br>
+ ftrunc.c:5:15: runtime error: 4.29497e+09 is outside the range of representable values of type 'int'<br>
+ junk in the ftrunc: 0.000000<br>
+<br>
+<br>
* Note..<br>
<br>
.. NOTE<br>
<br>
Modified: llvm/trunk/include/llvm/<wbr>CodeGen/ISDOpcodes.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/include/<wbr>llvm/CodeGen/ISDOpcodes.h?rev=<wbr>330437&r1=330436&r2=330437&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/<wbr>CodeGen/ISDOpcodes.h (original)<br>
+++ llvm/trunk/include/llvm/<wbr>CodeGen/ISDOpcodes.h Fri Apr 20 08:07:55 2018<br>
@@ -495,7 +495,8 @@ namespace ISD {<br>
ZERO_EXTEND_VECTOR_INREG,<br>
<br>
/// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned<br>
- /// integer.<br>
+ /// integer. These have the same semantics as fptosi and fptoui in IR. If<br>
+ /// the FP value cannot fit in the integer type, the results are undefined.<br>
FP_TO_SINT,<br>
FP_TO_UINT,<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/SelectionDAG/<wbr>DAGCombiner.cpp?rev=330437&r1=<wbr>330436&r2=330437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp Fri Apr 20 08:07:55 2018<br>
@@ -10890,6 +10890,15 @@ SDValue DAGCombiner::visitSINT_TO_FP(<wbr>SDN<br>
}<br>
}<br>
<br>
+ // fptosi rounds towards zero, so converting from FP to integer and back is<br>
+ // the same as an 'ftrunc': sitofp (fptosi X) --> ftrunc X<br>
+ // We only do this if the target has legal ftrunc, otherwise we'd likely be<br>
+ // replacing casts with a libcall.<br>
+ if (N0.getOpcode() == ISD::FP_TO_SINT &&<br>
+ N0.getOperand(0).getValueType(<wbr>) == VT &&<br>
+ TLI.isOperationLegal(ISD::<wbr>FTRUNC, VT))<br>
+ return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0));<br>
+<br>
return SDValue();<br>
}<br>
<br>
@@ -10929,6 +10938,15 @@ SDValue DAGCombiner::visitUINT_TO_FP(<wbr>SDN<br>
}<br>
}<br>
<br>
+ // fptoui rounds towards zero, so converting from FP to integer and back is<br>
+ // the same as an 'ftrunc': uitofp (fptoui X) --> ftrunc X<br>
+ // We only do this if the target has legal ftrunc, otherwise we'd likely be<br>
+ // replacing casts with a libcall.<br>
+ if (N0.getOpcode() == ISD::FP_TO_UINT &&<br>
+ N0.getOperand(0).getValueType(<wbr>) == VT &&<br>
+ TLI.isOperationLegal(ISD::<wbr>FTRUNC, VT))<br>
+ return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0));<br>
+<br>
return SDValue();<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/ftrunc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ftrunc.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/ftrunc.ll?rev=<wbr>330437&r1=330436&r2=330437&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/ftrunc.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/ftrunc.ll Fri Apr 20 08:07:55 2018<br>
@@ -4,8 +4,7 @@<br>
define float @trunc_unsigned_f32(float %x) {<br>
; CHECK-LABEL: trunc_unsigned_f32:<br>
; CHECK: // %bb.0:<br>
-; CHECK-NEXT: fcvtzu w8, s0<br>
-; CHECK-NEXT: ucvtf s0, w8<br>
+; CHECK-NEXT: frintz s0, s0<br>
; CHECK-NEXT: ret<br>
%i = fptoui float %x to i32<br>
%r = uitofp i32 %i to float<br>
@@ -15,8 +14,7 @@ define float @trunc_unsigned_f32(float %<br>
define double @trunc_unsigned_f64(double %x) {<br>
; CHECK-LABEL: trunc_unsigned_f64:<br>
; CHECK: // %bb.0:<br>
-; CHECK-NEXT: fcvtzu x8, d0<br>
-; CHECK-NEXT: ucvtf d0, x8<br>
+; CHECK-NEXT: frintz d0, d0<br>
; CHECK-NEXT: ret<br>
%i = fptoui double %x to i64<br>
%r = uitofp i64 %i to double<br>
@@ -26,8 +24,7 @@ define double @trunc_unsigned_f64(double<br>
define float @trunc_signed_f32(float %x) {<br>
; CHECK-LABEL: trunc_signed_f32:<br>
; CHECK: // %bb.0:<br>
-; CHECK-NEXT: fcvtzs w8, s0<br>
-; CHECK-NEXT: scvtf s0, w8<br>
+; CHECK-NEXT: frintz s0, s0<br>
; CHECK-NEXT: ret<br>
%i = fptosi float %x to i32<br>
%r = sitofp i32 %i to float<br>
@@ -37,8 +34,7 @@ define float @trunc_signed_f32(float %x)<br>
define double @trunc_signed_f64(double %x) {<br>
; CHECK-LABEL: trunc_signed_f64:<br>
; CHECK: // %bb.0:<br>
-; CHECK-NEXT: fcvtzs x8, d0<br>
-; CHECK-NEXT: scvtf d0, x8<br>
+; CHECK-NEXT: frintz d0, d0<br>
; CHECK-NEXT: ret<br>
%i = fptosi double %x to i64<br>
%r = sitofp i64 %i to double<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>PowerPC/fp-int128-fp-combine.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fp-int128-fp-combine.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/PowerPC/fp-int128-fp-<wbr>combine.ll?rev=330437&r1=<wbr>330436&r2=330437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>PowerPC/fp-int128-fp-combine.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>PowerPC/fp-int128-fp-combine.<wbr>ll Fri Apr 20 08:07:55 2018<br>
@@ -5,18 +5,7 @@<br>
define float @f_i128_f(float %v) {<br>
; CHECK-LABEL: f_i128_f:<br>
; CHECK: # %bb.0: # %entry<br>
-; CHECK-NEXT: mflr 0<br>
-; CHECK-NEXT: std 0, 16(1)<br>
-; CHECK-NEXT: stdu 1, -32(1)<br>
-; CHECK-NEXT: .cfi_def_cfa_offset 32<br>
-; CHECK-NEXT: .cfi_offset lr, 16<br>
-; CHECK-NEXT: bl __fixsfti<br>
-; CHECK-NEXT: nop<br>
-; CHECK-NEXT: bl __floattisf<br>
-; CHECK-NEXT: nop<br>
-; CHECK-NEXT: addi 1, 1, 32<br>
-; CHECK-NEXT: ld 0, 16(1)<br>
-; CHECK-NEXT: mtlr 0<br>
+; CHECK-NEXT: friz 1, 1<br>
; CHECK-NEXT: blr<br>
entry:<br>
%a = fptosi float %v to i128<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>PowerPC/fp-to-int-to-fp.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fp-to-int-to-fp.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/PowerPC/fp-to-int-to-<wbr>fp.ll?rev=330437&r1=330436&r2=<wbr>330437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>PowerPC/fp-to-int-to-fp.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>PowerPC/fp-to-int-to-fp.ll Fri Apr 20 08:07:55 2018<br>
@@ -11,8 +11,7 @@ entry:<br>
ret float %conv1<br>
<br>
; FPCVT-LABEL: @fool<br>
-; FPCVT: fctidz [[REG1:[0-9]+]], 1<br>
-; FPCVT: fcfids 1, [[REG1]]<br>
+; FPCVT: friz 1, 1<br>
; FPCVT: blr<br>
<br>
; PPC64-LABEL: @fool<br>
@@ -30,8 +29,7 @@ entry:<br>
ret double %conv1<br>
<br>
; FPCVT-LABEL: @foodl<br>
-; FPCVT: fctidz [[REG1:[0-9]+]], 1<br>
-; FPCVT: fcfid 1, [[REG1]]<br>
+; FPCVT: friz 1, 1<br>
; FPCVT: blr<br>
<br>
; PPC64-LABEL: @foodl<br>
@@ -48,8 +46,7 @@ entry:<br>
ret float %conv1<br>
<br>
; FPCVT-LABEL: @fooul<br>
-; FPCVT: fctiduz [[REG1:[0-9]+]], 1<br>
-; FPCVT: fcfidus 1, [[REG1]]<br>
+; FPCVT: friz 1, 1<br>
; FPCVT: blr<br>
}<br>
<br>
@@ -61,8 +58,7 @@ entry:<br>
ret double %conv1<br>
<br>
; FPCVT-LABEL: @fooudl<br>
-; FPCVT: fctiduz [[REG1:[0-9]+]], 1<br>
-; FPCVT: fcfidu 1, [[REG1]]<br>
+; FPCVT: friz 1, 1<br>
; FPCVT: blr<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>PowerPC/ftrunc-vec.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ftrunc-vec.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/PowerPC/ftrunc-vec.ll?<wbr>rev=330437&r1=330436&r2=<wbr>330437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>PowerPC/ftrunc-vec.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>PowerPC/ftrunc-vec.ll Fri Apr 20 08:07:55 2018<br>
@@ -4,8 +4,7 @@<br>
define <4 x float> @truncf32(<4 x float> %a) {<br>
; CHECK-LABEL: truncf32:<br>
; CHECK: # %bb.0:<br>
-; CHECK-NEXT: xvcvspsxws 0, 34<br>
-; CHECK-NEXT: xvcvsxwsp 34, 0<br>
+; CHECK-NEXT: xvrspiz 34, 34<br>
; CHECK-NEXT: blr<br>
%t0 = fptosi <4 x float> %a to <4 x i32><br>
%t1 = sitofp <4 x i32> %t0 to <4 x float><br>
@@ -15,8 +14,7 @@ define <4 x float> @truncf32(<4 x float><br>
define <2 x double> @truncf64(<2 x double> %a) {<br>
; CHECK-LABEL: truncf64:<br>
; CHECK: # %bb.0:<br>
-; CHECK-NEXT: xvcvdpsxds 34, 34<br>
-; CHECK-NEXT: xvcvsxddp 34, 34<br>
+; CHECK-NEXT: xvrdpiz 34, 34<br>
; CHECK-NEXT: blr<br>
%t0 = fptosi <2 x double> %a to <2 x i64><br>
%t1 = sitofp <2 x i64> %t0 to <2 x double><br>
@@ -26,8 +24,7 @@ define <2 x double> @truncf64(<2 x doubl<br>
define <4 x float> @truncf32u(<4 x float> %a) {<br>
; CHECK-LABEL: truncf32u:<br>
; CHECK: # %bb.0:<br>
-; CHECK-NEXT: xvcvspuxws 0, 34<br>
-; CHECK-NEXT: xvcvuxwsp 34, 0<br>
+; CHECK-NEXT: xvrspiz 34, 34<br>
; CHECK-NEXT: blr<br>
%t0 = fptoui <4 x float> %a to <4 x i32><br>
%t1 = uitofp <4 x i32> %t0 to <4 x float><br>
@@ -37,8 +34,7 @@ define <4 x float> @truncf32u(<4 x float<br>
define <2 x double> @truncf64u(<2 x double> %a) {<br>
; CHECK-LABEL: truncf64u:<br>
; CHECK: # %bb.0:<br>
-; CHECK-NEXT: xvcvdpuxds 34, 34<br>
-; CHECK-NEXT: xvcvuxddp 34, 34<br>
+; CHECK-NEXT: xvrdpiz 34, 34<br>
; CHECK-NEXT: blr<br>
%t0 = fptoui <2 x double> %a to <2 x i64><br>
%t1 = uitofp <2 x i64> %t0 to <2 x double><br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>PowerPC/no-extra-fp-conv-ldst.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/PowerPC/no-extra-fp-<wbr>conv-ldst.ll?rev=330437&r1=<wbr>330436&r2=330437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>PowerPC/no-extra-fp-conv-ldst.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>PowerPC/no-extra-fp-conv-ldst.<wbr>ll Fri Apr 20 08:07:55 2018<br>
@@ -36,11 +36,7 @@ entry:<br>
ret float %conv1<br>
<br>
; CHECK-LABEL: @foo<br>
-; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1<br>
-; CHECK-DAG: addi [[REG1:[0-9]+]], 1,<br>
-; CHECK: stfiwx [[REG2]], 0, [[REG1]]<br>
-; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]<br>
-; CHECK: fcfids 1, [[REG3]]<br>
+; CHECK: friz 1, 1<br>
; CHECK: blr<br>
}<br>
<br>
@@ -52,11 +48,7 @@ entry:<br>
ret double %conv1<br>
<br>
; CHECK-LABEL: @food<br>
-; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1<br>
-; CHECK-DAG: addi [[REG1:[0-9]+]], 1,<br>
-; CHECK: stfiwx [[REG2]], 0, [[REG1]]<br>
-; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]<br>
-; CHECK: fcfid 1, [[REG3]]<br>
+; CHECK: friz 1, 1<br>
; CHECK: blr<br>
}<br>
<br>
@@ -68,11 +60,7 @@ entry:<br>
ret float %conv1<br>
<br>
; CHECK-LABEL: @foou<br>
-; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1<br>
-; CHECK-DAG: addi [[REG1:[0-9]+]], 1,<br>
-; CHECK: stfiwx [[REG2]], 0, [[REG1]]<br>
-; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]]<br>
-; CHECK: fcfidus 1, [[REG3]]<br>
+; CHECK: friz 1, 1<br>
; CHECK: blr<br>
}<br>
<br>
@@ -84,11 +72,7 @@ entry:<br>
ret double %conv1<br>
<br>
; CHECK-LABEL: @fooud<br>
-; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1<br>
-; CHECK-DAG: addi [[REG1:[0-9]+]], 1,<br>
-; CHECK: stfiwx [[REG2]], 0, [[REG1]]<br>
-; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]]<br>
-; CHECK: fcfidu 1, [[REG3]]<br>
+; CHECK: friz 1, 1<br>
; CHECK: blr<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>2011-10-19-widen_vselect.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/2011-10-19-widen_<wbr>vselect.ll?rev=330437&r1=<wbr>330436&r2=330437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>2011-10-19-widen_vselect.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>2011-10-19-widen_vselect.ll Fri Apr 20 08:07:55 2018<br>
@@ -71,8 +71,7 @@ define void @full_test() {<br>
; X32-NEXT: subl $60, %esp<br>
; X32-NEXT: .cfi_def_cfa_offset 64<br>
; X32-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero<br>
-; X32-NEXT: cvttps2dq %xmm2, %xmm0<br>
-; X32-NEXT: cvtdq2ps %xmm0, %xmm1<br>
+; X32-NEXT: roundps $11, %xmm2, %xmm1<br>
; X32-NEXT: xorps %xmm0, %xmm0<br>
; X32-NEXT: cmpltps %xmm2, %xmm0<br>
; X32-NEXT: movaps {{.*#+}} xmm3 = <1,1,u,u><br>
@@ -93,8 +92,7 @@ define void @full_test() {<br>
; X64-LABEL: full_test:<br>
; X64: # %bb.0: # %entry<br>
; X64-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero<br>
-; X64-NEXT: cvttps2dq %xmm2, %xmm0<br>
-; X64-NEXT: cvtdq2ps %xmm0, %xmm1<br>
+; X64-NEXT: roundps $11, %xmm2, %xmm1<br>
; X64-NEXT: xorps %xmm0, %xmm0<br>
; X64-NEXT: cmpltps %xmm2, %xmm0<br>
; X64-NEXT: movaps {{.*#+}} xmm3 = <1,1,u,u><br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>ftrunc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ftrunc.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/ftrunc.ll?rev=<wbr>330437&r1=330436&r2=330437&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>ftrunc.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>ftrunc.ll Fri Apr 20 08:07:55 2018<br>
@@ -14,17 +14,12 @@ define float @trunc_unsigned_f32(float %<br>
;<br>
; SSE41-LABEL: trunc_unsigned_f32:<br>
; SSE41: # %bb.0:<br>
-; SSE41-NEXT: cvttss2si %xmm0, %rax<br>
-; SSE41-NEXT: movl %eax, %eax<br>
-; SSE41-NEXT: xorps %xmm0, %xmm0<br>
-; SSE41-NEXT: cvtsi2ssq %rax, %xmm0<br>
+; SSE41-NEXT: roundss $11, %xmm0, %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: trunc_unsigned_f32:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vcvttss2si %xmm0, %rax<br>
-; AVX1-NEXT: movl %eax, %eax<br>
-; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm0<br>
+; AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0<br>
; AVX1-NEXT: retq<br>
%i = fptoui float %x to i32<br>
%r = uitofp i32 %i to float<br>
@@ -52,35 +47,12 @@ define double @trunc_unsigned_f64(double<br>
;<br>
; SSE41-LABEL: trunc_unsigned_f64:<br>
; SSE41: # %bb.0:<br>
-; SSE41-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero<br>
-; SSE41-NEXT: movapd %xmm0, %xmm2<br>
-; SSE41-NEXT: subsd %xmm1, %xmm2<br>
-; SSE41-NEXT: cvttsd2si %xmm2, %rax<br>
-; SSE41-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000<br>
-; SSE41-NEXT: xorq %rax, %rcx<br>
-; SSE41-NEXT: cvttsd2si %xmm0, %rax<br>
-; SSE41-NEXT: ucomisd %xmm1, %xmm0<br>
-; SSE41-NEXT: cmovaeq %rcx, %rax<br>
-; SSE41-NEXT: movq %rax, %xmm0<br>
-; SSE41-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]<br>
-; SSE41-NEXT: subpd {{.*}}(%rip), %xmm0<br>
-; SSE41-NEXT: haddpd %xmm0, %xmm0<br>
+; SSE41-NEXT: roundsd $11, %xmm0, %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: trunc_unsigned_f64:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero<br>
-; AVX1-NEXT: vsubsd %xmm1, %xmm0, %xmm2<br>
-; AVX1-NEXT: vcvttsd2si %xmm2, %rax<br>
-; AVX1-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000<br>
-; AVX1-NEXT: xorq %rax, %rcx<br>
-; AVX1-NEXT: vcvttsd2si %xmm0, %rax<br>
-; AVX1-NEXT: vucomisd %xmm1, %xmm0<br>
-; AVX1-NEXT: cmovaeq %rcx, %rax<br>
-; AVX1-NEXT: vmovq %rax, %xmm0<br>
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]<br>
-; AVX1-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0<br>
-; AVX1-NEXT: vhaddpd %xmm0, %xmm0, %xmm0<br>
+; AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0<br>
; AVX1-NEXT: retq<br>
%i = fptoui double %x to i64<br>
%r = uitofp i64 %i to double<br>
@@ -118,45 +90,12 @@ define <4 x float> @trunc_unsigned_v4f32<br>
;<br>
; SSE41-LABEL: trunc_unsigned_v4f32:<br>
; SSE41: # %bb.0:<br>
-; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]<br>
-; SSE41-NEXT: cvttss2si %xmm1, %rax<br>
-; SSE41-NEXT: cvttss2si %xmm0, %rcx<br>
-; SSE41-NEXT: movd %ecx, %xmm1<br>
-; SSE41-NEXT: pinsrd $1, %eax, %xmm1<br>
-; SSE41-NEXT: movaps %xmm0, %xmm2<br>
-; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]<br>
-; SSE41-NEXT: cvttss2si %xmm2, %rax<br>
-; SSE41-NEXT: pinsrd $2, %eax, %xmm1<br>
-; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]<br>
-; SSE41-NEXT: cvttss2si %xmm0, %rax<br>
-; SSE41-NEXT: pinsrd $3, %eax, %xmm1<br>
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [1258291200,1258291200,<wbr>1258291200,1258291200]<br>
-; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[<wbr>3],xmm1[4],xmm0[5],xmm1[6],<wbr>xmm0[7]<br>
-; SSE41-NEXT: psrld $16, %xmm1<br>
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0],mem[1],xmm1[2],mem[3],<wbr>xmm1[4],mem[5],xmm1[6],mem[7]<br>
-; SSE41-NEXT: addps {{.*}}(%rip), %xmm1<br>
-; SSE41-NEXT: addps %xmm0, %xmm1<br>
-; SSE41-NEXT: movaps %xmm1, %xmm0<br>
+; SSE41-NEXT: roundps $11, %xmm0, %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: trunc_unsigned_v4f32:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]<br>
-; AVX1-NEXT: vcvttss2si %xmm1, %rax<br>
-; AVX1-NEXT: vcvttss2si %xmm0, %rcx<br>
-; AVX1-NEXT: vmovd %ecx, %xmm1<br>
-; AVX1-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1<br>
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]<br>
-; AVX1-NEXT: vcvttss2si %xmm2, %rax<br>
-; AVX1-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1<br>
-; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3]<br>
-; AVX1-NEXT: vcvttss2si %xmm0, %rax<br>
-; AVX1-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0<br>
-; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],<wbr>xmm0[4],mem[5],xmm0[6],mem[7]<br>
-; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0<br>
-; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],<wbr>xmm0[4],mem[5],xmm0[6],mem[7]<br>
-; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0<br>
-; AVX1-NEXT: vaddps %xmm0, %xmm1, %xmm0<br>
+; AVX1-NEXT: vroundps $11, %xmm0, %xmm0<br>
; AVX1-NEXT: retq<br>
%i = fptoui <4 x float> %x to <4 x i32><br>
%r = uitofp <4 x i32> %i to <4 x float><br>
@@ -201,61 +140,12 @@ define <2 x double> @trunc_unsigned_v2f6<br>
;<br>
; SSE41-LABEL: trunc_unsigned_v2f64:<br>
; SSE41: # %bb.0:<br>
-; SSE41-NEXT: movaps %xmm0, %xmm1<br>
-; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]<br>
-; SSE41-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero<br>
-; SSE41-NEXT: movaps %xmm1, %xmm3<br>
-; SSE41-NEXT: subsd %xmm2, %xmm3<br>
-; SSE41-NEXT: cvttsd2si %xmm3, %rax<br>
-; SSE41-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000<br>
-; SSE41-NEXT: xorq %rcx, %rax<br>
-; SSE41-NEXT: cvttsd2si %xmm1, %rdx<br>
-; SSE41-NEXT: ucomisd %xmm2, %xmm1<br>
-; SSE41-NEXT: cmovaeq %rax, %rdx<br>
-; SSE41-NEXT: movaps %xmm0, %xmm1<br>
-; SSE41-NEXT: subsd %xmm2, %xmm1<br>
-; SSE41-NEXT: cvttsd2si %xmm1, %rax<br>
-; SSE41-NEXT: xorq %rcx, %rax<br>
-; SSE41-NEXT: cvttsd2si %xmm0, %rcx<br>
-; SSE41-NEXT: ucomisd %xmm2, %xmm0<br>
-; SSE41-NEXT: cmovaeq %rax, %rcx<br>
-; SSE41-NEXT: movq %rcx, %xmm0<br>
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]<br>
-; SSE41-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1]<br>
-; SSE41-NEXT: movapd {{.*#+}} xmm2 = [4.503600e+15,1.934281e+25]<br>
-; SSE41-NEXT: subpd %xmm2, %xmm0<br>
-; SSE41-NEXT: movq %rdx, %xmm3<br>
-; SSE41-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[<wbr>1]<br>
-; SSE41-NEXT: subpd %xmm2, %xmm3<br>
-; SSE41-NEXT: haddpd %xmm3, %xmm0<br>
+; SSE41-NEXT: roundpd $11, %xmm0, %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: trunc_unsigned_v2f64:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]<br>
-; AVX1-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero<br>
-; AVX1-NEXT: vsubsd %xmm2, %xmm1, %xmm3<br>
-; AVX1-NEXT: vcvttsd2si %xmm3, %rax<br>
-; AVX1-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000<br>
-; AVX1-NEXT: xorq %rcx, %rax<br>
-; AVX1-NEXT: vcvttsd2si %xmm1, %rdx<br>
-; AVX1-NEXT: vucomisd %xmm2, %xmm1<br>
-; AVX1-NEXT: cmovaeq %rax, %rdx<br>
-; AVX1-NEXT: vsubsd %xmm2, %xmm0, %xmm1<br>
-; AVX1-NEXT: vcvttsd2si %xmm1, %rax<br>
-; AVX1-NEXT: xorq %rcx, %rax<br>
-; AVX1-NEXT: vcvttsd2si %xmm0, %rcx<br>
-; AVX1-NEXT: vucomisd %xmm2, %xmm0<br>
-; AVX1-NEXT: cmovaeq %rax, %rcx<br>
-; AVX1-NEXT: vmovq %rcx, %xmm0<br>
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]<br>
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1]<br>
-; AVX1-NEXT: vmovapd {{.*#+}} xmm2 = [4.503600e+15,1.934281e+25]<br>
-; AVX1-NEXT: vsubpd %xmm2, %xmm0, %xmm0<br>
-; AVX1-NEXT: vmovq %rdx, %xmm3<br>
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[<wbr>1]<br>
-; AVX1-NEXT: vsubpd %xmm2, %xmm1, %xmm1<br>
-; AVX1-NEXT: vhaddpd %xmm1, %xmm0, %xmm0<br>
+; AVX1-NEXT: vroundpd $11, %xmm0, %xmm0<br>
; AVX1-NEXT: retq<br>
%i = fptoui <2 x double> %x to <2 x i64><br>
%r = uitofp <2 x i64> %i to <2 x double><br>
@@ -327,106 +217,13 @@ define <4 x double> @trunc_unsigned_v4f6<br>
;<br>
; SSE41-LABEL: trunc_unsigned_v4f64:<br>
; SSE41: # %bb.0:<br>
-; SSE41-NEXT: movaps %xmm1, %xmm3<br>
-; SSE41-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]<br>
-; SSE41-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero<br>
-; SSE41-NEXT: movaps %xmm3, %xmm4<br>
-; SSE41-NEXT: subsd %xmm2, %xmm4<br>
-; SSE41-NEXT: cvttsd2si %xmm4, %rcx<br>
-; SSE41-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000<br>
-; SSE41-NEXT: xorq %rdx, %rcx<br>
-; SSE41-NEXT: cvttsd2si %xmm3, %rax<br>
-; SSE41-NEXT: ucomisd %xmm2, %xmm3<br>
-; SSE41-NEXT: cmovaeq %rcx, %rax<br>
-; SSE41-NEXT: movaps %xmm1, %xmm3<br>
-; SSE41-NEXT: subsd %xmm2, %xmm3<br>
-; SSE41-NEXT: cvttsd2si %xmm3, %rsi<br>
-; SSE41-NEXT: xorq %rdx, %rsi<br>
-; SSE41-NEXT: cvttsd2si %xmm1, %rcx<br>
-; SSE41-NEXT: ucomisd %xmm2, %xmm1<br>
-; SSE41-NEXT: cmovaeq %rsi, %rcx<br>
-; SSE41-NEXT: movaps %xmm0, %xmm1<br>
-; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]<br>
-; SSE41-NEXT: movaps %xmm1, %xmm3<br>
-; SSE41-NEXT: subsd %xmm2, %xmm3<br>
-; SSE41-NEXT: cvttsd2si %xmm3, %rsi<br>
-; SSE41-NEXT: xorq %rdx, %rsi<br>
-; SSE41-NEXT: cvttsd2si %xmm1, %rdi<br>
-; SSE41-NEXT: ucomisd %xmm2, %xmm1<br>
-; SSE41-NEXT: cmovaeq %rsi, %rdi<br>
-; SSE41-NEXT: movaps %xmm0, %xmm1<br>
-; SSE41-NEXT: subsd %xmm2, %xmm1<br>
-; SSE41-NEXT: cvttsd2si %xmm1, %rsi<br>
-; SSE41-NEXT: xorq %rdx, %rsi<br>
-; SSE41-NEXT: cvttsd2si %xmm0, %rdx<br>
-; SSE41-NEXT: ucomisd %xmm2, %xmm0<br>
-; SSE41-NEXT: cmovaeq %rsi, %rdx<br>
-; SSE41-NEXT: movq %rdx, %xmm0<br>
-; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [1127219200,1160773632,0,0]<br>
-; SSE41-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1]<br>
-; SSE41-NEXT: movapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]<br>
-; SSE41-NEXT: subpd %xmm3, %xmm0<br>
-; SSE41-NEXT: movq %rdi, %xmm1<br>
-; SSE41-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[<wbr>1]<br>
-; SSE41-NEXT: subpd %xmm3, %xmm1<br>
-; SSE41-NEXT: haddpd %xmm1, %xmm0<br>
-; SSE41-NEXT: movq %rcx, %xmm1<br>
-; SSE41-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[<wbr>1]<br>
-; SSE41-NEXT: subpd %xmm3, %xmm1<br>
-; SSE41-NEXT: movq %rax, %xmm4<br>
-; SSE41-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[<wbr>1]<br>
-; SSE41-NEXT: subpd %xmm3, %xmm4<br>
-; SSE41-NEXT: haddpd %xmm4, %xmm1<br>
+; SSE41-NEXT: roundpd $11, %xmm0, %xmm0<br>
+; SSE41-NEXT: roundpd $11, %xmm1, %xmm1<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: trunc_unsigned_v4f64:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]<br>
-; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero<br>
-; AVX1-NEXT: vsubsd %xmm1, %xmm2, %xmm3<br>
-; AVX1-NEXT: vcvttsd2si %xmm3, %rcx<br>
-; AVX1-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000<br>
-; AVX1-NEXT: xorq %rdx, %rcx<br>
-; AVX1-NEXT: vcvttsd2si %xmm2, %rax<br>
-; AVX1-NEXT: vucomisd %xmm1, %xmm2<br>
-; AVX1-NEXT: cmovaeq %rcx, %rax<br>
-; AVX1-NEXT: vsubsd %xmm1, %xmm0, %xmm2<br>
-; AVX1-NEXT: vcvttsd2si %xmm2, %rcx<br>
-; AVX1-NEXT: xorq %rdx, %rcx<br>
-; AVX1-NEXT: vcvttsd2si %xmm0, %rsi<br>
-; AVX1-NEXT: vucomisd %xmm1, %xmm0<br>
-; AVX1-NEXT: cmovaeq %rcx, %rsi<br>
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0<br>
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]<br>
-; AVX1-NEXT: vsubsd %xmm1, %xmm2, %xmm3<br>
-; AVX1-NEXT: vcvttsd2si %xmm3, %rcx<br>
-; AVX1-NEXT: xorq %rdx, %rcx<br>
-; AVX1-NEXT: vcvttsd2si %xmm2, %rdi<br>
-; AVX1-NEXT: vucomisd %xmm1, %xmm2<br>
-; AVX1-NEXT: cmovaeq %rcx, %rdi<br>
-; AVX1-NEXT: vsubsd %xmm1, %xmm0, %xmm2<br>
-; AVX1-NEXT: vcvttsd2si %xmm2, %rcx<br>
-; AVX1-NEXT: xorq %rdx, %rcx<br>
-; AVX1-NEXT: vcvttsd2si %xmm0, %rdx<br>
-; AVX1-NEXT: vucomisd %xmm1, %xmm0<br>
-; AVX1-NEXT: cmovaeq %rcx, %rdx<br>
-; AVX1-NEXT: vmovq %rdx, %xmm0<br>
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]<br>
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1]<br>
-; AVX1-NEXT: vmovapd {{.*#+}} xmm2 = [4.503600e+15,1.934281e+25]<br>
-; AVX1-NEXT: vsubpd %xmm2, %xmm0, %xmm0<br>
-; AVX1-NEXT: vmovq %rdi, %xmm3<br>
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[<wbr>1]<br>
-; AVX1-NEXT: vsubpd %xmm2, %xmm3, %xmm3<br>
-; AVX1-NEXT: vhaddpd %xmm3, %xmm0, %xmm0<br>
-; AVX1-NEXT: vmovq %rsi, %xmm3<br>
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[<wbr>1]<br>
-; AVX1-NEXT: vsubpd %xmm2, %xmm3, %xmm3<br>
-; AVX1-NEXT: vmovq %rax, %xmm4<br>
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm4[0],xmm1[0],xmm4[1],xmm1[<wbr>1]<br>
-; AVX1-NEXT: vsubpd %xmm2, %xmm1, %xmm1<br>
-; AVX1-NEXT: vhaddpd %xmm1, %xmm3, %xmm1<br>
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
+; AVX1-NEXT: vroundpd $11, %ymm0, %ymm0<br>
; AVX1-NEXT: retq<br>
%i = fptoui <4 x double> %x to <4 x i64><br>
%r = uitofp <4 x i64> %i to <4 x double><br>
@@ -443,15 +240,12 @@ define float @trunc_signed_f32(float %x)<br>
;<br>
; SSE41-LABEL: trunc_signed_f32:<br>
; SSE41: # %bb.0:<br>
-; SSE41-NEXT: cvttss2si %xmm0, %eax<br>
-; SSE41-NEXT: xorps %xmm0, %xmm0<br>
-; SSE41-NEXT: cvtsi2ssl %eax, %xmm0<br>
+; SSE41-NEXT: roundss $11, %xmm0, %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: trunc_signed_f32:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vcvttss2si %xmm0, %eax<br>
-; AVX1-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm0<br>
+; AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0<br>
; AVX1-NEXT: retq<br>
%i = fptosi float %x to i32<br>
%r = sitofp i32 %i to float<br>
@@ -468,15 +262,12 @@ define double @trunc_signed_f64(double %<br>
;<br>
; SSE41-LABEL: trunc_signed_f64:<br>
; SSE41: # %bb.0:<br>
-; SSE41-NEXT: cvttsd2si %xmm0, %rax<br>
-; SSE41-NEXT: xorps %xmm0, %xmm0<br>
-; SSE41-NEXT: cvtsi2sdq %rax, %xmm0<br>
+; SSE41-NEXT: roundsd $11, %xmm0, %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: trunc_signed_f64:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vcvttsd2si %xmm0, %rax<br>
-; AVX1-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm0<br>
+; AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0<br>
; AVX1-NEXT: retq<br>
%i = fptosi double %x to i64<br>
%r = sitofp i64 %i to double<br>
@@ -492,14 +283,12 @@ define <4 x float> @trunc_signed_v4f32(<<br>
;<br>
; SSE41-LABEL: trunc_signed_v4f32:<br>
; SSE41: # %bb.0:<br>
-; SSE41-NEXT: cvttps2dq %xmm0, %xmm0<br>
-; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0<br>
+; SSE41-NEXT: roundps $11, %xmm0, %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: trunc_signed_v4f32:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vcvttps2dq %xmm0, %xmm0<br>
-; AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0<br>
+; AVX1-NEXT: vroundps $11, %xmm0, %xmm0<br>
; AVX1-NEXT: retq<br>
%i = fptosi <4 x float> %x to <4 x i32><br>
%r = sitofp <4 x i32> %i to <4 x float><br>
@@ -520,23 +309,12 @@ define <2 x double> @trunc_signed_v2f64(<br>
;<br>
; SSE41-LABEL: trunc_signed_v2f64:<br>
; SSE41: # %bb.0:<br>
-; SSE41-NEXT: cvttsd2si %xmm0, %rax<br>
-; SSE41-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]<br>
-; SSE41-NEXT: cvttsd2si %xmm0, %rcx<br>
-; SSE41-NEXT: xorps %xmm0, %xmm0<br>
-; SSE41-NEXT: cvtsi2sdq %rax, %xmm0<br>
-; SSE41-NEXT: cvtsi2sdq %rcx, %xmm1<br>
-; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br>
+; SSE41-NEXT: roundpd $11, %xmm0, %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: trunc_signed_v2f64:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]<br>
-; AVX1-NEXT: vcvttsd2si %xmm1, %rax<br>
-; AVX1-NEXT: vcvttsd2si %xmm0, %rcx<br>
-; AVX1-NEXT: vcvtsi2sdq %rcx, %xmm2, %xmm0<br>
-; AVX1-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm1<br>
-; AVX1-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br>
+; AVX1-NEXT: vroundpd $11, %xmm0, %xmm0<br>
; AVX1-NEXT: retq<br>
%i = fptosi <2 x double> %x to <2 x i64><br>
%r = sitofp <2 x i64> %i to <2 x double><br>
@@ -565,39 +343,13 @@ define <4 x double> @trunc_signed_v4f64(<br>
;<br>
; SSE41-LABEL: trunc_signed_v4f64:<br>
; SSE41: # %bb.0:<br>
-; SSE41-NEXT: cvttsd2si %xmm1, %rax<br>
-; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]<br>
-; SSE41-NEXT: cvttsd2si %xmm1, %rcx<br>
-; SSE41-NEXT: cvttsd2si %xmm0, %rdx<br>
-; SSE41-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]<br>
-; SSE41-NEXT: cvttsd2si %xmm0, %rsi<br>
-; SSE41-NEXT: xorps %xmm0, %xmm0<br>
-; SSE41-NEXT: cvtsi2sdq %rdx, %xmm0<br>
-; SSE41-NEXT: xorps %xmm1, %xmm1<br>
-; SSE41-NEXT: cvtsi2sdq %rsi, %xmm1<br>
-; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br>
-; SSE41-NEXT: xorps %xmm1, %xmm1<br>
-; SSE41-NEXT: cvtsi2sdq %rax, %xmm1<br>
-; SSE41-NEXT: cvtsi2sdq %rcx, %xmm2<br>
-; SSE41-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]<br>
+; SSE41-NEXT: roundpd $11, %xmm0, %xmm0<br>
+; SSE41-NEXT: roundpd $11, %xmm1, %xmm1<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: trunc_signed_v4f64:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]<br>
-; AVX1-NEXT: vcvttsd2si %xmm1, %rax<br>
-; AVX1-NEXT: vcvttsd2si %xmm0, %rcx<br>
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0<br>
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]<br>
-; AVX1-NEXT: vcvttsd2si %xmm1, %rdx<br>
-; AVX1-NEXT: vcvttsd2si %xmm0, %rsi<br>
-; AVX1-NEXT: vcvtsi2sdq %rsi, %xmm2, %xmm0<br>
-; AVX1-NEXT: vcvtsi2sdq %rdx, %xmm2, %xmm1<br>
-; AVX1-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br>
-; AVX1-NEXT: vcvtsi2sdq %rcx, %xmm2, %xmm1<br>
-; AVX1-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2<br>
-; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]<br>
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
+; AVX1-NEXT: vroundpd $11, %ymm0, %ymm0<br>
; AVX1-NEXT: retq<br>
%i = fptosi <4 x double> %x to <4 x i64><br>
%r = sitofp <4 x i64> %i to <4 x double><br>
<br>
<br>
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