<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">We should also add an intrinsic for fpto[us]I with defined overflow behavior, and have the sanitizer call it to people’s attention. Otherwise people will roll their own clamping and most of them will get it wrong, because INT_MAX isn’t representable as a float.<div class=""><br class=""></div><div class="">Ideally we should expose this at the clang level as something like bool __builtin_convert_overflow(src, &dst) and make the one builtin work across types, as with __builtin_add_overflow and friends.<br class=""><div class=""><br class=""></div><div class="">– Steve<br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Apr 25, 2018, at 6:11 PM, Chandler Carruth via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class=""><div class="gmail_quote"><div dir="ltr" class="">On Wed, Apr 25, 2018 at 2:58 PM Sanjay Patel <<a href="mailto:spatel@rotateright.com" class="">spatel@rotateright.com</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr" class=""><div class=""><div class="">Damn...<br class=""><br class=""></div>1. I've never actually used the sanitizers for anything more than simple experiments. But a look at the docs and simple test says this will do it:<br class=""><a href="https://clang.llvm.org/docs/UndefinedBehaviorSanitizer.html" target="_blank" class="">https://clang.llvm.org/docs/UndefinedBehaviorSanitizer.html</a><br class=""><code class="m_-4827511685014259881gmail-docutils m_-4827511685014259881gmail-literal"><span class="m_-4827511685014259881gmail-pre">-fsanitize=float-cast-overflow</span></code></div></div></blockquote><div class=""><br class=""></div><div class="">If this covers everything, great. Maybe document this in the release notes as well? </div><div class=""> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr" class=""><div class=""></div>2. Yes, that's probably wiser. -fjunk-in-trunc ? :)<br class=""></div></blockquote><div class=""><br class=""></div><div class="">-fstrict-fp-trunc-semantics maybe?</div><div class=""><br class=""></div><div class="">Or maybe we should phrase it more:</div><div class=""><br class=""></div><div class="">-ffp-cast-overflow-workaround</div><div class=""><br class=""></div><div class="">To make it clear that enabling this is a bad idea and something that needs to go away?</div><div class=""><br class=""></div><div class="">We should be *really* clear around the documentation of the flag that it will not be supported long term and will go away in a future release. (And be really clear about that in the release notes as well.)</div><div class=""><br class=""></div><div class="">May make sense to make it CC1 only.</div><div class=""><br class=""></div><div class="">Anyways, all of this is a better clang commits list discussion. =]</div><div class=""> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr" class=""><div class=""><br class=""><br class=""></div></div><div class="gmail_extra"><br class=""><div class="gmail_quote">On Wed, Apr 25, 2018 at 3:38 PM, Chandler Carruth <span dir="ltr" class=""><<a href="mailto:chandlerc@gmail.com" target="_blank" class="">chandlerc@gmail.com</a>></span> wrote:<br class=""><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr" class="">Hey Sanjay, this is hitting a *lot* of code, even outside of Chrome....<div class=""><br class=""></div><div class="">I think we need a more nuanced way to handle this.</div><div class=""><br class=""></div><div class="">1) Is there a specific sanitizer that we can enable that will point out *just* the issues this impacts?</div><div class=""><br class=""></div><div class="">2) Can we have a flag to control this behavior at least for a temporary period of time? that would make it much easier to roll out when there are very large numbers of issues encountered.</div></div><div class="m_-4827511685014259881HOEnZb"><div class="m_-4827511685014259881h5"><br class=""><div class="gmail_quote"><div dir="ltr" class="">On Fri, Apr 20, 2018 at 8:11 AM Sanjay Patel via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: spatel<br class="">
Date: Fri Apr 20 08:07:55 2018<br class="">
New Revision: 330437<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=330437&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project?rev=330437&view=rev</a><br class="">
Log:<br class="">
[DAGCombine] (float)((int) f) --> ftrunc (PR36617)<br class="">
<br class="">
This was originally committed at rL328921 and reverted at rL329920 to<br class="">
investigate failures in Chrome. This time I've added to the ReleaseNotes<br class="">
to warn users of the potential of exposing UB and let me repeat that<br class="">
here for more exposure:<br class="">
<br class="">
Optimization of floating-point casts is improved. This may cause surprising<br class="">
results for code that is relying on undefined behavior. Code sanitizers can<br class="">
be used to detect affected patterns such as this:<br class="">
<br class="">
int main() {<br class="">
float x = 4294967296.0f;<br class="">
x = (float)((int)x);<br class="">
printf("junk in the ftrunc: %f\n", x);<br class="">
return 0;<br class="">
}<br class="">
<br class="">
$ clang -O1 ftrunc.c -fsanitize=undefined ; ./a.out<br class="">
ftrunc.c:5:15: runtime error: 4.29497e+09 is outside the range of <br class="">
representable values of type 'int'<br class="">
junk in the ftrunc: 0.000000<br class="">
<br class="">
<br class="">
Original commit message:<br class="">
<br class="">
fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC,<br class="">
so replace a pair of casts with the equivalent node. We don't have to account for<br class="">
special cases (NaN, INF) because out-of-range casts are undefined.<br class="">
<br class="">
Differential Revision: <a href="https://reviews.llvm.org/D44909" rel="noreferrer" target="_blank" class="">https://reviews.llvm.org/D44909</a><br class="">
<br class="">
Added:<br class="">
llvm/trunk/test/CodeGen/ARM/ftrunc.ll<br class="">
- copied unchanged from r329919, llvm/trunk/test/CodeGen/ARM/ftrunc.ll<br class="">
Modified:<br class="">
llvm/trunk/docs/ReleaseNotes.rst<br class="">
llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h<br class="">
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br class="">
llvm/trunk/test/CodeGen/AArch64/ftrunc.ll<br class="">
llvm/trunk/test/CodeGen/PowerPC/fp-int128-fp-combine.ll<br class="">
llvm/trunk/test/CodeGen/PowerPC/fp-to-int-to-fp.ll<br class="">
llvm/trunk/test/CodeGen/PowerPC/ftrunc-vec.ll<br class="">
llvm/trunk/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll<br class="">
llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll<br class="">
llvm/trunk/test/CodeGen/X86/ftrunc.ll<br class="">
<br class="">
Modified: llvm/trunk/docs/ReleaseNotes.rst<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.rst?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.rst?rev=330437&r1=330436&r2=330437&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/docs/ReleaseNotes.rst (original)<br class="">
+++ llvm/trunk/docs/ReleaseNotes.rst Fri Apr 20 08:07:55 2018<br class="">
@@ -61,6 +61,26 @@ Non-comprehensive list of changes in thi<br class="">
* The optimization flag to merge constants (-fmerge-all-constants) is no longer<br class="">
applied by default.<br class="">
<br class="">
+* Optimization of floating-point casts is improved. This may cause surprising<br class="">
+ results for code that is relying on undefined behavior. Code sanitizers can<br class="">
+ be used to detect affected patterns such as this:<br class="">
+<br class="">
+.. code-block:: c<br class="">
+<br class="">
+ int main() {<br class="">
+ float x = 4294967296.0f;<br class="">
+ x = (float)((int)x);<br class="">
+ printf("junk in the ftrunc: %f\n", x);<br class="">
+ return 0;<br class="">
+ }<br class="">
+<br class="">
+.. code-block:: bash<br class="">
+<br class="">
+ clang -O1 ftrunc.c -fsanitize=undefined ; ./a.out <br class="">
+ ftrunc.c:5:15: runtime error: 4.29497e+09 is outside the range of representable values of type 'int'<br class="">
+ junk in the ftrunc: 0.000000<br class="">
+<br class="">
+<br class="">
* Note..<br class="">
<br class="">
.. NOTE<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h?rev=330437&r1=330436&r2=330437&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h (original)<br class="">
+++ llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Fri Apr 20 08:07:55 2018<br class="">
@@ -495,7 +495,8 @@ namespace ISD {<br class="">
ZERO_EXTEND_VECTOR_INREG,<br class="">
<br class="">
/// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned<br class="">
- /// integer.<br class="">
+ /// integer. These have the same semantics as fptosi and fptoui in IR. If<br class="">
+ /// the FP value cannot fit in the integer type, the results are undefined.<br class="">
FP_TO_SINT,<br class="">
FP_TO_UINT,<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=330437&r1=330436&r2=330437&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Apr 20 08:07:55 2018<br class="">
@@ -10890,6 +10890,15 @@ SDValue DAGCombiner::visitSINT_TO_FP(SDN<br class="">
}<br class="">
}<br class="">
<br class="">
+ // fptosi rounds towards zero, so converting from FP to integer and back is<br class="">
+ // the same as an 'ftrunc': sitofp (fptosi X) --> ftrunc X<br class="">
+ // We only do this if the target has legal ftrunc, otherwise we'd likely be<br class="">
+ // replacing casts with a libcall.<br class="">
+ if (N0.getOpcode() == ISD::FP_TO_SINT &&<br class="">
+ N0.getOperand(0).getValueType() == VT &&<br class="">
+ TLI.isOperationLegal(ISD::FTRUNC, VT))<br class="">
+ return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0));<br class="">
+<br class="">
return SDValue();<br class="">
}<br class="">
<br class="">
@@ -10929,6 +10938,15 @@ SDValue DAGCombiner::visitUINT_TO_FP(SDN<br class="">
}<br class="">
}<br class="">
<br class="">
+ // fptoui rounds towards zero, so converting from FP to integer and back is<br class="">
+ // the same as an 'ftrunc': uitofp (fptoui X) --> ftrunc X<br class="">
+ // We only do this if the target has legal ftrunc, otherwise we'd likely be<br class="">
+ // replacing casts with a libcall.<br class="">
+ if (N0.getOpcode() == ISD::FP_TO_UINT &&<br class="">
+ N0.getOperand(0).getValueType() == VT &&<br class="">
+ TLI.isOperationLegal(ISD::FTRUNC, VT))<br class="">
+ return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0));<br class="">
+<br class="">
return SDValue();<br class="">
}<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AArch64/ftrunc.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ftrunc.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ftrunc.ll?rev=330437&r1=330436&r2=330437&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AArch64/ftrunc.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/AArch64/ftrunc.ll Fri Apr 20 08:07:55 2018<br class="">
@@ -4,8 +4,7 @@<br class="">
define float @trunc_unsigned_f32(float %x) {<br class="">
; CHECK-LABEL: trunc_unsigned_f32:<br class="">
; CHECK: // %bb.0:<br class="">
-; CHECK-NEXT: fcvtzu w8, s0<br class="">
-; CHECK-NEXT: ucvtf s0, w8<br class="">
+; CHECK-NEXT: frintz s0, s0<br class="">
; CHECK-NEXT: ret<br class="">
%i = fptoui float %x to i32<br class="">
%r = uitofp i32 %i to float<br class="">
@@ -15,8 +14,7 @@ define float @trunc_unsigned_f32(float %<br class="">
define double @trunc_unsigned_f64(double %x) {<br class="">
; CHECK-LABEL: trunc_unsigned_f64:<br class="">
; CHECK: // %bb.0:<br class="">
-; CHECK-NEXT: fcvtzu x8, d0<br class="">
-; CHECK-NEXT: ucvtf d0, x8<br class="">
+; CHECK-NEXT: frintz d0, d0<br class="">
; CHECK-NEXT: ret<br class="">
%i = fptoui double %x to i64<br class="">
%r = uitofp i64 %i to double<br class="">
@@ -26,8 +24,7 @@ define double @trunc_unsigned_f64(double<br class="">
define float @trunc_signed_f32(float %x) {<br class="">
; CHECK-LABEL: trunc_signed_f32:<br class="">
; CHECK: // %bb.0:<br class="">
-; CHECK-NEXT: fcvtzs w8, s0<br class="">
-; CHECK-NEXT: scvtf s0, w8<br class="">
+; CHECK-NEXT: frintz s0, s0<br class="">
; CHECK-NEXT: ret<br class="">
%i = fptosi float %x to i32<br class="">
%r = sitofp i32 %i to float<br class="">
@@ -37,8 +34,7 @@ define float @trunc_signed_f32(float %x)<br class="">
define double @trunc_signed_f64(double %x) {<br class="">
; CHECK-LABEL: trunc_signed_f64:<br class="">
; CHECK: // %bb.0:<br class="">
-; CHECK-NEXT: fcvtzs x8, d0<br class="">
-; CHECK-NEXT: scvtf d0, x8<br class="">
+; CHECK-NEXT: frintz d0, d0<br class="">
; CHECK-NEXT: ret<br class="">
%i = fptosi double %x to i64<br class="">
%r = sitofp i64 %i to double<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/PowerPC/fp-int128-fp-combine.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fp-int128-fp-combine.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fp-int128-fp-combine.ll?rev=330437&r1=330436&r2=330437&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/PowerPC/fp-int128-fp-combine.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/PowerPC/fp-int128-fp-combine.ll Fri Apr 20 08:07:55 2018<br class="">
@@ -5,18 +5,7 @@<br class="">
define float @f_i128_f(float %v) {<br class="">
; CHECK-LABEL: f_i128_f:<br class="">
; CHECK: # %bb.0: # %entry<br class="">
-; CHECK-NEXT: mflr 0<br class="">
-; CHECK-NEXT: std 0, 16(1)<br class="">
-; CHECK-NEXT: stdu 1, -32(1)<br class="">
-; CHECK-NEXT: .cfi_def_cfa_offset 32<br class="">
-; CHECK-NEXT: .cfi_offset lr, 16<br class="">
-; CHECK-NEXT: bl __fixsfti<br class="">
-; CHECK-NEXT: nop<br class="">
-; CHECK-NEXT: bl __floattisf<br class="">
-; CHECK-NEXT: nop<br class="">
-; CHECK-NEXT: addi 1, 1, 32<br class="">
-; CHECK-NEXT: ld 0, 16(1)<br class="">
-; CHECK-NEXT: mtlr 0<br class="">
+; CHECK-NEXT: friz 1, 1<br class="">
; CHECK-NEXT: blr<br class="">
entry:<br class="">
%a = fptosi float %v to i128<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/PowerPC/fp-to-int-to-fp.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fp-to-int-to-fp.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fp-to-int-to-fp.ll?rev=330437&r1=330436&r2=330437&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/PowerPC/fp-to-int-to-fp.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/PowerPC/fp-to-int-to-fp.ll Fri Apr 20 08:07:55 2018<br class="">
@@ -11,8 +11,7 @@ entry:<br class="">
ret float %conv1<br class="">
<br class="">
; FPCVT-LABEL: @fool<br class="">
-; FPCVT: fctidz [[REG1:[0-9]+]], 1<br class="">
-; FPCVT: fcfids 1, [[REG1]]<br class="">
+; FPCVT: friz 1, 1<br class="">
; FPCVT: blr<br class="">
<br class="">
; PPC64-LABEL: @fool<br class="">
@@ -30,8 +29,7 @@ entry:<br class="">
ret double %conv1<br class="">
<br class="">
; FPCVT-LABEL: @foodl<br class="">
-; FPCVT: fctidz [[REG1:[0-9]+]], 1<br class="">
-; FPCVT: fcfid 1, [[REG1]]<br class="">
+; FPCVT: friz 1, 1<br class="">
; FPCVT: blr<br class="">
<br class="">
; PPC64-LABEL: @foodl<br class="">
@@ -48,8 +46,7 @@ entry:<br class="">
ret float %conv1<br class="">
<br class="">
; FPCVT-LABEL: @fooul<br class="">
-; FPCVT: fctiduz [[REG1:[0-9]+]], 1<br class="">
-; FPCVT: fcfidus 1, [[REG1]]<br class="">
+; FPCVT: friz 1, 1<br class="">
; FPCVT: blr<br class="">
}<br class="">
<br class="">
@@ -61,8 +58,7 @@ entry:<br class="">
ret double %conv1<br class="">
<br class="">
; FPCVT-LABEL: @fooudl<br class="">
-; FPCVT: fctiduz [[REG1:[0-9]+]], 1<br class="">
-; FPCVT: fcfidu 1, [[REG1]]<br class="">
+; FPCVT: friz 1, 1<br class="">
; FPCVT: blr<br class="">
}<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/PowerPC/ftrunc-vec.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ftrunc-vec.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ftrunc-vec.ll?rev=330437&r1=330436&r2=330437&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/PowerPC/ftrunc-vec.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/PowerPC/ftrunc-vec.ll Fri Apr 20 08:07:55 2018<br class="">
@@ -4,8 +4,7 @@<br class="">
define <4 x float> @truncf32(<4 x float> %a) {<br class="">
; CHECK-LABEL: truncf32:<br class="">
; CHECK: # %bb.0:<br class="">
-; CHECK-NEXT: xvcvspsxws 0, 34<br class="">
-; CHECK-NEXT: xvcvsxwsp 34, 0<br class="">
+; CHECK-NEXT: xvrspiz 34, 34<br class="">
; CHECK-NEXT: blr<br class="">
%t0 = fptosi <4 x float> %a to <4 x i32><br class="">
%t1 = sitofp <4 x i32> %t0 to <4 x float><br class="">
@@ -15,8 +14,7 @@ define <4 x float> @truncf32(<4 x float><br class="">
define <2 x double> @truncf64(<2 x double> %a) {<br class="">
; CHECK-LABEL: truncf64:<br class="">
; CHECK: # %bb.0:<br class="">
-; CHECK-NEXT: xvcvdpsxds 34, 34<br class="">
-; CHECK-NEXT: xvcvsxddp 34, 34<br class="">
+; CHECK-NEXT: xvrdpiz 34, 34<br class="">
; CHECK-NEXT: blr<br class="">
%t0 = fptosi <2 x double> %a to <2 x i64><br class="">
%t1 = sitofp <2 x i64> %t0 to <2 x double><br class="">
@@ -26,8 +24,7 @@ define <2 x double> @truncf64(<2 x doubl<br class="">
define <4 x float> @truncf32u(<4 x float> %a) {<br class="">
; CHECK-LABEL: truncf32u:<br class="">
; CHECK: # %bb.0:<br class="">
-; CHECK-NEXT: xvcvspuxws 0, 34<br class="">
-; CHECK-NEXT: xvcvuxwsp 34, 0<br class="">
+; CHECK-NEXT: xvrspiz 34, 34<br class="">
; CHECK-NEXT: blr<br class="">
%t0 = fptoui <4 x float> %a to <4 x i32><br class="">
%t1 = uitofp <4 x i32> %t0 to <4 x float><br class="">
@@ -37,8 +34,7 @@ define <4 x float> @truncf32u(<4 x float<br class="">
define <2 x double> @truncf64u(<2 x double> %a) {<br class="">
; CHECK-LABEL: truncf64u:<br class="">
; CHECK: # %bb.0:<br class="">
-; CHECK-NEXT: xvcvdpuxds 34, 34<br class="">
-; CHECK-NEXT: xvcvuxddp 34, 34<br class="">
+; CHECK-NEXT: xvrdpiz 34, 34<br class="">
; CHECK-NEXT: blr<br class="">
%t0 = fptoui <2 x double> %a to <2 x i64><br class="">
%t1 = uitofp <2 x i64> %t0 to <2 x double><br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll?rev=330437&r1=330436&r2=330437&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll Fri Apr 20 08:07:55 2018<br class="">
@@ -36,11 +36,7 @@ entry:<br class="">
ret float %conv1<br class="">
<br class="">
; CHECK-LABEL: @foo<br class="">
-; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1<br class="">
-; CHECK-DAG: addi [[REG1:[0-9]+]], 1,<br class="">
-; CHECK: stfiwx [[REG2]], 0, [[REG1]]<br class="">
-; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]<br class="">
-; CHECK: fcfids 1, [[REG3]]<br class="">
+; CHECK: friz 1, 1<br class="">
; CHECK: blr<br class="">
}<br class="">
<br class="">
@@ -52,11 +48,7 @@ entry:<br class="">
ret double %conv1<br class="">
<br class="">
; CHECK-LABEL: @food<br class="">
-; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1<br class="">
-; CHECK-DAG: addi [[REG1:[0-9]+]], 1,<br class="">
-; CHECK: stfiwx [[REG2]], 0, [[REG1]]<br class="">
-; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]<br class="">
-; CHECK: fcfid 1, [[REG3]]<br class="">
+; CHECK: friz 1, 1<br class="">
; CHECK: blr<br class="">
}<br class="">
<br class="">
@@ -68,11 +60,7 @@ entry:<br class="">
ret float %conv1<br class="">
<br class="">
; CHECK-LABEL: @foou<br class="">
-; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1<br class="">
-; CHECK-DAG: addi [[REG1:[0-9]+]], 1,<br class="">
-; CHECK: stfiwx [[REG2]], 0, [[REG1]]<br class="">
-; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]]<br class="">
-; CHECK: fcfidus 1, [[REG3]]<br class="">
+; CHECK: friz 1, 1<br class="">
; CHECK: blr<br class="">
}<br class="">
<br class="">
@@ -84,11 +72,7 @@ entry:<br class="">
ret double %conv1<br class="">
<br class="">
; CHECK-LABEL: @fooud<br class="">
-; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1<br class="">
-; CHECK-DAG: addi [[REG1:[0-9]+]], 1,<br class="">
-; CHECK: stfiwx [[REG2]], 0, [[REG1]]<br class="">
-; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]]<br class="">
-; CHECK: fcfidu 1, [[REG3]]<br class="">
+; CHECK: friz 1, 1<br class="">
; CHECK: blr<br class="">
}<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll?rev=330437&r1=330436&r2=330437&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll Fri Apr 20 08:07:55 2018<br class="">
@@ -71,8 +71,7 @@ define void @full_test() {<br class="">
; X32-NEXT: subl $60, %esp<br class="">
; X32-NEXT: .cfi_def_cfa_offset 64<br class="">
; X32-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero<br class="">
-; X32-NEXT: cvttps2dq %xmm2, %xmm0<br class="">
-; X32-NEXT: cvtdq2ps %xmm0, %xmm1<br class="">
+; X32-NEXT: roundps $11, %xmm2, %xmm1<br class="">
; X32-NEXT: xorps %xmm0, %xmm0<br class="">
; X32-NEXT: cmpltps %xmm2, %xmm0<br class="">
; X32-NEXT: movaps {{.*#+}} xmm3 = <1,1,u,u><br class="">
@@ -93,8 +92,7 @@ define void @full_test() {<br class="">
; X64-LABEL: full_test:<br class="">
; X64: # %bb.0: # %entry<br class="">
; X64-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero<br class="">
-; X64-NEXT: cvttps2dq %xmm2, %xmm0<br class="">
-; X64-NEXT: cvtdq2ps %xmm0, %xmm1<br class="">
+; X64-NEXT: roundps $11, %xmm2, %xmm1<br class="">
; X64-NEXT: xorps %xmm0, %xmm0<br class="">
; X64-NEXT: cmpltps %xmm2, %xmm0<br class="">
; X64-NEXT: movaps {{.*#+}} xmm3 = <1,1,u,u><br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/ftrunc.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ftrunc.ll?rev=330437&r1=330436&r2=330437&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ftrunc.ll?rev=330437&r1=330436&r2=330437&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/ftrunc.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/ftrunc.ll Fri Apr 20 08:07:55 2018<br class="">
@@ -14,17 +14,12 @@ define float @trunc_unsigned_f32(float %<br class="">
;<br class="">
; SSE41-LABEL: trunc_unsigned_f32:<br class="">
; SSE41: # %bb.0:<br class="">
-; SSE41-NEXT: cvttss2si %xmm0, %rax<br class="">
-; SSE41-NEXT: movl %eax, %eax<br class="">
-; SSE41-NEXT: xorps %xmm0, %xmm0<br class="">
-; SSE41-NEXT: cvtsi2ssq %rax, %xmm0<br class="">
+; SSE41-NEXT: roundss $11, %xmm0, %xmm0<br class="">
; SSE41-NEXT: retq<br class="">
;<br class="">
; AVX1-LABEL: trunc_unsigned_f32:<br class="">
; AVX1: # %bb.0:<br class="">
-; AVX1-NEXT: vcvttss2si %xmm0, %rax<br class="">
-; AVX1-NEXT: movl %eax, %eax<br class="">
-; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm0<br class="">
+; AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0<br class="">
; AVX1-NEXT: retq<br class="">
%i = fptoui float %x to i32<br class="">
%r = uitofp i32 %i to float<br class="">
@@ -52,35 +47,12 @@ define double @trunc_unsigned_f64(double<br class="">
;<br class="">
; SSE41-LABEL: trunc_unsigned_f64:<br class="">
; SSE41: # %bb.0:<br class="">
-; SSE41-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero<br class="">
-; SSE41-NEXT: movapd %xmm0, %xmm2<br class="">
-; SSE41-NEXT: subsd %xmm1, %xmm2<br class="">
-; SSE41-NEXT: cvttsd2si %xmm2, %rax<br class="">
-; SSE41-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000<br class="">
-; SSE41-NEXT: xorq %rax, %rcx<br class="">
-; SSE41-NEXT: cvttsd2si %xmm0, %rax<br class="">
-; SSE41-NEXT: ucomisd %xmm1, %xmm0<br class="">
-; SSE41-NEXT: cmovaeq %rcx, %rax<br class="">
-; SSE41-NEXT: movq %rax, %xmm0<br class="">
-; SSE41-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]<br class="">
-; SSE41-NEXT: subpd {{.*}}(%rip), %xmm0<br class="">
-; SSE41-NEXT: haddpd %xmm0, %xmm0<br class="">
+; SSE41-NEXT: roundsd $11, %xmm0, %xmm0<br class="">
; SSE41-NEXT: retq<br class="">
;<br class="">
; AVX1-LABEL: trunc_unsigned_f64:<br class="">
; AVX1: # %bb.0:<br class="">
-; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero<br class="">
-; AVX1-NEXT: vsubsd %xmm1, %xmm0, %xmm2<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm2, %rax<br class="">
-; AVX1-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000<br class="">
-; AVX1-NEXT: xorq %rax, %rcx<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm0, %rax<br class="">
-; AVX1-NEXT: vucomisd %xmm1, %xmm0<br class="">
-; AVX1-NEXT: cmovaeq %rcx, %rax<br class="">
-; AVX1-NEXT: vmovq %rax, %xmm0<br class="">
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]<br class="">
-; AVX1-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0<br class="">
-; AVX1-NEXT: vhaddpd %xmm0, %xmm0, %xmm0<br class="">
+; AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0<br class="">
; AVX1-NEXT: retq<br class="">
%i = fptoui double %x to i64<br class="">
%r = uitofp i64 %i to double<br class="">
@@ -118,45 +90,12 @@ define <4 x float> @trunc_unsigned_v4f32<br class="">
;<br class="">
; SSE41-LABEL: trunc_unsigned_v4f32:<br class="">
; SSE41: # %bb.0:<br class="">
-; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]<br class="">
-; SSE41-NEXT: cvttss2si %xmm1, %rax<br class="">
-; SSE41-NEXT: cvttss2si %xmm0, %rcx<br class="">
-; SSE41-NEXT: movd %ecx, %xmm1<br class="">
-; SSE41-NEXT: pinsrd $1, %eax, %xmm1<br class="">
-; SSE41-NEXT: movaps %xmm0, %xmm2<br class="">
-; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]<br class="">
-; SSE41-NEXT: cvttss2si %xmm2, %rax<br class="">
-; SSE41-NEXT: pinsrd $2, %eax, %xmm1<br class="">
-; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]<br class="">
-; SSE41-NEXT: cvttss2si %xmm0, %rax<br class="">
-; SSE41-NEXT: pinsrd $3, %eax, %xmm1<br class="">
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [1258291200,1258291200,1258291200,1258291200]<br class="">
-; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3],xmm1[4],xmm0[5],xmm1[6],xmm0[7]<br class="">
-; SSE41-NEXT: psrld $16, %xmm1<br class="">
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0],mem[1],xmm1[2],mem[3],xmm1[4],mem[5],xmm1[6],mem[7]<br class="">
-; SSE41-NEXT: addps {{.*}}(%rip), %xmm1<br class="">
-; SSE41-NEXT: addps %xmm0, %xmm1<br class="">
-; SSE41-NEXT: movaps %xmm1, %xmm0<br class="">
+; SSE41-NEXT: roundps $11, %xmm0, %xmm0<br class="">
; SSE41-NEXT: retq<br class="">
;<br class="">
; AVX1-LABEL: trunc_unsigned_v4f32:<br class="">
; AVX1: # %bb.0:<br class="">
-; AVX1-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]<br class="">
-; AVX1-NEXT: vcvttss2si %xmm1, %rax<br class="">
-; AVX1-NEXT: vcvttss2si %xmm0, %rcx<br class="">
-; AVX1-NEXT: vmovd %ecx, %xmm1<br class="">
-; AVX1-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1<br class="">
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]<br class="">
-; AVX1-NEXT: vcvttss2si %xmm2, %rax<br class="">
-; AVX1-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1<br class="">
-; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3]<br class="">
-; AVX1-NEXT: vcvttss2si %xmm0, %rax<br class="">
-; AVX1-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0<br class="">
-; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]<br class="">
-; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0<br class="">
-; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]<br class="">
-; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0<br class="">
-; AVX1-NEXT: vaddps %xmm0, %xmm1, %xmm0<br class="">
+; AVX1-NEXT: vroundps $11, %xmm0, %xmm0<br class="">
; AVX1-NEXT: retq<br class="">
%i = fptoui <4 x float> %x to <4 x i32><br class="">
%r = uitofp <4 x i32> %i to <4 x float><br class="">
@@ -201,61 +140,12 @@ define <2 x double> @trunc_unsigned_v2f6<br class="">
;<br class="">
; SSE41-LABEL: trunc_unsigned_v2f64:<br class="">
; SSE41: # %bb.0:<br class="">
-; SSE41-NEXT: movaps %xmm0, %xmm1<br class="">
-; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]<br class="">
-; SSE41-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero<br class="">
-; SSE41-NEXT: movaps %xmm1, %xmm3<br class="">
-; SSE41-NEXT: subsd %xmm2, %xmm3<br class="">
-; SSE41-NEXT: cvttsd2si %xmm3, %rax<br class="">
-; SSE41-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000<br class="">
-; SSE41-NEXT: xorq %rcx, %rax<br class="">
-; SSE41-NEXT: cvttsd2si %xmm1, %rdx<br class="">
-; SSE41-NEXT: ucomisd %xmm2, %xmm1<br class="">
-; SSE41-NEXT: cmovaeq %rax, %rdx<br class="">
-; SSE41-NEXT: movaps %xmm0, %xmm1<br class="">
-; SSE41-NEXT: subsd %xmm2, %xmm1<br class="">
-; SSE41-NEXT: cvttsd2si %xmm1, %rax<br class="">
-; SSE41-NEXT: xorq %rcx, %rax<br class="">
-; SSE41-NEXT: cvttsd2si %xmm0, %rcx<br class="">
-; SSE41-NEXT: ucomisd %xmm2, %xmm0<br class="">
-; SSE41-NEXT: cmovaeq %rax, %rcx<br class="">
-; SSE41-NEXT: movq %rcx, %xmm0<br class="">
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]<br class="">
-; SSE41-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]<br class="">
-; SSE41-NEXT: movapd {{.*#+}} xmm2 = [4.503600e+15,1.934281e+25]<br class="">
-; SSE41-NEXT: subpd %xmm2, %xmm0<br class="">
-; SSE41-NEXT: movq %rdx, %xmm3<br class="">
-; SSE41-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]<br class="">
-; SSE41-NEXT: subpd %xmm2, %xmm3<br class="">
-; SSE41-NEXT: haddpd %xmm3, %xmm0<br class="">
+; SSE41-NEXT: roundpd $11, %xmm0, %xmm0<br class="">
; SSE41-NEXT: retq<br class="">
;<br class="">
; AVX1-LABEL: trunc_unsigned_v2f64:<br class="">
; AVX1: # %bb.0:<br class="">
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]<br class="">
-; AVX1-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero<br class="">
-; AVX1-NEXT: vsubsd %xmm2, %xmm1, %xmm3<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm3, %rax<br class="">
-; AVX1-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000<br class="">
-; AVX1-NEXT: xorq %rcx, %rax<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm1, %rdx<br class="">
-; AVX1-NEXT: vucomisd %xmm2, %xmm1<br class="">
-; AVX1-NEXT: cmovaeq %rax, %rdx<br class="">
-; AVX1-NEXT: vsubsd %xmm2, %xmm0, %xmm1<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm1, %rax<br class="">
-; AVX1-NEXT: xorq %rcx, %rax<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm0, %rcx<br class="">
-; AVX1-NEXT: vucomisd %xmm2, %xmm0<br class="">
-; AVX1-NEXT: cmovaeq %rax, %rcx<br class="">
-; AVX1-NEXT: vmovq %rcx, %xmm0<br class="">
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]<br class="">
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]<br class="">
-; AVX1-NEXT: vmovapd {{.*#+}} xmm2 = [4.503600e+15,1.934281e+25]<br class="">
-; AVX1-NEXT: vsubpd %xmm2, %xmm0, %xmm0<br class="">
-; AVX1-NEXT: vmovq %rdx, %xmm3<br class="">
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]<br class="">
-; AVX1-NEXT: vsubpd %xmm2, %xmm1, %xmm1<br class="">
-; AVX1-NEXT: vhaddpd %xmm1, %xmm0, %xmm0<br class="">
+; AVX1-NEXT: vroundpd $11, %xmm0, %xmm0<br class="">
; AVX1-NEXT: retq<br class="">
%i = fptoui <2 x double> %x to <2 x i64><br class="">
%r = uitofp <2 x i64> %i to <2 x double><br class="">
@@ -327,106 +217,13 @@ define <4 x double> @trunc_unsigned_v4f6<br class="">
;<br class="">
; SSE41-LABEL: trunc_unsigned_v4f64:<br class="">
; SSE41: # %bb.0:<br class="">
-; SSE41-NEXT: movaps %xmm1, %xmm3<br class="">
-; SSE41-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]<br class="">
-; SSE41-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero<br class="">
-; SSE41-NEXT: movaps %xmm3, %xmm4<br class="">
-; SSE41-NEXT: subsd %xmm2, %xmm4<br class="">
-; SSE41-NEXT: cvttsd2si %xmm4, %rcx<br class="">
-; SSE41-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000<br class="">
-; SSE41-NEXT: xorq %rdx, %rcx<br class="">
-; SSE41-NEXT: cvttsd2si %xmm3, %rax<br class="">
-; SSE41-NEXT: ucomisd %xmm2, %xmm3<br class="">
-; SSE41-NEXT: cmovaeq %rcx, %rax<br class="">
-; SSE41-NEXT: movaps %xmm1, %xmm3<br class="">
-; SSE41-NEXT: subsd %xmm2, %xmm3<br class="">
-; SSE41-NEXT: cvttsd2si %xmm3, %rsi<br class="">
-; SSE41-NEXT: xorq %rdx, %rsi<br class="">
-; SSE41-NEXT: cvttsd2si %xmm1, %rcx<br class="">
-; SSE41-NEXT: ucomisd %xmm2, %xmm1<br class="">
-; SSE41-NEXT: cmovaeq %rsi, %rcx<br class="">
-; SSE41-NEXT: movaps %xmm0, %xmm1<br class="">
-; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]<br class="">
-; SSE41-NEXT: movaps %xmm1, %xmm3<br class="">
-; SSE41-NEXT: subsd %xmm2, %xmm3<br class="">
-; SSE41-NEXT: cvttsd2si %xmm3, %rsi<br class="">
-; SSE41-NEXT: xorq %rdx, %rsi<br class="">
-; SSE41-NEXT: cvttsd2si %xmm1, %rdi<br class="">
-; SSE41-NEXT: ucomisd %xmm2, %xmm1<br class="">
-; SSE41-NEXT: cmovaeq %rsi, %rdi<br class="">
-; SSE41-NEXT: movaps %xmm0, %xmm1<br class="">
-; SSE41-NEXT: subsd %xmm2, %xmm1<br class="">
-; SSE41-NEXT: cvttsd2si %xmm1, %rsi<br class="">
-; SSE41-NEXT: xorq %rdx, %rsi<br class="">
-; SSE41-NEXT: cvttsd2si %xmm0, %rdx<br class="">
-; SSE41-NEXT: ucomisd %xmm2, %xmm0<br class="">
-; SSE41-NEXT: cmovaeq %rsi, %rdx<br class="">
-; SSE41-NEXT: movq %rdx, %xmm0<br class="">
-; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [1127219200,1160773632,0,0]<br class="">
-; SSE41-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]<br class="">
-; SSE41-NEXT: movapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]<br class="">
-; SSE41-NEXT: subpd %xmm3, %xmm0<br class="">
-; SSE41-NEXT: movq %rdi, %xmm1<br class="">
-; SSE41-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]<br class="">
-; SSE41-NEXT: subpd %xmm3, %xmm1<br class="">
-; SSE41-NEXT: haddpd %xmm1, %xmm0<br class="">
-; SSE41-NEXT: movq %rcx, %xmm1<br class="">
-; SSE41-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]<br class="">
-; SSE41-NEXT: subpd %xmm3, %xmm1<br class="">
-; SSE41-NEXT: movq %rax, %xmm4<br class="">
-; SSE41-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]<br class="">
-; SSE41-NEXT: subpd %xmm3, %xmm4<br class="">
-; SSE41-NEXT: haddpd %xmm4, %xmm1<br class="">
+; SSE41-NEXT: roundpd $11, %xmm0, %xmm0<br class="">
+; SSE41-NEXT: roundpd $11, %xmm1, %xmm1<br class="">
; SSE41-NEXT: retq<br class="">
;<br class="">
; AVX1-LABEL: trunc_unsigned_v4f64:<br class="">
; AVX1: # %bb.0:<br class="">
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]<br class="">
-; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero<br class="">
-; AVX1-NEXT: vsubsd %xmm1, %xmm2, %xmm3<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm3, %rcx<br class="">
-; AVX1-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000<br class="">
-; AVX1-NEXT: xorq %rdx, %rcx<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm2, %rax<br class="">
-; AVX1-NEXT: vucomisd %xmm1, %xmm2<br class="">
-; AVX1-NEXT: cmovaeq %rcx, %rax<br class="">
-; AVX1-NEXT: vsubsd %xmm1, %xmm0, %xmm2<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm2, %rcx<br class="">
-; AVX1-NEXT: xorq %rdx, %rcx<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm0, %rsi<br class="">
-; AVX1-NEXT: vucomisd %xmm1, %xmm0<br class="">
-; AVX1-NEXT: cmovaeq %rcx, %rsi<br class="">
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0<br class="">
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]<br class="">
-; AVX1-NEXT: vsubsd %xmm1, %xmm2, %xmm3<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm3, %rcx<br class="">
-; AVX1-NEXT: xorq %rdx, %rcx<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm2, %rdi<br class="">
-; AVX1-NEXT: vucomisd %xmm1, %xmm2<br class="">
-; AVX1-NEXT: cmovaeq %rcx, %rdi<br class="">
-; AVX1-NEXT: vsubsd %xmm1, %xmm0, %xmm2<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm2, %rcx<br class="">
-; AVX1-NEXT: xorq %rdx, %rcx<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm0, %rdx<br class="">
-; AVX1-NEXT: vucomisd %xmm1, %xmm0<br class="">
-; AVX1-NEXT: cmovaeq %rcx, %rdx<br class="">
-; AVX1-NEXT: vmovq %rdx, %xmm0<br class="">
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]<br class="">
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]<br class="">
-; AVX1-NEXT: vmovapd {{.*#+}} xmm2 = [4.503600e+15,1.934281e+25]<br class="">
-; AVX1-NEXT: vsubpd %xmm2, %xmm0, %xmm0<br class="">
-; AVX1-NEXT: vmovq %rdi, %xmm3<br class="">
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]<br class="">
-; AVX1-NEXT: vsubpd %xmm2, %xmm3, %xmm3<br class="">
-; AVX1-NEXT: vhaddpd %xmm3, %xmm0, %xmm0<br class="">
-; AVX1-NEXT: vmovq %rsi, %xmm3<br class="">
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]<br class="">
-; AVX1-NEXT: vsubpd %xmm2, %xmm3, %xmm3<br class="">
-; AVX1-NEXT: vmovq %rax, %xmm4<br class="">
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]<br class="">
-; AVX1-NEXT: vsubpd %xmm2, %xmm1, %xmm1<br class="">
-; AVX1-NEXT: vhaddpd %xmm1, %xmm3, %xmm1<br class="">
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br class="">
+; AVX1-NEXT: vroundpd $11, %ymm0, %ymm0<br class="">
; AVX1-NEXT: retq<br class="">
%i = fptoui <4 x double> %x to <4 x i64><br class="">
%r = uitofp <4 x i64> %i to <4 x double><br class="">
@@ -443,15 +240,12 @@ define float @trunc_signed_f32(float %x)<br class="">
;<br class="">
; SSE41-LABEL: trunc_signed_f32:<br class="">
; SSE41: # %bb.0:<br class="">
-; SSE41-NEXT: cvttss2si %xmm0, %eax<br class="">
-; SSE41-NEXT: xorps %xmm0, %xmm0<br class="">
-; SSE41-NEXT: cvtsi2ssl %eax, %xmm0<br class="">
+; SSE41-NEXT: roundss $11, %xmm0, %xmm0<br class="">
; SSE41-NEXT: retq<br class="">
;<br class="">
; AVX1-LABEL: trunc_signed_f32:<br class="">
; AVX1: # %bb.0:<br class="">
-; AVX1-NEXT: vcvttss2si %xmm0, %eax<br class="">
-; AVX1-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm0<br class="">
+; AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0<br class="">
; AVX1-NEXT: retq<br class="">
%i = fptosi float %x to i32<br class="">
%r = sitofp i32 %i to float<br class="">
@@ -468,15 +262,12 @@ define double @trunc_signed_f64(double %<br class="">
;<br class="">
; SSE41-LABEL: trunc_signed_f64:<br class="">
; SSE41: # %bb.0:<br class="">
-; SSE41-NEXT: cvttsd2si %xmm0, %rax<br class="">
-; SSE41-NEXT: xorps %xmm0, %xmm0<br class="">
-; SSE41-NEXT: cvtsi2sdq %rax, %xmm0<br class="">
+; SSE41-NEXT: roundsd $11, %xmm0, %xmm0<br class="">
; SSE41-NEXT: retq<br class="">
;<br class="">
; AVX1-LABEL: trunc_signed_f64:<br class="">
; AVX1: # %bb.0:<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm0, %rax<br class="">
-; AVX1-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm0<br class="">
+; AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0<br class="">
; AVX1-NEXT: retq<br class="">
%i = fptosi double %x to i64<br class="">
%r = sitofp i64 %i to double<br class="">
@@ -492,14 +283,12 @@ define <4 x float> @trunc_signed_v4f32(<<br class="">
;<br class="">
; SSE41-LABEL: trunc_signed_v4f32:<br class="">
; SSE41: # %bb.0:<br class="">
-; SSE41-NEXT: cvttps2dq %xmm0, %xmm0<br class="">
-; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0<br class="">
+; SSE41-NEXT: roundps $11, %xmm0, %xmm0<br class="">
; SSE41-NEXT: retq<br class="">
;<br class="">
; AVX1-LABEL: trunc_signed_v4f32:<br class="">
; AVX1: # %bb.0:<br class="">
-; AVX1-NEXT: vcvttps2dq %xmm0, %xmm0<br class="">
-; AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0<br class="">
+; AVX1-NEXT: vroundps $11, %xmm0, %xmm0<br class="">
; AVX1-NEXT: retq<br class="">
%i = fptosi <4 x float> %x to <4 x i32><br class="">
%r = sitofp <4 x i32> %i to <4 x float><br class="">
@@ -520,23 +309,12 @@ define <2 x double> @trunc_signed_v2f64(<br class="">
;<br class="">
; SSE41-LABEL: trunc_signed_v2f64:<br class="">
; SSE41: # %bb.0:<br class="">
-; SSE41-NEXT: cvttsd2si %xmm0, %rax<br class="">
-; SSE41-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]<br class="">
-; SSE41-NEXT: cvttsd2si %xmm0, %rcx<br class="">
-; SSE41-NEXT: xorps %xmm0, %xmm0<br class="">
-; SSE41-NEXT: cvtsi2sdq %rax, %xmm0<br class="">
-; SSE41-NEXT: cvtsi2sdq %rcx, %xmm1<br class="">
-; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br class="">
+; SSE41-NEXT: roundpd $11, %xmm0, %xmm0<br class="">
; SSE41-NEXT: retq<br class="">
;<br class="">
; AVX1-LABEL: trunc_signed_v2f64:<br class="">
; AVX1: # %bb.0:<br class="">
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm1, %rax<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm0, %rcx<br class="">
-; AVX1-NEXT: vcvtsi2sdq %rcx, %xmm2, %xmm0<br class="">
-; AVX1-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm1<br class="">
-; AVX1-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br class="">
+; AVX1-NEXT: vroundpd $11, %xmm0, %xmm0<br class="">
; AVX1-NEXT: retq<br class="">
%i = fptosi <2 x double> %x to <2 x i64><br class="">
%r = sitofp <2 x i64> %i to <2 x double><br class="">
@@ -565,39 +343,13 @@ define <4 x double> @trunc_signed_v4f64(<br class="">
;<br class="">
; SSE41-LABEL: trunc_signed_v4f64:<br class="">
; SSE41: # %bb.0:<br class="">
-; SSE41-NEXT: cvttsd2si %xmm1, %rax<br class="">
-; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]<br class="">
-; SSE41-NEXT: cvttsd2si %xmm1, %rcx<br class="">
-; SSE41-NEXT: cvttsd2si %xmm0, %rdx<br class="">
-; SSE41-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]<br class="">
-; SSE41-NEXT: cvttsd2si %xmm0, %rsi<br class="">
-; SSE41-NEXT: xorps %xmm0, %xmm0<br class="">
-; SSE41-NEXT: cvtsi2sdq %rdx, %xmm0<br class="">
-; SSE41-NEXT: xorps %xmm1, %xmm1<br class="">
-; SSE41-NEXT: cvtsi2sdq %rsi, %xmm1<br class="">
-; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br class="">
-; SSE41-NEXT: xorps %xmm1, %xmm1<br class="">
-; SSE41-NEXT: cvtsi2sdq %rax, %xmm1<br class="">
-; SSE41-NEXT: cvtsi2sdq %rcx, %xmm2<br class="">
-; SSE41-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]<br class="">
+; SSE41-NEXT: roundpd $11, %xmm0, %xmm0<br class="">
+; SSE41-NEXT: roundpd $11, %xmm1, %xmm1<br class="">
; SSE41-NEXT: retq<br class="">
;<br class="">
; AVX1-LABEL: trunc_signed_v4f64:<br class="">
; AVX1: # %bb.0:<br class="">
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm1, %rax<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm0, %rcx<br class="">
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0<br class="">
-; AVX1-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm1, %rdx<br class="">
-; AVX1-NEXT: vcvttsd2si %xmm0, %rsi<br class="">
-; AVX1-NEXT: vcvtsi2sdq %rsi, %xmm2, %xmm0<br class="">
-; AVX1-NEXT: vcvtsi2sdq %rdx, %xmm2, %xmm1<br class="">
-; AVX1-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br class="">
-; AVX1-NEXT: vcvtsi2sdq %rcx, %xmm2, %xmm1<br class="">
-; AVX1-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2<br class="">
-; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]<br class="">
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br class="">
+; AVX1-NEXT: vroundpd $11, %ymm0, %ymm0<br class="">
; AVX1-NEXT: retq<br class="">
%i = fptosi <4 x double> %x to <4 x i64><br class="">
%r = sitofp <4 x i64> %i to <4 x double><br class="">
<br class="">
<br class="">
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