<div dir="ltr">What do we want to do about LEAs having different scheduling data based on the number of components used in the address?</div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br><div class="gmail_quote">On Mon, Apr 23, 2018 at 2:04 PM, Simon Pilgrim via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rksimon<br>
Date: Mon Apr 23 14:04:23 2018<br>
New Revision: 330648<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=330648&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=330648&view=rev</a><br>
Log:<br>
[X86] Remove unnecessary WriteLEA InstRW overrides.<br>
<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/<wbr>X86SchedBroadwell.td<br>
llvm/trunk/lib/Target/X86/<wbr>X86SchedHaswell.td<br>
llvm/trunk/lib/Target/X86/<wbr>X86SchedSandyBridge.td<br>
llvm/trunk/lib/Target/X86/<wbr>X86SchedSkylakeClient.td<br>
llvm/trunk/lib/Target/X86/<wbr>X86SchedSkylakeServer.td<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86SchedBroadwell.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330648&r1=330647&r2=330648&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86SchedBroadwell.td?rev=<wbr>330648&r1=330647&r2=330648&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86SchedBroadwell.td (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86SchedBroadwell.td Mon Apr 23 14:04:23 2018<br>
@@ -401,8 +401,7 @@ def BWWriteResGroup7 : SchedWriteRes<[BW<br>
def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",<br>
"BLSI(32|64)rr",<br>
"BLSMSK(32|64)rr",<br>
- "BLSR(32|64)rr",<br>
- "LEA(16|32|64)(_32)?r")>;<br>
+ "BLSR(32|64)rr")>;<br>
<br>
def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {<br>
let Latency = 1;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86SchedHaswell.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330648&r1=330647&r2=330648&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86SchedHaswell.td?rev=<wbr>330648&r1=330647&r2=330648&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86SchedHaswell.td (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86SchedHaswell.td Mon Apr 23 14:04:23 2018<br>
@@ -745,8 +745,7 @@ def HWWriteResGroup8 : SchedWriteRes<[HW<br>
def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr",<br>
"BLSI(32|64)rr",<br>
"BLSMSK(32|64)rr",<br>
- "BLSR(32|64)rr",<br>
- "LEA(16|32|64)(_32)?r")>;<br>
+ "BLSR(32|64)rr")>;<br>
<br>
def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {<br>
let Latency = 1;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86SchedSandyBridge.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=330648&r1=330647&r2=330648&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86SchedSandyBridge.td?<wbr>rev=330648&r1=330647&r2=<wbr>330648&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86SchedSandyBridge.td (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86SchedSandyBridge.td Mon Apr 23 14:04:23 2018<br>
@@ -120,7 +120,7 @@ def : WriteRes<WriteSETCCStore, [SBPort<br>
// This is for simple LEAs with one or two input operands.<br>
// The complex ones can only execute on port 1, and they require two cycles on<br>
// the port to read all inputs. We don't model that.<br>
-def : WriteRes<WriteLEA, [SBPort15]>;<br>
+def : WriteRes<WriteLEA, [SBPort01]>;<br>
<br>
// Bit counts.<br>
defm : SBWriteResPair<WriteBitScan, [SBPort1], 3, [1], 1, 5>;<br>
@@ -341,13 +341,6 @@ def: InstRW<[SBWriteResGroup2], (instreg<br>
"(V?)MOV64toPQIrr",<br>
"(V?)MOVDI2PDIrr")>;<br>
<br>
-def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 1;<br>
- let ResourceCycles = [1];<br>
-}<br>
-def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)(_32)?r")>;<br>
-<br>
def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {<br>
let Latency = 1;<br>
let NumMicroOps = 1;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86SchedSkylakeClient.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330648&r1=330647&r2=330648&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86SchedSkylakeClient.td?<wbr>rev=330648&r1=330647&r2=<wbr>330648&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86SchedSkylakeClient.td (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86SchedSkylakeClient.td Mon Apr 23 14:04:23 2018<br>
@@ -485,8 +485,7 @@ def SKLWriteResGroup8 : SchedWriteRes<[S<br>
def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr",<br>
"BLSI(32|64)rr",<br>
"BLSMSK(32|64)rr",<br>
- "BLSR(32|64)rr",<br>
- "LEA(16|32|64)(_32)?r")>;<br>
+ "BLSR(32|64)rr")>;<br>
<br>
def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {<br>
let Latency = 1;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86SchedSkylakeServer.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330648&r1=330647&r2=330648&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86SchedSkylakeServer.td?<wbr>rev=330648&r1=330647&r2=<wbr>330648&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86SchedSkylakeServer.td (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86SchedSkylakeServer.td Mon Apr 23 14:04:23 2018<br>
@@ -790,8 +790,7 @@ def SKXWriteResGroup8 : SchedWriteRes<[S<br>
def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr",<br>
"BLSI(32|64)rr",<br>
"BLSMSK(32|64)rr",<br>
- "BLSR(32|64)rr",<br>
- "LEA(16|32|64)(_32)?r")>;<br>
+ "BLSR(32|64)rr")>;<br>
<br>
def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {<br>
let Latency = 1;<br>
<br>
<br>
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</blockquote></div><br></div>