<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Apr 21, 2018, at 12:55 AM, Francis Visoiu Mistrih <<a href="mailto:francisvm@yahoo.com" class="">francisvm@yahoo.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><meta http-equiv="Content-Type" content="text/html; charset=utf-8" class=""><div style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">Hi Vedant,<br class=""><div class=""><br class=""><blockquote type="cite" class=""><div class="">On 21 Apr 2018, at 01:32, Vedant Kumar <<a href="mailto:vsk@apple.com" class="">vsk@apple.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><meta http-equiv="Content-Type" content="text/html; charset=us-ascii" class=""><div style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">Hi Francis,<div class=""><br class=""></div><div class="">I'm debugging an issue in selection-dag which results in strange stepping behavior for swift code (<a href="rdar://33755881" class="">rdar://33755881</a>).</div><div class=""><br class=""></div><div class="">Before this patch, the output of -print-after-all would show this:</div><div class=""><br class=""></div><div class=""><div class=""><span class="Apple-tab-span" style="white-space:pre"> </span>MOV16mr %rbp, 1, %noreg, -112, %noreg, killed renamable %ax; mem:ST2[%92] dbg:stepping.swift:8:17</div><div class=""><span class="Apple-tab-span" style="white-space:pre"> </span>renamable %edx = MOVZX32rm16 %rbp, 1, %noreg, -112, %noreg; mem:LD2[%93](dereferenceable) dbg:stepping.swift:10:17</div><div class=""><br class=""></div><div class="">It's clear to see where the bug is based on this output, because we'd step from line 8 to line 10 and skip line 9.</div><div class=""><br class=""></div><div class="">After this patch, it's harder to identify the issue:</div><div class=""><br class=""></div><div class=""><div class=""> MOV16mr $rbp, 1, $noreg, -112, $noreg, killed renamable $ax, debug-location !56 :: (store 2 into %ir.._value12)</div><div class=""> renamable $edx = MOVZX32rm16 $rbp, 1, $noreg, -112, $noreg, debug-location !62 :: (dereferenceable load 2 from %ir.._value13)</div></div><div class=""><br class=""></div><div class="">The problem is that it's not immediately clear that locations 56 and 62 are on different lines.</div></div></div></div></blockquote><div class=""><br class=""></div><div class="">I agree, sorry about that.</div><br class=""><blockquote type="cite" class=""><div class=""><div style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div class=""><div class=""><br class=""></div><div class="">Would you be open to bringing the old kind of output back (possibly under a flag)?</div></div></div></div></blockquote><div class=""><br class=""></div><div class="">Sure. How about keeping both? Something like:</div><div class=""><br class=""></div><div class=""><div class="" style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;"><div class=""><div class=""><div class="">MOV16mr $rbp, 1, $noreg, -112, $noreg, killed renamable $ax, debug-location !56 :: (store 2 into %ir.._value12) ; stepping.swift:10:17</div><div class=""> renamable $edx = MOVZX32rm16 $rbp, 1, $noreg, -112, $noreg, debug-location !62 :: (dereferenceable load 2 from %ir.._value13) ; stepping.swift:10:17</div><div class=""><br class=""></div><div class="">The main goal here was to be able to copy-paste MI from -print-after-all to MIR files easily. Even though it’s not completely true today, it’s still pretty close.</div><div class=""><br class=""></div><div class="">I’ll put up a patch for that if it works for you.</div></div></div></div></div></div></div></div></blockquote><div><br class=""></div>That looks perfect, thanks a lot!</div><div><br class=""></div><div>vedant</div><div><br class=""><blockquote type="cite" class=""><div class=""><div style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div class=""><div class=""><div class="" style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;"><div class=""><div class=""><div class=""><br class=""></div><div class="">Thanks,</div><div class=""><br class=""></div><div class="">— </div><div class="">Francis</div></div></div></div></div><br class=""><blockquote type="cite" class=""><div class=""><div style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div class=""><div class=""><br class=""></div><div class="">vedant</div><div class=""><br class=""><blockquote type="cite" class=""><div class="">On Jan 19, 2018, at 3:44 AM, Francis Visoiu Mistrih via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="">Author: thegameg<br class="">Date: Fri Jan 19 03:44:42 2018<br class="">New Revision: 322936<br class=""><br class="">URL: <a href="http://llvm.org/viewvc/llvm-project?rev=322936&view=rev" class="">http://llvm.org/viewvc/llvm-project?rev=322936&view=rev</a><br class="">Log:<br class="">[CodeGen] Unify printing format of debug-location in both MIR and -debug<br class=""><br class="">Use "debug-location" instead of "; dbg:" in MI::print.<br class=""><br class="">Modified:<br class=""> llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br class=""> llvm/trunk/lib/CodeGen/MachineInstr.cpp<br class=""> llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=322936&r1=322935&r2=322936&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=322936&r1=322935&r2=322936&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Fri Jan 19 03:44:42 2018<br class="">@@ -686,11 +686,11 @@ void MIPrinter::print(const MachineInstr<br class=""> NeedComma = true;<br class=""> }<br class=""><br class="">- if (MI.getDebugLoc()) {<br class="">+ if (const DebugLoc &DL = MI.getDebugLoc()) {<br class=""> if (NeedComma)<br class=""> OS << ',';<br class=""> OS << " debug-location ";<br class="">- MI.getDebugLoc()->printAsOperand(OS, MST);<br class="">+ DL->printAsOperand(OS, MST);<br class=""> }<br class=""><br class=""> if (!MI.memoperands_empty()) {<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=322936&r1=322935&r2=322936&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=322936&r1=322935&r2=322936&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Fri Jan 19 03:44:42 2018<br class="">@@ -1425,6 +1425,15 @@ void MachineInstr::print(raw_ostream &OS<br class=""> }<br class=""> }<br class=""><br class="">+ if (!SkipDebugLoc) {<br class="">+ if (const DebugLoc &DL = getDebugLoc()) {<br class="">+ if (!FirstOp)<br class="">+ OS << ',';<br class="">+ OS << " debug-location ";<br class="">+ DL->printAsOperand(OS, MST);<br class="">+ }<br class="">+ }<br class="">+<br class=""> bool HaveSemi = false;<br class=""> if (!memoperands_empty()) {<br class=""> if (!HaveSemi) {<br class="">@@ -1441,6 +1450,9 @@ void MachineInstr::print(raw_ostream &OS<br class=""> }<br class=""> }<br class=""><br class="">+ if (SkipDebugLoc)<br class="">+ return;<br class="">+<br class=""> // Print debug location information.<br class=""> if (isDebugValue() && getOperand(e - 2).isMetadata()) {<br class=""> if (!HaveSemi)<br class="">@@ -1457,13 +1469,6 @@ void MachineInstr::print(raw_ostream &OS<br class=""> }<br class=""> if (isIndirectDebugValue())<br class=""> OS << " indirect";<br class="">- } else if (SkipDebugLoc) {<br class="">- return;<br class="">- } else if (debugLoc && MF) {<br class="">- if (!HaveSemi)<br class="">- OS << ";";<br class="">- OS << " dbg:";<br class="">- debugLoc.print(OS);<br class=""> }<br class=""><br class=""> OS << '\n';<br class=""><br class="">Modified: llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp?rev=322936&r1=322935&r2=322936&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp?rev=322936&r1=322935&r2=322936&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp (original)<br class="">+++ llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp Fri Jan 19 03:44:42 2018<br class="">@@ -14,6 +14,8 @@<br class=""> #include "llvm/CodeGen/TargetInstrInfo.h"<br class=""> #include "llvm/CodeGen/TargetLowering.h"<br class=""> #include "llvm/CodeGen/TargetSubtargetInfo.h"<br class="">+#include "llvm/IR/DebugInfoMetadata.h"<br class="">+#include "llvm/IR/ModuleSlotTracker.h"<br class=""> #include "llvm/Support/TargetRegistry.h"<br class=""> #include "llvm/Support/TargetSelect.h"<br class=""> #include "llvm/Target/TargetMachine.h"<br class="">@@ -244,4 +246,25 @@ TEST(MachineInstrExpressionTraitTest, Is<br class=""><br class=""> checkHashAndIsEqualMatch(VD2PU, VD2PD);<br class=""> }<br class="">+<br class="">+TEST(MachineInstrPrintingTest, DebugLocPrinting) {<br class="">+ auto MF = createMachineFunction();<br class="">+<br class="">+ MCOperandInfo OpInfo{0, 0, MCOI::OPERAND_REGISTER, 0};<br class="">+ MCInstrDesc MCID = {0, 1, 1, 0, 0, 0,<br class="">+ 0, nullptr, nullptr, &OpInfo, 0, nullptr};<br class="">+<br class="">+ LLVMContext Ctx;<br class="">+ DILocation *DIL = DILocation::get(Ctx, 1, 5, (Metadata *)nullptr, nullptr);<br class="">+ DebugLoc DL(DIL);<br class="">+ MachineInstr *MI = MF->CreateMachineInstr(MCID, DL);<br class="">+ MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true));<br class="">+<br class="">+ std::string str;<br class="">+ raw_string_ostream OS(str);<br class="">+ MI->print(OS);<br class="">+ ASSERT_TRUE(<br class="">+ StringRef(OS.str()).startswith("%noreg = UNKNOWN debug-location "));<br class="">+}<br class="">+<br class=""> } // end namespace<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class=""><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br class=""></div></div></blockquote></div><br class=""></div></div></div></blockquote></div><br class=""></div></div></blockquote></div><br class=""></body></html>