<div dir="ltr">
Hello Krzysztof,<br><br>> llvm/trunk/test/CodeGen/Hexagon/swp-vmult.ll<br><br>This test is flaky as it depends on a certain order of commands which could be different time to time. Either test or CodeGen shall be fixed.<br><br>C:\ps4-buildslave2\llvm-clang-x86_64-expensive-checks-win\llvm\test\CodeGen\Hexagon\swp-vmult.ll:5:15: error: CHECK-NEXT: is not on the line after the previous match<br>; CHECK-NEXT: [[REG1]] = memw(r{{[0-9]+}}++#4)<br> ^<br><stdin>:30:2: note: 'next' match was here<br> r3 = memw(r2++#4)<br> ^<br><stdin>:28:19: note: previous match ended here<br> r0 += mpyi(r4,r3)<br> ^<br><stdin>:29:1: note: non-matching line after previous match is here<br> r4 = memw(r1++#4)<br>^<br><br>Please also find attached the intermediate IR file I have got on the buildbot in case that would help with your debugging.<br>I have made this test unsupported in r329763 for now with till it gets fixed.<br><br>Hope this helps.<br><br>Thanks<br><br>Galina<br><div><span style="color:rgb(34,34,34);font-family:arial,sans-serif;font-size:small;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline"><br></span></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Mar 26, 2018 at 8:32 AM, Krzysztof Parzyszek via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: kparzysz<br>
Date: Mon Mar 26 08:32:03 2018<br>
New Revision: 328506<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=328506&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=328506&view=rev</a><br>
Log:<br>
[Hexagon] Give priority to post-incremementing memory accesses in LSR<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/<wbr>HexagonTargetTransformInfo.cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>HexagonTargetTransformInfo.h<br>
llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-epilog-numphis.ll<br>
llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-vmult.ll<br>
llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-vsum.ll<br>
llvm/trunk/test/CodeGen/<wbr>Hexagon/vect-downscale.ll<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/<wbr>HexagonTargetTransformInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp?rev=328506&r1=328505&r2=328506&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>Hexagon/<wbr>HexagonTargetTransformInfo.<wbr>cpp?rev=328506&r1=328505&r2=<wbr>328506&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>HexagonTargetTransformInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>HexagonTargetTransformInfo.cpp Mon Mar 26 08:32:03 2018<br>
@@ -43,6 +43,10 @@ void HexagonTTIImpl::<wbr>getUnrollingPrefere<br>
UP.Runtime = UP.Partial = true;<br>
}<br>
<br>
+bool HexagonTTIImpl::<wbr>shouldFavorPostInc() const {<br>
+ return true;<br>
+}<br>
+<br>
unsigned HexagonTTIImpl::<wbr>getNumberOfRegisters(bool vector) const {<br>
return vector ? 0 : 32;<br>
}<br>
@@ -81,5 +85,5 @@ int HexagonTTIImpl::getUserCost(<wbr>const Us<br>
}<br>
<br>
bool HexagonTTIImpl::<wbr>shouldBuildLookupTables() const {<br>
- return EmitLookupTables;<br>
+ return EmitLookupTables;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/<wbr>HexagonTargetTransformInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.h?rev=328506&r1=328505&r2=328506&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>Hexagon/<wbr>HexagonTargetTransformInfo.h?<wbr>rev=328506&r1=328505&r2=<wbr>328506&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>HexagonTargetTransformInfo.h (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>HexagonTargetTransformInfo.h Mon Mar 26 08:32:03 2018<br>
@@ -57,6 +57,9 @@ public:<br>
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,<br>
TTI::UnrollingPreferences &UP);<br>
<br>
+ /// Bias LSR towards creating post-increment opportunities.<br>
+ bool shouldFavorPostInc() const;<br>
+<br>
// L1 cache prefetch.<br>
unsigned getPrefetchDistance() const;<br>
unsigned getCacheLineSize() const;<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-epilog-numphis.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-epilog-numphis.ll?rev=328506&r1=328505&r2=328506&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Hexagon/swp-epilog-<wbr>numphis.ll?rev=328506&r1=<wbr>328505&r2=328506&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-epilog-numphis.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-epilog-numphis.ll Mon Mar 26 08:32:03 2018<br>
@@ -1,3 +1,5 @@<br>
+; XFAIL: *<br>
+; Needs some fixed in the pipeliner.<br>
; RUN: llc -march=hexagon < %s | FileCheck %s<br>
<br>
; CHECK: endloop0<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-vmult.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-vmult.ll?rev=328506&r1=328505&r2=328506&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Hexagon/swp-vmult.ll?<wbr>rev=328506&r1=328505&r2=<wbr>328506&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-vmult.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-vmult.ll Mon Mar 26 08:32:03 2018<br>
@@ -1,33 +1,30 @@<br>
; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s | FileCheck %s<br>
-; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s<br>
<br>
; Multiply and accumulate<br>
; CHECK: mpyi([[REG0:r([0-9]+)]],[[<wbr>REG1:r([0-9]+)]])<br>
-; CHECK-NEXT: add(r{{[0-9]+}},#4)<br>
-; CHECK-DAG: [[REG1]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<<wbr>#0)<br>
-; CHECK-DAG: [[REG0]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<<wbr>#0)<br>
+; CHECK-NEXT: [[REG1]] = memw(r{{[0-9]+}}++#4)<br>
+; CHECK-NEXT: [[REG0]] = memw(r{{[0-9]+}}++#4)<br>
; CHECK-NEXT: endloop0<br>
<br>
-define i32 @foo(i32* %a, i32* %b, i32 %n) {<br>
-entry:<br>
- br label %for.body<br>
+define i32 @f0(i32* %a0, i32* %a1, i32 %a2) {<br>
+b0:<br>
+ br label %b1<br>
<br>
-for.body:<br>
- %sum.03 = phi i32 [ 0, %entry ], [ %add, %for.body ]<br>
- %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]<br>
- %arrayidx1.phi = phi i32* [ %b, %entry ], [ %arrayidx1.inc, %for.body ]<br>
- %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]<br>
- %0 = load i32, i32* %arrayidx.phi, align 4<br>
- %1 = load i32, i32* %arrayidx1.phi, align 4<br>
- %mul = mul nsw i32 %1, %0<br>
- %add = add nsw i32 %mul, %sum.03<br>
- %inc = add nsw i32 %i.02, 1<br>
- %exitcond = icmp eq i32 %inc, 10000<br>
- %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1<br>
- %arrayidx1.inc = getelementptr i32, i32* %arrayidx1.phi, i32 1<br>
- br i1 %exitcond, label %for.end, label %for.body<br>
+b1: ; preds = %b1, %b0<br>
+ %v0 = phi i32 [ 0, %b0 ], [ %v7, %b1 ]<br>
+ %v1 = phi i32* [ %a0, %b0 ], [ %v10, %b1 ]<br>
+ %v2 = phi i32* [ %a1, %b0 ], [ %v11, %b1 ]<br>
+ %v3 = phi i32 [ 0, %b0 ], [ %v8, %b1 ]<br>
+ %v4 = load i32, i32* %v1, align 4<br>
+ %v5 = load i32, i32* %v2, align 4<br>
+ %v6 = mul nsw i32 %v5, %v4<br>
+ %v7 = add nsw i32 %v6, %v0<br>
+ %v8 = add nsw i32 %v3, 1<br>
+ %v9 = icmp eq i32 %v8, 10000<br>
+ %v10 = getelementptr i32, i32* %v1, i32 1<br>
+ %v11 = getelementptr i32, i32* %v2, i32 1<br>
+ br i1 %v9, label %b2, label %b1<br>
<br>
-for.end:<br>
- ret i32 %add<br>
+b2: ; preds = %b1<br>
+ ret i32 %v7<br>
}<br>
-<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-vsum.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-vsum.ll?rev=328506&r1=328505&r2=328506&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Hexagon/swp-vsum.ll?<wbr>rev=328506&r1=328505&r2=<wbr>328506&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-vsum.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-vsum.ll Mon Mar 26 08:32:03 2018<br>
@@ -1,29 +1,32 @@<br>
; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s | FileCheck %s<br>
-; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s<br>
+; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-pipeliner < %s | FileCheck %s --check-prefix=CHECKV60<br>
<br>
; Simple vector total.<br>
; CHECK: loop0(.LBB0_[[LOOP:.]],<br>
; CHECK: .LBB0_[[LOOP]]:<br>
-; CHECK: add([[REG:r([0-9]+)]],r{{[0-9]<wbr>+}})<br>
-; CHECK-NEXT: add(r{{[0-9]+}},#4)<br>
-; CHECK-NEXT: [[REG]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<<wbr>#0)<br>
+; CHECK: add(r{{[0-9]+}},r{{[0-9]+}})<br>
+; CHECK-NEXT: memw(r{{[0-9]+}}++#4)<br>
; CHECK-NEXT: endloop0<br>
<br>
-define i32 @foo(i32* %a, i32 %n) {<br>
-entry:<br>
- br label %for.body<br>
+; V60 does not pipeline due to latencies.<br>
+; CHECKV60: memw(r{{[0-9]+}}++#4)<br>
+; CHECKV60: add(r{{[0-9]+}},r{{[0-9]+}})<br>
<br>
-for.body:<br>
- %sum.02 = phi i32 [ 0, %entry ], [ %add, %for.body ]<br>
- %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]<br>
- %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]<br>
- %0 = load i32, i32* %arrayidx.phi, align 4<br>
- %add = add nsw i32 %0, %sum.02<br>
- %inc = add nsw i32 %i.01, 1<br>
- %exitcond = icmp eq i32 %inc, 10000<br>
- %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1<br>
- br i1 %exitcond, label %for.end, label %for.body<br>
+define i32 @f0(i32* %a0, i32 %a1) {<br>
+b0:<br>
+ br label %b1<br>
<br>
-for.end:<br>
- ret i32 %add<br>
+b1: ; preds = %b1, %b0<br>
+ %v0 = phi i32 [ 0, %b0 ], [ %v4, %b1 ]<br>
+ %v1 = phi i32* [ %a0, %b0 ], [ %v7, %b1 ]<br>
+ %v2 = phi i32 [ 0, %b0 ], [ %v5, %b1 ]<br>
+ %v3 = load i32, i32* %v1, align 4<br>
+ %v4 = add nsw i32 %v3, %v0<br>
+ %v5 = add nsw i32 %v2, 1<br>
+ %v6 = icmp eq i32 %v5, 10000<br>
+ %v7 = getelementptr i32, i32* %v1, i32 1<br>
+ br i1 %v6, label %b2, label %b1<br>
+<br>
+b2: ; preds = %b1<br>
+ ret i32 %v4<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>Hexagon/vect-downscale.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vect-downscale.ll?rev=328506&r1=328505&r2=328506&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Hexagon/vect-<wbr>downscale.ll?rev=328506&r1=<wbr>328505&r2=328506&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>Hexagon/vect-downscale.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>Hexagon/vect-downscale.ll Mon Mar 26 08:32:03 2018<br>
@@ -12,6 +12,8 @@<br>
; CHECK: {<br>
; CHECK: }<br>
; CHECK: {<br>
+; CHECK: }<br>
+; CHECK: {<br>
; CHECK-NOT: }<br>
; CHECK: }{{[ \t]*}}:endloop0<br>
<br>
<br>
<br>
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</blockquote></div><br></div></div>