<div dir="ltr">Ok the other issue should be fixed by r<span style="color:rgb(34,34,34);font-family:arial,sans-serif;font-size:12.8px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline">329771</span>
</div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br><div class="gmail_quote">On Tue, Apr 10, 2018 at 12:33 PM, Craig Topper <span dir="ltr"><<a href="mailto:craig.topper@gmail.com" target="_blank">craig.topper@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Vlad, how do I make use of that test case? It just looks like a copy of the machine IR but I dont' think its a valid MIR test file.</div><div class="gmail_extra"><span class="HOEnZb"><font color="#888888"><br clear="all"><div><div class="m_-7864328274113987586gmail_signature" data-smartmail="gmail_signature">~Craig</div></div></font></span><div><div class="h5">
<br><div class="gmail_quote">On Tue, Apr 10, 2018 at 11:49 AM, Craig Topper <span dir="ltr"><<a href="mailto:craig.topper@gmail.com" target="_blank">craig.topper@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">The failure for the stack dump in <a href="https://crbug.com/831158" target="_blank">https://crbug.com/831158</a> has been fixed r329734 and a clang test for ms inline assembly was added in r329738.</div><div class="gmail_extra"><span class="m_-7864328274113987586HOEnZb"><font color="#888888"><br clear="all"><div><div class="m_-7864328274113987586m_-3090959762194490745gmail_signature" data-smartmail="gmail_signature">~Craig</div></div></font></span><div><div class="m_-7864328274113987586h5">
<br><div class="gmail_quote">On Tue, Apr 10, 2018 at 11:42 AM, Vlad Tsyrklevich <span dir="ltr"><<a href="mailto:vlad@tsyrklevich.net" target="_blank">vlad@tsyrklevich.net</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hmm, actually after looking at Nico's crbug I've realized the failure and MIR I've provided looks like a different failure in the same pass, e.g. <a href="https://logs.chromium.org/v/?s=chromium%2Fbb%2Fchromium.clang%2FCFI_Linux__icall_%2F9494%2F%2B%2Frecipes%2Fsteps%2Fcompile%2F0%2Fstdout" target="_blank">this</a> on a CFI ToT bot.</div><div class="m_-7864328274113987586m_-3090959762194490745HOEnZb"><div class="m_-7864328274113987586m_-3090959762194490745h5"><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Apr 10, 2018 at 11:37 AM, Vlad Tsyrklevich <span dir="ltr"><<a href="mailto:vlad@tsyrklevich.net" target="_blank">vlad@tsyrklevich.net</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">In case a test case is still useful, it's failing in rewriteSetCC() on<br>
the call to getReg() because operand 0 is not a register for the<br>
instruction:<br>
SETEm %stack.9, 1, $noreg, 0, $noreg, implicit $eflags,<br>
debug-location !113 :: (store 1 into %ir.16)<br>
<br>
The original unminimized IR for the failing function is attached.<br>
<div class="m_-7864328274113987586m_-3090959762194490745m_73922515974701117HOEnZb"><div class="m_-7864328274113987586m_-3090959762194490745m_73922515974701117h5"><br>
On Tue, Apr 10, 2018 at 10:37 AM, Craig Topper via llvm-commits<br>
<<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br>
> Working on this.<br>
><br>
> ~Craig<br>
><br>
> On Tue, Apr 10, 2018 at 9:55 AM, Chandler Carruth <<a href="mailto:chandlerc@gmail.com" target="_blank">chandlerc@gmail.com</a>><br>
> wrote:<br>
>><br>
>> Ah, yeah. That'll be the fix.<br>
>><br>
>> We should get a test case.<br>
>><br>
>> I'm stuck in meetings non-stop until about 5pm PST today, so someone else<br>
>> may want to try and fix and/or revert until then if its blocking folks.<br>
>><br>
>> On Tue, Apr 10, 2018 at 8:36 AM Craig Topper <<a href="mailto:craig.topper@gmail.com" target="_blank">craig.topper@gmail.com</a>><br>
>> wrote:<br>
>>><br>
>>> May we need to change the string here to be "dirflag"?<br>
>>><br>
>>> def DF : X86Reg<"DF", 0>;<br>
>>><br>
>>> ~Craig<br>
>>><br>
>>> On Tue, Apr 10, 2018 at 8:22 AM, Hans Wennborg via llvm-commits<br>
>>> <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br>
>>>><br>
>>>> We're hitting an assert in Chromium due to this, see<br>
>>>> <a href="https://crbug.com/831158" rel="noreferrer" target="_blank">https://crbug.com/831158</a><br>
>>>><br>
>>>> I've started looking but have to head out now, so maybe you or Nico<br>
>>>> will get to it before I do.<br>
>>>><br>
>>>> On Tue, Apr 10, 2018 at 8:40 AM, Chandler Carruth via llvm-commits<br>
>>>> <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br>
>>>> > Author: chandlerc<br>
>>>> > Date: Mon Apr 9 23:40:51 2018<br>
>>>> > New Revision: 329673<br>
>>>> ><br>
>>>> > URL: <a href="http://llvm.org/viewvc/llvm-project?rev=329673&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=329673&view=rev</a><br>
>>>> > Log:<br>
>>>> > [x86] Model the direction flag (DF) separately from the rest of<br>
>>>> > EFLAGS.<br>
>>>> ><br>
>>>> > This cleans up a number of operations that only claimed te use EFLAGS<br>
>>>> > due to using DF. But no instructions which we think of us setting<br>
>>>> > EFLAGS<br>
>>>> > actually modify DF (other than things like popf) and so this<br>
>>>> > needlessly<br>
>>>> > creates uses of EFLAGS that aren't really there.<br>
>>>> ><br>
>>>> > In fact, DF is so restrictive it is pretty easy to model. Only STD,<br>
>>>> > CLD,<br>
>>>> > and the whole-flags writes (WRFLAGS and POPF) need to model this.<br>
>>>> ><br>
>>>> > I've also somewhat cleaned up some of the flag management instruction<br>
>>>> > definitions to be in the correct .td file.<br>
>>>> ><br>
>>>> > Adding this extra register also uncovered a failure to use the correct<br>
>>>> > datatype to hold X86 registers, and I've corrected that as necessary<br>
>>>> > here.<br>
>>>> ><br>
>>>> > Differential Revision: <a href="https://reviews.llvm.org/D45154" rel="noreferrer" target="_blank">https://reviews.llvm.org/D4515<wbr>4</a><br>
>>>> ><br>
>>>> > Modified:<br>
>>>> > llvm/trunk/lib/Target/X86/Dis<wbr>assembler/X86Disassembler.cpp<br>
>>>> > llvm/trunk/lib/Target/X86/X86<wbr>ISelLowering.cpp<br>
>>>> > llvm/trunk/lib/Target/X86/X86<wbr>InstrCompiler.td<br>
>>>> > llvm/trunk/lib/Target/X86/X86<wbr>InstrInfo.cpp<br>
>>>> > llvm/trunk/lib/Target/X86/X86<wbr>InstrInfo.td<br>
>>>> > llvm/trunk/lib/Target/X86/X86<wbr>InstrSystem.td<br>
>>>> > llvm/trunk/lib/Target/X86/X86<wbr>RegisterInfo.td<br>
>>>> > llvm/trunk/test/CodeGen/X86/i<wbr>pra-reg-usage.ll<br>
>>>> ><br>
>>>> > Modified: llvm/trunk/lib/Target/X86/Disa<wbr>ssembler/X86Disassembler.cpp<br>
>>>> > URL:<br>
>>>> > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=329673&r1=329672&r2=329673&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/Disassembler/X86Disassembler<wbr>.cpp?rev=329673&r1=329672&r2=3<wbr>29673&view=diff</a><br>
>>>> ><br>
>>>> > ==============================<wbr>==============================<wbr>==================<br>
>>>> > --- llvm/trunk/lib/Target/X86/Disa<wbr>ssembler/X86Disassembler.cpp<br>
>>>> > (original)<br>
>>>> > +++ llvm/trunk/lib/Target/X86/Disa<wbr>ssembler/X86Disassembler.cpp Mon Apr<br>
>>>> > 9 23:40:51 2018<br>
>>>> > @@ -265,13 +265,10 @@ MCDisassembler::DecodeStatus X86GenericD<br>
>>>> > /// @param reg - The Reg to append.<br>
>>>> > static void translateRegister(MCInst &mcInst, Reg reg) {<br>
>>>> > #define ENTRY(x) X86::x,<br>
>>>> > - uint8_t llvmRegnums[] = {<br>
>>>> > - ALL_REGS<br>
>>>> > - 0<br>
>>>> > - };<br>
>>>> > + static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};<br>
>>>> > #undef ENTRY<br>
>>>> ><br>
>>>> > - uint8_t llvmRegnum = llvmRegnums[reg];<br>
>>>> > + MCPhysReg llvmRegnum = llvmRegnums[reg];<br>
>>>> > mcInst.addOperand(MCOperand::c<wbr>reateReg(llvmRegnum));<br>
>>>> > }<br>
>>>> ><br>
>>>> ><br>
>>>> > Modified: llvm/trunk/lib/Target/X86/X86I<wbr>SelLowering.cpp<br>
>>>> > URL:<br>
>>>> > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=329673&r1=329672&r2=329673&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86ISelLowering.cpp?rev=3296<wbr>73&r1=329672&r2=329673&view=di<wbr>ff</a><br>
>>>> ><br>
>>>> > ==============================<wbr>==============================<wbr>==================<br>
>>>> > --- llvm/trunk/lib/Target/X86/X86I<wbr>SelLowering.cpp (original)<br>
>>>> > +++ llvm/trunk/lib/Target/X86/X86I<wbr>SelLowering.cpp Mon Apr 9 23:40:51<br>
>>>> > 2018<br>
>>>> > @@ -28066,11 +28066,16 @@ X86TargetLowering::EmitInstrWi<wbr>thCustomIn<br>
>>>> > MI.getOpcode() == X86::RDFLAGS32 ? X86::PUSHF32 :<br>
>>>> > X86::PUSHF64;<br>
>>>> > unsigned Pop = MI.getOpcode() == X86::RDFLAGS32 ? X86::POP32r :<br>
>>>> > X86::POP64r;<br>
>>>> > MachineInstr *Push = BuildMI(*BB, MI, DL, TII->get(PushF));<br>
>>>> > - // Permit reads of the FLAGS register without it being defined.<br>
>>>> > + // Permit reads of the EFLAGS and DF registers without them being<br>
>>>> > defined.<br>
>>>> > // This intrinsic exists to read external processor state in<br>
>>>> > flags, such as<br>
>>>> > // the trap flag, interrupt flag, and direction flag, none of<br>
>>>> > which are<br>
>>>> > // modeled by the backend.<br>
>>>> > + assert(Push->getOperand(2).get<wbr>Reg() == X86::EFLAGS &&<br>
>>>> > + "Unexpected register in operand!");<br>
>>>> > Push->getOperand(2).setIsUndef<wbr>();<br>
>>>> > + assert(Push->getOperand(3).get<wbr>Reg() == X86::DF &&<br>
>>>> > + "Unexpected register in operand!");<br>
>>>> > + Push->getOperand(3).setIsUndef<wbr>();<br>
>>>> > BuildMI(*BB, MI, DL, TII->get(Pop), MI.getOperand(0).getReg());<br>
>>>> ><br>
>>>> > MI.eraseFromParent(); // The pseudo is gone now.<br>
>>>> ><br>
>>>> > Modified: llvm/trunk/lib/Target/X86/X86I<wbr>nstrCompiler.td<br>
>>>> > URL:<br>
>>>> > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=329673&r1=329672&r2=329673&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86InstrCompiler.td?rev=3296<wbr>73&r1=329672&r2=329673&view=di<wbr>ff</a><br>
>>>> ><br>
>>>> > ==============================<wbr>==============================<wbr>==================<br>
>>>> > --- llvm/trunk/lib/Target/X86/X86I<wbr>nstrCompiler.td (original)<br>
>>>> > +++ llvm/trunk/lib/Target/X86/X86I<wbr>nstrCompiler.td Mon Apr 9 23:40:51<br>
>>>> > 2018<br>
>>>> > @@ -473,7 +473,7 @@ let Defs = [EAX, ECX, EDX, FP0, FP1, FP2<br>
>>>> > ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,<br>
>>>> > MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,<br>
>>>> > XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,<br>
>>>> > - XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15,<br>
>>>> > EFLAGS],<br>
>>>> > + XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15,<br>
>>>> > EFLAGS, DF],<br>
>>>> > usesCustomInserter = 1, Uses = [ESP, SSP] in {<br>
>>>> > def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),<br>
>>>> > "# TLS_addr32",<br>
>>>> > @@ -493,7 +493,7 @@ let Defs = [RAX, RCX, RDX, RSI, RDI, R8,<br>
>>>> > ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,<br>
>>>> > MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,<br>
>>>> > XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,<br>
>>>> > - XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15,<br>
>>>> > EFLAGS],<br>
>>>> > + XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15,<br>
>>>> > EFLAGS, DF],<br>
>>>> > usesCustomInserter = 1, Uses = [RSP, SSP] in {<br>
>>>> > def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),<br>
>>>> > "# TLS_addr64",<br>
>>>> > @@ -509,7 +509,7 @@ def TLS_base_addr64 : I<0, Pseudo, (outs<br>
>>>> > // For i386, the address of the thunk is passed on the stack, on<br>
>>>> > return the<br>
>>>> > // address of the variable is in %eax. %ecx is trashed during the<br>
>>>> > function<br>
>>>> > // call. All other registers are preserved.<br>
>>>> > -let Defs = [EAX, ECX, EFLAGS],<br>
>>>> > +let Defs = [EAX, ECX, EFLAGS, DF],<br>
>>>> > Uses = [ESP, SSP],<br>
>>>> > usesCustomInserter = 1 in<br>
>>>> > def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),<br>
>>>> > @@ -522,7 +522,7 @@ def TLSCall_32 : I<0, Pseudo, (outs), (i<br>
>>>> > // %rdi. The lowering will do the right thing with RDI.<br>
>>>> > // On return the address of the variable is in %rax. All other<br>
>>>> > // registers are preserved.<br>
>>>> > -let Defs = [RAX, EFLAGS],<br>
>>>> > +let Defs = [RAX, EFLAGS, DF],<br>
>>>> > Uses = [RSP, SSP],<br>
>>>> > usesCustomInserter = 1 in<br>
>>>> > def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),<br>
>>>> ><br>
>>>> > Modified: llvm/trunk/lib/Target/X86/X86I<wbr>nstrInfo.cpp<br>
>>>> > URL:<br>
>>>> > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=329673&r1=329672&r2=329673&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86InstrInfo.cpp?rev=329673&<wbr>r1=329672&r2=329673&view=diff</a><br>
>>>> ><br>
>>>> > ==============================<wbr>==============================<wbr>==================<br>
>>>> > --- llvm/trunk/lib/Target/X86/X86I<wbr>nstrInfo.cpp (original)<br>
>>>> > +++ llvm/trunk/lib/Target/X86/X86I<wbr>nstrInfo.cpp Mon Apr 9 23:40:51<br>
>>>> > 2018<br>
>>>> > @@ -9481,8 +9481,9 @@ bool X86InstrInfo::<br>
>>>> > isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {<br>
>>>> > // FIXME: Return false for x87 stack register classes for now. We<br>
>>>> > can't<br>
>>>> > // allow any loads of these registers before FpGet_ST0_80.<br>
>>>> > - return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||<br>
>>>> > - RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);<br>
>>>> > + return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||<br>
>>>> > + RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||<br>
>>>> > + RC == &X86::RFP80RegClass);<br>
>>>> > }<br>
>>>> ><br>
>>>> > /// Return a virtual register initialized with the<br>
>>>> ><br>
>>>> > Modified: llvm/trunk/lib/Target/X86/X86I<wbr>nstrInfo.td<br>
>>>> > URL:<br>
>>>> > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=329673&r1=329672&r2=329673&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86InstrInfo.td?rev=329673&r<wbr>1=329672&r2=329673&view=diff</a><br>
>>>> ><br>
>>>> > ==============================<wbr>==============================<wbr>==================<br>
>>>> > --- llvm/trunk/lib/Target/X86/X86I<wbr>nstrInfo.td (original)<br>
>>>> > +++ llvm/trunk/lib/Target/X86/X86I<wbr>nstrInfo.td Mon Apr 9 23:40:51 2018<br>
>>>> > @@ -1235,18 +1235,18 @@ let mayLoad = 1, mayStore = 1, usesCusto<br>
>>>> ><br>
>>>> > let mayLoad = 1, mayStore = 1, usesCustomInserter = 1,<br>
>>>> > SchedRW = [WriteRMW] in {<br>
>>>> > - let Defs = [ESP, EFLAGS], Uses = [ESP] in<br>
>>>> > + let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in<br>
>>>> > def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src),<br>
>>>> > [(int_x86_flags_write_u32 GR32:$src)]>,<br>
>>>> > Requires<[Not64BitMode]>;<br>
>>>> ><br>
>>>> > - let Defs = [RSP, EFLAGS], Uses = [RSP] in<br>
>>>> > + let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in<br>
>>>> > def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src),<br>
>>>> > [(int_x86_flags_write_u64 GR64:$src)]>,<br>
>>>> > Requires<[In64BitMode]>;<br>
>>>> > }<br>
>>>> ><br>
>>>> > -let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1,<br>
>>>> > hasSideEffects=0,<br>
>>>> > +let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1,<br>
>>>> > hasSideEffects=0,<br>
>>>> > SchedRW = [WriteLoad] in {<br>
>>>> > def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [],<br>
>>>> > IIC_POP_F>,<br>
>>>> > OpSize16;<br>
>>>> > @@ -1254,7 +1254,7 @@ def POPF32 : I<0x9D, RawFrm, (outs), (<br>
>>>> > OpSize32, Requires<[Not64BitMode]>;<br>
>>>> > }<br>
>>>> ><br>
>>>> > -let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1,<br>
>>>> > hasSideEffects=0,<br>
>>>> > +let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1,<br>
>>>> > hasSideEffects=0,<br>
>>>> > SchedRW = [WriteStore] in {<br>
>>>> > def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [],<br>
>>>> > IIC_PUSH_F>,<br>
>>>> > OpSize16;<br>
>>>> > @@ -1294,10 +1294,10 @@ def PUSH64i32 : Ii32S<0x68, RawFrm, (ou<br>
>>>> > Requires<[In64BitMode]>;<br>
>>>> > }<br>
>>>> ><br>
>>>> > -let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0<br>
>>>> > in<br>
>>>> > +let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1,<br>
>>>> > hasSideEffects=0 in<br>
>>>> > def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [],<br>
>>>> > IIC_POP_FD>,<br>
>>>> > OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;<br>
>>>> > -let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1,<br>
>>>> > hasSideEffects=0 in<br>
>>>> > +let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1,<br>
>>>> > hasSideEffects=0 in<br>
>>>> > def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [],<br>
>>>> > IIC_PUSH_F>,<br>
>>>> > OpSize32, Requires<[In64BitMode]>,<br>
>>>> > Sched<[WriteStore]>;<br>
>>>> ><br>
>>>> > @@ -1382,8 +1382,7 @@ def BSR64rm : RI<0xBD, MRMSrcMem, (outs<br>
>>>> > } // Defs = [EFLAGS]<br>
>>>> ><br>
>>>> > let SchedRW = [WriteMicrocoded] in {<br>
>>>> > -// These uses the DF flag in the EFLAGS register to inc or dec EDI<br>
>>>> > and ESI<br>
>>>> > -let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {<br>
>>>> > +let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in {<br>
>>>> > def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst,<br>
>>>> > srcidx8:$src),<br>
>>>> > "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;<br>
>>>> > def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst,<br>
>>>> > srcidx16:$src),<br>
>>>> > @@ -1395,38 +1394,35 @@ def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs<br>
>>>> > Requires<[In64BitMode]>;<br>
>>>> > }<br>
>>>> ><br>
>>>> > -// These uses the DF flag in the EFLAGS register to inc or dec EDI<br>
>>>> > and ESI<br>
>>>> > -let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in<br>
>>>> > +let Defs = [EDI], Uses = [AL,EDI,DF] in<br>
>>>> > def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst),<br>
>>>> > "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;<br>
>>>> > -let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in<br>
>>>> > +let Defs = [EDI], Uses = [AX,EDI,DF] in<br>
>>>> > def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst),<br>
>>>> > "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;<br>
>>>> > -let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in<br>
>>>> > +let Defs = [EDI], Uses = [EAX,EDI,DF] in<br>
>>>> > def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst),<br>
>>>> > "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>,<br>
>>>> > OpSize32;<br>
>>>> > -let Defs = [RDI], Uses = [RAX,RDI,EFLAGS] in<br>
>>>> > +let Defs = [RDI], Uses = [RAX,RDI,DF] in<br>
>>>> > def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst),<br>
>>>> > "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>,<br>
>>>> > Requires<[In64BitMode]>;<br>
>>>> ><br>
>>>> > -// These uses the DF flag in the EFLAGS register to inc or dec EDI<br>
>>>> > and ESI<br>
>>>> > -let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in<br>
>>>> > +let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in<br>
>>>> > def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),<br>
>>>> > "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;<br>
>>>> > -let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in<br>
>>>> > +let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in<br>
>>>> > def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),<br>
>>>> > "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;<br>
>>>> > -let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in<br>
>>>> > +let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in<br>
>>>> > def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),<br>
>>>> > "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>,<br>
>>>> > OpSize32;<br>
>>>> > -let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in<br>
>>>> > +let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in<br>
>>>> > def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),<br>
>>>> > "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>,<br>
>>>> > Requires<[In64BitMode]>;<br>
>>>> ><br>
>>>> > -// These uses the DF flag in the EFLAGS register to inc or dec EDI<br>
>>>> > and ESI<br>
>>>> > -let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {<br>
>>>> > +let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in {<br>
>>>> > def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst,<br>
>>>> > srcidx8:$src),<br>
>>>> > "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;<br>
>>>> > def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst,<br>
>>>> > srcidx16:$src),<br>
>>>> > @@ -2069,8 +2065,7 @@ def DATA32_PREFIX : I<0x66, RawFrm, (out<br>
>>>> > } // SchedRW<br>
>>>> ><br>
>>>> > // Repeat string operation instruction prefixes<br>
>>>> > -// These use the DF flag in the EFLAGS register to inc or dec ECX<br>
>>>> > -let Defs = [ECX], Uses = [ECX,EFLAGS], SchedRW = [WriteMicrocoded] in<br>
>>>> > {<br>
>>>> > +let Defs = [ECX], Uses = [ECX,DF], SchedRW = [WriteMicrocoded] in {<br>
>>>> > // Repeat (used with INS, OUTS, MOVS, LODS and STOS)<br>
>>>> > def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;<br>
>>>> > // Repeat while not equal (used with CMPS and SCAS)<br>
>>>> > @@ -2079,25 +2074,23 @@ def REPNE_PREFIX : I<0xF2, RawFrm, (outs<br>
>>>> ><br>
>>>> > // String manipulation instructions<br>
>>>> > let SchedRW = [WriteMicrocoded] in {<br>
>>>> > -// These uses the DF flag in the EFLAGS register to inc or dec EDI<br>
>>>> > and ESI<br>
>>>> > -let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in<br>
>>>> > +let Defs = [AL,ESI], Uses = [ESI,DF] in<br>
>>>> > def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),<br>
>>>> > "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;<br>
>>>> > -let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in<br>
>>>> > +let Defs = [AX,ESI], Uses = [ESI,DF] in<br>
>>>> > def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),<br>
>>>> > "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;<br>
>>>> > -let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in<br>
>>>> > +let Defs = [EAX,ESI], Uses = [ESI,DF] in<br>
>>>> > def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),<br>
>>>> > "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>,<br>
>>>> > OpSize32;<br>
>>>> > -let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in<br>
>>>> > +let Defs = [RAX,ESI], Uses = [ESI,DF] in<br>
>>>> > def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),<br>
>>>> > "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>,<br>
>>>> > Requires<[In64BitMode]>;<br>
>>>> > }<br>
>>>> ><br>
>>>> > let SchedRW = [WriteSystem] in {<br>
>>>> > -// These uses the DF flag in the EFLAGS register to inc or dec EDI<br>
>>>> > and ESI<br>
>>>> > -let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {<br>
>>>> > +let Defs = [ESI], Uses = [DX,ESI,DF] in {<br>
>>>> > def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),<br>
>>>> > "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;<br>
>>>> > def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),<br>
>>>> > @@ -2106,8 +2099,7 @@ def OUTSL : I<0x6F, RawFrmSrc, (outs), (<br>
>>>> > "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>,<br>
>>>> > OpSize32;<br>
>>>> > }<br>
>>>> ><br>
>>>> > -// These uses the DF flag in the EFLAGS register to inc or dec EDI<br>
>>>> > and ESI<br>
>>>> > -let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {<br>
>>>> > +let Defs = [EDI], Uses = [DX,EDI,DF] in {<br>
>>>> > def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst),<br>
>>>> > "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;<br>
>>>> > def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst),<br>
>>>> > @@ -2117,19 +2109,22 @@ def INSL : I<0x6D, RawFrmDst, (outs), (i<br>
>>>> > }<br>
>>>> > }<br>
>>>> ><br>
>>>> > -// Flag instructions<br>
>>>> > -let SchedRW = [WriteALU] in {<br>
>>>> > +// EFLAGS management instructions.<br>
>>>> > +let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in {<br>
>>>> > def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC_CMC_STC>;<br>
>>>> > def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_CLC_CMC_STC>;<br>
>>>> > -def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;<br>
>>>> > -def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;<br>
>>>> > -def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;<br>
>>>> > -def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;<br>
>>>> > def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CLC_CMC_STC>;<br>
>>>> > +}<br>
>>>> ><br>
>>>> > -def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;<br>
>>>> > +// DF management instructions.<br>
>>>> > +// FIXME: These are a bit more expensive than CLC and STC. We should<br>
>>>> > consider<br>
>>>> > +// adjusting their schedule bucket.<br>
>>>> > +let SchedRW = [WriteALU], Defs = [DF] in {<br>
>>>> > +def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;<br>
>>>> > +def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;<br>
>>>> > }<br>
>>>> ><br>
>>>> > +<br>
>>>> > // Table lookup instructions<br>
>>>> > let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in<br>
>>>> > def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,<br>
>>>> ><br>
>>>> > Modified: llvm/trunk/lib/Target/X86/X86I<wbr>nstrSystem.td<br>
>>>> > URL:<br>
>>>> > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=329673&r1=329672&r2=329673&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86InstrSystem.td?rev=329673<wbr>&r1=329672&r2=329673&view=diff</a><br>
>>>> ><br>
>>>> > ==============================<wbr>==============================<wbr>==================<br>
>>>> > --- llvm/trunk/lib/Target/X86/X86I<wbr>nstrSystem.td (original)<br>
>>>> > +++ llvm/trunk/lib/Target/X86/X86I<wbr>nstrSystem.td Mon Apr 9 23:40:51<br>
>>>> > 2018<br>
>>>> > @@ -700,6 +700,19 @@ let Uses = [RAX, RBX, RCX, RDX], Defs =<br>
>>>> > } // SchedRW<br>
>>>> ><br>
>>>> ><br>
>>>> > //===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
>>>> > +// TS flag control instruction.<br>
>>>> > +let SchedRW = [WriteSystem] in {<br>
>>>> > +def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;<br>
>>>> > +}<br>
>>>> > +<br>
>>>> ><br>
>>>> > +//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
>>>> > +// IF (inside EFLAGS) management instructions.<br>
>>>> > +let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {<br>
>>>> > +def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;<br>
>>>> > +def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;<br>
>>>> > +}<br>
>>>> > +<br>
>>>> ><br>
>>>> > +//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
>>>> > // RDPID Instruction<br>
>>>> > let SchedRW = [WriteSystem] in {<br>
>>>> > def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),<br>
>>>> ><br>
>>>> > Modified: llvm/trunk/lib/Target/X86/X86R<wbr>egisterInfo.td<br>
>>>> > URL:<br>
>>>> > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=329673&r1=329672&r2=329673&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86RegisterInfo.td?rev=32967<wbr>3&r1=329672&r2=329673&view=dif<wbr>f</a><br>
>>>> ><br>
>>>> > ==============================<wbr>==============================<wbr>==================<br>
>>>> > --- llvm/trunk/lib/Target/X86/X86R<wbr>egisterInfo.td (original)<br>
>>>> > +++ llvm/trunk/lib/Target/X86/X86R<wbr>egisterInfo.td Mon Apr 9 23:40:51<br>
>>>> > 2018<br>
>>>> > @@ -265,9 +265,19 @@ def ST7 : X86Reg<"st(7)", 7>, DwarfRegNu<br>
>>>> > // Floating-point status word<br>
>>>> > def FPSW : X86Reg<"fpsw", 0>;<br>
>>>> ><br>
>>>> > -// Status flags register<br>
>>>> > +// Status flags register.<br>
>>>> > +//<br>
>>>> > +// Note that some flags that are commonly thought of as part of the<br>
>>>> > status<br>
>>>> > +// flags register are modeled separately. Typically this is due to<br>
>>>> > instructions<br>
>>>> > +// reading and updating those flags independently of all the others.<br>
>>>> > We don't<br>
>>>> > +// want to create false dependencies between these instructions and<br>
>>>> > so we use<br>
>>>> > +// a separate register to model them.<br>
>>>> > def EFLAGS : X86Reg<"flags", 0>;<br>
>>>> ><br>
>>>> > +// The direction flag.<br>
>>>> > +def DF : X86Reg<"DF", 0>;<br>
>>>> > +<br>
>>>> > +<br>
>>>> > // Segment registers<br>
>>>> > def CS : X86Reg<"cs", 1>;<br>
>>>> > def DS : X86Reg<"ds", 3>;<br>
>>>> > @@ -510,6 +520,10 @@ def FPCCR : RegisterClass<"X86", [i16],<br>
>>>> > let CopyCost = -1; // Don't allow copying of status registers.<br>
>>>> > let isAllocatable = 0;<br>
>>>> > }<br>
>>>> > +def DFCCR : RegisterClass<"X86", [i32], 32, (add DF)> {<br>
>>>> > + let CopyCost = -1; // Don't allow copying of status registers.<br>
>>>> > + let isAllocatable = 0;<br>
>>>> > +}<br>
>>>> ><br>
>>>> > // AVX-512 vector/mask registers.<br>
>>>> > def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16,<br>
>>>> > v16i32, v8i64],<br>
>>>> ><br>
>>>> > Modified: llvm/trunk/test/CodeGen/X86/ip<wbr>ra-reg-usage.ll<br>
>>>> > URL:<br>
>>>> > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ipra-reg-usage.ll?rev=329673&r1=329672&r2=329673&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/ipra-reg-usage.ll?rev=3296<wbr>73&r1=329672&r2=329673&view=di<wbr>ff</a><br>
>>>> ><br>
>>>> > ==============================<wbr>==============================<wbr>==================<br>
>>>> > --- llvm/trunk/test/CodeGen/X86/ip<wbr>ra-reg-usage.ll (original)<br>
>>>> > +++ llvm/trunk/test/CodeGen/X86/ip<wbr>ra-reg-usage.ll Mon Apr 9 23:40:51<br>
>>>> > 2018<br>
>>>> > @@ -3,7 +3,7 @@<br>
>>>> > target triple = "x86_64-unknown-unknown"<br>
>>>> > declare void @bar1()<br>
>>>> > define preserve_allcc void @foo()#0 {<br>
>>>> > -; CHECK: foo Clobbered Registers: $cs $ds $eflags $eip $eiz $es $fpsw<br>
>>>> > $fs $gs $hip $ip $rip $riz $ss $ssp $bnd0 $bnd1 $bnd2 $bnd3 $cr0 $cr1 $cr2<br>
>>>> > $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0<br>
>>>> > $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14<br>
>>>> > $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5 $k6<br>
>>>> > $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4<br>
>>>> > $st5 $st6 $st7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23<br>
>>>> > $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2<br>
>>>> > $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14<br>
>>>> > $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25<br>
>>>> > $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4<br>
>>>> > $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15<br>
>>>> > $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26<br>
>>>> > $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11d $r11w<br>
>>>> > +; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es<br>
>>>> > $fpsw $fs $gs $hip $ip $rip $riz $ss $ssp $bnd0 $bnd1 $bnd2 $bnd3 $cr0 $cr1<br>
>>>> > $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15<br>
>>>> > $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13<br>
>>>> > $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5<br>
>>>> > $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3<br>
>>>> > $st4 $st5 $st6 $st7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23<br>
>>>> > $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2<br>
>>>> > $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14<br>
>>>> > $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25<br>
>>>> > $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4<br>
>>>> > $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15<br>
>>>> > $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26<br>
>>>> > $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11d $r11w<br>
>>>> > call void @bar1()<br>
>>>> > call void @bar2()<br>
>>>> > ret void<br>
>>>> ><br>
>>>> ><br>
>>>> > ______________________________<wbr>_________________<br>
>>>> > llvm-commits mailing list<br>
>>>> > <a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
>>>> > <a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/<wbr>mailman/listinfo/llvm-commits</a><br>
>>>> ______________________________<wbr>_________________<br>
>>>> llvm-commits mailing list<br>
>>>> <a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
>>>> <a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/<wbr>mailman/listinfo/llvm-commits</a><br>
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