<div dir="ltr"><div>Hello Tim,<br><br>This commit added broken test to one of our builders:<br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/8706">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/8706</a><br><br>. . .<br>Failing Tests (1):<br> LLVM :: CodeGen/AMDGPU/amdpal.ll<br><br>Please have a look?<br><br>The builder was already red and did not send notifications.<br><br>Thanks<br><br></div>Galina<br><br><div><br><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Mar 27, 2018 at 2:35 PM, Tim Renouf via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: tpr<br>
Date: Tue Mar 27 14:35:00 2018<br>
New Revision: 328673<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=328673&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=328673&view=rev</a><br>
Log:<br>
[AMDGPU] For OS type AMDPAL, fixed scratch on compute shader<br>
<br>
Summary:<br>
For OS type AMDPAL, the scratch descriptor is loaded from offset 0 of<br>
the GIT, whose 32 bit pointer is in s0 (s8 for gfx9 merged shaders).<br>
<br>
This commit fixes that to use offset 0x10 instead of offset 0 for a<br>
compute shader, per the PAL ABI spec.<br>
<br>
Reviewers: kzhuravl, nhaehnle, timcorringham<br>
<br>
Subscribers: kzhuravl, wdng, yaxunl, t-tye, llvm-commits, dstuttard, nhaehnle, arsenm<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D44468" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D44468</a><br>
<br>
Change-Id: I93dffa647758e37f613bb5e0dfca8<wbr>40d82e6d26f<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AMDGPU/<wbr>SIFrameLowering.cpp<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/amdpal.ll<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/<wbr>SIFrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp?rev=328673&r1=328672&r2=328673&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AMDGPU/SIFrameLowering.cpp?<wbr>rev=328673&r1=328672&r2=<wbr>328673&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AMDGPU/<wbr>SIFrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/<wbr>SIFrameLowering.cpp Tue Mar 27 14:35:00 2018<br>
@@ -405,7 +405,7 @@ void SIFrameLowering::<wbr>emitEntryFunctionS<br>
.addReg(ScratchRsrcReg, RegState::ImplicitDefine);<br>
<br>
// We now have the GIT ptr - now get the scratch descriptor from the entry<br>
- // at offset 0.<br>
+ // at offset 0 (or offset 16 for a compute shader).<br>
PointerType *PtrTy =<br>
PointerType::get(Type::<wbr>getInt64Ty(MF.getFunction().<wbr>getContext()),<br>
AMDGPUAS::CONSTANT_ADDRESS);<br>
@@ -416,9 +416,11 @@ void SIFrameLowering::<wbr>emitEntryFunctionS<br>
MachineMemOperand::MOInvariant |<br>
MachineMemOperand::<wbr>MODereferenceable,<br>
0, 0);<br>
+ unsigned Offset<br>
+ = MF.getFunction().<wbr>getCallingConv() == CallingConv::AMDGPU_CS ? 16 : 0;<br>
BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)<br>
.addReg(Rsrc01)<br>
- .addImm(0) // offset<br>
+ .addImm(Offset) // offset<br>
.addImm(0) // glc<br>
.addReg(ScratchRsrcReg, RegState::ImplicitDefine)<br>
.addMemOperand(MMO);<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/amdpal.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/amdpal.ll?rev=328673&r1=328672&r2=328673&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/amdpal.ll?rev=<wbr>328673&r1=328672&r2=328673&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/amdpal.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/amdpal.ll Tue Mar 27 14:35:00 2018<br>
@@ -52,7 +52,36 @@ entry:<br>
ret void<br>
}<br>
<br>
+; Check code sequence for amdpal use of scratch for alloca in a compute shader.<br>
+; The scratch descriptor is loaded from offset 0x10 of the GIT, rather than offset<br>
+; 0 in a graphics shader.<br>
+<br>
+; PAL-LABEL: {{^}}scratch2_cs:<br>
+; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234<br>
+; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0<br>
+; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:<wbr>{{[0-9]+]}}, s{{\[}}[[GITPTR]]:{{[0-9]+\]}}<wbr>, 0x10<br>
+; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:<br>
+<br>
+define amdgpu_cs void @scratch2_cs(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #0 {<br>
+entry:<br>
+ %v = alloca [3 x i32], addrspace(5)<br>
+ %v0 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 0<br>
+ %v1 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 1<br>
+ store i32 %extra, i32 addrspace(5)* %v0<br>
+ %v1a = bitcast i32 addrspace(5)* %v1 to [2 x i32] addrspace(5)*<br>
+ %vv = bitcast [2 x i32] addrspace(5)* %v1a to <2 x i32> addrspace(5)*<br>
+ store <2 x i32> %in, <2 x i32> addrspace(5)* %vv<br>
+ %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v1a, i32 0, i32 %idx<br>
+ %x = load i32, i32 addrspace(5)* %e<br>
+ %xf = bitcast i32 %x to float<br>
+ call void @llvm.amdgcn.buffer.store.f32(<wbr>float %xf, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)<br>
+ ret void<br>
+}<br>
+<br>
attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" }<br>
<br>
+declare void @llvm.amdgcn.buffer.store.f32(<wbr>float, <4 x i32>, i32, i32, i1, i1)<br>
+<br>
+<br>
; Check we have CS_NUM_USED_VGPRS in PAL metadata.<br>
; PAL: .amd_amdgpu_pal_metadata {{.*}},0x10000027,<br>
<br>
<br>
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</blockquote></div><br></div></div></div>