<div dir="ltr">Unsurprisingly, this appears to be causing crashes when building Chromium, so I'm going to flag this off for now.</div><br><br><div class="gmail_quote"><div dir="ltr">On Wed, Mar 14, 2018 at 2:56 PM Reid Kleckner via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rnk<br>
Date: Wed Mar 14 14:54:21 2018<br>
New Revision: 327581<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=327581&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=327581&view=rev</a><br>
Log:<br>
[FastISel] Sink local value materializations to first use<br>
<br>
Summary:<br>
Local values are constants, global addresses, and stack addresses that<br>
can't be folded into the instruction that uses them. For example, when<br>
storing the address of a global variable into memory, we need to<br>
materialize that address into a register.<br>
<br>
FastISel doesn't want to materialize any given local value more than<br>
once, so it generates all local value materialization code at<br>
EmitStartPt, which always dominates the current insertion point. This<br>
allows it to maintain a map of local value registers, and it knows that<br>
the local value area will always dominate the current insertion point.<br>
<br>
The downside is that local value instructions are always emitted without<br>
a source location. This is done to prevent jumpy line tables, but it<br>
means that the local value area will be considered part of the previous<br>
statement. Consider this C code:<br>
call1(); // line 1<br>
++global; // line 2<br>
++global; // line 3<br>
call2(&global, &local); // line 4<br>
<br>
Today we end up with assembly and line tables like this:<br>
.loc 1 1<br>
callq call1<br>
leaq global(%rip), %rdi<br>
leaq local(%rsp), %rsi<br>
.loc 1 2<br>
addq $1, global(%rip)<br>
.loc 1 3<br>
addq $1, global(%rip)<br>
.loc 1 4<br>
callq call2<br>
<br>
The LEA instructions in the local value area have no source location and<br>
are treated as being on line 1. Stepping through the code in a debugger<br>
and correlating it with the assembly won't make much sense, because<br>
these materializations are only required for line 4.<br>
<br>
This is actually problematic for the VS debugger "set next statement"<br>
feature, which effectively assumes that there are no registers live<br>
across statement boundaries. By sinking the local value code into the<br>
statement and fixing up the source location, we can make that feature<br>
work. This was filed as <a href="https://bugs.llvm.org/show_bug.cgi?id=35975" rel="noreferrer" target="_blank">https://bugs.llvm.org/show_bug.cgi?id=35975</a> and<br>
<a href="https://crbug.com/793819" rel="noreferrer" target="_blank">https://crbug.com/793819</a>.<br>
<br>
This change is obviously not enough to make this feature work reliably<br>
in all cases, but I felt that it was worth doing anyway because it<br>
usually generates smaller, more comprehensible -O0 code. I measured a<br>
0.12% regression in code generation time with LLC on the sqlite3<br>
amalgamation, so I think this is worth doing.<br>
<br>
There are some special cases worth calling out in the commit message:<br>
1. local values materialized for phis<br>
2. local values used by no-op casts<br>
3. dead local value code<br>
<br>
Local values can be materialized for phis, and this does not show up as<br>
a vreg use in MachineRegisterInfo. In this case, if there are no other<br>
uses, this patch sinks the value to the first terminator, EH label, or<br>
the end of the BB if nothing else exists.<br>
<br>
Local values may also be used by no-op casts, which adds the register to<br>
the RegFixups table. Without reversing the RegFixups map direction, we<br>
don't have enough information to sink these instructions.<br>
<br>
Lastly, if the local value register has no other uses, we can delete it.<br>
This comes up when fastisel tries two instruction selection approaches<br>
and the first materializes the value but fails and the second succeeds<br>
without using the local value.<br>
<br>
Reviewers: aprantl, dblaikie, qcolombet, MatzeB, vsk, echristo<br>
<br>
Subscribers: dotdash, chandlerc, hans, sdardis, amccarth, javed.absar, zturner, llvm-commits, hiraditya<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D43093" rel="noreferrer" target="_blank">https://reviews.llvm.org/D43093</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/sink-local-value.ll<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/FastISel.h<br>
llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h<br>
llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp<br>
llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-call.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-gv.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll<br>
llvm/trunk/test/CodeGen/AArch64/swifterror.ll<br>
llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll<br>
llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll<br>
llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll<br>
llvm/trunk/test/CodeGen/ARM/fast-isel-vararg.ll<br>
llvm/trunk/test/CodeGen/ARM/swifterror.ll<br>
llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll<br>
llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestore.ll<br>
llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestorei.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-mask-zext-bugfix.ll<br>
llvm/trunk/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll<br>
llvm/trunk/test/CodeGen/X86/fast-isel-call-cleanup.ll<br>
llvm/trunk/test/CodeGen/X86/fast-isel-store.ll<br>
llvm/trunk/test/CodeGen/X86/inreg.ll<br>
llvm/trunk/test/CodeGen/X86/pr32241.ll<br>
llvm/trunk/test/CodeGen/X86/pr32284.ll<br>
llvm/trunk/test/CodeGen/X86/pr32340.ll<br>
llvm/trunk/test/CodeGen/X86/pr32345.ll<br>
llvm/trunk/test/CodeGen/X86/pr32484.ll<br>
llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll<br>
llvm/trunk/test/CodeGen/X86/win32_sret.ll<br>
llvm/trunk/test/DebugInfo/COFF/lines-bb-start.ll<br>
llvm/trunk/test/DebugInfo/Mips/delay-slot.ll<br>
llvm/trunk/test/DebugInfo/X86/debug-loc-asan.ll<br>
llvm/trunk/test/DebugInfo/X86/prologue-stack.ll<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Wed Mar 14 14:54:21 2018<br>
@@ -241,9 +241,12 @@ public:<br>
}<br>
<br>
/// \brief Set the current block to which generated machine instructions will<br>
- /// be appended, and clear the local CSE map.<br>
+ /// be appended.<br>
void startNewBlock();<br>
<br>
+ /// Flush the local value map and sink local values if possible.<br>
+ void finishBasicBlock();<br>
+<br>
/// \brief Return current debug location information.<br>
DebugLoc getCurDebugLoc() const { return DbgLoc; }<br>
<br>
@@ -560,6 +563,19 @@ private:<br>
/// \brief Removes dead local value instructions after SavedLastLocalvalue.<br>
void removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue);<br>
<br>
+ struct InstOrderMap {<br>
+ DenseMap<MachineInstr *, unsigned> Orders;<br>
+ MachineInstr *FirstTerminator = nullptr;<br>
+ unsigned FirstTerminatorOrder = std::numeric_limits<unsigned>::max();<br>
+<br>
+ void initialize(MachineBasicBlock *MBB);<br>
+ };<br>
+<br>
+ /// Sinks the local value materialization instruction LocalMI to its first use<br>
+ /// in the basic block, or deletes it if it is not used.<br>
+ void sinkLocalValueMaterialization(MachineInstr &LocalMI, unsigned DefReg,<br>
+ InstOrderMap &OrderMap);<br>
+<br>
/// \brief Insertion point before trying to select the current instruction.<br>
MachineBasicBlock::iterator SavedInsertPt;<br>
<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h Wed Mar 14 14:54:21 2018<br>
@@ -178,6 +178,8 @@ public:<br>
/// RegFixups - Registers which need to be replaced after isel is done.<br>
DenseMap<unsigned, unsigned> RegFixups;<br>
<br>
+ DenseSet<unsigned> RegsWithFixups;<br>
+<br>
/// StatepointStackSlots - A list of temporary stack slots (frame indices)<br>
/// used to spill values at a statepoint. We store them here to enable<br>
/// reuse of the same stack slots across different statepoints in different<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Mar 14 14:54:21 2018<br>
@@ -120,9 +120,10 @@ STATISTIC(NumFastIselSuccessTarget, "Num<br>
STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");<br>
<br>
/// Set the current block to which generated machine instructions will be<br>
-/// appended, and clear the local CSE map.<br>
+/// appended.<br>
void FastISel::startNewBlock() {<br>
- LocalValueMap.clear();<br>
+ assert(LocalValueMap.empty() &&<br>
+ "local values should be cleared after finishing a BB");<br>
<br>
// Instructions are appended to FuncInfo.MBB. If the basic block already<br>
// contains labels or copies, use the last instruction as the last local<br>
@@ -133,6 +134,9 @@ void FastISel::startNewBlock() {<br>
LastLocalValue = EmitStartPt;<br>
}<br>
<br>
+/// Flush the local CSE map and sink anything we can.<br>
+void FastISel::finishBasicBlock() { flushLocalValueMap(); }<br>
+<br>
bool FastISel::lowerArguments() {<br>
if (!FuncInfo.CanLowerReturn)<br>
// Fallback to SDISel argument lowering code to deal with sret pointer<br>
@@ -153,13 +157,160 @@ bool FastISel::lowerArguments() {<br>
return true;<br>
}<br>
<br>
+/// Return the defined register if this instruction defines exactly one<br>
+/// virtual register and uses no other virtual registers. Otherwise return 0.<br>
+static unsigned findSinkableLocalRegDef(MachineInstr &MI) {<br>
+ unsigned RegDef = 0;<br>
+ for (const MachineOperand &MO : MI.operands()) {<br>
+ if (!MO.isReg())<br>
+ continue;<br>
+ if (MO.isDef()) {<br>
+ if (RegDef)<br>
+ return 0;<br>
+ RegDef = MO.getReg();<br>
+ } else if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {<br>
+ // This is another use of a vreg. Don't try to sink it.<br>
+ return 0;<br>
+ }<br>
+ }<br>
+ return RegDef;<br>
+}<br>
+<br>
void FastISel::flushLocalValueMap() {<br>
+ // Try to sink local values down to their first use so that we can give them a<br>
+ // better debug location. This has the side effect of shrinking local value<br>
+ // live ranges, which helps out fast regalloc.<br>
+ if (LastLocalValue != EmitStartPt) {<br>
+ // Sink local value materialization instructions between EmitStartPt and<br>
+ // LastLocalValue. Visit them bottom-up, starting from LastLocalValue, to<br>
+ // avoid inserting into the range that we're iterating over.<br>
+ MachineBasicBlock::reverse_iterator RE =<br>
+ EmitStartPt ? MachineBasicBlock::reverse_iterator(EmitStartPt)<br>
+ : FuncInfo.MBB->rend();<br>
+ MachineBasicBlock::reverse_iterator RI(LastLocalValue);<br>
+<br>
+ InstOrderMap OrderMap;<br>
+ for (; RI != RE;) {<br>
+ MachineInstr &LocalMI = *RI;<br>
+ ++RI;<br>
+ bool Store = true;<br>
+ if (!LocalMI.isSafeToMove(nullptr, Store))<br>
+ continue;<br>
+ unsigned DefReg = findSinkableLocalRegDef(LocalMI);<br>
+ if (DefReg == 0)<br>
+ continue;<br>
+<br>
+ sinkLocalValueMaterialization(LocalMI, DefReg, OrderMap);<br>
+ }<br>
+ }<br>
+<br>
LocalValueMap.clear();<br>
LastLocalValue = EmitStartPt;<br>
recomputeInsertPt();<br>
SavedInsertPt = FuncInfo.InsertPt;<br>
}<br>
<br>
+static bool isRegUsedByPhiNodes(unsigned DefReg,<br>
+ FunctionLoweringInfo &FuncInfo) {<br>
+ for (auto &P : FuncInfo.PHINodesToUpdate)<br>
+ if (P.second == DefReg)<br>
+ return true;<br>
+ return false;<br>
+}<br>
+<br>
+/// Build a map of instruction orders. Return the first terminator and its<br>
+/// order. Consider EH_LABEL instructions to be terminators as well, since local<br>
+/// values for phis after invokes must be materialized before the call.<br>
+void FastISel::InstOrderMap::initialize(MachineBasicBlock *MBB) {<br>
+ unsigned Order = 0;<br>
+ for (MachineInstr &I : *MBB) {<br>
+ if (!FirstTerminator &&<br>
+ (I.isTerminator() || (I.isEHLabel() && &I != &MBB->front()))) {<br>
+ FirstTerminator = &I;<br>
+ FirstTerminatorOrder = Order;<br>
+ }<br>
+ Orders[&I] = Order++;<br>
+ }<br>
+}<br>
+<br>
+void FastISel::sinkLocalValueMaterialization(MachineInstr &LocalMI,<br>
+ unsigned DefReg,<br>
+ InstOrderMap &OrderMap) {<br>
+ // If this register is used by a register fixup, MRI will not contain all<br>
+ // the uses until after register fixups, so don't attempt to sink or DCE<br>
+ // this instruction. Register fixups typically come from no-op cast<br>
+ // instructions, which replace the cast instruction vreg with the local<br>
+ // value vreg.<br>
+ if (FuncInfo.RegsWithFixups.count(DefReg))<br>
+ return;<br>
+<br>
+ // We can DCE this instruction if there are no uses and it wasn't a<br>
+ // materialized for a successor PHI node.<br>
+ bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo);<br>
+ if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) {<br>
+ if (EmitStartPt == &LocalMI)<br>
+ EmitStartPt = EmitStartPt->getPrevNode();<br>
+ DEBUG(dbgs() << "removing dead local value materialization " << LocalMI);<br>
+ OrderMap.Orders.erase(&LocalMI);<br>
+ LocalMI.eraseFromParent();<br>
+ return;<br>
+ }<br>
+<br>
+ // Number the instructions if we haven't yet so we can efficiently find the<br>
+ // earliest use.<br>
+ if (OrderMap.Orders.empty())<br>
+ OrderMap.initialize(FuncInfo.MBB);<br>
+<br>
+ // Find the first user in the BB.<br>
+ MachineInstr *FirstUser = nullptr;<br>
+ unsigned FirstOrder = std::numeric_limits<unsigned>::max();<br>
+ for (MachineInstr &UseInst : MRI.use_nodbg_instructions(DefReg)) {<br>
+ unsigned UseOrder = OrderMap.Orders[&UseInst];<br>
+ if (UseOrder < FirstOrder) {<br>
+ FirstOrder = UseOrder;<br>
+ FirstUser = &UseInst;<br>
+ }<br>
+ }<br>
+<br>
+ // The insertion point will be the first terminator or the first user,<br>
+ // whichever came first. If there was no terminator, this must be a<br>
+ // fallthrough block and the insertion point is the end of the block.<br>
+ MachineBasicBlock::instr_iterator SinkPos;<br>
+ if (UsedByPHI && OrderMap.FirstTerminatorOrder < FirstOrder) {<br>
+ FirstOrder = OrderMap.FirstTerminatorOrder;<br>
+ SinkPos = OrderMap.FirstTerminator->getIterator();<br>
+ } else if (FirstUser) {<br>
+ SinkPos = FirstUser->getIterator();<br>
+ } else {<br>
+ assert(UsedByPHI && "must be users if not used by a phi");<br>
+ SinkPos = FuncInfo.MBB->instr_end();<br>
+ }<br>
+<br>
+ // Collect all DBG_VALUEs before the new insertion position so that we can<br>
+ // sink them.<br>
+ SmallVector<MachineInstr *, 1> DbgValues;<br>
+ for (MachineInstr &DbgVal : MRI.use_instructions(DefReg)) {<br>
+ if (!DbgVal.isDebugValue())<br>
+ continue;<br>
+ unsigned UseOrder = OrderMap.Orders[&DbgVal];<br>
+ if (UseOrder < FirstOrder)<br>
+ DbgValues.push_back(&DbgVal);<br>
+ }<br>
+<br>
+ // Sink LocalMI before SinkPos and assign it the same DebugLoc.<br>
+ DEBUG(dbgs() << "sinking local value to first use " << LocalMI);<br>
+ FuncInfo.MBB->remove(&LocalMI);<br>
+ FuncInfo.MBB->insert(SinkPos, &LocalMI);<br>
+ if (SinkPos != FuncInfo.MBB->end())<br>
+ LocalMI.setDebugLoc(SinkPos->getDebugLoc());<br>
+<br>
+ // Sink any debug values that we've collected.<br>
+ for (MachineInstr *DI : DbgValues) {<br>
+ FuncInfo.MBB->remove(DI);<br>
+ FuncInfo.MBB->insert(SinkPos, DI);<br>
+ }<br>
+}<br>
+<br>
bool FastISel::hasTrivialKill(const Value *V) {<br>
// Don't consider constants or arguments to have trivial kills.<br>
const Instruction *I = dyn_cast<Instruction>(V);<br>
@@ -328,8 +479,10 @@ void FastISel::updateValueMap(const Valu<br>
AssignedReg = Reg;<br>
else if (Reg != AssignedReg) {<br>
// Arrange for uses of AssignedReg to be replaced by uses of Reg.<br>
- for (unsigned i = 0; i < NumRegs; i++)<br>
+ for (unsigned i = 0; i < NumRegs; i++) {<br>
FuncInfo.RegFixups[AssignedReg + i] = Reg + i;<br>
+ FuncInfo.RegsWithFixups.insert(Reg + i);<br>
+ }<br>
<br>
AssignedReg = Reg;<br>
}<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Wed Mar 14 14:54:21 2018<br>
@@ -318,6 +318,7 @@ void FunctionLoweringInfo::clear() {<br>
ArgDbgValues.clear();<br>
ByValArgFrameIndexMap.clear();<br>
RegFixups.clear();<br>
+ RegsWithFixups.clear();<br>
StatepointStackSlots.clear();<br>
StatepointSpillMaps.clear();<br>
PreferredExtendType.clear();<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Mar 14 14:54:21 2018<br>
@@ -1658,6 +1658,8 @@ void SelectionDAGISel::SelectAllBasicBlo<br>
FastIS->removeDeadCode(FuncInfo->InsertPt, FuncInfo->MBB->end());<br>
}<br>
<br>
+ if (FastIS)<br>
+ FastIS->finishBasicBlock();<br>
FinishBasicBlock();<br>
FuncInfo->PHINodesToUpdate.clear();<br>
ElidedArgCopyInstrs.clear();<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll Wed Mar 14 14:54:21 2018<br>
@@ -290,13 +290,14 @@ entry:<br>
; Space for s2 is allocated at sp<br>
<br>
; FAST-LABEL: caller42<br>
-; FAST: sub sp, sp, #112<br>
-; Space for s1 is allocated at fp-24 = sp+72<br>
-; Space for s2 is allocated at sp+48<br>
+; FAST: sub sp, sp, #96<br>
+; Space for s1 is allocated at fp-24 = sp+56<br>
; FAST: sub x[[A:[0-9]+]], x29, #24<br>
-; FAST: add x[[A:[0-9]+]], sp, #48<br>
; Call memcpy with size = 24 (0x18)<br>
; FAST: orr {{x[0-9]+}}, xzr, #0x18<br>
+; Space for s2 is allocated at sp+32<br>
+; FAST: add x[[A:[0-9]+]], sp, #32<br>
+; FAST: bl _memcpy<br>
%tmp = alloca %struct.s42, align 4<br>
%tmp1 = alloca %struct.s42, align 4<br>
%0 = bitcast %struct.s42* %tmp to i8*<br>
@@ -334,13 +335,16 @@ entry:<br>
<br>
; FAST-LABEL: caller42_stack<br>
; Space for s1 is allocated at fp-24<br>
-; Space for s2 is allocated at fp-48<br>
; FAST: sub x[[A:[0-9]+]], x29, #24<br>
-; FAST: sub x[[B:[0-9]+]], x29, #48<br>
; Call memcpy with size = 24 (0x18)<br>
; FAST: orr {{x[0-9]+}}, xzr, #0x18<br>
-; FAST: str {{w[0-9]+}}, [sp]<br>
+; FAST: bl _memcpy<br>
+; Space for s2 is allocated at fp-48<br>
+; FAST: sub x[[B:[0-9]+]], x29, #48<br>
+; Call memcpy again<br>
+; FAST: bl _memcpy<br>
; Address of s1 is passed on stack at sp+8<br>
+; FAST: str {{w[0-9]+}}, [sp]<br>
; FAST: str {{x[0-9]+}}, [sp, #8]<br>
; FAST: str {{x[0-9]+}}, [sp, #16]<br>
%tmp = alloca %struct.s42, align 4<br>
@@ -401,8 +405,6 @@ entry:<br>
; FAST: add x29, sp, #64<br>
; Space for s1 is allocated at sp+32<br>
; Space for s2 is allocated at sp<br>
-; FAST: add x1, sp, #32<br>
-; FAST: mov x2, sp<br>
; FAST: str {{x[0-9]+}}, [sp, #32]<br>
; FAST: str {{x[0-9]+}}, [sp, #40]<br>
; FAST: str {{x[0-9]+}}, [sp, #48]<br>
@@ -411,6 +413,8 @@ entry:<br>
; FAST: str {{x[0-9]+}}, [sp, #8]<br>
; FAST: str {{x[0-9]+}}, [sp, #16]<br>
; FAST: str {{x[0-9]+}}, [sp, #24]<br>
+; FAST: add x1, sp, #32<br>
+; FAST: mov x2, sp<br>
%tmp = alloca %struct.s43, align 16<br>
%tmp1 = alloca %struct.s43, align 16<br>
%0 = bitcast %struct.s43* %tmp to i8*<br>
@@ -448,8 +452,6 @@ entry:<br>
; FAST: sub sp, sp, #112<br>
; Space for s1 is allocated at fp-32 = sp+64<br>
; Space for s2 is allocated at sp+32<br>
-; FAST: sub x[[A:[0-9]+]], x29, #32<br>
-; FAST: add x[[B:[0-9]+]], sp, #32<br>
; FAST: stur {{x[0-9]+}}, [x29, #-32]<br>
; FAST: stur {{x[0-9]+}}, [x29, #-24]<br>
; FAST: stur {{x[0-9]+}}, [x29, #-16]<br>
@@ -460,8 +462,10 @@ entry:<br>
; FAST: str {{x[0-9]+}}, [sp, #56]<br>
; FAST: str {{w[0-9]+}}, [sp]<br>
; Address of s1 is passed on stack at sp+8<br>
-; FAST: str {{x[0-9]+}}, [sp, #8]<br>
-; FAST: str {{x[0-9]+}}, [sp, #16]<br>
+; FAST: sub x[[A:[0-9]+]], x29, #32<br>
+; FAST: str x[[A]], [sp, #8]<br>
+; FAST: add x[[B:[0-9]+]], sp, #32<br>
+; FAST: str x[[B]], [sp, #16]<br>
%tmp = alloca %struct.s43, align 16<br>
%tmp1 = alloca %struct.s43, align 16<br>
%0 = bitcast %struct.s43* %tmp to i8*<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-call.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-call.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-call.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-call.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-call.ll Wed Mar 14 14:54:21 2018<br>
@@ -80,15 +80,15 @@ define i32 @t2() {<br>
entry:<br>
; CHECK-LABEL: t2<br>
; CHECK: mov [[REG1:x[0-9]+]], xzr<br>
+; CHECK: mov x0, [[REG1]]<br>
; CHECK: orr w1, wzr, #0xfffffff8<br>
; CHECK: orr [[REG2:w[0-9]+]], wzr, #0x3ff<br>
-; CHECK: orr [[REG3:w[0-9]+]], wzr, #0x2<br>
-; CHECK: mov [[REG4:w[0-9]+]], wzr<br>
-; CHECK: orr [[REG5:w[0-9]+]], wzr, #0x1<br>
-; CHECK: mov x0, [[REG1]]<br>
; CHECK: uxth w2, [[REG2]]<br>
+; CHECK: orr [[REG3:w[0-9]+]], wzr, #0x2<br>
; CHECK: sxtb w3, [[REG3]]<br>
+; CHECK: mov [[REG4:w[0-9]+]], wzr<br>
; CHECK: and w4, [[REG4]], #0x1<br>
+; CHECK: orr [[REG5:w[0-9]+]], wzr, #0x1<br>
; CHECK: and w5, [[REG5]], #0x1<br>
; CHECK: bl _func2<br>
%call = call i32 @func2(i64 zeroext 0, i32 signext -8, i16 zeroext 1023, i8 signext -254, i1 zeroext 0, i1 zeroext 1)<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-gv.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-gv.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-gv.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-gv.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-gv.ll Wed Mar 14 14:54:21 2018<br>
@@ -18,10 +18,10 @@ entry:<br>
; CHECK: @Rand<br>
; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE<br>
; CHECK: ldr [[REG2:x[0-9]+]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}}<br>
-; CHECK: mov [[REG3:x[0-9]+]], #13849<br>
-; CHECK: mov [[REG4:x[0-9]+]], #1309<br>
; CHECK: ldr [[REG5:x[0-9]+]], {{\[}}[[REG2]]{{\]}}<br>
+; CHECK: mov [[REG4:x[0-9]+]], #1309<br>
; CHECK: mul [[REG6:x[0-9]+]], [[REG5]], [[REG4]]<br>
+; CHECK: mov [[REG3:x[0-9]+]], #13849<br>
; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]]<br>
; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff<br>
; CHECK: str [[REG8]], {{\[}}[[REG1]]{{\]}}<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll Wed Mar 14 14:54:21 2018<br>
@@ -8,8 +8,8 @@ define void @t1() {<br>
; ARM64: adrp x8, _message@PAGE<br>
; ARM64: add x0, x8, _message@PAGEOFF<br>
; ARM64: mov w9, wzr<br>
-; ARM64: mov x2, #80<br>
; ARM64: uxtb w1, w9<br>
+; ARM64: mov x2, #80<br>
; ARM64: bl _memset<br>
call void @llvm.memset.p0i8.i64(i8* align 16 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i8 0, i64 80, i1 false)<br>
ret void<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll Wed Mar 14 14:54:21 2018<br>
@@ -95,6 +95,8 @@ declare void @llvm.trap() nounwind<br>
define void @ands(i32* %addr) {<br>
; CHECK-LABEL: ands:<br>
; CHECK: tst [[COND:w[0-9]+]], #0x1<br>
+; CHECK-NEXT: orr w{{[0-9]+}}, wzr, #0x2<br>
+; CHECK-NEXT: orr w{{[0-9]+}}, wzr, #0x1<br>
; CHECK-NEXT: csel [[COND]],<br>
entry:<br>
%cond91 = select i1 undef, i32 1, i32 2<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll Wed Mar 14 14:54:21 2018<br>
@@ -51,10 +51,10 @@ entry:<br>
; CHECK-NEXT: blr x16<br>
; FAST-LABEL: jscall_patchpoint_codegen2:<br>
; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2<br>
-; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4<br>
-; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6<br>
; FAST-NEXT: str [[REG1]], [sp]<br>
+; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4<br>
; FAST-NEXT: str [[REG2]], [sp, #16]<br>
+; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6<br>
; FAST-NEXT: str [[REG3]], [sp, #24]<br>
; FAST: Ltmp<br>
; FAST-NEXT: mov x16, #281470681743360<br>
@@ -87,14 +87,14 @@ entry:<br>
; CHECK-NEXT: blr x16<br>
; FAST-LABEL: jscall_patchpoint_codegen3:<br>
; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2<br>
-; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4<br>
-; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6<br>
-; FAST-NEXT: orr [[REG4:w[0-9]+]], wzr, #0x8<br>
-; FAST-NEXT: mov [[REG5:x[0-9]+]], #10<br>
; FAST-NEXT: str [[REG1]], [sp]<br>
+; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4<br>
; FAST-NEXT: str [[REG2]], [sp, #16]<br>
+; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6<br>
; FAST-NEXT: str [[REG3]], [sp, #24]<br>
+; FAST-NEXT: orr [[REG4:w[0-9]+]], wzr, #0x8<br>
; FAST-NEXT: str [[REG4]], [sp, #36]<br>
+; FAST-NEXT: mov [[REG5:x[0-9]+]], #10<br>
; FAST-NEXT: str [[REG5]], [sp, #48]<br>
; FAST: Ltmp<br>
; FAST-NEXT: mov x16, #281470681743360<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/swifterror.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/swifterror.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/swifterror.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/swifterror.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/swifterror.ll Wed Mar 14 14:54:21 2018<br>
@@ -189,10 +189,10 @@ define float @foo_loop(%swift_error** sw<br>
; CHECK-O0:[[BB2]]:<br>
; CHECK-O0: ldr x0, [sp, [[SLOT2]]]<br>
; CHECK-O0: fcmp<br>
-; CHECK-O0: str x0, [sp]<br>
+; CHECK-O0: str x0, [sp, [[SLOT3:#[0-9]+]]<br>
; CHECK-O0: b.le [[BB1]]<br>
; reload from stack<br>
-; CHECK-O0: ldr [[ID3:x[0-9]+]], [sp]<br>
+; CHECK-O0: ldr [[ID3:x[0-9]+]], [sp, [[SLOT3]]]<br>
; CHECK-O0: mov x21, [[ID3]]<br>
; CHECK-O0: ret<br>
entry:<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll Wed Mar 14 14:54:21 2018<br>
@@ -95,51 +95,54 @@ declare zeroext i1 @t9();<br>
define i32 @t10() {<br>
entry:<br>
; ARM: @t10<br>
-; ARM: movw [[R0:l?r[0-9]*]], #0<br>
-; ARM: movw [[R1:l?r[0-9]*]], #248<br>
-; ARM: movw [[R2:l?r[0-9]*]], #187<br>
-; ARM: movw [[R3:l?r[0-9]*]], #28<br>
-; ARM: movw [[R4:l?r[0-9]*]], #40<br>
-; ARM: movw [[R5:l?r[0-9]*]], #186<br>
-; ARM: and [[R0]], [[R0]], #255<br>
-; ARM: and [[R1]], [[R1]], #255<br>
-; ARM: and [[R2]], [[R2]], #255<br>
-; ARM: and [[R3]], [[R3]], #255<br>
-; ARM: and [[R4]], [[R4]], #255<br>
-; ARM: str [[R4]], [sp]<br>
-; ARM: and [[R4]], [[R5]], #255<br>
-; ARM: str [[R4]], [sp, #4]<br>
+; ARM-DAG: movw [[R0:l?r[0-9]*]], #0<br>
+; ARM-DAG: movw [[R1:l?r[0-9]*]], #248<br>
+; ARM-DAG: movw [[R2:l?r[0-9]*]], #187<br>
+; ARM-DAG: movw [[R3:l?r[0-9]*]], #28<br>
+; ARM-DAG: movw [[R4:l?r[0-9]*]], #40<br>
+; ARM-DAG: movw [[R5:l?r[0-9]*]], #186<br>
+; ARM-DAG: and [[R0]], [[R0]], #255<br>
+; ARM-DAG: and [[R1]], [[R1]], #255<br>
+; ARM-DAG: and [[R2]], [[R2]], #255<br>
+; ARM-DAG: and [[R3]], [[R3]], #255<br>
+; ARM-DAG: and [[R4]], [[R4]], #255<br>
+; ARM-DAG: str [[R4]], [sp]<br>
+; ARM-DAG: and [[R4]], [[R5]], #255<br>
+; ARM-DAG: str [[R4]], [sp, #4]<br>
; ARM: bl {{_?}}bar<br>
-; ARM-LONG: @t10<br>
+; ARM-LONG-LABEL: @t10<br>
<br>
; ARM-LONG-MACHO: {{(movw)|(ldr)}} [[R:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}<br>
; ARM-LONG-MACHO: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}}<br>
-; ARM-LONG-MACHO: ldr [[R]], {{\[}}[[R]]{{\]}}<br>
+; ARM-LONG-MACHO: str [[R]], [r7, [[SLOT:#[-0-9]+]]] @ 4-byte Spill<br>
+; ARM-LONG-MACHO: ldr [[R:l?r[0-9]*]], [r7, [[SLOT]]] @ 4-byte Reload<br>
<br>
; ARM-LONG-ELF: movw [[R:l?r[0-9]*]], :lower16:bar<br>
; ARM-LONG-ELF: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}}<br>
<br>
; ARM-LONG: blx [[R]]<br>
; THUMB: @t10<br>
-; THUMB: movs [[R0:l?r[0-9]*]], #0<br>
-; THUMB: movs [[R1:l?r[0-9]*]], #248<br>
-; THUMB: movs [[R2:l?r[0-9]*]], #187<br>
-; THUMB: movs [[R3:l?r[0-9]*]], #28<br>
-; THUMB: movw [[R4:l?r[0-9]*]], #40<br>
-; THUMB: movw [[R5:l?r[0-9]*]], #186<br>
-; THUMB: and [[R0]], [[R0]], #255<br>
-; THUMB: and [[R1]], [[R1]], #255<br>
-; THUMB: and [[R2]], [[R2]], #255<br>
-; THUMB: and [[R3]], [[R3]], #255<br>
-; THUMB: and [[R4]], [[R4]], #255<br>
-; THUMB: str.w [[R4]], [sp]<br>
-; THUMB: and [[R4]], [[R5]], #255<br>
-; THUMB: str.w [[R4]], [sp, #4]<br>
+; THUMB-DAG: movs [[R0:l?r[0-9]*]], #0<br>
+; THUMB-DAG: movs [[R1:l?r[0-9]*]], #248<br>
+; THUMB-DAG: movs [[R2:l?r[0-9]*]], #187<br>
+; THUMB-DAG: movs [[R3:l?r[0-9]*]], #28<br>
+; THUMB-DAG: movw [[R4:l?r[0-9]*]], #40<br>
+; THUMB-DAG: movw [[R5:l?r[0-9]*]], #186<br>
+; THUMB-DAG: and [[R0]], [[R0]], #255<br>
+; THUMB-DAG: and [[R1]], [[R1]], #255<br>
+; THUMB-DAG: and [[R2]], [[R2]], #255<br>
+; THUMB-DAG: and [[R3]], [[R3]], #255<br>
+; THUMB-DAG: and [[R4]], [[R4]], #255<br>
+; THUMB-DAG: str.w [[R4]], [sp]<br>
+; THUMB-DAG: and [[R4]], [[R5]], #255<br>
+; THUMB-DAG: str.w [[R4]], [sp, #4]<br>
; THUMB: bl {{_?}}bar<br>
-; THUMB-LONG: @t10<br>
+; THUMB-LONG-LABEL: @t10<br>
; THUMB-LONG: {{(movw)|(ldr.n)}} [[R:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}<br>
; THUMB-LONG: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}}<br>
; THUMB-LONG: ldr{{(.w)?}} [[R]], {{\[}}[[R]]{{\]}}<br>
+; THUMB-LONG: str [[R]], [sp, [[SLOT:#[-0-9]+]]] @ 4-byte Spill<br>
+; THUMB-LONG: ldr.w [[R:l?r[0-9]*]], [sp, [[SLOT]]] @ 4-byte Reload<br>
; THUMB-LONG: blx [[R]]<br>
%call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70)<br>
ret i32 0<br>
@@ -152,14 +155,15 @@ define i32 @bar0(i32 %i) nounwind {<br>
}<br>
<br>
define void @foo3() uwtable {<br>
-; ARM: movw r0, #0<br>
-; ARM: {{(movw r1, :lower16:_?bar0)|(ldr r1, .LCPI)}}<br>
-; ARM: {{(movt r1, :upper16:_?bar0)|(ldr r1, \[r1\])}}<br>
-; ARM: blx r1<br>
-; THUMB: movs r0, #0<br>
-; THUMB: {{(movw r1, :lower16:_?bar0)|(ldr.n r1, .LCPI)}}<br>
-; THUMB: {{(movt r1, :upper16:_?bar0)|(ldr r1, \[r1\])}}<br>
-; THUMB: blx r1<br>
+; ARM: @foo3<br>
+; ARM: {{(movw r[0-9]+, :lower16:_?bar0)|(ldr r[0-9]+, .LCPI)}}<br>
+; ARM: {{(movt r[0-9]+, :upper16:_?bar0)|(ldr r[0-9]+, \[r[0-9]+\])}}<br>
+; ARM: movw {{r[0-9]+}}, #0<br>
+; ARM: blx {{r[0-9]+}}<br>
+; THUMB: {{(movw r[0-9]+, :lower16:_?bar0)|(ldr.n r[0-9]+, .LCPI)}}<br>
+; THUMB: {{(movt r[0-9]+, :upper16:_?bar0)|(ldr r[0-9]+, \[r[0-9]+\])}}<br>
+; THUMB: movs {{r[0-9]+}}, #0<br>
+; THUMB: blx {{r[0-9]+}}<br>
%fptr = alloca i32 (i32)*, align 8<br>
store i32 (i32)* @bar0, i32 (i32)** %fptr, align 8<br>
%1 = load i32 (i32)*, i32 (i32)** %fptr, align 8<br>
@@ -171,7 +175,7 @@ define i32 @LibCall(i32 %a, i32 %b) {<br>
entry:<br>
; ARM: LibCall<br>
; ARM: bl {{___udivsi3|__aeabi_uidiv}}<br>
-; ARM-LONG: LibCall<br>
+; ARM-LONG-LABEL: LibCall<br>
<br>
; ARM-LONG-MACHO: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr r2, .LCPI)}}<br>
; ARM-LONG-MACHO: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}}<br>
@@ -183,7 +187,7 @@ entry:<br>
; ARM-LONG: blx r2<br>
; THUMB: LibCall<br>
; THUMB: bl {{___udivsi3|__aeabi_uidiv}}<br>
-; THUMB-LONG: LibCall<br>
+; THUMB-LONG-LABEL: LibCall<br>
; THUMB-LONG: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr.n r2, .LCPI)}}<br>
; THUMB-LONG: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}}<br>
; THUMB-LONG: ldr r2, [r2]<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll Wed Mar 14 14:54:21 2018<br>
@@ -16,10 +16,10 @@ define void @t1() nounwind ssp {<br>
; ARM-LABEL: t1:<br>
; ARM: {{(movw r0, :lower16:_?message1)|(ldr r0, .LCPI)}}<br>
; ARM: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}<br>
-; ARM: add r0, r0, #5<br>
-; ARM: movw r1, #64<br>
-; ARM: movw r2, #10<br>
-; ARM: and r1, r1, #255<br>
+; ARM-DAG: add r0, r0, #5<br>
+; ARM-DAG: movw r1, #64<br>
+; ARM-DAG: movw r2, #10<br>
+; ARM-DAG: and r1, r1, #255<br>
; ARM: bl {{_?}}memset<br>
; ARM-LONG-LABEL: t1:<br>
<br>
@@ -36,8 +36,8 @@ define void @t1() nounwind ssp {<br>
; THUMB: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}<br>
; THUMB: adds r0, #5<br>
; THUMB: movs r1, #64<br>
-; THUMB: movs r2, #10<br>
; THUMB: and r1, r1, #255<br>
+; THUMB: movs r2, #10<br>
; THUMB: bl {{_?}}memset<br>
; THUMB-LONG-LABEL: t1:<br>
; THUMB-LONG: movw r3, :lower16:L_memset$non_lazy_ptr<br>
@@ -62,10 +62,10 @@ define void @t2() nounwind ssp {<br>
<br>
; ARM: add r1, r0, #4<br>
; ARM: add r0, r0, #16<br>
-; ARM: movw r2, #17<br>
; ARM: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill<br>
; ARM: mov r0, r1<br>
; ARM: ldr r1, [sp[[SLOT]]] @ 4-byte Reload<br>
+; ARM: movw r2, #17<br>
; ARM: bl {{_?}}memcpy<br>
; ARM-LONG-LABEL: t2:<br>
<br>
@@ -83,10 +83,10 @@ define void @t2() nounwind ssp {<br>
; THUMB: ldr r0, [r0]<br>
; THUMB: adds r1, r0, #4<br>
; THUMB: adds r0, #16<br>
-; THUMB: movs r2, #17<br>
; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill<br>
; THUMB: mov r0, r1<br>
; THUMB: ldr r1, [sp[[SLOT]]] @ 4-byte Reload<br>
+; THUMB: movs r2, #17<br>
; THUMB: bl {{_?}}memcpy<br>
; THUMB-LONG-LABEL: t2:<br>
; THUMB-LONG: movw r3, :lower16:L_memcpy$non_lazy_ptr<br>
@@ -112,8 +112,8 @@ define void @t3() nounwind ssp {<br>
<br>
; ARM: add r1, r0, #4<br>
; ARM: add r0, r0, #16<br>
-; ARM: movw r2, #10<br>
; ARM: mov r0, r1<br>
+; ARM: movw r2, #10<br>
; ARM: bl {{_?}}memmove<br>
; ARM-LONG-LABEL: t3:<br>
<br>
@@ -131,10 +131,10 @@ define void @t3() nounwind ssp {<br>
; THUMB: ldr r0, [r0]<br>
; THUMB: adds r1, r0, #4<br>
; THUMB: adds r0, #16<br>
-; THUMB: movs r2, #10<br>
; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill<br>
; THUMB: mov r0, r1<br>
; THUMB: ldr r1, [sp[[SLOT]]] @ 4-byte Reload<br>
+; THUMB: movs r2, #10<br>
; THUMB: bl {{_?}}memmove<br>
; THUMB-LONG-LABEL: t3:<br>
; THUMB-LONG: movw r3, :lower16:L_memmove$non_lazy_ptr<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll Wed Mar 14 14:54:21 2018<br>
@@ -6,16 +6,14 @@<br>
define i32 @t1(i1 %c) nounwind readnone {<br>
entry:<br>
; ARM: t1<br>
-; ARM: movw r{{[1-9]}}, #10<br>
; ARM: tst r0, #1<br>
-; ARM: moveq r{{[1-9]}}, #20<br>
-; ARM: mov r0, r{{[1-9]}}<br>
+; ARM: movw r0, #10<br>
+; ARM: moveq r0, #20<br>
; THUMB: t1<br>
-; THUMB: movs r{{[1-9]}}, #10<br>
; THUMB: tst.w r0, #1<br>
+; THUMB: movw r0, #10<br>
; THUMB: it eq<br>
-; THUMB: moveq r{{[1-9]}}, #20<br>
-; THUMB: mov r0, r{{[1-9]}}<br>
+; THUMB: moveq r0, #20<br>
%0 = select i1 %c, i32 10, i32 20<br>
ret i32 %0<br>
}<br>
@@ -26,7 +24,7 @@ entry:<br>
; ARM: tst r0, #1<br>
; ARM: moveq r{{[1-9]}}, #20<br>
; ARM: mov r0, r{{[1-9]}}<br>
-; THUMB: t2<br>
+; THUMB-LABEL: t2<br>
; THUMB: tst.w r0, #1<br>
; THUMB: it eq<br>
; THUMB: moveq r{{[1-9]}}, #20<br>
@@ -54,16 +52,14 @@ entry:<br>
define i32 @t4(i1 %c) nounwind readnone {<br>
entry:<br>
; ARM: t4<br>
-; ARM: mvn r{{[1-9]}}, #9<br>
; ARM: tst r0, #1<br>
-; ARM: mvneq r{{[1-9]}}, #0<br>
-; ARM: mov r0, r{{[1-9]}}<br>
+; ARM: mvn r0, #9<br>
+; ARM: mvneq r0, #0<br>
; THUMB-LABEL: t4<br>
-; THUMB: mvn [[REG:r[1-9]+]], #9<br>
; THUMB: tst.w r0, #1<br>
+; THUMB: mvn r0, #9<br>
; THUMB: it eq<br>
-; THUMB: mvneq [[REG]], #0<br>
-; THUMB: mov r0, [[REG]]<br>
+; THUMB: mvneq r0, #0<br>
%0 = select i1 %c, i32 -10, i32 -1<br>
ret i32 %0<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-vararg.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-vararg.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-vararg.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/fast-isel-vararg.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-vararg.ll Wed Mar 14 14:54:21 2018<br>
@@ -17,23 +17,24 @@ entry:<br>
%4 = load i32, i32* %n, align 4<br>
; ARM: VarArg<br>
; ARM: mov [[FP:r[0-9]+]], sp<br>
-; ARM: sub sp, sp, #32<br>
-; ARM: movw r0, #5<br>
+; ARM: sub sp, sp, #{{(36|40)}}<br>
; ARM: ldr r1, {{\[}}[[FP]], #-4]<br>
; ARM: ldr r2, {{\[}}[[FP]], #-8]<br>
; ARM: ldr r3, {{\[}}[[FP]], #-12]<br>
-; ARM: ldr [[Ra:r[0-9]+]], [sp, #16]<br>
-; ARM: ldr [[Rb:[lr]+[0-9]*]], [sp, #12]<br>
-; ARM: str [[Ra]], [sp]<br>
+; ARM: ldr [[Ra:r[0-9]+]], {{\[}}[[FP]], #-16]<br>
+; ARM: ldr [[Rb:[lr]+[0-9]*]], [sp, #{{(16|20)}}]<br>
+; ARM: movw [[Rc:[lr]+[0-9]*]], #5<br>
+; Ra got spilled<br>
+; ARM: mov r0, [[Rc]]<br>
+; ARM: str {{.*}}, [sp]<br>
; ARM: str [[Rb]], [sp, #4]<br>
; ARM: bl {{_?CallVariadic}}<br>
-; THUMB: sub sp, #32<br>
-; THUMB: movs r0, #5<br>
-; THUMB: ldr r1, [sp, #28]<br>
-; THUMB: ldr r2, [sp, #24]<br>
-; THUMB: ldr r3, [sp, #20]<br>
+; THUMB: sub sp, #{{36}}<br>
+; THUMB: ldr r1, [sp, #32]<br>
+; THUMB: ldr r2, [sp, #28]<br>
+; THUMB: ldr r3, [sp, #24]<br>
+; THUMB: ldr {{[a-z0-9]+}}, [sp, #20]<br>
; THUMB: ldr.w {{[a-z0-9]+}}, [sp, #16]<br>
-; THUMB: ldr.w {{[a-z0-9]+}}, [sp, #12]<br>
; THUMB: str.w {{[a-z0-9]+}}, [sp]<br>
; THUMB: str.w {{[a-z0-9]+}}, [sp, #4]<br>
; THUMB: bl {{_?}}CallVariadic<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/swifterror.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/swifterror.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/swifterror.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/swifterror.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/swifterror.ll Wed Mar 14 14:54:21 2018<br>
@@ -188,11 +188,10 @@ define float @foo_loop(%swift_error** sw<br>
; CHECK-O0: mov r{{.*}}, r8<br>
; CHECK-O0: cmp r{{.*}}, #0<br>
; CHECK-O0: beq<br>
-; CHECK-O0-DAG: movw r{{.*}}, #1<br>
-; CHECK-O0-DAG: mov r{{.*}}, #16<br>
+; CHECK-O0: mov r0, #16<br>
; CHECK-O0: malloc<br>
; CHECK-O0-DAG: mov [[ID:r[0-9]+]], r0<br>
-; CHECK-O0-DAG: ldr [[ID2:r[0-9]+]], [sp{{.*}}]<br>
+; CHECK-O0-DAG: movw [[ID2:.*]], #1<br>
; CHECK-O0: strb [[ID2]], [{{.*}}[[ID]], #8]<br>
; spill r0<br>
; CHECK-O0: str r0, [sp{{.*}}]<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll Wed Mar 14 14:54:21 2018<br>
@@ -163,32 +163,26 @@ declare void @xcccc(i8, i8, i8, i8)<br>
define void @cxcccc() {<br>
; ALL-LABEL: cxcccc:<br>
<br>
- ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88<br>
- ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44<br>
- ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11<br>
- ; ALL-DAG: addiu $[[T3:[0-9]+]], $zero, 33<br>
-<br>
- ; FIXME: We should avoid the unnecessary spill/reload here.<br>
-<br>
- ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T0]], 24<br>
- ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24<br>
- ; 32R1-DAG: sw $4, 16($sp)<br>
- ; 32R1-DAG: move $4, $[[T5]]<br>
- ; 32R1-DAG: sll $[[T6:[0-9]+]], $[[T1]], 24<br>
- ; 32R1-DAG: sra $5, $[[T6]], 24<br>
- ; 32R1-DAG: sll $[[T7:[0-9]+]], $[[T2]], 24<br>
- ; 32R1-DAG: sra $6, $[[T7]], 24<br>
- ; 32R1: lw $[[T8:[0-9]+]], 16($sp)<br>
- ; 32R1: sll $[[T9:[0-9]+]], $[[T8]], 24<br>
- ; 32R1: sra $7, $[[T9]], 24<br>
-<br>
- ; 32R2-DAG: seb $[[T4:[0-9]+]], $[[T0]]<br>
- ; 32R2-DAG: sw $4, 16($sp)<br>
- ; 32R2-DAG: move $4, $[[T4]]<br>
- ; 32R2-DAG: seb $5, $[[T1]]<br>
- ; 32R2-DAG: seb $6, $[[T2]]<br>
- ; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp)<br>
- ; 32R2: seb $7, $[[T5]]<br>
+ ; ALL: addiu $[[R:[0-9]+]], $zero, 88<br>
+ ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24<br>
+ ; 32R1: sra $4, $[[R]], 24<br>
+ ; 32R2: seb $4, $[[R]]<br>
+ ; ALL: addiu $[[R:[0-9]+]], $zero, 44<br>
+ ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24<br>
+ ; 32R1: sra $5, $[[R]], 24<br>
+ ; 32R2: seb $5, $[[R]]<br>
+ ; ALL: addiu $[[R:[0-9]+]], $zero, 11<br>
+ ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24<br>
+ ; 32R1: sra $6, $[[R]], 24<br>
+ ; 32R2: seb $6, $[[R]]<br>
+ ; ALL: addiu $[[R:[0-9]+]], $zero, 33<br>
+ ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24<br>
+ ; 32R1: sra $7, $[[R]], 24<br>
+ ; 32R2: seb $7, $[[R]]<br>
+<br>
+ ; ALL: lw $25, %got(xcccc)($2)<br>
+ ; ALL: jalr $25<br>
+ ; ALL: jr $ra<br>
call void @xcccc(i8 88, i8 44, i8 11, i8 33)<br>
ret void<br>
}<br>
@@ -198,32 +192,27 @@ declare void @xhhhh(i16, i16, i16, i16)<br>
define void @cxhhhh() {<br>
; ALL-LABEL: cxhhhh:<br>
<br>
- ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88<br>
- ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44<br>
- ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11<br>
- ; ALL-DAG: addiu $[[T3:[0-9]+]], $zero, 33<br>
-<br>
- ; FIXME: We should avoid the unnecessary spill/reload here.<br>
-<br>
- ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T0]], 16<br>
- ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16<br>
- ; 32R1-DAG: sw $4, 16($sp)<br>
- ; 32R1-DAG: move $4, $[[T5]]<br>
- ; 32R1-DAG: sll $[[T6:[0-9]+]], $[[T1]], 16<br>
- ; 32R1-DAG: sra $5, $[[T6]], 16<br>
- ; 32R1-DAG: sll $[[T7:[0-9]+]], $[[T2]], 16<br>
- ; 32R1-DAG: sra $6, $[[T7]], 16<br>
- ; 32R1: lw $[[T8:[0-9]+]], 16($sp)<br>
- ; 32R1: sll $[[T9:[0-9]+]], $[[T8]], 16<br>
- ; 32R1: sra $7, $[[T9]], 16<br>
-<br>
- ; 32R2-DAG: seh $[[T4:[0-9]+]], $[[T0]]<br>
- ; 32R2-DAG: sw $4, 16($sp)<br>
- ; 32R2-DAG: move $4, $[[T4]]<br>
- ; 32R2-DAG: seh $5, $[[T1]]<br>
- ; 32R2-DAG: seh $6, $[[T2]]<br>
- ; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp)<br>
- ; 32R2: seh $7, $[[T5]]<br>
+ ; ALL: addiu $[[R:[0-9]+]], $zero, 88<br>
+ ; 32R1: sll $[[R]], $[[R]], 16<br>
+ ; 32R1: sra $4, $[[R]], 16<br>
+ ; 32R2: seh $4, $[[R]]<br>
+ ; ALL: addiu $[[R:[0-9]+]], $zero, 44<br>
+ ; 32R1: sll $[[R]], $[[R]], 16<br>
+ ; 32R1: sra $5, $[[R]], 16<br>
+ ; 32R2: seh $5, $[[R]]<br>
+ ; ALL: addiu $[[R:[0-9]+]], $zero, 11<br>
+ ; 32R1: sll $[[R]], $[[R]], 16<br>
+ ; 32R1: sra $6, $[[R]], 16<br>
+ ; 32R2: seh $6, $[[R]]<br>
+ ; ALL: addiu $[[R:[0-9]+]], $zero, 33<br>
+ ; 32R1: sll $[[R]], $[[R]], 16<br>
+ ; 32R1: sra $7, $[[R]], 16<br>
+ ; 32R2: seh $7, $[[R]]<br>
+<br>
+ ; ALL: lw $25, %got(xhhhh)($2)<br>
+ ; ALL: jalr $25<br>
+ ; ALL: jr $ra<br>
+<br>
call void @xhhhh(i16 88, i16 44, i16 11, i16 33)<br>
ret void<br>
}<br>
@@ -437,13 +426,13 @@ define void @cxiff() {<br>
; ALL-LABEL: cxiff:<br>
<br>
; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
- ; ALL-DAG: addiu $4, $zero, 12239<br>
; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17526<br>
; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 55706<br>
; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]<br>
; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 16543<br>
; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 65326<br>
; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]<br>
+ ; ALL-DAG: addiu $4, $zero, 12239<br>
; ALL-DAG: mfc1 $5, $f[[REGF0_3]]<br>
; ALL-DAG: mfc1 $6, $f[[REGF1_3]]<br>
; ALL-DAG: lw $25, %got(xiff)($[[REG_GP]])<br>
@@ -481,11 +470,11 @@ define void @cxifif() {<br>
; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17527<br>
; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 2015<br>
; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]<br>
- ; ALL-DAG: addiu $6, $zero, 9991<br>
; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17802<br>
; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 58470<br>
; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]<br>
; ALL-DAG: mfc1 $5, $f[[REGF0_3]]<br>
+ ; ALL-DAG: addiu $6, $zero, 9991<br>
; ALL-DAG: mfc1 $7, $f[[REGF1_3]]<br>
; ALL-DAG: lw $25, %got(xifif)($[[REG_GP]])<br>
; ALL: jalr $25<br>
@@ -500,16 +489,16 @@ define void @cxiffi() {<br>
; ALL-LABEL: cxiffi:<br>
<br>
; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
- ; ALL-DAG: addiu $4, $zero, 45<br>
; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 16307<br>
; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 13107<br>
; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]<br>
; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17529<br>
; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 39322<br>
; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]<br>
- ; ALL-DAG: addiu $7, $zero, 234<br>
+ ; ALL-DAG: addiu $4, $zero, 45<br>
; ALL-DAG: mfc1 $5, $f[[REGF0_3]]<br>
; ALL-DAG: mfc1 $6, $f[[REGF1_3]]<br>
+ ; ALL-DAG: addiu $7, $zero, 234<br>
; ALL-DAG: lw $25, %got(xiffi)($[[REG_GP]])<br>
; ALL: jalr $25<br>
call void @xiffi(i32 45, float 0x3FF6666660000000,<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestore.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestore.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestore.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestore.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestore.ll Wed Mar 14 14:54:21 2018<br>
@@ -9,8 +9,8 @@<br>
define void @foo() {<br>
entry:<br>
store i32 12345, i32* @abcd, align 4<br>
-; CHECK: addiu $[[REG1:[0-9]+]], $zero, 12345<br>
; CHECK: lw $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}})<br>
+; CHECK: addiu $[[REG1:[0-9]+]], $zero, 12345<br>
; CHECK: sw $[[REG1]], 0($[[REG2]])<br>
ret void<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestorei.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestorei.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestorei.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestorei.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestorei.ll Wed Mar 14 14:54:21 2018<br>
@@ -10,8 +10,8 @@ define void @si2_1() #0 {<br>
entry:<br>
store i32 32767, i32* @ijk, align 4<br>
; CHECK: .ent si2_1<br>
-; CHECK: addiu $[[REG1:[0-9]+]], $zero, 32767<br>
; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})<br>
+; CHECK: addiu $[[REG1:[0-9]+]], $zero, 32767<br>
; CHECK: sw $[[REG1]], 0($[[REG2]])<br>
<br>
ret void<br>
@@ -34,8 +34,8 @@ define void @ui2_1() #0 {<br>
entry:<br>
store i32 65535, i32* @ijk, align 4<br>
; CHECK: .ent ui2_1<br>
-; CHECK: ori $[[REG1:[0-9]+]], $zero, 65535<br>
; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})<br>
+; CHECK: ori $[[REG1:[0-9]+]], $zero, 65535<br>
; CHECK: sw $[[REG1]], 0($[[REG2]])<br>
ret void<br>
}<br>
@@ -45,8 +45,8 @@ define void @ui4_1() #0 {<br>
entry:<br>
store i32 983040, i32* @ijk, align 4<br>
; CHECK: .ent ui4_1<br>
-; CHECK: lui $[[REG1:[0-9]+]], 15<br>
; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})<br>
+; CHECK: lui $[[REG1:[0-9]+]], 15<br>
; CHECK: sw $[[REG1]], 0($[[REG2]])<br>
ret void<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-mask-zext-bugfix.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-mask-zext-bugfix.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-mask-zext-bugfix.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512-mask-zext-bugfix.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-mask-zext-bugfix.ll Wed Mar 14 14:54:21 2018<br>
@@ -17,25 +17,21 @@ declare i32 @check_mask16(i16 zeroext %r<br>
define void @test_xmm(i32 %shift, i32 %mulp, <2 x i64> %a,i8* %arraydecay,i8* %fname){<br>
; CHECK-LABEL: test_xmm:<br>
; CHECK: ## %bb.0:<br>
-; CHECK-NEXT: subq $72, %rsp<br>
-; CHECK-NEXT: .cfi_def_cfa_offset 80<br>
-; CHECK-NEXT: movl $4, %eax<br>
+; CHECK-NEXT: subq $56, %rsp<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 64<br>
; CHECK-NEXT: vpmovw2m %xmm0, %k0<br>
; CHECK-NEXT: movl $2, %esi<br>
-; CHECK-NEXT: movl $8, %edi<br>
-; CHECK-NEXT: movl %edi, {{[0-9]+}}(%rsp) ## 4-byte Spill<br>
+; CHECK-NEXT: movl $8, %eax<br>
; CHECK-NEXT: movq %rdx, %rdi<br>
-; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %r8d ## 4-byte Reload<br>
; CHECK-NEXT: movq %rdx, {{[0-9]+}}(%rsp) ## 8-byte Spill<br>
-; CHECK-NEXT: movl %r8d, %edx<br>
+; CHECK-NEXT: movl %eax, %edx<br>
+; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill<br>
; CHECK-NEXT: movq %rcx, {{[0-9]+}}(%rsp) ## 8-byte Spill<br>
; CHECK-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp) ## 16-byte Spill<br>
-; CHECK-NEXT: movl %eax, {{[0-9]+}}(%rsp) ## 4-byte Spill<br>
-; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill<br>
; CHECK-NEXT: callq _calc_expected_mask_val<br>
; CHECK-NEXT: movl %eax, %edx<br>
-; CHECK-NEXT: movw %dx, %r9w<br>
-; CHECK-NEXT: movzwl %r9w, %esi<br>
+; CHECK-NEXT: movw %dx, %r8w<br>
+; CHECK-NEXT: movzwl %r8w, %esi<br>
; CHECK-NEXT: kmovw {{[0-9]+}}(%rsp), %k0 ## 2-byte Reload<br>
; CHECK-NEXT: kmovb %k0, %edi<br>
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx ## 8-byte Reload<br>
@@ -45,25 +41,26 @@ define void @test_xmm(i32 %shift, i32 %m<br>
; CHECK-NEXT: vpmovd2m %xmm0, %k0<br>
; CHECK-NEXT: kmovq %k0, %k1<br>
; CHECK-NEXT: kmovd %k0, %esi<br>
-; CHECK-NEXT: movb %sil, %r10b<br>
-; CHECK-NEXT: movzbl %r10b, %esi<br>
-; CHECK-NEXT: movw %si, %r9w<br>
+; CHECK-NEXT: movb %sil, %r9b<br>
+; CHECK-NEXT: movzbl %r9b, %esi<br>
+; CHECK-NEXT: movw %si, %r8w<br>
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdi ## 8-byte Reload<br>
-; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %esi ## 4-byte Reload<br>
+; CHECK-NEXT: movl $4, %esi<br>
+; CHECK-NEXT: movl %esi, {{[0-9]+}}(%rsp) ## 4-byte Spill<br>
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %edx ## 4-byte Reload<br>
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%rsp) ## 4-byte Spill<br>
; CHECK-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ## 2-byte Spill<br>
-; CHECK-NEXT: movw %r9w, {{[0-9]+}}(%rsp) ## 2-byte Spill<br>
+; CHECK-NEXT: movw %r8w, {{[0-9]+}}(%rsp) ## 2-byte Spill<br>
; CHECK-NEXT: callq _calc_expected_mask_val<br>
-; CHECK-NEXT: movw %ax, %r9w<br>
-; CHECK-NEXT: movw {{[0-9]+}}(%rsp), %r11w ## 2-byte Reload<br>
-; CHECK-NEXT: movzwl %r11w, %edi<br>
-; CHECK-NEXT: movzwl %r9w, %esi<br>
+; CHECK-NEXT: movw %ax, %r8w<br>
+; CHECK-NEXT: movw {{[0-9]+}}(%rsp), %r10w ## 2-byte Reload<br>
+; CHECK-NEXT: movzwl %r10w, %edi<br>
+; CHECK-NEXT: movzwl %r8w, %esi<br>
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx ## 8-byte Reload<br>
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx ## 8-byte Reload<br>
; CHECK-NEXT: callq _check_mask16<br>
-; CHECK-NEXT: movl %eax, {{[0-9]+}}(%rsp) ## 4-byte Spill<br>
-; CHECK-NEXT: addq $72, %rsp<br>
+; CHECK-NEXT: movl %eax, (%rsp) ## 4-byte Spill<br>
+; CHECK-NEXT: addq $56, %rsp<br>
; CHECK-NEXT: retq<br>
%d2 = bitcast <2 x i64> %a to <8 x i16><br>
%m2 = call i8 @llvm.x86.avx512.cvtw2mask.128(<8 x i16> %d2)<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll Wed Mar 14 14:54:21 2018<br>
@@ -24,11 +24,11 @@ define i16 @test__tzcnt_u16(i16 %a0) {<br>
;<br>
; X64-LABEL: test__tzcnt_u16:<br>
; X64: # %bb.0:<br>
-; X64-NEXT: movw $16, %cx<br>
-; X64-NEXT: movzwl %di, %edx<br>
-; X64-NEXT: tzcntw %dx, %ax<br>
-; X64-NEXT: cmpl $0, %edx<br>
-; X64-NEXT: cmovew %cx, %ax<br>
+; X64-NEXT: movzwl %di, %eax<br>
+; X64-NEXT: tzcntw %ax, %cx<br>
+; X64-NEXT: cmpl $0, %eax<br>
+; X64-NEXT: movw $16, %ax<br>
+; X64-NEXT: cmovnew %cx, %ax<br>
; X64-NEXT: retq<br>
%zext = zext i16 %a0 to i32<br>
%cmp = icmp ne i32 %zext, 0<br>
@@ -146,9 +146,9 @@ define i32 @test__tzcnt_u32(i32 %a0) {<br>
;<br>
; X64-LABEL: test__tzcnt_u32:<br>
; X64: # %bb.0:<br>
-; X64-NEXT: movl $32, %ecx<br>
-; X64-NEXT: tzcntl %edi, %eax<br>
-; X64-NEXT: cmovbl %ecx, %eax<br>
+; X64-NEXT: tzcntl %edi, %ecx<br>
+; X64-NEXT: movl $32, %eax<br>
+; X64-NEXT: cmovael %ecx, %eax<br>
; X64-NEXT: retq<br>
%cmp = icmp ne i32 %a0, 0<br>
%cttz = call i32 @llvm.cttz.i32(i32 %a0, i1 true)<br>
@@ -176,11 +176,11 @@ define i16 @test_tzcnt_u16(i16 %a0) {<br>
;<br>
; X64-LABEL: test_tzcnt_u16:<br>
; X64: # %bb.0:<br>
-; X64-NEXT: movw $16, %cx<br>
-; X64-NEXT: movzwl %di, %edx<br>
-; X64-NEXT: tzcntw %dx, %ax<br>
-; X64-NEXT: cmpl $0, %edx<br>
-; X64-NEXT: cmovew %cx, %ax<br>
+; X64-NEXT: movzwl %di, %eax<br>
+; X64-NEXT: tzcntw %ax, %cx<br>
+; X64-NEXT: cmpl $0, %eax<br>
+; X64-NEXT: movw $16, %ax<br>
+; X64-NEXT: cmovnew %cx, %ax<br>
; X64-NEXT: retq<br>
%zext = zext i16 %a0 to i32<br>
%cmp = icmp ne i32 %zext, 0<br>
@@ -311,9 +311,9 @@ define i32 @test_tzcnt_u32(i32 %a0) {<br>
;<br>
; X64-LABEL: test_tzcnt_u32:<br>
; X64: # %bb.0:<br>
-; X64-NEXT: movl $32, %ecx<br>
-; X64-NEXT: tzcntl %edi, %eax<br>
-; X64-NEXT: cmovbl %ecx, %eax<br>
+; X64-NEXT: tzcntl %edi, %ecx<br>
+; X64-NEXT: movl $32, %eax<br>
+; X64-NEXT: cmovael %ecx, %eax<br>
; X64-NEXT: retq<br>
%cmp = icmp ne i32 %a0, 0<br>
%cttz = call i32 @llvm.cttz.i32(i32 %a0, i1 true)<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-call-cleanup.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-call-cleanup.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-call-cleanup.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/fast-isel-call-cleanup.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/fast-isel-call-cleanup.ll Wed Mar 14 14:54:21 2018<br>
@@ -6,10 +6,8 @@ entry:<br>
%call = call i32 @targetfn(i32 42)<br>
ret void<br>
; CHECK-LABEL: fastiselcall:<br>
-; Local value area is still there:<br>
-; CHECK: movl $42, {{%[a-z]+}}<br>
-; Fast-ISel's arg mov is not here:<br>
-; CHECK-NOT: movl $42, (%esp)<br>
+; FastISel's local value code was dead, so it's gone.<br>
+; CHECK-NOT: movl $42,<br>
; SDag-ISel's arg mov:<br>
; CHECK: movabsq $_targetfn, %[[REG:[^ ]*]]<br>
; CHECK: movl $42, %edi<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-store.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-store.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-store.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/fast-isel-store.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/fast-isel-store.ll Wed Mar 14 14:54:21 2018<br>
@@ -58,11 +58,11 @@ define <4 x i32> @test_store_4xi32(<4 x<br>
; SSE64-NEXT: movdqu %xmm0, (%eax)<br>
; SSE64-NEXT: retl<br>
;<br>
-; AVXONLY32-LABEL: test_store_4xi32:<br>
-; AVXONLY32: # %bb.0:<br>
-; AVXONLY32-NEXT: vpaddd %xmm1, %xmm0, %xmm0<br>
-; AVXONLY32-NEXT: vmovdqu %xmm0, (%rdi)<br>
-; AVXONLY32-NEXT: retq<br>
+; AVX32-LABEL: test_store_4xi32:<br>
+; AVX32: # %bb.0:<br>
+; AVX32-NEXT: vpaddd %xmm1, %xmm0, %xmm0<br>
+; AVX32-NEXT: vmovdqu %xmm0, (%rdi)<br>
+; AVX32-NEXT: retq<br>
;<br>
; AVX64-LABEL: test_store_4xi32:<br>
; AVX64: # %bb.0:<br>
@@ -70,18 +70,6 @@ define <4 x i32> @test_store_4xi32(<4 x<br>
; AVX64-NEXT: vpaddd %xmm1, %xmm0, %xmm0<br>
; AVX64-NEXT: vmovdqu %xmm0, (%eax)<br>
; AVX64-NEXT: retl<br>
-;<br>
-; KNL32-LABEL: test_store_4xi32:<br>
-; KNL32: # %bb.0:<br>
-; KNL32-NEXT: vpaddd %xmm1, %xmm0, %xmm0<br>
-; KNL32-NEXT: vmovdqu %xmm0, (%rdi)<br>
-; KNL32-NEXT: retq<br>
-;<br>
-; SKX32-LABEL: test_store_4xi32:<br>
-; SKX32: # %bb.0:<br>
-; SKX32-NEXT: vpaddd %xmm1, %xmm0, %xmm0<br>
-; SKX32-NEXT: vmovdqu %xmm0, (%rdi)<br>
-; SKX32-NEXT: retq<br>
%foo = add <4 x i32> %value, %value2 ; to force integer type on store<br>
store <4 x i32> %foo, <4 x i32>* %addr, align 1<br>
ret <4 x i32> %foo<br>
@@ -101,11 +89,11 @@ define <4 x i32> @test_store_4xi32_align<br>
; SSE64-NEXT: movdqa %xmm0, (%eax)<br>
; SSE64-NEXT: retl<br>
;<br>
-; AVXONLY32-LABEL: test_store_4xi32_aligned:<br>
-; AVXONLY32: # %bb.0:<br>
-; AVXONLY32-NEXT: vpaddd %xmm1, %xmm0, %xmm0<br>
-; AVXONLY32-NEXT: vmovdqa %xmm0, (%rdi)<br>
-; AVXONLY32-NEXT: retq<br>
+; AVX32-LABEL: test_store_4xi32_aligned:<br>
+; AVX32: # %bb.0:<br>
+; AVX32-NEXT: vpaddd %xmm1, %xmm0, %xmm0<br>
+; AVX32-NEXT: vmovdqa %xmm0, (%rdi)<br>
+; AVX32-NEXT: retq<br>
;<br>
; AVX64-LABEL: test_store_4xi32_aligned:<br>
; AVX64: # %bb.0:<br>
@@ -113,18 +101,6 @@ define <4 x i32> @test_store_4xi32_align<br>
; AVX64-NEXT: vpaddd %xmm1, %xmm0, %xmm0<br>
; AVX64-NEXT: vmovdqa %xmm0, (%eax)<br>
; AVX64-NEXT: retl<br>
-;<br>
-; KNL32-LABEL: test_store_4xi32_aligned:<br>
-; KNL32: # %bb.0:<br>
-; KNL32-NEXT: vpaddd %xmm1, %xmm0, %xmm0<br>
-; KNL32-NEXT: vmovdqa %xmm0, (%rdi)<br>
-; KNL32-NEXT: retq<br>
-;<br>
-; SKX32-LABEL: test_store_4xi32_aligned:<br>
-; SKX32: # %bb.0:<br>
-; SKX32-NEXT: vpaddd %xmm1, %xmm0, %xmm0<br>
-; SKX32-NEXT: vmovdqa %xmm0, (%rdi)<br>
-; SKX32-NEXT: retq<br>
%foo = add <4 x i32> %value, %value2 ; to force integer type on store<br>
store <4 x i32> %foo, <4 x i32>* %addr, align 16<br>
ret <4 x i32> %foo<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/inreg.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inreg.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inreg.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/inreg.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/inreg.ll Wed Mar 14 14:54:21 2018<br>
@@ -20,7 +20,7 @@ entry:<br>
<br>
; FAST-LABEL: g1:<br>
; FAST: subl $[[AMT:.*]], %esp<br>
- ; FAST-NEXT: leal 8(%esp), %eax<br>
+ ; FAST-NEXT: leal 16(%esp), %eax<br>
; FAST-NEXT: movl $41, %edx<br>
; FAST-NEXT: movl $42, %ecx<br>
; FAST: $43, (%esp)<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/pr32241.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32241.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32241.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/pr32241.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/pr32241.ll Wed Mar 14 14:54:21 2018<br>
@@ -4,19 +4,16 @@<br>
define i32 @_Z3foov() {<br>
; CHECK-LABEL: _Z3foov:<br>
; CHECK: # %bb.0: # %entry<br>
-; CHECK-NEXT: pushl %esi<br>
-; CHECK-NEXT: .cfi_def_cfa_offset 8<br>
; CHECK-NEXT: subl $16, %esp<br>
-; CHECK-NEXT: .cfi_def_cfa_offset 24<br>
-; CHECK-NEXT: .cfi_offset %esi, -8<br>
-; CHECK-NEXT: movb $1, %al<br>
+; CHECK-NEXT: .cfi_def_cfa_offset 20<br>
; CHECK-NEXT: movw $10959, {{[0-9]+}}(%esp) # imm = 0x2ACF<br>
; CHECK-NEXT: movw $-15498, {{[0-9]+}}(%esp) # imm = 0xC376<br>
; CHECK-NEXT: movw $19417, {{[0-9]+}}(%esp) # imm = 0x4BD9<br>
-; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ecx<br>
+; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax<br>
; CHECK-NEXT: cmpw $0, {{[0-9]+}}(%esp)<br>
-; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill<br>
-; CHECK-NEXT: movb %al, {{[0-9]+}}(%esp) # 1-byte Spill<br>
+; CHECK-NEXT: movb $1, %cl<br>
+; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill<br>
+; CHECK-NEXT: movb %cl, {{[0-9]+}}(%esp) # 1-byte Spill<br>
; CHECK-NEXT: jne .LBB0_2<br>
; CHECK-NEXT: # %bb.1: # %lor.rhs<br>
; CHECK-NEXT: xorl %eax, %eax<br>
@@ -25,17 +22,17 @@ define i32 @_Z3foov() {<br>
; CHECK-NEXT: jmp .LBB0_2<br>
; CHECK-NEXT: .LBB0_2: # %lor.end<br>
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al # 1-byte Reload<br>
-; CHECK-NEXT: movb $1, %cl<br>
; CHECK-NEXT: andb $1, %al<br>
-; CHECK-NEXT: movzbl %al, %edx<br>
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi # 4-byte Reload<br>
-; CHECK-NEXT: cmpl %edx, %esi<br>
+; CHECK-NEXT: movzbl %al, %ecx<br>
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx # 4-byte Reload<br>
+; CHECK-NEXT: cmpl %ecx, %edx<br>
; CHECK-NEXT: setl %al<br>
; CHECK-NEXT: andb $1, %al<br>
-; CHECK-NEXT: movzbl %al, %edx<br>
-; CHECK-NEXT: xorl $-1, %edx<br>
-; CHECK-NEXT: cmpl $0, %edx<br>
-; CHECK-NEXT: movb %cl, {{[0-9]+}}(%esp) # 1-byte Spill<br>
+; CHECK-NEXT: movzbl %al, %ecx<br>
+; CHECK-NEXT: xorl $-1, %ecx<br>
+; CHECK-NEXT: cmpl $0, %ecx<br>
+; CHECK-NEXT: movb $1, %al<br>
+; CHECK-NEXT: movb %al, {{[0-9]+}}(%esp) # 1-byte Spill<br>
; CHECK-NEXT: jne .LBB0_4<br>
; CHECK-NEXT: # %bb.3: # %lor.rhs4<br>
; CHECK-NEXT: xorl %eax, %eax<br>
@@ -50,7 +47,6 @@ define i32 @_Z3foov() {<br>
; CHECK-NEXT: movw %dx, {{[0-9]+}}(%esp)<br>
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax<br>
; CHECK-NEXT: addl $16, %esp<br>
-; CHECK-NEXT: popl %esi<br>
; CHECK-NEXT: retl<br>
entry:<br>
%aa = alloca i16, align 2<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/pr32284.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32284.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32284.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/pr32284.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/pr32284.ll Wed Mar 14 14:54:21 2018<br>
@@ -121,10 +121,10 @@ entry:<br>
define void @f1() {<br>
; X86-O0-LABEL: f1:<br>
; X86-O0: # %bb.0: # %entry<br>
-; X86-O0-NEXT: movabsq $8381627093, %rax # imm = 0x1F3957AD5<br>
-; X86-O0-NEXT: movslq var_5, %rcx<br>
-; X86-O0-NEXT: addq %rax, %rcx<br>
-; X86-O0-NEXT: cmpq $0, %rcx<br>
+; X86-O0-NEXT: movslq var_5, %rax<br>
+; X86-O0-NEXT: movabsq $8381627093, %rcx # imm = 0x1F3957AD5<br>
+; X86-O0-NEXT: addq %rcx, %rax<br>
+; X86-O0-NEXT: cmpq $0, %rax<br>
; X86-O0-NEXT: setne %dl<br>
; X86-O0-NEXT: andb $1, %dl<br>
; X86-O0-NEXT: movb %dl, -{{[0-9]+}}(%rsp)<br>
@@ -308,30 +308,30 @@ entry:<br>
define void @f2() {<br>
; X86-O0-LABEL: f2:<br>
; X86-O0: # %bb.0: # %entry<br>
-; X86-O0-NEXT: # implicit-def: $rax<br>
-; X86-O0-NEXT: movzbl var_7, %ecx<br>
+; X86-O0-NEXT: movzbl var_7, %eax<br>
; X86-O0-NEXT: cmpb $0, var_7<br>
-; X86-O0-NEXT: setne %dl<br>
-; X86-O0-NEXT: xorb $-1, %dl<br>
-; X86-O0-NEXT: andb $1, %dl<br>
-; X86-O0-NEXT: movzbl %dl, %esi<br>
-; X86-O0-NEXT: xorl %esi, %ecx<br>
-; X86-O0-NEXT: movw %cx, %di<br>
-; X86-O0-NEXT: movw %di, -{{[0-9]+}}(%rsp)<br>
-; X86-O0-NEXT: movzbl var_7, %ecx<br>
-; X86-O0-NEXT: movw %cx, %di<br>
-; X86-O0-NEXT: cmpw $0, %di<br>
-; X86-O0-NEXT: setne %dl<br>
-; X86-O0-NEXT: xorb $-1, %dl<br>
-; X86-O0-NEXT: andb $1, %dl<br>
-; X86-O0-NEXT: movzbl %dl, %ecx<br>
-; X86-O0-NEXT: movzbl var_7, %esi<br>
-; X86-O0-NEXT: cmpl %esi, %ecx<br>
-; X86-O0-NEXT: sete %dl<br>
-; X86-O0-NEXT: andb $1, %dl<br>
-; X86-O0-NEXT: movzbl %dl, %ecx<br>
-; X86-O0-NEXT: movw %cx, %di<br>
-; X86-O0-NEXT: movw %di, (%rax)<br>
+; X86-O0-NEXT: setne %cl<br>
+; X86-O0-NEXT: xorb $-1, %cl<br>
+; X86-O0-NEXT: andb $1, %cl<br>
+; X86-O0-NEXT: movzbl %cl, %edx<br>
+; X86-O0-NEXT: xorl %edx, %eax<br>
+; X86-O0-NEXT: movw %ax, %si<br>
+; X86-O0-NEXT: movw %si, -{{[0-9]+}}(%rsp)<br>
+; X86-O0-NEXT: movzbl var_7, %eax<br>
+; X86-O0-NEXT: movw %ax, %si<br>
+; X86-O0-NEXT: cmpw $0, %si<br>
+; X86-O0-NEXT: setne %cl<br>
+; X86-O0-NEXT: xorb $-1, %cl<br>
+; X86-O0-NEXT: andb $1, %cl<br>
+; X86-O0-NEXT: movzbl %cl, %eax<br>
+; X86-O0-NEXT: movzbl var_7, %edx<br>
+; X86-O0-NEXT: cmpl %edx, %eax<br>
+; X86-O0-NEXT: sete %cl<br>
+; X86-O0-NEXT: andb $1, %cl<br>
+; X86-O0-NEXT: movzbl %cl, %eax<br>
+; X86-O0-NEXT: movw %ax, %si<br>
+; X86-O0-NEXT: # implicit-def: $rdi<br>
+; X86-O0-NEXT: movw %si, (%rdi)<br>
; X86-O0-NEXT: retq<br>
;<br>
; X64-LABEL: f2:<br>
@@ -353,41 +353,37 @@ define void @f2() {<br>
;<br>
; 686-O0-LABEL: f2:<br>
; 686-O0: # %bb.0: # %entry<br>
-; 686-O0-NEXT: pushl %edi<br>
-; 686-O0-NEXT: .cfi_def_cfa_offset 8<br>
; 686-O0-NEXT: pushl %esi<br>
-; 686-O0-NEXT: .cfi_def_cfa_offset 12<br>
+; 686-O0-NEXT: .cfi_def_cfa_offset 8<br>
; 686-O0-NEXT: subl $2, %esp<br>
-; 686-O0-NEXT: .cfi_def_cfa_offset 14<br>
-; 686-O0-NEXT: .cfi_offset %esi, -12<br>
-; 686-O0-NEXT: .cfi_offset %edi, -8<br>
-; 686-O0-NEXT: # implicit-def: $eax<br>
-; 686-O0-NEXT: movzbl var_7, %ecx<br>
+; 686-O0-NEXT: .cfi_def_cfa_offset 10<br>
+; 686-O0-NEXT: .cfi_offset %esi, -8<br>
+; 686-O0-NEXT: movzbl var_7, %eax<br>
; 686-O0-NEXT: cmpb $0, var_7<br>
-; 686-O0-NEXT: setne %dl<br>
-; 686-O0-NEXT: xorb $-1, %dl<br>
-; 686-O0-NEXT: andb $1, %dl<br>
-; 686-O0-NEXT: movzbl %dl, %esi<br>
-; 686-O0-NEXT: xorl %esi, %ecx<br>
-; 686-O0-NEXT: movw %cx, %di<br>
-; 686-O0-NEXT: movw %di, (%esp)<br>
-; 686-O0-NEXT: movzbl var_7, %ecx<br>
-; 686-O0-NEXT: movw %cx, %di<br>
-; 686-O0-NEXT: cmpw $0, %di<br>
-; 686-O0-NEXT: setne %dl<br>
-; 686-O0-NEXT: xorb $-1, %dl<br>
-; 686-O0-NEXT: andb $1, %dl<br>
-; 686-O0-NEXT: movzbl %dl, %ecx<br>
-; 686-O0-NEXT: movzbl var_7, %esi<br>
-; 686-O0-NEXT: cmpl %esi, %ecx<br>
-; 686-O0-NEXT: sete %dl<br>
-; 686-O0-NEXT: andb $1, %dl<br>
-; 686-O0-NEXT: movzbl %dl, %ecx<br>
-; 686-O0-NEXT: movw %cx, %di<br>
-; 686-O0-NEXT: movw %di, (%eax)<br>
+; 686-O0-NEXT: setne %cl<br>
+; 686-O0-NEXT: xorb $-1, %cl<br>
+; 686-O0-NEXT: andb $1, %cl<br>
+; 686-O0-NEXT: movzbl %cl, %edx<br>
+; 686-O0-NEXT: xorl %edx, %eax<br>
+; 686-O0-NEXT: movw %ax, %si<br>
+; 686-O0-NEXT: movw %si, (%esp)<br>
+; 686-O0-NEXT: movzbl var_7, %eax<br>
+; 686-O0-NEXT: movw %ax, %si<br>
+; 686-O0-NEXT: cmpw $0, %si<br>
+; 686-O0-NEXT: setne %cl<br>
+; 686-O0-NEXT: xorb $-1, %cl<br>
+; 686-O0-NEXT: andb $1, %cl<br>
+; 686-O0-NEXT: movzbl %cl, %eax<br>
+; 686-O0-NEXT: movzbl var_7, %edx<br>
+; 686-O0-NEXT: cmpl %edx, %eax<br>
+; 686-O0-NEXT: sete %cl<br>
+; 686-O0-NEXT: andb $1, %cl<br>
+; 686-O0-NEXT: movzbl %cl, %eax<br>
+; 686-O0-NEXT: movw %ax, %si<br>
+; 686-O0-NEXT: # implicit-def: $eax<br>
+; 686-O0-NEXT: movw %si, (%eax)<br>
; 686-O0-NEXT: addl $2, %esp<br>
; 686-O0-NEXT: popl %esi<br>
-; 686-O0-NEXT: popl %edi<br>
; 686-O0-NEXT: retl<br>
;<br>
; 686-LABEL: f2:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/pr32340.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32340.ll?rev=327581&r1=327580&r2=327581&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32340.ll?rev=327581&r1=327580&r2=327581&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/pr32340.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/pr32340.ll Wed Mar 14 14:54:21 2018<br>
@@ -15,31 +15,31 @@ define void @foo() {<br>
; X64: # %bb.0: # %entry<br>
; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: movl %eax, %ecx<br>
-; X64-NEXT: movabsq $-1142377792914660288, %rdx # imm = 0xF02575732E06E440<br>
; X64-NEXT: movw $0, var_825<br>
; X64-NEXT: movzwl var_32, %eax<br>
-; X64-NEXT: movzwl var_901, %esi<br>
-; X64-NEXT: movl %eax, %edi<br>
-; X64-NEXT: xorl %esi, %edi<br>
+; X64-NEXT: movzwl var_901, %edx<br>
; X64-NEXT: movl %eax, %esi<br>
-; X64-NEXT: xorl %edi, %esi<br>
-; X64-NEXT: addl %eax, %esi<br>
-; X64-NEXT: movslq %esi, %r8<br>
-; X64-NEXT: movq %r8, var_826<br>
+; X64-NEXT: xorl %edx, %esi<br>
+; X64-NEXT: movl %eax, %edx<br>
+; X64-NEXT: xorl %esi, %edx<br>
+; X64-NEXT: addl %eax, %edx<br>
+; X64-NEXT: movslq %edx, %rdi<br>
+; X64-NEXT: movq %rdi, var_826<br>
; X64-NEXT: movzwl var_32, %eax<br>
-; X64-NEXT: movl %eax, %r8d<br>
+; X64-NEXT: movl %eax, %edi<br>
; X64-NEXT: movzwl var_901, %eax<br>
; X64-NEXT: xorl $51981, %eax # imm = 0xCB0D<br>
-; X64-NEXT: movslq %eax, %r9<br>
-; X64-NEXT: xorq %rdx, %r9<br>
-; X64-NEXT: movq %r8, %rdx<br>
-; X64-NEXT: xorq %r9, %rdx<br>
-; X64-NEXT: xorq $-1, %rdx<br>
-; X64-NEXT: xorq %rdx, %r8<br>
-; X64-NEXT: movq %r8, %rdx<br>
-; X64-NEXT: orq var_57, %rdx<br>
-; X64-NEXT: orq %rdx, %r8<br>
-; X64-NEXT: movw %r8w, %r10w<br>
+; X64-NEXT: movslq %eax, %r8<br>
+; X64-NEXT: movabsq $-1142377792914660288, %r9 # imm = 0xF02575732E06E440<br>
+; X64-NEXT: xorq %r9, %r8<br>
+; X64-NEXT: movq %rdi, %r9<br>
+; X64-NEXT: xorq %r8, %r9<br>
+; X64-NEXT: xorq $-1, %r9<br>
+; X64-NEXT: xorq %r9, %rdi<br>
+; X64-NEXT: movq %rdi, %r8<br>
+; X64-NEXT: orq var_57, %r8<br>
+; X</blockquote></div>