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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><b>From:</b> qcolombet@apple.com [mailto:qcolombet@apple.com] <br><b>Sent:</b> Wednesday, February 28, 2018 5:20 PM<br><br><o:p></o:p></p><div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><p class=MsoNormal>On Feb 28, 2018, at 11:58 AM, Quentin Colombet via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><br><br><br><o:p></o:p></span></p><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>On Feb 28, 2018, at 8:44 AM,<span class=apple-converted-space> </span><a href="mailto:gberry@codeaurora.org">gberry@codeaurora.org</a><span class=apple-converted-space> </span>wrote:<o:p></o:p></span></p></div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><o:p> </o:p></span></p><div><div><p class=MsoNormal>Hi Quentin,<o:p></o:p></p></div><div><p class=MsoNormal> <o:p></o:p></p></div><div><p class=MsoNormal>I believe there are two issues here:<o:p></o:p></p></div><div><p class=MsoNormal> <o:p></o:p></p></div><ul style='margin-top:0in' type=disc><li class=MsoNormal style='mso-list:l0 level1 lfo1'>Running MachineCopyPropagation for targets with AllowRegisterRenaming set is wasted compile time:<o:p></o:p></li></ul><div style='margin-left:.5in'><p class=MsoNormal>This is true for the COPY forwarding part of MCP, but the original redundant COPY elimination part does not check isRenamable. If we don’t run MCP for targets with AllowRegisterRenaming set to 0, that will potentially cause regressions for those targets since they will lose the redundant COPY elimination that was happening before.<o:p></o:p></p></div></div></blockquote><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>We would indeed lose the redundant COPY elimination, but<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>- It may break some target as it does for us<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>- We only have it for like a week<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>Anyhow, we could keep it unconditionally as long as we fix it for bundles.<o:p></o:p></span></p></div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><br><br><o:p></o:p></span></p><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div style='margin-left:.5in'><p class=MsoNormal> We could skip the COPY forwarding code only for those targets by checking the target property. I considered doing this, but all it really saves is checking the renamable bit on each MachineOperand since it bails out very early. Given that MCP never showed up in any compile-time profiles, I figured this wasn’t worth doing, but if that’s not the case in some custom pipeline I’m happy to work on making this change.<o:p></o:p></p></div><div style='margin-left:.5in'><p class=MsoNormal> <o:p></o:p></p></div><ul style='margin-top:0in' type=disc><li class=MsoNormal style='mso-list:l1 level1 lfo2'>Some targets that use bundles are broken by MCP:<o:p></o:p></li></ul><div style='margin-left:.5in'><p class=MsoNormal>If I recall correctly from discussing this with escha, even the pre-existing redundant COPY elimination part of MCP breaks on these targets.<o:p></o:p></p></div></div></blockquote><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><o:p> </o:p></span></p></div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div style='margin-left:.5in'><p class=MsoNormal> This seems like an independent issue. Presumably the pre-existing MCP pass in addMachineLateOptimization() would also cause problems on these targets?<o:p></o:p></p></div></div></blockquote><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>That’s a good point, we actually have our own copy of </span><span style='font-size:8.5pt;font-family:"Menlo",serif;color:white;background:black'>addMachineLateOptimization</span><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'> where we don’t run it. We could do the same with addOptimizedRegAlloc, you’re right.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>Let me try this way.<o:p></o:p></span></p></div></div></div></blockquote><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Works great. Now remains the question of should we run the full MCP for targets that don’t allow register renaming.<o:p></o:p></p></div><div><p class=MsoNormal>Correctly if I am wrong, but I suspect the overhead to be relatively small (assuming the targets want the other part of MCP), so we should be fine.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Thanks for your follow-up on this.<o:p></o:p></p></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>No problem. I believe the compile time savings from not doing the copy forwarding part of MCP on such targets should be insignificant (at least in the default optimization pipeline).<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><o:p> </o:p></span></p></div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div style='margin-left:.5in'><p class=MsoNormal> Can this be worked around by just disabling MCP for this target by doing something like this in these targets pass config:<o:p></o:p></p></div><div style='margin-left:.5in'><p class=MsoNormal> <o:p></o:p></p></div><div style='margin-left:.5in'><p class=MsoNormal><span style='font-family:"Courier New"'>void BundleTargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {</span><o:p></o:p></p></div><div style='margin-left:1.0in'><p class=MsoNormal><span style='font-family:"Courier New"'> // MCP breaks bundled instructions.</span><o:p></o:p></p></div><div style='margin-left:1.0in'><p class=MsoNormal><span style='font-family:"Courier New"'> disablePass(&MachineCopyPropagationID);</span><o:p></o:p></p></div><div style='margin-left:1.0in'><p class=MsoNormal><span style='font-family:"Courier New"'> TargetPassConfig::addPostRegAlloc();</span><o:p></o:p></p></div><div><p class=MsoNormal style='text-indent:.5in'><span style='font-family:"Courier New"'>}</span><o:p></o:p></p></div><div><p class=MsoNormal> <o:p></o:p></p></div><div><div><p class=MsoNormal>--<span class=apple-converted-space> </span><o:p></o:p></p></div><div><p class=MsoNormal>Geoff Berry<o:p></o:p></p></div><div><p class=MsoNormal>Employee of Qualcomm Datacenter Technologies, Inc.<o:p></o:p></p></div><div><p class=MsoNormal>Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.<o:p></o:p></p></div></div><div><p class=MsoNormal> <o:p></o:p></p></div><div style='border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt'><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><div><p class=MsoNormal><b>From:</b><span class=apple-converted-space> </span><a href="mailto:qcolombet@apple.com">qcolombet@apple.com</a><span class=apple-converted-space> </span>[<a href="mailto:qcolombet@apple.com">mailto:qcolombet@apple.com</a>]<span class=apple-converted-space> </span><br><b>Sent:</b><span class=apple-converted-space> </span>Tuesday, February 27, 2018 6:33 PM<br><b>To:</b><span class=apple-converted-space> </span>Geoff Berry <<a href="mailto:gberry@codeaurora.org">gberry@codeaurora.org</a>><br><b>Cc:</b><span class=apple-converted-space> </span><a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a><br><b>Subject:</b><span class=apple-converted-space> </span>Re: [llvm] r326208 - Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"<o:p></o:p></p></div></div></div><div><p class=MsoNormal> <o:p></o:p></p></div><div><p class=MsoNormal>Hi Geoff,<o:p></o:p></p></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>Unfortunately this is causing more problems that we didn’t catch the first time.<o:p></o:p></p></div></div><div><div><div><p class=MsoNormal><br><br><br><o:p></o:p></p></div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><p class=MsoNormal>On Feb 27, 2018, at 8:59 AM, Geoff Berry via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org"><span style='color:purple'>llvm-commits@lists.llvm.org</span></a>> wrote:<o:p></o:p></p></div></div><div><p class=MsoNormal> <o:p></o:p></p></div><div><div><div><p class=MsoNormal>Author: gberry<br>Date: Tue Feb 27 08:59:10 2018<br>New Revision: 326208<br><br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project?rev=326208&view=rev"><span style='color:purple'>http://llvm.org/viewvc/llvm-project?rev=326208&view=rev</span></a><br>Log:<br>Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"<br><br>Re-enable commit r323991 now that r325931 has been committed to make<br>MachineOperand::isRenamable() check more conservative w.r.t. code<br>changes and opt-in on a per-target basis.<br><br>Added:<br> llvm/trunk/test/CodeGen/AArch64/copyprop.mir<br>Modified:<br> llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp<br> llvm/trunk/lib/CodeGen/TargetPassConfig.cpp<br> llvm/trunk/test/CodeGen/AArch64/aarch64-fold-lslfast.ll<br> llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll<br> llvm/trunk/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll<br> llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll<br> llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll<br> llvm/trunk/test/CodeGen/AArch64/flags-multiuse.ll<br> llvm/trunk/test/CodeGen/AArch64/ldst-opt.ll<br> llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll<br> llvm/trunk/test/CodeGen/AArch64/neg-imm.ll<br> llvm/trunk/test/CodeGen/AArch64/swifterror.ll<br> llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll<br> llvm/trunk/test/CodeGen/AMDGPU/fix-vgpr-copies.mir<br> llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll<br> llvm/trunk/test/CodeGen/AMDGPU/ret.ll<br> llvm/trunk/test/CodeGen/ARM/atomic-op.ll<br> llvm/trunk/test/CodeGen/ARM/intrinsics-overflow.ll<br> llvm/trunk/test/CodeGen/ARM/swifterror.ll<br> llvm/trunk/test/CodeGen/Mips/analyzebranch.ll<br> llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll<br> llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll<br> llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll<br> llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll<br> llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll<br> llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll<br> llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll<br> llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll<br> llvm/trunk/test/CodeGen/PowerPC/fma-mutate.ll<br> llvm/trunk/test/CodeGen/PowerPC/gpr-vsr-spill.ll<br> llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll<br> llvm/trunk/test/CodeGen/PowerPC/opt-li-add-to-addi.ll<br> llvm/trunk/test/CodeGen/PowerPC/tail-dup-layout.ll<br> llvm/trunk/test/CodeGen/SPARC/32abi.ll<br> llvm/trunk/test/CodeGen/SPARC/atomics.ll<br> llvm/trunk/test/CodeGen/SystemZ/vec-sub-01.ll<br> llvm/trunk/test/CodeGen/Thumb/pr35836.ll<br> llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll<br> llvm/trunk/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll<br> llvm/trunk/test/CodeGen/X86/arg-copy-elide.ll<br> llvm/trunk/test/CodeGen/X86/avg.ll<br> llvm/trunk/test/CodeGen/X86/avx-load-store.ll<br> llvm/trunk/test/CodeGen/X86/avx512-bugfix-25270.ll<br> llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll<br> llvm/trunk/test/CodeGen/X86/avx512-intel-ocl.ll<br> llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll<br> llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll<br> llvm/trunk/test/CodeGen/X86/combine-fcopysign.ll<br> llvm/trunk/test/CodeGen/X86/combine-shl.ll<br> llvm/trunk/test/CodeGen/X86/complex-fastmath.ll<br> llvm/trunk/test/CodeGen/X86/divide-by-constant.ll<br> llvm/trunk/test/CodeGen/X86/fmaxnum.ll<br> llvm/trunk/test/CodeGen/X86/fmf-flags.ll<br> llvm/trunk/test/CodeGen/X86/fminnum.ll<br> llvm/trunk/test/CodeGen/X86/fp128-i128.ll<br> llvm/trunk/test/CodeGen/X86/h-registers-1.ll<br> llvm/trunk/test/CodeGen/X86/haddsub-2.ll<br> llvm/trunk/test/CodeGen/X86/haddsub-3.ll<br> llvm/trunk/test/CodeGen/X86/haddsub-undef.ll<br> llvm/trunk/test/CodeGen/X86/half.ll<br> llvm/trunk/test/CodeGen/X86/horizontal-reduce-smax.ll<br> llvm/trunk/test/CodeGen/X86/horizontal-reduce-smin.ll<br> llvm/trunk/test/CodeGen/X86/horizontal-reduce-umax.ll<br> llvm/trunk/test/CodeGen/X86/horizontal-reduce-umin.ll<br> llvm/trunk/test/CodeGen/X86/i128-mul.ll<br> llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll<br> llvm/trunk/test/CodeGen/X86/ipra-local-linkage.ll<br> llvm/trunk/test/CodeGen/X86/legalize-shift.ll<br> llvm/trunk/test/CodeGen/X86/localescape.ll<br> llvm/trunk/test/CodeGen/X86/machine-cp.ll<br> llvm/trunk/test/CodeGen/X86/mmx-arith.ll<br> llvm/trunk/test/CodeGen/X86/mul-i1024.ll<br> llvm/trunk/test/CodeGen/X86/mul-i256.ll<br> llvm/trunk/test/CodeGen/X86/mul-i512.ll<br> llvm/trunk/test/CodeGen/X86/mul128.ll<br> llvm/trunk/test/CodeGen/X86/mulvi32.ll<br> llvm/trunk/test/CodeGen/X86/musttail-varargs.ll<br> llvm/trunk/test/CodeGen/X86/pmul.ll<br> llvm/trunk/test/CodeGen/X86/powi.ll<br> llvm/trunk/test/CodeGen/X86/pr11334.ll<br> llvm/trunk/test/CodeGen/X86/pr29112.ll<br> llvm/trunk/test/CodeGen/X86/pr34080-2.ll<br> llvm/trunk/test/CodeGen/X86/retpoline-external.ll<br> llvm/trunk/test/CodeGen/X86/retpoline.ll<br> llvm/trunk/test/CodeGen/X86/sad.ll<br> llvm/trunk/test/CodeGen/X86/safestack.ll<br> llvm/trunk/test/CodeGen/X86/safestack_inline.ll<br> llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll<br> llvm/trunk/test/CodeGen/X86/select.ll<br> llvm/trunk/test/CodeGen/X86/shrink-wrap-chkstk.ll<br> llvm/trunk/test/CodeGen/X86/slow-pmulld.ll<br> llvm/trunk/test/CodeGen/X86/sqrt-fastmath.ll<br> llvm/trunk/test/CodeGen/X86/sse-scalar-fp-arith.ll<br> llvm/trunk/test/CodeGen/X86/sse1.ll<br> llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll<br> llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll<br> llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll<br> llvm/trunk/test/CodeGen/X86/vec_fp_to_int.ll<br> llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll<br> llvm/trunk/test/CodeGen/X86/vec_minmax_uint.ll<br> llvm/trunk/test/CodeGen/X86/vec_shift4.ll<br> llvm/trunk/test/CodeGen/X86/vector-blend.ll<br> llvm/trunk/test/CodeGen/X86/vector-idiv-sdiv-128.ll<br> llvm/trunk/test/CodeGen/X86/vector-idiv-udiv-128.ll<br> llvm/trunk/test/CodeGen/X86/vector-mul.ll<br> llvm/trunk/test/CodeGen/X86/vector-rotate-128.ll<br> llvm/trunk/test/CodeGen/X86/vector-sext.ll<br> llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll<br> llvm/trunk/test/CodeGen/X86/vector-shift-lshr-128.ll<br> llvm/trunk/test/CodeGen/X86/vector-shift-shl-128.ll<br> llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll<br> llvm/trunk/test/CodeGen/X86/vector-trunc-math.ll<br> llvm/trunk/test/CodeGen/X86/vector-zext.ll<br> llvm/trunk/test/CodeGen/X86/vselect-minmax.ll<br> llvm/trunk/test/CodeGen/X86/widen_conv-3.ll<br> llvm/trunk/test/CodeGen/X86/widen_conv-4.ll<br> llvm/trunk/test/CodeGen/X86/win64_frame.ll<br> llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll<br> llvm/trunk/test/CodeGen/X86/x86-shrink-wrap-unwind.ll<br> llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll<br> llvm/trunk/test/DebugInfo/COFF/fpo-shrink-wrap.ll<br> llvm/trunk/test/DebugInfo/X86/spill-nospill.ll<br><br>Modified: llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp (original)<br>+++ llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp Tue Feb 27 08:59:10 2018<br>@@ -9,6 +9,35 @@<br>//<br>// This is an extremely simple MachineInstr-level copy propagation pass.<br>//<br>+// This pass forwards the source of COPYs to the users of their destinations<br>+// when doing so is legal. For example:<br>+//<br>+// %reg1 = COPY %reg0<br>+// ...<br>+// ... = OP %reg1<br>+//<br>+// If<br>+// - %reg0 has not been clobbered by the time of the use of %reg1<br>+// - the register class constraints are satisfied<br>+// - the COPY def is the only value that reaches OP<br>+// then this pass replaces the above with:<br>+//<br>+// %reg1 = COPY %reg0<br>+// ...<br>+// ... = OP %reg0<br>+//<br>+// This pass also removes some redundant COPYs. For example:<br>+//<br>+// %R1 = COPY %R0<br>+// ... // No clobber of %R1<br>+// %R0 = COPY %R1 <<< Removed<br>+//<br>+// or<br>+//<br>+// %R1 = COPY %R0<br>+// ... // No clobber of %R0<br>+// %R1 = COPY %R0 <<< Removed<br>+//<br>//===----------------------------------------------------------------------===//<br><br>#include "llvm/ADT/DenseMap.h"<br>@@ -23,11 +52,13 @@<br>#include "llvm/CodeGen/MachineInstr.h"<br>#include "llvm/CodeGen/MachineOperand.h"<br>#include "llvm/CodeGen/MachineRegisterInfo.h"<br>+#include "llvm/CodeGen/TargetInstrInfo.h"<br>#include "llvm/CodeGen/TargetRegisterInfo.h"<br>#include "llvm/CodeGen/TargetSubtargetInfo.h"<br>#include "llvm/MC/MCRegisterInfo.h"<br>#include "llvm/Pass.h"<br>#include "llvm/Support/Debug.h"<br>+#include "llvm/Support/DebugCounter.h"<br>#include "llvm/Support/raw_ostream.h"<br>#include <cassert><br>#include <iterator><br>@@ -37,6 +68,9 @@ using namespace llvm;<br>#define DEBUG_TYPE "machine-cp"<br><br>STATISTIC(NumDeletes, "Number of dead copies deleted");<br>+STATISTIC(NumCopyForwards, "Number of copy uses forwarded");<br>+DEBUG_COUNTER(FwdCounter, "machine-cp-fwd",<br>+ "Controls which register COPYs are forwarded");<br><br>namespace {<br><br>@@ -73,6 +107,10 @@ using Reg2MIMap = DenseMap<unsigned, Mac<br> void ReadRegister(unsigned Reg);<br> void CopyPropagateBlock(MachineBasicBlock &MBB);<br> bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def);<br>+ void forwardUses(MachineInstr &MI);<br>+ bool isForwardableRegClassCopy(const MachineInstr &Copy,<br>+ const MachineInstr &UseI, unsigned UseIdx);<br>+ bool hasImplicitOverlap(const MachineInstr &MI, const MachineOperand &Use);<br><br> /// Candidates for deletion.<br> SmallSetVector<MachineInstr*, 8> MaybeDeadCopies;<br>@@ -208,6 +246,152 @@ bool MachineCopyPropagation::eraseIfRedu<br> return true;<br>}<br><br>+/// Decide whether we should forward the source of \param Copy to its use in<br>+/// \param UseI based on the physical register class constraints of the opcode<br>+/// and avoiding introducing more cross-class COPYs.<br>+bool MachineCopyPropagation::isForwardableRegClassCopy(const MachineInstr &Copy,<br>+ const MachineInstr &UseI,<br>+ unsigned UseIdx) {<br>+<br>+ unsigned CopySrcReg = Copy.getOperand(1).getReg();<br>+<br>+ // If the new register meets the opcode register constraints, then allow<br>+ // forwarding.<br>+ if (const TargetRegisterClass *URC =<br>+ UseI.getRegClassConstraint(UseIdx, TII, TRI))<br>+ return URC->contains(CopySrcReg);<br>+<br>+ if (!UseI.isCopy())<br>+ return false;<br>+<br>+ /// COPYs don't have register class constraints, so if the user instruction<br>+ /// is a COPY, we just try to avoid introducing additional cross-class<br>+ /// COPYs. For example:<br>+ ///<br>+ /// RegClassA = COPY RegClassB // Copy parameter<br>+ /// ...<br>+ /// RegClassB = COPY RegClassA // UseI parameter<br>+ ///<br>+ /// which after forwarding becomes<br>+ ///<br>+ /// RegClassA = COPY RegClassB<br>+ /// ...<br>+ /// RegClassB = COPY RegClassB<br>+ ///<br>+ /// so we have reduced the number of cross-class COPYs and potentially<br>+ /// introduced a nop COPY that can be removed.<br>+ const TargetRegisterClass *UseDstRC =<br>+ TRI->getMinimalPhysRegClass(UseI.getOperand(0).getReg());<br>+<br>+ const TargetRegisterClass *SuperRC = UseDstRC;<br>+ for (TargetRegisterClass::sc_iterator SuperRCI = UseDstRC->getSuperClasses();<br>+ SuperRC; SuperRC = *SuperRCI++)<br>+ if (SuperRC->contains(CopySrcReg))<br>+ return true;<br>+<br>+ return false;<br>+}<br>+<br>+/// Check that \p MI does not have implicit uses that overlap with it's \p Use<br>+/// operand (the register being replaced), since these can sometimes be<br>+/// implicitly tied to other operands. For example, on AMDGPU:<br>+///<br>+/// V_MOVRELS_B32_e32 %VGPR2, %M0<imp-use>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use><br>+///<br>+/// the %VGPR2 is implicitly tied to the larger reg operand, but we have no<br>+/// way of knowing we need to update the latter when updating the former.<br>+bool MachineCopyPropagation::hasImplicitOverlap(const MachineInstr &MI,<br>+ const MachineOperand &Use) {<br>+ for (const MachineOperand &MIUse : MI.uses())<br>+ if (&MIUse != &Use && MIUse.isReg() && MIUse.isImplicit() &&<br>+ MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg()))<br>+ return true;<br>+<br>+ return false;<br>+}<br>+<br>+/// Look for available copies whose destination register is used by \p MI and<br>+/// replace the use in \p MI with the copy's source register.<br>+void MachineCopyPropagation::forwardUses(MachineInstr &MI) {<br>+ if (AvailCopyMap.empty())<br>+ return;<br>+<br>+ // Look for non-tied explicit vreg uses that have an active COPY<br>+ // instruction that defines the physical register allocated to them.<br>+ // Replace the vreg with the source of the active COPY.<br>+ for (unsigned OpIdx = 0, OpEnd = MI.getNumOperands(); OpIdx < OpEnd;<br>+ ++OpIdx) {<br>+ MachineOperand &MOUse = MI.getOperand(OpIdx);<br>+ // Don't forward into undef use operands since doing so can cause problems<br>+ // with the machine verifier, since it doesn't treat undef reads as reads,<br>+ // so we can end up with a live range that ends on an undef read, leading to<br>+ // an error that the live range doesn't end on a read of the live range<br>+ // register.<br>+ if (!MOUse.isReg() || MOUse.isTied() || MOUse.isUndef() || MOUse.isDef() ||<br>+ MOUse.isImplicit())<br>+ continue;<br>+<br>+ if (!MOUse.getReg())<br>+ continue;<br>+<br>+ // Check that the register is marked 'renamable' so we know it is safe to<br>+ // rename it without violating any constraints that aren't expressed in the<br>+ // IR (e.g. ABI or opcode requirements).<br>+ if (!MOUse.isRenamable())<br>+ continue;<br>+<br>+ auto CI = AvailCopyMap.find(MOUse.getReg());<br>+ if (CI == AvailCopyMap.end())<br>+ continue;<br>+<br>+ MachineInstr &Copy = *CI->second;<br>+ unsigned CopyDstReg = Copy.getOperand(0).getReg();<br>+ const MachineOperand &CopySrc = Copy.getOperand(1);<br>+ unsigned CopySrcReg = CopySrc.getReg();<br>+<br>+ // FIXME: Don't handle partial uses of wider COPYs yet.<br>+ if (MOUse.getReg() != CopyDstReg) {<br>+ DEBUG(dbgs() << "MCP: FIXME! Not forwarding COPY to sub-register use:\n "<br>+ << MI);<br>+ continue;<br>+ }<br>+<br>+ // Don't forward COPYs of reserved regs unless they are constant.<br>+ if (MRI->isReserved(CopySrcReg) && !MRI->isConstantPhysReg(CopySrcReg))<br>+ continue;<br>+<br>+ if (!isForwardableRegClassCopy(Copy, MI, OpIdx))<br>+ continue;<br>+<br>+ if (hasImplicitOverlap(MI, MOUse))<br>+ continue;<br>+<br>+ if (!DebugCounter::shouldExecute(FwdCounter)) {<br>+ DEBUG(dbgs() << "MCP: Skipping forwarding due to debug counter:\n "<br>+ << MI);<br>+ continue;<br>+ }<br>+<br>+ DEBUG(dbgs() << "MCP: Replacing " << printReg(MOUse.getReg(), TRI)<br>+ << "\n with " << printReg(CopySrcReg, TRI) << "\n in "<br>+ << MI << " from " << Copy);<br>+<br>+ MOUse.setReg(CopySrcReg);<br>+ if (!CopySrc.isRenamable())<br>+ MOUse.setIsRenamable(false);<br>+<br>+ DEBUG(dbgs() << "MCP: After replacement: " << MI << "\n");<br>+<br>+ // Clear kill markers that may have been invalidated.<br>+ for (MachineInstr &KMI :<br>+ make_range(Copy.getIterator(), std::next(MI.getIterator())))<br>+ KMI.clearRegisterKills(CopySrcReg, TRI);<br>+<br>+ ++NumCopyForwards;<br>+ Changed = true;<br>+ }<br>+}<br>+<br>void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {<br> DEBUG(dbgs() << "MCP: CopyPropagateBlock " << MBB.getName() << "\n");<br><br>@@ -241,6 +425,11 @@ void MachineCopyPropagation::CopyPropaga<br> if (eraseIfRedundant(*MI, Def, Src) || eraseIfRedundant(*MI, Src, Def))<br> continue;<br><br>+ forwardUses(*MI);<br>+<br>+ // Src may have been changed by forwardUses()<br>+ Src = MI->getOperand(1).getReg();<br>+<br> // If Src is defined by a previous copy, the previous copy cannot be<br> // eliminated.<br> ReadRegister(Src);<br>@@ -292,6 +481,20 @@ void MachineCopyPropagation::CopyPropaga<br> continue;<br> }<br><br>+ // Clobber any earlyclobber regs first.<br>+ for (const MachineOperand &MO : MI->operands())<br>+ if (MO.isReg() && MO.isEarlyClobber()) {<br>+ unsigned Reg = MO.getReg();<br>+ // If we have a tied earlyclobber, that means it is also read by this<br>+ // instruction, so we need to make sure we don't remove it as dead<br>+ // later.<br>+ if (MO.isTied())<br>+ ReadRegister(Reg);<br>+ ClobberRegister(Reg);<br>+ }<br>+<br>+ forwardUses(*MI);<br>+<br> // Not a copy.<br> SmallVector<unsigned, 2> Defs;<br> const MachineOperand *RegMask = nullptr;<br>@@ -307,7 +510,7 @@ void MachineCopyPropagation::CopyPropaga<br> assert(!TargetRegisterInfo::isVirtualRegister(Reg) &&<br> "MachineCopyPropagation should be run after register allocation!");<br><br>- if (MO.isDef()) {<br>+ if (MO.isDef() && !MO.isEarlyClobber()) {<br> Defs.push_back(Reg);<br> continue;<br> } else if (MO.readsReg())<br>@@ -364,6 +567,8 @@ void MachineCopyPropagation::CopyPropaga<br> // since we don't want to trust live-in lists.<br> if (MBB.succ_empty()) {<br> for (MachineInstr *MaybeDead : MaybeDeadCopies) {<br>+ DEBUG(dbgs() << "MCP: Removing copy due to no live-out succ: ";<br>+ MaybeDead->dump());<br> assert(!MRI->isReserved(MaybeDead->getOperand(0).getReg()));<br> MaybeDead->eraseFromParent();<br> Changed = true;<br><br>Modified: llvm/trunk/lib/CodeGen/TargetPassConfig.cpp<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetPassConfig.cpp?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetPassConfig.cpp?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/lib/CodeGen/TargetPassConfig.cpp (original)<br>+++ llvm/trunk/lib/CodeGen/TargetPassConfig.cpp Tue Feb 27 08:59:10 2018<br>@@ -1083,6 +1083,10 @@ void TargetPassConfig::addOptimizedRegAl<br> // kill markers.<br> addPass(&StackSlotColoringID);<br><br>+ // Copy propagate to forward register uses and try to eliminate COPYs that<br>+ // were not coalesced.<br>+ addPass(&MachineCopyPropagationID);<br>+<o:p></o:p></p></div></div></div></blockquote><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>This part is wasteful if the target does not allow register renaming.<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>Could we tie that to the setting of<span class=apple-converted-space> </span><span style='font-size:8.5pt;font-family:"Menlo",serif;background:white'>AllowRegisterRenaming</span><span class=apple-converted-space><span style='background:white'> </span></span><span style='background:white'>in TableGen?</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='background:white'>Moreover, this pass doesn’t actually play nice with bundles when the headers are not set and right now we do enforce that the headers should be set.</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='background:white'>In other words, by putting this pass in the default pipeline, we potentially break targets that don’t allow register renaming because that pass still does DCE on copies will potential ignoring the uses/defs happening in bundles.</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='background:white'>(This happens for us.)</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='background:white'>Do you mind if I revert this change while you work on plumbing AllowRegisterRenaming all the way up?</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='background:white'>(I would be fine with another TargetPassConfig hook similar to addInstructionSelector.)</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='background:white'>Cheers,</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='background:white'>-Quentin</span><o:p></o:p></p></div></div><div><p class=MsoNormal><br><br><br><o:p></o:p></p></div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><div><p class=MsoNormal> // Run post-ra machine LICM to hoist reloads / remats.<br> //<br> // FIXME: can this move into MachineLateOptimization?<br><br>Modified: llvm/trunk/test/CodeGen/AArch64/aarch64-fold-lslfast.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/aarch64-fold-lslfast.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/aarch64-fold-lslfast.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/aarch64-fold-lslfast.ll (original)<br>+++ llvm/trunk/test/CodeGen/AArch64/aarch64-fold-lslfast.ll Tue Feb 27 08:59:10 2018<br>@@ -9,7 +9,8 @@ define i16 @halfword(%struct.a* %ctx, i3<br>; CHECK-LABEL: halfword:<br>; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8<br>; CHECK: ldrh [[REG1:w[0-9]+]], [{{.*}}[[REG2:x[0-9]+]], [[REG]], lsl #1]<br>-; CHECK: strh [[REG1]], [{{.*}}[[REG2]], [[REG]], lsl #1]<br>+; CHECK: mov [[REG3:x[0-9]+]], [[REG2]]<br>+; CHECK: strh [[REG1]], [{{.*}}[[REG3]], [[REG]], lsl #1]<br> %shr81 = lshr i32 %xor72, 9<br> %conv82 = zext i32 %shr81 to i64<br> %idxprom83 = and i64 %conv82, 255<br>@@ -24,7 +25,8 @@ define i32 @word(%struct.b* %ctx, i32 %x<br>; CHECK-LABEL: word:<br>; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8<br>; CHECK: ldr [[REG1:w[0-9]+]], [{{.*}}[[REG2:x[0-9]+]], [[REG]], lsl #2]<br>-; CHECK: str [[REG1]], [{{.*}}[[REG2]], [[REG]], lsl #2]<br>+; CHECK: mov [[REG3:x[0-9]+]], [[REG2]]<br>+; CHECK: str [[REG1]], [{{.*}}[[REG3]], [[REG]], lsl #2]<br> %shr81 = lshr i32 %xor72, 9<br> %conv82 = zext i32 %shr81 to i64<br> %idxprom83 = and i64 %conv82, 255<br>@@ -39,7 +41,8 @@ define i64 @doubleword(%struct.c* %ctx,<br>; CHECK-LABEL: doubleword:<br>; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8<br>; CHECK: ldr [[REG1:x[0-9]+]], [{{.*}}[[REG2:x[0-9]+]], [[REG]], lsl #3]<br>-; CHECK: str [[REG1]], [{{.*}}[[REG2]], [[REG]], lsl #3]<br>+; CHECK: mov [[REG3:x[0-9]+]], [[REG2]]<br>+; CHECK: str [[REG1]], [{{.*}}[[REG3]], [[REG]], lsl #3]<br> %shr81 = lshr i32 %xor72, 9<br> %conv82 = zext i32 %shr81 to i64<br> %idxprom83 = and i64 %conv82, 255<br><br>Modified: llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll (original)<br>+++ llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll Tue Feb 27 08:59:10 2018<br>@@ -8,15 +8,9 @@ define <2 x i64> @bar(<2 x i64> %a, <2 x<br>; CHECK: add.2d<span class=apple-tab-span> </span><span class=apple-converted-space> </span>v[[REG:[0-9]+]], v0, v1<br>; CHECK: add<span class=apple-tab-span> </span><span class=apple-converted-space> </span>d[[REG3:[0-9]+]], d[[REG]], d1<br>; CHECK: sub<span class=apple-tab-span> </span><span class=apple-converted-space> </span>d[[REG2:[0-9]+]], d[[REG]], d1<br>-; Without advanced copy optimization, we end up with cross register<br>-; banks copies that cannot be coalesced.<br>-; CHECK-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]]<br>-; With advanced copy optimization, we end up with just one copy<br>-; to insert the computed high part into the V register.<span class=apple-converted-space> </span><br>-; CHECK-OPT-NOT: fmov<br>+; CHECK-NOT: fmov<br>; CHECK: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]<br>-; CHECK-NOOPT: fmov d0, [[COPY_REG3]]<br>-; CHECK-OPT-NOT: fmov<br>+; CHECK-NOT: fmov<br>; CHECK: mov.d v0[1], [[COPY_REG2]]<br>; CHECK-NEXT: ret<br>;<br>@@ -24,11 +18,9 @@ define <2 x i64> @bar(<2 x i64> %a, <2 x<br>; GENERIC: add<span class=apple-tab-span> </span><span class=apple-converted-space> </span>v[[REG:[0-9]+]].2d, v0.2d, v1.2d<br>; GENERIC: add<span class=apple-tab-span> </span><span class=apple-converted-space> </span>d[[REG3:[0-9]+]], d[[REG]], d1<br>; GENERIC: sub<span class=apple-converted-space> </span>d[[REG2:[0-9]+]], d[[REG]], d1<br>-; GENERIC-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]]<br>-; GENERIC-OPT-NOT: fmov<br>+; GENERIC-NOT: fmov<br>; GENERIC: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]<br>-; GENERIC-NOOPT: fmov d0, [[COPY_REG3]]<br>-; GENERIC-OPT-NOT: fmov<br>+; GENERIC-NOT: fmov<br>; GENERIC: mov v0.d[1], [[COPY_REG2]]<br>; GENERIC-NEXT: ret<br> %add = add <2 x i64> %a, %b<br><br>Modified: llvm/trunk/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll (original)<br>+++ llvm/trunk/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll Tue Feb 27 08:59:10 2018<br>@@ -4,8 +4,10 @@<br>define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind ssp {<br>entry:<br>; CHECK-LABEL: t:<br>-; CHECK: mov x0, [[REG1:x[0-9]+]]<br>-; CHECK: mov x1, [[REG2:x[0-9]+]]<br>+; CHECK: mov [[REG2:x[0-9]+]], x3<br>+; CHECK: mov [[REG1:x[0-9]+]], x2<br>+; CHECK: mov x0, x2<br>+; CHECK: mov x1, x3<br>; CHECK: bl _foo<br>; CHECK: mov x0, [[REG1]]<br>; CHECK: mov x1, [[REG2]]<br><br>Modified: llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll (original)<br>+++ llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll Tue Feb 27 08:59:10 2018<br>@@ -45,8 +45,7 @@ define i1 @test_return_bool(i8* %value,<br><br>; CHECK: [[FAILED]]:<br>; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}<br>-; CHECK: mov [[TMP:w[0-9]+]], wzr<br>-; CHECK: eor w0, [[TMP]], #0x1<br>+; CHECK: eor w0, wzr, #0x1<br>; CHECK: ret<br><br> %pair = cmpxchg i8* %value, i8 %oldValue, i8 %newValue acq_rel monotonic<br><br>Added: llvm/trunk/test/CodeGen/AArch64/copyprop.mir<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/copyprop.mir?rev=326208&view=auto"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/copyprop.mir?rev=326208&view=auto</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/copyprop.mir (added)<br>+++ llvm/trunk/test/CodeGen/AArch64/copyprop.mir Tue Feb 27 08:59:10 2018<br>@@ -0,0 +1,104 @@<br>+# RUN: llc -mtriple=aarch64-linux-gnu -run-pass machine-cp -o - %s | FileCheck %s<br>+# Tests for MachineCopyPropagation copy forwarding.<br>+---<br>+# Simple forwarding.<br>+# CHECK-LABEL: name: test1<br>+# CHECK: $x0 = SUBXri $x0, 1, 0<br>+name: test1<br>+tracksRegLiveness: true<br>+body: |<br>+ bb.0:<br>+ liveins: $x0<br>+ renamable $x1 = COPY $x0<br>+ $x0 = SUBXri renamable $x1, 1, 0<br>+...<br>+---<br>+# Don't forward if not renamable.<br>+# CHECK-LABEL: name: test2<br>+# CHECK: $x0 = SUBXri $x1, 1, 0<br>+name: test2<br>+tracksRegLiveness: true<br>+body: |<br>+ bb.0:<br>+ liveins: $x0<br>+ $x1 = COPY $x0<br>+ $x0 = SUBXri $x1, 1, 0<br>+...<br>+---<br>+# Don't forward reserved non-constant reg values.<br>+# CHECK-LABEL: name: test4<br>+# CHECK: $x0 = SUBXri renamable $x1, 1, 0<br>+name: test4<br>+tracksRegLiveness: true<br>+body: |<br>+ bb.0:<br>+ liveins: $x0<br>+ $sp = SUBXri $sp, 16, 0<br>+ renamable $x1 = COPY $sp<br>+ $x0 = SUBXri renamable $x1, 1, 0<br>+ $sp = ADDXri $sp, 16, 0<br>+...<br>+---<br>+# Don't violate opcode constraints when forwarding.<br>+# CHECK-LABEL: name: test5<br>+# CHECK: $x0 = SUBXri renamable $x1, 1, 0<br>+name: test5<br>+tracksRegLiveness: true<br>+body: |<br>+ bb.0:<br>+ liveins: $x0<br>+ renamable $x1 = COPY $xzr<br>+ $x0 = SUBXri renamable $x1, 1, 0<br>+...<br>+---<br>+# Test cross-class COPY forwarding.<br>+# CHECK-LABEL: name: test6<br>+# CHECK: $x2 = COPY $x0<br>+name: test6<br>+tracksRegLiveness: true<br>+body: |<br>+ bb.0:<br>+ liveins: $x0<br>+ renamable $d1 = COPY $x0<br>+ $x2 = COPY renamable $d1<br>+ RET_ReallyLR implicit $x2<br>+...<br>+---<br>+# Don't forward if there are overlapping implicit operands.<br>+# CHECK-LABEL: name: test7<br>+# CHECK: $w0 = SUBWri killed renamable $w1, 1, 0<br>+name: test7<br>+tracksRegLiveness: true<br>+body: |<br>+ bb.0:<br>+ liveins: $w0<br>+ renamable $w1 = COPY $w0<br>+ $w0 = SUBWri killed renamable $w1, 1, 0, implicit killed $x1<br>+...<br>+---<br>+# Check that kill flags are cleared.<br>+# CHECK-LABEL: name: test8<br>+# CHECK: $x2 = ADDXri $x0, 1, 0<br>+# CHECK: $x0 = SUBXri $x0, 1, 0<br>+name: test8<br>+tracksRegLiveness: true<br>+body: |<br>+ bb.0:<br>+ liveins: $x0<br>+ renamable $x1 = COPY $x0<br>+ $x2 = ADDXri killed $x0, 1, 0<br>+ $x0 = SUBXri renamable $x1, 1, 0<br>+...<br>+---<br>+# Don't forward if value is clobbered.<br>+# CHECK-LABEL: name: test9<br>+# CHECK: $x2 = SUBXri renamable $x1, 1, 0<br>+name: test9<br>+tracksRegLiveness: true<br>+body: |<br>+ bb.0:<br>+ liveins: $x0<br>+ renamable $x1 = COPY $x0<br>+ $x0 = ADDXri $x0, 1, 0<br>+ $x2 = SUBXri renamable $x1, 1, 0<br>+...<br><br>Modified: llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll (original)<br>+++ llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll Tue Feb 27 08:59:10 2018<br>@@ -489,7 +489,7 @@ else:<br><br>; CHECK-COMMON-LABEL: test_phi:<br>; CHECK-COMMON: mov x[[PTR:[0-9]+]], x0<br>-; CHECK-COMMON: ldr h[[AB:[0-9]+]], [x[[PTR]]]<br>+; CHECK-COMMON: ldr h[[AB:[0-9]+]], [x0]<br>; CHECK-COMMON: [[LOOP:LBB[0-9_]+]]:<br>; CHECK-COMMON: mov.16b v[[R:[0-9]+]], v[[AB]]<br>; CHECK-COMMON: ldr h[[AB]], [x[[PTR]]]<br><br>Modified: llvm/trunk/test/CodeGen/AArch64/flags-multiuse.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/flags-multiuse.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/flags-multiuse.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/flags-multiuse.ll (original)<br>+++ llvm/trunk/test/CodeGen/AArch64/flags-multiuse.ll Tue Feb 27 08:59:10 2018<br>@@ -17,6 +17,9 @@ define i32 @test_multiflag(i32 %n, i32 %<br> %val = zext i1 %test to i32<br>; CHECK: cset {{[xw][0-9]+}}, ne<br><br>+; CHECK: mov [[RHSCOPY:w[0-9]+]], [[RHS]]<br>+; CHECK: mov [[LHSCOPY:w[0-9]+]], [[LHS]]<br>+<br> store i32 %val, i32* @var<br><br> call void @bar()<br>@@ -25,7 +28,7 @@ define i32 @test_multiflag(i32 %n, i32 %<br> ; Currently, the comparison is emitted again. An MSR/MRS pair would also be<br> ; acceptable, but assuming the call preserves NZCV is not.<br> br i1 %test, label %iftrue, label %iffalse<br>-; CHECK: cmp [[LHS]], [[RHS]]<br>+; CHECK: cmp [[LHSCOPY]], [[RHSCOPY]]<br>; CHECK: b.eq<br><br>iftrue:<br><br>Modified: llvm/trunk/test/CodeGen/AArch64/ldst-opt.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-opt.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-opt.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/ldst-opt.ll (original)<br>+++ llvm/trunk/test/CodeGen/AArch64/ldst-opt.ll Tue Feb 27 08:59:10 2018<br>@@ -1671,7 +1671,7 @@ entry:<br>; CHECK-LABEL: bug34674:<br>; CHECK: // %entry<br>; CHECK-NEXT: mov [[ZREG:x[0-9]+]], xzr<br>-; CHECK-DAG: stp [[ZREG]], [[ZREG]], [x0]<br>+; CHECK-DAG: stp xzr, xzr, [x0]<br>; CHECK-DAG: add x{{[0-9]+}}, [[ZREG]], #1<br>define i64 @bug34674(<2 x i64>* %p) {<br>entry:<br><br>Modified: llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll (original)<br>+++ llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll Tue Feb 27 08:59:10 2018<br>@@ -11,7 +11,7 @@ entry:<br>; A53: mov [[DATA:w[0-9]+]], w1<br>; A53: str q{{[0-9]+}}, {{.*}}<br>; A53: str q{{[0-9]+}}, {{.*}}<br>-; A53: str [[DATA]], {{.*}}<br>+; A53: str w1, {{.*}}<br><br> %0 = bitcast %struct1* %fde to i8*<br> tail call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 40, i1 false)<br><br>Modified: llvm/trunk/test/CodeGen/AArch64/neg-imm.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neg-imm.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neg-imm.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/neg-imm.ll (original)<br>+++ llvm/trunk/test/CodeGen/AArch64/neg-imm.ll Tue Feb 27 08:59:10 2018<br>@@ -7,8 +7,8 @@ declare void @foo(i32)<br>define void @test(i32 %px) {<br>; CHECK_LABEL: test:<br>; CHECK_LABEL: %entry<br>-; CHECK: subs<br>-; CHECK-NEXT: csel<br>+; CHECK: subs [[REG0:w[0-9]+]],<br>+; CHECK: csel {{w[0-9]+}}, wzr, [[REG0]]<br>entry:<br> %sub = add nsw i32 %px, -1<br> %cmp = icmp slt i32 %px, 1<br><br>Modified: llvm/trunk/test/CodeGen/AArch64/swifterror.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/swifterror.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/swifterror.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/swifterror.ll (original)<br>+++ llvm/trunk/test/CodeGen/AArch64/swifterror.ll Tue Feb 27 08:59:10 2018<br>@@ -41,7 +41,7 @@ define float @caller(i8* %error_ref) {<br>; CHECK-APPLE: mov x21, xzr<br>; CHECK-APPLE: bl {{.*}}foo<br>; CHECK-APPLE: mov x0, x21<br>-; CHECK-APPLE: cbnz x0<br>+; CHECK-APPLE: cbnz x21<br>; Access part of the error object and save it to error_ref<br>; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x0, #8]<br>; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]<br>@@ -264,7 +264,7 @@ define float @caller3(i8* %error_ref) {<br>; CHECK-APPLE: mov x21, xzr<br>; CHECK-APPLE: bl {{.*}}foo_sret<br>; CHECK-APPLE: mov x0, x21<br>-; CHECK-APPLE: cbnz x0<br>+; CHECK-APPLE: cbnz x21<br>; Access part of the error object and save it to error_ref<br>; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x0, #8]<br>; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]<br>@@ -358,7 +358,7 @@ define float @caller4(i8* %error_ref) {<br>; CHECK-APPLE: mov x21, xzr<br>; CHECK-APPLE: bl {{.*}}foo_vararg<br>; CHECK-APPLE: mov x0, x21<br>-; CHECK-APPLE: cbnz x0<br>+; CHECK-APPLE: cbnz x21<br>; Access part of the error object and save it to error_ref<br>; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x0, #8]<br>; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]<br><br>Modified: llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll (original)<br>+++ llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll Tue Feb 27 08:59:10 2018<br>@@ -547,16 +547,16 @@ define void @func_use_every_sgpr_input_c<br>; GCN: s_mov_b32 s5, s32<br>; GCN: s_add_u32 s32, s32, 0x300<br><br>-; GCN-DAG: s_mov_b32 [[SAVE_X:s[0-9]+]], s14<br>-; GCN-DAG: s_mov_b32 [[SAVE_Y:s[0-9]+]], s15<br>-; GCN-DAG: s_mov_b32 [[SAVE_Z:s[0-9]+]], s16<br>+; GCN-DAG: s_mov_b32 [[SAVE_X:s[0-57-9][0-9]*]], s14<br>+; GCN-DAG: s_mov_b32 [[SAVE_Y:s[0-68-9][0-9]*]], s15<br>+; GCN-DAG: s_mov_b32 [[SAVE_Z:s[0-79][0-9]*]], s16<br>; GCN-DAG: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, s[6:7]<br>; GCN-DAG: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, s[8:9]<br>; GCN-DAG: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, s[10:11]<br><br>-; GCN-DAG: s_mov_b32 s6, [[SAVE_X]]<br>-; GCN-DAG: s_mov_b32 s7, [[SAVE_Y]]<br>-; GCN-DAG: s_mov_b32 s8, [[SAVE_Z]]<br>+; GCN-DAG: s_mov_b32 s6, s14<br>+; GCN-DAG: s_mov_b32 s7, s15<br>+; GCN-DAG: s_mov_b32 s8, s16<br>; GCN: s_swappc_b64<br><br>; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset:4<br><br>Modified: llvm/trunk/test/CodeGen/AMDGPU/fix-vgpr-copies.mir<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fix-vgpr-copies.mir?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fix-vgpr-copies.mir?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AMDGPU/fix-vgpr-copies.mir (original)<br>+++ llvm/trunk/test/CodeGen/AMDGPU/fix-vgpr-copies.mir Tue Feb 27 08:59:10 2018<br>@@ -1,4 +1,4 @@<br>-# RUN: llc -march=amdgcn -start-after=greedy -stop-after=si-optimize-exec-masking -o - %s | FileCheck %s<br>+# RUN: llc -march=amdgcn -start-after=greedy -disable-copyprop -stop-after=si-optimize-exec-masking -o - %s | FileCheck %s<br># Check that we first do all vector instructions and only then change exec<br># CHECK-DAG: COPY $vgpr10_vgpr11<br># CHECK-DAG: COPY $vgpr12_vgpr13<br><br>Modified: llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll (original)<br>+++ llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll Tue Feb 27 08:59:10 2018<br>@@ -78,7 +78,7 @@ ENDIF:<br><br>; Uses a copy intsead of an or<br>; GCN: s_mov_b64 [[COPY:s\[[0-9]+:[0-9]+\]]], [[BREAK_REG]]<br>-; GCN: s_or_b64 [[BREAK_REG]], exec, [[COPY]]<br>+; GCN: s_or_b64 [[BREAK_REG]], exec, [[BREAK_REG]]<br>define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {<br>bb:<br> %id = call i32 @llvm.amdgcn.workitem.id.x()<br><br>Modified: llvm/trunk/test/CodeGen/AMDGPU/ret.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/ret.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/ret.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AMDGPU/ret.ll (original)<br>+++ llvm/trunk/test/CodeGen/AMDGPU/ret.ll Tue Feb 27 08:59:10 2018<br>@@ -2,10 +2,10 @@<br>; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s<br><br>; GCN-LABEL: {{^}}vgpr:<br>-; GCN: v_mov_b32_e32 v1, v0<br>-; GCN-DAG: v_add_f32_e32 v0, 1.0, v1<br>-; GCN-DAG: exp mrt0 v1, v1, v1, v1 done vm<br>+; GCN-DAG: v_mov_b32_e32 v1, v0<br>+; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm<br>; GCN: s_waitcnt expcnt(0)<br>+; GCN: v_add_f32_e32 v0, 1.0, v1<br>; GCN-NOT: s_endpgm<br>define amdgpu_vs { float, float } @vgpr([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {<br>bb:<br>@@ -179,7 +179,7 @@ bb:<br><br>; GCN-LABEL: {{^}}sgpr:<br>; GCN: s_mov_b32 s2, s3<br>-; GCN: s_add_i32 s0, s2, 2<br>+; GCN: s_add_i32 s0, s3, 2<br>; GCN-NOT: s_endpgm<br>define amdgpu_vs { i32, i32, i32 } @sgpr([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {<br>bb:<br>@@ -204,13 +204,13 @@ bb:<br>}<br><br>; GCN-LABEL: {{^}}both:<br>-; GCN: v_mov_b32_e32 v1, v0<br>-; GCN-DAG: exp mrt0 v1, v1, v1, v1 done vm<br>-; GCN-DAG: v_add_f32_e32 v0, 1.0, v1<br>-; GCN-DAG: s_add_i32 s0, s3, 2<br>+; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm<br>+; GCN-DAG: v_mov_b32_e32 v1, v0<br>; GCN-DAG: s_mov_b32 s1, s2<br>-; GCN: s_mov_b32 s2, s3<br>; GCN: s_waitcnt expcnt(0)<br>+; GCN: v_add_f32_e32 v0, 1.0, v1<br>+; GCN-DAG: s_add_i32 s0, s3, 2<br>+; GCN-DAG: s_mov_b32 s2, s3<br>; GCN-NOT: s_endpgm<br>define amdgpu_vs { float, i32, float, i32, i32 } @both([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {<br>bb:<br><br>Modified: llvm/trunk/test/CodeGen/ARM/atomic-op.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/ARM/atomic-op.ll (original)<br>+++ llvm/trunk/test/CodeGen/ARM/atomic-op.ll Tue Feb 27 08:59:10 2018<br>@@ -287,7 +287,8 @@ define i32 @test_cmpxchg_fail_order(i32<br><br> %pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic<br> %oldval = extractvalue { i32, i1 } %pair, 0<br>-; CHECK-ARMV7: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]<br>+; CHECK-ARMV7: mov r[[ADDR:[0-9]+]], r0<br>+; CHECK-ARMV7: ldrex [[OLDVAL:r[0-9]+]], [r0]<br>; CHECK-ARMV7: cmp [[OLDVAL]], r1<br>; CHECK-ARMV7: bne [[FAIL_BB:\.?LBB[0-9]+_[0-9]+]]<br>; CHECK-ARMV7: dmb ish<br>@@ -305,7 +306,8 @@ define i32 @test_cmpxchg_fail_order(i32<br>; CHECK-ARMV7: dmb ish<br>; CHECK-ARMV7: bx lr<br><br>-; CHECK-T2: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]<br>+; CHECK-T2: mov r[[ADDR:[0-9]+]], r0<br>+; CHECK-T2: ldrex [[OLDVAL:r[0-9]+]], [r0]<br>; CHECK-T2: cmp [[OLDVAL]], r1<br>; CHECK-T2: bne [[FAIL_BB:\.?LBB.*]]<br>; CHECK-T2: dmb ish<br><br>Modified: llvm/trunk/test/CodeGen/ARM/intrinsics-overflow.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/intrinsics-overflow.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/intrinsics-overflow.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/ARM/intrinsics-overflow.ll (original)<br>+++ llvm/trunk/test/CodeGen/ARM/intrinsics-overflow.ll Tue Feb 27 08:59:10 2018<br>@@ -39,7 +39,7 @@ define i32 @sadd_overflow(i32 %a, i32 %b<br> ; ARM: mov pc, lr<br><br> ; THUMBV6: mov r[[R2:[0-9]+]], r[[R0:[0-9]+]]<br>- ; THUMBV6: adds r[[R3:[0-9]+]], r[[R2]], r[[R1:[0-9]+]]<br>+ ; THUMBV6: adds r[[R3:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]<br> ; THUMBV6: movs r[[R0]], #0<br> ; THUMBV6: movs r[[R1]], #1<br> ; THUMBV6: cmp r[[R3]], r[[R2]]<br><br>Modified: llvm/trunk/test/CodeGen/ARM/swifterror.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/swifterror.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/swifterror.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/ARM/swifterror.ll (original)<br>+++ llvm/trunk/test/CodeGen/ARM/swifterror.ll Tue Feb 27 08:59:10 2018<br>@@ -40,7 +40,7 @@ define float @caller(i8* %error_ref) {<br>; CHECK-APPLE-DAG: mov r8, #0<br>; CHECK-APPLE: bl {{.*}}foo<br>; CHECK-APPLE: mov r0, r8<br>-; CHECK-APPLE: cmp r0, #0<br>+; CHECK-APPLE: cmp r8, #0<br>; Access part of the error object and save it to error_ref<br>; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r0, #8]<br>; CHECK-APPLE: strbeq [[CODE]], [{{.*}}[[ID]]]<br>@@ -181,8 +181,7 @@ define float @foo_loop(%swift_error** sw<br>; CHECK-APPLE: beq<br>; CHECK-APPLE: mov r0, #16<br>; CHECK-APPLE: malloc<br>-; CHECK-APPLE: mov r8, r0<br>-; CHECK-APPLE: strb r{{.*}}, [r8, #8]<br>+; CHECK-APPLE: strb r{{.*}}, [r0, #8]<br>; CHECK-APPLE: ble<br><br>; CHECK-O0-LABEL: foo_loop:<br>@@ -266,7 +265,7 @@ define float @caller3(i8* %error_ref) {<br>; CHECK-APPLE: mov r8, #0<br>; CHECK-APPLE: bl {{.*}}foo_sret<br>; CHECK-APPLE: mov r0, r8<br>-; CHECK-APPLE: cmp r0, #0<br>+; CHECK-APPLE: cmp r8, #0<br>; Access part of the error object and save it to error_ref<br>; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r0, #8]<br>; CHECK-APPLE: strbeq [[CODE]], [{{.*}}[[ID]]]<br>@@ -347,7 +346,7 @@ define float @caller4(i8* %error_ref) {<br>; CHECK-APPLE: mov r8, #0<br>; CHECK-APPLE: bl {{.*}}foo_vararg<br>; CHECK-APPLE: mov r0, r8<br>-; CHECK-APPLE: cmp r0, #0<br>+; CHECK-APPLE: cmp r8, #0<br>; Access part of the error object and save it to error_ref<br>; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r0, #8]<br>; CHECK-APPLE: strbeq [[CODE]], [{{.*}}[[ID]]]<br><br>Modified: llvm/trunk/test/CodeGen/Mips/analyzebranch.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/analyzebranch.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/analyzebranch.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Mips/analyzebranch.ll (original)<br>+++ llvm/trunk/test/CodeGen/Mips/analyzebranch.ll Tue Feb 27 08:59:10 2018<br>@@ -10,12 +10,11 @@<br>define double @foo(double %a, double %b) nounwind readnone {<br>; MIPS32-LABEL: foo:<br>; MIPS32: # %bb.0: # %entry<br>-; MIPS32-NEXT: mov.d $f0, $f12<br>; MIPS32-NEXT: mtc1 $zero, $f2<br>; MIPS32-NEXT: mtc1 $zero, $f3<br>-; MIPS32-NEXT: c.ule.d $f0, $f2<br>+; MIPS32-NEXT: c.ule.d $f12, $f2<br>; MIPS32-NEXT: bc1f $BB0_2<br>-; MIPS32-NEXT: nop<br>+; MIPS32-NEXT: mov.d $f0, $f12<br>; MIPS32-NEXT: # %bb.1: # %if.else<br>; MIPS32-NEXT: mtc1 $zero, $f0<br>; MIPS32-NEXT: mtc1 $zero, $f1<br>@@ -34,7 +33,7 @@ define double @foo(double %a, double %b)<br>; MIPS32R2-NEXT: mov.d $f0, $f12<br>; MIPS32R2-NEXT: mtc1 $zero, $f2<br>; MIPS32R2-NEXT: mthc1 $zero, $f2<br>-; MIPS32R2-NEXT: c.ule.d $f0, $f2<br>+; MIPS32R2-NEXT: c.ule.d $f12, $f2<br>; MIPS32R2-NEXT: bc1f $BB0_2<br>; MIPS32R2-NEXT: nop<br>; MIPS32R2-NEXT: # %bb.1: # %if.else<br>@@ -55,7 +54,7 @@ define double @foo(double %a, double %b)<br>; MIPS32r6-NEXT: mov.d $f0, $f12<br>; MIPS32r6-NEXT: mtc1 $zero, $f1<br>; MIPS32r6-NEXT: mthc1 $zero, $f1<br>-; MIPS32r6-NEXT: cmp.lt.d $f1, $f1, $f0<br>+; MIPS32r6-NEXT: cmp.lt.d $f1, $f1, $f12<br>; MIPS32r6-NEXT: mfc1 $1, $f1<br>; MIPS32r6-NEXT: andi $1, $1, 1<br>; MIPS32r6-NEXT: bnezc $1, $BB0_2<br>@@ -74,11 +73,10 @@ define double @foo(double %a, double %b)<br>;<br>; MIPS4-LABEL: foo:<br>; MIPS4: # %bb.0: # %entry<br>-; MIPS4-NEXT: mov.d $f0, $f12<br>; MIPS4-NEXT: dmtc1 $zero, $f1<br>-; MIPS4-NEXT: c.ule.d $f0, $f1<br>+; MIPS4-NEXT: c.ule.d $f12, $f1<br>; MIPS4-NEXT: bc1f .LBB0_2<br>-; MIPS4-NEXT: nop<br>+; MIPS4-NEXT: mov.d $f0, $f12<br>; MIPS4-NEXT: # %bb.1: # %if.else<br>; MIPS4-NEXT: dmtc1 $zero, $f0<br>; MIPS4-NEXT: c.ule.d $f13, $f0<br>@@ -93,11 +91,10 @@ define double @foo(double %a, double %b)<br>;<br>; MIPS64-LABEL: foo:<br>; MIPS64: # %bb.0: # %entry<br>-; MIPS64-NEXT: mov.d $f0, $f12<br>; MIPS64-NEXT: dmtc1 $zero, $f1<br>-; MIPS64-NEXT: c.ule.d $f0, $f1<br>+; MIPS64-NEXT: c.ule.d $f12, $f1<br>; MIPS64-NEXT: bc1f .LBB0_2<br>-; MIPS64-NEXT: nop<br>+; MIPS64-NEXT: mov.d $f0, $f12<br>; MIPS64-NEXT: # %bb.1: # %if.else<br>; MIPS64-NEXT: dmtc1 $zero, $f0<br>; MIPS64-NEXT: c.ule.d $f13, $f0<br>@@ -112,11 +109,10 @@ define double @foo(double %a, double %b)<br>;<br>; MIPS64R2-LABEL: foo:<br>; MIPS64R2: # %bb.0: # %entry<br>-; MIPS64R2-NEXT: mov.d $f0, $f12<br>; MIPS64R2-NEXT: dmtc1 $zero, $f1<br>-; MIPS64R2-NEXT: c.ule.d $f0, $f1<br>+; MIPS64R2-NEXT: c.ule.d $f12, $f1<br>; MIPS64R2-NEXT: bc1f .LBB0_2<br>-; MIPS64R2-NEXT: nop<br>+; MIPS64R2-NEXT: mov.d $f0, $f12<br>; MIPS64R2-NEXT: # %bb.1: # %if.else<br>; MIPS64R2-NEXT: dmtc1 $zero, $f0<br>; MIPS64R2-NEXT: c.ule.d $f13, $f0<br>@@ -131,12 +127,12 @@ define double @foo(double %a, double %b)<br>;<br>; MIPS64R6-LABEL: foo:<br>; MIPS64R6: # %bb.0: # %entry<br>-; MIPS64R6-NEXT: mov.d $f0, $f12<br>; MIPS64R6-NEXT: dmtc1 $zero, $f1<br>-; MIPS64R6-NEXT: cmp.lt.d $f1, $f1, $f0<br>+; MIPS64R6-NEXT: cmp.lt.d $f1, $f1, $f12<br>; MIPS64R6-NEXT: mfc1 $1, $f1<br>; MIPS64R6-NEXT: andi $1, $1, 1<br>-; MIPS64R6-NEXT: bnezc $1, .LBB0_2<br>+; MIPS64R6-NEXT: bnez $1, .LBB0_2<br>+; MIPS64R6-NEXT: mov.d<span class=apple-tab-span> </span><span class=apple-converted-space> </span>$f0, $f12<br>; MIPS64R6-NEXT: # %bb.1: # %if.else<br>; MIPS64R6-NEXT: dmtc1 $zero, $f0<br>; MIPS64R6-NEXT: cmp.ule.d $f1, $f13, $f0<br><br>Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll (original)<br>+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll Tue Feb 27 08:59:10 2018<br>@@ -800,7 +800,7 @@ define signext i128 @ashr_i128(i128 sign<br>; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill<br>; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill<br>; MMR3-NEXT: lw $16, 76($sp)<br>-; MMR3-NEXT: srlv $4, $8, $16<br>+; MMR3-NEXT: srlv $4, $7, $16<br>; MMR3-NEXT: not16 $3, $16<br>; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill<br>; MMR3-NEXT: sll16 $2, $6, 1<br><br>Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll (original)<br>+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll Tue Feb 27 08:59:10 2018<br>@@ -828,7 +828,7 @@ define signext i128 @lshr_i128(i128 sign<br>; MMR3-NEXT: move $17, $5<br>; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill<br>; MMR3-NEXT: lw $16, 76($sp)<br>-; MMR3-NEXT: srlv $7, $8, $16<br>+; MMR3-NEXT: srlv $7, $7, $16<br>; MMR3-NEXT: not16 $3, $16<br>; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill<br>; MMR3-NEXT: sll16 $2, $6, 1<br>@@ -919,14 +919,14 @@ define signext i128 @lshr_i128(i128 sign<br>; MMR6-NEXT: not16 $5, $3<br>; MMR6-NEXT: sw $5, 12($sp) # 4-byte Folded Spill<br>; MMR6-NEXT: move $17, $6<br>-; MMR6-NEXT: sw $17, 16($sp) # 4-byte Folded Spill<br>-; MMR6-NEXT: sll16 $6, $17, 1<br>+; MMR6-NEXT: sw $6, 16($sp) # 4-byte Folded Spill<br>+; MMR6-NEXT: sll16 $6, $6, 1<br>; MMR6-NEXT: sllv $6, $6, $5<br>; MMR6-NEXT: or $8, $6, $2<br>; MMR6-NEXT: addiu $5, $3, -64<br>; MMR6-NEXT: srlv $9, $7, $5<br>; MMR6-NEXT: move $6, $4<br>-; MMR6-NEXT: sll16 $2, $6, 1<br>+; MMR6-NEXT: sll16 $2, $4, 1<br>; MMR6-NEXT: sw $2, 8($sp) # 4-byte Folded Spill<br>; MMR6-NEXT: not16 $16, $5<br>; MMR6-NEXT: sllv $10, $2, $16<br>@@ -948,7 +948,7 @@ define signext i128 @lshr_i128(i128 sign<br>; MMR6-NEXT: selnez $11, $12, $4<br>; MMR6-NEXT: sllv $12, $6, $2<br>; MMR6-NEXT: move $7, $6<br>-; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill<br>+; MMR6-NEXT: sw $6, 4($sp) # 4-byte Folded Spill<br>; MMR6-NEXT: not16 $2, $2<br>; MMR6-NEXT: srl16 $6, $17, 1<br>; MMR6-NEXT: srlv $2, $6, $2<br><br>Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll (original)<br>+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll Tue Feb 27 08:59:10 2018<br>@@ -201,10 +201,9 @@ entry:<br>define double @tst_select_fcmp_olt_double(double %x, double %y) {<br>; M2-LABEL: tst_select_fcmp_olt_double:<br>; M2: # %bb.0: # %entry<br>-; M2-NEXT: mov.d $f0, $f12<br>-; M2-NEXT: c.olt.d $f0, $f14<br>+; M2-NEXT: c.olt.d $f12, $f14<br>; M2-NEXT: bc1t $BB2_2<br>-; M2-NEXT: nop<br>+; M2-NEXT: mov.d $f0, $f12<br>; M2-NEXT: # %bb.1: # %entry<br>; M2-NEXT: mov.d $f0, $f14<br>; M2-NEXT: $BB2_2: # %entry<br>@@ -214,14 +213,14 @@ define double @tst_select_fcmp_olt_doubl<br>; CMOV32R1-LABEL: tst_select_fcmp_olt_double:<br>; CMOV32R1: # %bb.0: # %entry<br>; CMOV32R1-NEXT: mov.d $f0, $f14<br>-; CMOV32R1-NEXT: c.olt.d $f12, $f0<br>+; CMOV32R1-NEXT: c.olt.d $f12, $f14<br>; CMOV32R1-NEXT: jr $ra<br>; CMOV32R1-NEXT: movt.d $f0, $f12, $fcc0<br>;<br>; CMOV32R2-LABEL: tst_select_fcmp_olt_double:<br>; CMOV32R2: # %bb.0: # %entry<br>; CMOV32R2-NEXT: mov.d $f0, $f14<br>-; CMOV32R2-NEXT: c.olt.d $f12, $f0<br>+; CMOV32R2-NEXT: c.olt.d $f12, $f14<br>; CMOV32R2-NEXT: jr $ra<br>; CMOV32R2-NEXT: movt.d $f0, $f12, $fcc0<br>;<br>@@ -235,10 +234,9 @@ define double @tst_select_fcmp_olt_doubl<br>;<br>; M3-LABEL: tst_select_fcmp_olt_double:<br>; M3: # %bb.0: # %entry<br>-; M3-NEXT: mov.d $f0, $f12<br>-; M3-NEXT: c.olt.d $f0, $f13<br>+; M3-NEXT: c.olt.d $f12, $f13<br>; M3-NEXT: bc1t .LBB2_2<br>-; M3-NEXT: nop<br>+; M3-NEXT: mov.d $f0, $f12<br>; M3-NEXT: # %bb.1: # %entry<br>; M3-NEXT: mov.d $f0, $f13<br>; M3-NEXT: .LBB2_2: # %entry<br>@@ -248,7 +246,7 @@ define double @tst_select_fcmp_olt_doubl<br>; CMOV64-LABEL: tst_select_fcmp_olt_double:<br>; CMOV64: # %bb.0: # %entry<br>; CMOV64-NEXT: mov.d $f0, $f13<br>-; CMOV64-NEXT: c.olt.d $f12, $f0<br>+; CMOV64-NEXT: c.olt.d $f12, $f13<br>; CMOV64-NEXT: jr $ra<br>; CMOV64-NEXT: movt.d $f0, $f12, $fcc0<br>;<br>@@ -263,7 +261,7 @@ define double @tst_select_fcmp_olt_doubl<br>; MM32R3-LABEL: tst_select_fcmp_olt_double:<br>; MM32R3: # %bb.0: # %entry<br>; MM32R3-NEXT: mov.d $f0, $f14<br>-; MM32R3-NEXT: c.olt.d $f12, $f0<br>+; MM32R3-NEXT: c.olt.d $f12, $f14<br>; MM32R3-NEXT: jr $ra<br>; MM32R3-NEXT: movt.d $f0, $f12, $fcc0<br>;<br>@@ -283,10 +281,9 @@ entry:<br>define double @tst_select_fcmp_ole_double(double %x, double %y) {<br>; M2-LABEL: tst_select_fcmp_ole_double:<br>; M2: # %bb.0: # %entry<br>-; M2-NEXT: mov.d $f0, $f12<br>-; M2-NEXT: c.ole.d $f0, $f14<br>+; M2-NEXT: c.ole.d $f12, $f14<br>; M2-NEXT: bc1t $BB3_2<br>-; M2-NEXT: nop<br>+; M2-NEXT: mov.d $f0, $f12<br>; M2-NEXT: # %bb.1: # %entry<br>; M2-NEXT: mov.d $f0, $f14<br>; M2-NEXT: $BB3_2: # %entry<br>@@ -296,14 +293,14 @@ define double @tst_select_fcmp_ole_doubl<br>; CMOV32R1-LABEL: tst_select_fcmp_ole_double:<br>; CMOV32R1: # %bb.0: # %entry<br>; CMOV32R1-NEXT: mov.d $f0, $f14<br>-; CMOV32R1-NEXT: c.ole.d $f12, $f0<br>+; CMOV32R1-NEXT: c.ole.d $f12, $f14<br>; CMOV32R1-NEXT: jr $ra<br>; CMOV32R1-NEXT: movt.d $f0, $f12, $fcc0<br>;<br>; CMOV32R2-LABEL: tst_select_fcmp_ole_double:<br>; CMOV32R2: # %bb.0: # %entry<br>; CMOV32R2-NEXT: mov.d $f0, $f14<br>-; CMOV32R2-NEXT: c.ole.d $f12, $f0<br>+; CMOV32R2-NEXT: c.ole.d $f12, $f14<br>; CMOV32R2-NEXT: jr $ra<br>; CMOV32R2-NEXT: movt.d $f0, $f12, $fcc0<br>;<br>@@ -317,10 +314,9 @@ define double @tst_select_fcmp_ole_doubl<br>;<br>; M3-LABEL: tst_select_fcmp_ole_double:<br>; M3: # %bb.0: # %entry<br>-; M3-NEXT: mov.d $f0, $f12<br>-; M3-NEXT: c.ole.d $f0, $f13<br>+; M3-NEXT: c.ole.d $f12, $f13<br>; M3-NEXT: bc1t .LBB3_2<br>-; M3-NEXT: nop<br>+; M3-NEXT: mov.d $f0, $f12<br>; M3-NEXT: # %bb.1: # %entry<br>; M3-NEXT: mov.d $f0, $f13<br>; M3-NEXT: .LBB3_2: # %entry<br>@@ -330,7 +326,7 @@ define double @tst_select_fcmp_ole_doubl<br>; CMOV64-LABEL: tst_select_fcmp_ole_double:<br>; CMOV64: # %bb.0: # %entry<br>; CMOV64-NEXT: mov.d $f0, $f13<br>-; CMOV64-NEXT: c.ole.d $f12, $f0<br>+; CMOV64-NEXT: c.ole.d $f12, $f13<br>; CMOV64-NEXT: jr $ra<br>; CMOV64-NEXT: movt.d $f0, $f12, $fcc0<br>;<br>@@ -345,7 +341,7 @@ define double @tst_select_fcmp_ole_doubl<br>; MM32R3-LABEL: tst_select_fcmp_ole_double:<br>; MM32R3: # %bb.0: # %entry<br>; MM32R3-NEXT: mov.d $f0, $f14<br>-; MM32R3-NEXT: c.ole.d $f12, $f0<br>+; MM32R3-NEXT: c.ole.d $f12, $f14<br>; MM32R3-NEXT: jr $ra<br>; MM32R3-NEXT: movt.d $f0, $f12, $fcc0<br>;<br>@@ -365,10 +361,9 @@ entry:<br>define double @tst_select_fcmp_ogt_double(double %x, double %y) {<br>; M2-LABEL: tst_select_fcmp_ogt_double:<br>; M2: # %bb.0: # %entry<br>-; M2-NEXT: mov.d $f0, $f12<br>-; M2-NEXT: c.ule.d $f0, $f14<br>+; M2-NEXT: c.ule.d $f12, $f14<br>; M2-NEXT: bc1f $BB4_2<br>-; M2-NEXT: nop<br>+; M2-NEXT: mov.d $f0, $f12<br>; M2-NEXT: # %bb.1: # %entry<br>; M2-NEXT: mov.d $f0, $f14<br>; M2-NEXT: $BB4_2: # %entry<br>@@ -378,14 +373,14 @@ define double @tst_select_fcmp_ogt_doubl<br>; CMOV32R1-LABEL: tst_select_fcmp_ogt_double:<br>; CMOV32R1: # %bb.0: # %entry<br>; CMOV32R1-NEXT: mov.d $f0, $f14<br>-; CMOV32R1-NEXT: c.ule.d $f12, $f0<br>+; CMOV32R1-NEXT: c.ule.d $f12, $f14<br>; CMOV32R1-NEXT: jr $ra<br>; CMOV32R1-NEXT: movf.d $f0, $f12, $fcc0<br>;<br>; CMOV32R2-LABEL: tst_select_fcmp_ogt_double:<br>; CMOV32R2: # %bb.0: # %entry<br>; CMOV32R2-NEXT: mov.d $f0, $f14<br>-; CMOV32R2-NEXT: c.ule.d $f12, $f0<br>+; CMOV32R2-NEXT: c.ule.d $f12, $f14<br>; CMOV32R2-NEXT: jr $ra<br>; CMOV32R2-NEXT: movf.d $f0, $f12, $fcc0<br>;<br>@@ -399,10 +394,9 @@ define double @tst_select_fcmp_ogt_doubl<br>;<br>; M3-LABEL: tst_select_fcmp_ogt_double:<br>; M3: # %bb.0: # %entry<br>-; M3-NEXT: mov.d $f0, $f12<br>-; M3-NEXT: c.ule.d $f0, $f13<br>+; M3-NEXT: c.ule.d $f12, $f13<br>; M3-NEXT: bc1f .LBB4_2<br>-; M3-NEXT: nop<br>+; M3-NEXT: mov.d $f0, $f12<br>; M3-NEXT: # %bb.1: # %entry<br>; M3-NEXT: mov.d $f0, $f13<br>; M3-NEXT: .LBB4_2: # %entry<br>@@ -412,7 +406,7 @@ define double @tst_select_fcmp_ogt_doubl<br>; CMOV64-LABEL: tst_select_fcmp_ogt_double:<br>; CMOV64: # %bb.0: # %entry<br>; CMOV64-NEXT: mov.d $f0, $f13<br>-; CMOV64-NEXT: c.ule.d $f12, $f0<br>+; CMOV64-NEXT: c.ule.d $f12, $f13<br>; CMOV64-NEXT: jr $ra<br>; CMOV64-NEXT: movf.d $f0, $f12, $fcc0<br>;<br>@@ -427,7 +421,7 @@ define double @tst_select_fcmp_ogt_doubl<br>; MM32R3-LABEL: tst_select_fcmp_ogt_double:<br>; MM32R3: # %bb.0: # %entry<br>; MM32R3-NEXT: mov.d $f0, $f14<br>-; MM32R3-NEXT: c.ule.d $f12, $f0<br>+; MM32R3-NEXT: c.ule.d $f12, $f14<br>; MM32R3-NEXT: jr $ra<br>; MM32R3-NEXT: movf.d $f0, $f12, $fcc0<br>;<br>@@ -447,10 +441,9 @@ entry:<br>define double @tst_select_fcmp_oge_double(double %x, double %y) {<br>; M2-LABEL: tst_select_fcmp_oge_double:<br>; M2: # %bb.0: # %entry<br>-; M2-NEXT: mov.d $f0, $f12<br>-; M2-NEXT: c.ult.d $f0, $f14<br>+; M2-NEXT: c.ult.d $f12, $f14<br>; M2-NEXT: bc1f $BB5_2<br>-; M2-NEXT: nop<br>+; M2-NEXT: mov.d $f0, $f12<br>; M2-NEXT: # %bb.1: # %entry<br>; M2-NEXT: mov.d $f0, $f14<br>; M2-NEXT: $BB5_2: # %entry<br>@@ -460,14 +453,14 @@ define double @tst_select_fcmp_oge_doubl<br>; CMOV32R1-LABEL: tst_select_fcmp_oge_double:<br>; CMOV32R1: # %bb.0: # %entry<br>; CMOV32R1-NEXT: mov.d $f0, $f14<br>-; CMOV32R1-NEXT: c.ult.d $f12, $f0<br>+; CMOV32R1-NEXT: c.ult.d $f12, $f14<br>; CMOV32R1-NEXT: jr $ra<br>; CMOV32R1-NEXT: movf.d $f0, $f12, $fcc0<br>;<br>; CMOV32R2-LABEL: tst_select_fcmp_oge_double:<br>; CMOV32R2: # %bb.0: # %entry<br>; CMOV32R2-NEXT: mov.d $f0, $f14<br>-; CMOV32R2-NEXT: c.ult.d $f12, $f0<br>+; CMOV32R2-NEXT: c.ult.d $f12, $f14<br>; CMOV32R2-NEXT: jr $ra<br>; CMOV32R2-NEXT: movf.d $f0, $f12, $fcc0<br>;<br>@@ -481,10 +474,9 @@ define double @tst_select_fcmp_oge_doubl<br>;<br>; M3-LABEL: tst_select_fcmp_oge_double:<br>; M3: # %bb.0: # %entry<br>-; M3-NEXT: mov.d $f0, $f12<br>-; M3-NEXT: c.ult.d $f0, $f13<br>+; M3-NEXT: c.ult.d $f12, $f13<br>; M3-NEXT: bc1f .LBB5_2<br>-; M3-NEXT: nop<br>+; M3-NEXT: mov.d $f0, $f12<br>; M3-NEXT: # %bb.1: # %entry<br>; M3-NEXT: mov.d $f0, $f13<br>; M3-NEXT: .LBB5_2: # %entry<br>@@ -494,7 +486,7 @@ define double @tst_select_fcmp_oge_doubl<br>; CMOV64-LABEL: tst_select_fcmp_oge_double:<br>; CMOV64: # %bb.0: # %entry<br>; CMOV64-NEXT: mov.d $f0, $f13<br>-; CMOV64-NEXT: c.ult.d $f12, $f0<br>+; CMOV64-NEXT: c.ult.d $f12, $f13<br>; CMOV64-NEXT: jr $ra<br>; CMOV64-NEXT: movf.d $f0, $f12, $fcc0<br>;<br>@@ -509,7 +501,7 @@ define double @tst_select_fcmp_oge_doubl<br>; MM32R3-LABEL: tst_select_fcmp_oge_double:<br>; MM32R3: # %bb.0: # %entry<br>; MM32R3-NEXT: mov.d $f0, $f14<br>-; MM32R3-NEXT: c.ult.d $f12, $f0<br>+; MM32R3-NEXT: c.ult.d $f12, $f14<br>; MM32R3-NEXT: jr $ra<br>; MM32R3-NEXT: movf.d $f0, $f12, $fcc0<br>;<br>@@ -529,10 +521,9 @@ entry:<br>define double @tst_select_fcmp_oeq_double(double %x, double %y) {<br>; M2-LABEL: tst_select_fcmp_oeq_double:<br>; M2: # %bb.0: # %entry<br>-; M2-NEXT: mov.d $f0, $f12<br>-; M2-NEXT: c.eq.d $f0, $f14<br>+; M2-NEXT: c.eq.d $f12, $f14<br>; M2-NEXT: bc1t $BB6_2<br>-; M2-NEXT: nop<br>+; M2-NEXT: mov.d $f0, $f12<br>; M2-NEXT: # %bb.1: # %entry<br>; M2-NEXT: mov.d $f0, $f14<br>; M2-NEXT: $BB6_2: # %entry<br>@@ -542,14 +533,14 @@ define double @tst_select_fcmp_oeq_doubl<br>; CMOV32R1-LABEL: tst_select_fcmp_oeq_double:<br>; CMOV32R1: # %bb.0: # %entry<br>; CMOV32R1-NEXT: mov.d $f0, $f14<br>-; CMOV32R1-NEXT: c.eq.d $f12, $f0<br>+; CMOV32R1-NEXT: c.eq.d $f12, $f14<br>; CMOV32R1-NEXT: jr $ra<br>; CMOV32R1-NEXT: movt.d $f0, $f12, $fcc0<br>;<br>; CMOV32R2-LABEL: tst_select_fcmp_oeq_double:<br>; CMOV32R2: # %bb.0: # %entry<br>; CMOV32R2-NEXT: mov.d $f0, $f14<br>-; CMOV32R2-NEXT: c.eq.d $f12, $f0<br>+; CMOV32R2-NEXT: c.eq.d $f12, $f14<br>; CMOV32R2-NEXT: jr $ra<br>; CMOV32R2-NEXT: movt.d $f0, $f12, $fcc0<br>;<br>@@ -563,10 +554,9 @@ define double @tst_select_fcmp_oeq_doubl<br>;<br>; M3-LABEL: tst_select_fcmp_oeq_double:<br>; M3: # %bb.0: # %entry<br>-; M3-NEXT: mov.d $f0, $f12<br>-; M3-NEXT: c.eq.d $f0, $f13<br>+; M3-NEXT: c.eq.d $f12, $f13<br>; M3-NEXT: bc1t .LBB6_2<br>-; M3-NEXT: nop<br>+; M3-NEXT: mov.d $f0, $f12<br>; M3-NEXT: # %bb.1: # %entry<br>; M3-NEXT: mov.d $f0, $f13<br>; M3-NEXT: .LBB6_2: # %entry<br>@@ -576,7 +566,7 @@ define double @tst_select_fcmp_oeq_doubl<br>; CMOV64-LABEL: tst_select_fcmp_oeq_double:<br>; CMOV64: # %bb.0: # %entry<br>; CMOV64-NEXT: mov.d $f0, $f13<br>-; CMOV64-NEXT: c.eq.d $f12, $f0<br>+; CMOV64-NEXT: c.eq.d $f12, $f13<br>; CMOV64-NEXT: jr $ra<br>; CMOV64-NEXT: movt.d $f0, $f12, $fcc0<br>;<br>@@ -591,7 +581,7 @@ define double @tst_select_fcmp_oeq_doubl<br>; MM32R3-LABEL: tst_select_fcmp_oeq_double:<br>; MM32R3: # %bb.0: # %entry<br>; MM32R3-NEXT: mov.d $f0, $f14<br>-; MM32R3-NEXT: c.eq.d $f12, $f0<br>+; MM32R3-NEXT: c.eq.d $f12, $f14<br>; MM32R3-NEXT: jr $ra<br>; MM32R3-NEXT: movt.d $f0, $f12, $fcc0<br>;<br>@@ -611,10 +601,9 @@ entry:<br>define double @tst_select_fcmp_one_double(double %x, double %y) {<br>; M2-LABEL: tst_select_fcmp_one_double:<br>; M2: # %bb.0: # %entry<br>-; M2-NEXT: mov.d $f0, $f12<br>-; M2-NEXT: c.ueq.d $f0, $f14<br>+; M2-NEXT: c.ueq.d $f12, $f14<br>; M2-NEXT: bc1f $BB7_2<br>-; M2-NEXT: nop<br>+; M2-NEXT: mov.d $f0, $f12<br>; M2-NEXT: # %bb.1: # %entry<br>; M2-NEXT: mov.d $f0, $f14<br>; M2-NEXT: $BB7_2: # %entry<br>@@ -624,14 +613,14 @@ define double @tst_select_fcmp_one_doubl<br>; CMOV32R1-LABEL: tst_select_fcmp_one_double:<br>; CMOV32R1: # %bb.0: # %entry<br>; CMOV32R1-NEXT: mov.d $f0, $f14<br>-; CMOV32R1-NEXT: c.ueq.d $f12, $f0<br>+; CMOV32R1-NEXT: c.ueq.d $f12, $f14<br>; CMOV32R1-NEXT: jr $ra<br>; CMOV32R1-NEXT: movf.d $f0, $f12, $fcc0<br>;<br>; CMOV32R2-LABEL: tst_select_fcmp_one_double:<br>; CMOV32R2: # %bb.0: # %entry<br>; CMOV32R2-NEXT: mov.d $f0, $f14<br>-; CMOV32R2-NEXT: c.ueq.d $f12, $f0<br>+; CMOV32R2-NEXT: c.ueq.d $f12, $f14<br>; CMOV32R2-NEXT: jr $ra<br>; CMOV32R2-NEXT: movf.d $f0, $f12, $fcc0<br>;<br>@@ -646,10 +635,9 @@ define double @tst_select_fcmp_one_doubl<br>;<br>; M3-LABEL: tst_select_fcmp_one_double:<br>; M3: # %bb.0: # %entry<br>-; M3-NEXT: mov.d $f0, $f12<br>-; M3-NEXT: c.ueq.d $f0, $f13<br>+; M3-NEXT: c.ueq.d $f12, $f13<br>; M3-NEXT: bc1f .LBB7_2<br>-; M3-NEXT: nop<br>+; M3-NEXT: mov.d $f0, $f12<br>; M3-NEXT: # %bb.1: # %entry<br>; M3-NEXT: mov.d $f0, $f13<br>; M3-NEXT: .LBB7_2: # %entry<br>@@ -659,7 +647,7 @@ define double @tst_select_fcmp_one_doubl<br>; CMOV64-LABEL: tst_select_fcmp_one_double:<br>; CMOV64: # %bb.0: # %entry<br>; CMOV64-NEXT: mov.d $f0, $f13<br>-; CMOV64-NEXT: c.ueq.d $f12, $f0<br>+; CMOV64-NEXT: c.ueq.d $f12, $f13<br>; CMOV64-NEXT: jr $ra<br>; CMOV64-NEXT: movf.d $f0, $f12, $fcc0<br>;<br>@@ -675,7 +663,7 @@ define double @tst_select_fcmp_one_doubl<br>; MM32R3-LABEL: tst_select_fcmp_one_double:<br>; MM32R3: # %bb.0: # %entry<br>; MM32R3-NEXT: mov.d $f0, $f14<br>-; MM32R3-NEXT: c.ueq.d $f12, $f0<br>+; MM32R3-NEXT: c.ueq.d $f12, $f14<br>; MM32R3-NEXT: jr $ra<br>; MM32R3-NEXT: movf.d $f0, $f12, $fcc0<br>;<br><br>Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll (original)<br>+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll Tue Feb 27 08:59:10 2018<br>@@ -188,10 +188,9 @@ entry:<br>define float @tst_select_fcmp_olt_float(float %x, float %y) {<br>; M2-LABEL: tst_select_fcmp_olt_float:<br>; M2: # %bb.0: # %entry<br>-; M2-NEXT: mov.s $f0, $f12<br>-; M2-NEXT: c.olt.s $f0, $f14<br>+; M2-NEXT: c.olt.s $f12, $f14<br>; M2-NEXT: bc1t $BB2_2<br>-; M2-NEXT: nop<br>+; M2-NEXT: mov.s $f0, $f12<br>; M2-NEXT: # %bb.1: # %entry<br>; M2-NEXT: mov.s $f0, $f14<br>; M2-NEXT: $BB2_2: # %entry<br>@@ -201,14 +200,14 @@ define float @tst_select_fcmp_olt_float(<br>; CMOV32R1-LABEL: tst_select_fcmp_olt_float:<br>; CMOV32R1: # %bb.0: # %entry<br>; CMOV32R1-NEXT: mov.s $f0, $f14<br>-; CMOV32R1-NEXT: c.olt.s $f12, $f0<br>+; CMOV32R1-NEXT: c.olt.s $f12, $f14<br>; CMOV32R1-NEXT: jr $ra<br>; CMOV32R1-NEXT: movt.s $f0, $f12, $fcc0<br>;<br>; CMOV32R2-LABEL: tst_select_fcmp_olt_float:<br>; CMOV32R2: # %bb.0: # %entry<br>; CMOV32R2-NEXT: mov.s $f0, $f14<br>-; CMOV32R2-NEXT: c.olt.s $f12, $f0<br>+; CMOV32R2-NEXT: c.olt.s $f12, $f14<br>; CMOV32R2-NEXT: jr $ra<br>; CMOV32R2-NEXT: movt.s $f0, $f12, $fcc0<br>;<br>@@ -220,10 +219,9 @@ define float @tst_select_fcmp_olt_float(<br>;<br>; M3-LABEL: tst_select_fcmp_olt_float:<br>; M3: # %bb.0: # %entry<br>-; M3-NEXT: mov.s $f0, $f12<br>-; M3-NEXT: c.olt.s $f0, $f13<br>+; M3-NEXT: c.olt.s $f12, $f13<br>; M3-NEXT: bc1t .LBB2_2<br>-; M3-NEXT: nop<br>+; M3-NEXT: mov.s $f0, $f12<br>; M3-NEXT: # %bb.1: # %entry<br>; M3-NEXT: mov.s $f0, $f13<br>; M3-NEXT: .LBB2_2: # %entry<br>@@ -233,7 +231,7 @@ define float @tst_select_fcmp_olt_float(<br>; CMOV64-LABEL: tst_select_fcmp_olt_float:<br>; CMOV64: # %bb.0: # %entry<br>; CMOV64-NEXT: mov.s $f0, $f13<br>-; CMOV64-NEXT: c.olt.s $f12, $f0<br>+; CMOV64-NEXT: c.olt.s $f12, $f13<br>; CMOV64-NEXT: jr $ra<br>; CMOV64-NEXT: movt.s $f0, $f12, $fcc0<br>;<br>@@ -246,7 +244,7 @@ define float @tst_select_fcmp_olt_float(<br>; MM32R3-LABEL: tst_select_fcmp_olt_float:<br>; MM32R3: # %bb.0: # %entry<br>; MM32R3-NEXT: mov.s $f0, $f14<br>-; MM32R3-NEXT: c.olt.s $f12, $f0<br>+; MM32R3-NEXT: c.olt.s $f12, $f14<br>; MM32R3-NEXT: jr $ra<br>; MM32R3-NEXT: movt.s $f0, $f12, $fcc0<br>;<br>@@ -264,10 +262,9 @@ entry:<br>define float @tst_select_fcmp_ole_float(float %x, float %y) {<br>; M2-LABEL: tst_select_fcmp_ole_float:<br>; M2: # %bb.0: # %entry<br>-; M2-NEXT: mov.s $f0, $f12<br>-; M2-NEXT: c.ole.s $f0, $f14<br>+; M2-NEXT: c.ole.s $f12, $f14<br>; M2-NEXT: bc1t $BB3_2<br>-; M2-NEXT: nop<br>+; M2-NEXT: mov.s $f0, $f12<br>; M2-NEXT: # %bb.1: # %entry<br>; M2-NEXT: mov.s $f0, $f14<br>; M2-NEXT: $BB3_2: # %entry<br>@@ -277,14 +274,14 @@ define float @tst_select_fcmp_ole_float(<br>; CMOV32R1-LABEL: tst_select_fcmp_ole_float:<br>; CMOV32R1: # %bb.0: # %entry<br>; CMOV32R1-NEXT: mov.s $f0, $f14<br>-; CMOV32R1-NEXT: c.ole.s $f12, $f0<br>+; CMOV32R1-NEXT: c.ole.s $f12, $f14<br>; CMOV32R1-NEXT: jr $ra<br>; CMOV32R1-NEXT: movt.s $f0, $f12, $fcc0<br>;<br>; CMOV32R2-LABEL: tst_select_fcmp_ole_float:<br>; CMOV32R2: # %bb.0: # %entry<br>; CMOV32R2-NEXT: mov.s $f0, $f14<br>-; CMOV32R2-NEXT: c.ole.s $f12, $f0<br>+; CMOV32R2-NEXT: c.ole.s $f12, $f14<br>; CMOV32R2-NEXT: jr $ra<br>; CMOV32R2-NEXT: movt.s $f0, $f12, $fcc0<br>;<br>@@ -296,10 +293,9 @@ define float @tst_select_fcmp_ole_float(<br>;<br>; M3-LABEL: tst_select_fcmp_ole_float:<br>; M3: # %bb.0: # %entry<br>-; M3-NEXT: mov.s $f0, $f12<br>-; M3-NEXT: c.ole.s $f0, $f13<br>+; M3-NEXT: c.ole.s $f12, $f13<br>; M3-NEXT: bc1t .LBB3_2<br>-; M3-NEXT: nop<br>+; M3-NEXT: mov.s $f0, $f12<br>; M3-NEXT: # %bb.1: # %entry<br>; M3-NEXT: mov.s $f0, $f13<br>; M3-NEXT: .LBB3_2: # %entry<br>@@ -309,7 +305,7 @@ define float @tst_select_fcmp_ole_float(<br>; CMOV64-LABEL: tst_select_fcmp_ole_float:<br>; CMOV64: # %bb.0: # %entry<br>; CMOV64-NEXT: mov.s $f0, $f13<br>-; CMOV64-NEXT: c.ole.s $f12, $f0<br>+; CMOV64-NEXT: c.ole.s $f12, $f13<br>; CMOV64-NEXT: jr $ra<br>; CMOV64-NEXT: movt.s $f0, $f12, $fcc0<br>;<br>@@ -322,7 +318,7 @@ define float @tst_select_fcmp_ole_float(<br>; MM32R3-LABEL: tst_select_fcmp_ole_float:<br>; MM32R3: # %bb.0: # %entry<br>; MM32R3-NEXT: mov.s $f0, $f14<br>-; MM32R3-NEXT: c.ole.s $f12, $f0<br>+; MM32R3-NEXT: c.ole.s $f12, $f14<br>; MM32R3-NEXT: jr $ra<br>; MM32R3-NEXT: movt.s $f0, $f12, $fcc0<br>;<br>@@ -340,10 +336,9 @@ entry:<br>define float @tst_select_fcmp_ogt_float(float %x, float %y) {<br>; M2-LABEL: tst_select_fcmp_ogt_float:<br>; M2: # %bb.0: # %entry<br>-; M2-NEXT: mov.s $f0, $f12<br>-; M2-NEXT: c.ule.s $f0, $f14<br>+; M2-NEXT: c.ule.s $f12, $f14<br>; M2-NEXT: bc1f $BB4_2<br>-; M2-NEXT: nop<br>+; M2-NEXT: mov.s $f0, $f12<br>; M2-NEXT: # %bb.1: # %entry<br>; M2-NEXT: mov.s $f0, $f14<br>; M2-NEXT: $BB4_2: # %entry<br>@@ -353,14 +348,14 @@ define float @tst_select_fcmp_ogt_float(<br>; CMOV32R1-LABEL: tst_select_fcmp_ogt_float:<br>; CMOV32R1: # %bb.0: # %entry<br>; CMOV32R1-NEXT: mov.s $f0, $f14<br>-; CMOV32R1-NEXT: c.ule.s $f12, $f0<br>+; CMOV32R1-NEXT: c.ule.s $f12, $f14<br>; CMOV32R1-NEXT: jr $ra<br>; CMOV32R1-NEXT: movf.s $f0, $f12, $fcc0<br>;<br>; CMOV32R2-LABEL: tst_select_fcmp_ogt_float:<br>; CMOV32R2: # %bb.0: # %entry<br>; CMOV32R2-NEXT: mov.s $f0, $f14<br>-; CMOV32R2-NEXT: c.ule.s $f12, $f0<br>+; CMOV32R2-NEXT: c.ule.s $f12, $f14<br>; CMOV32R2-NEXT: jr $ra<br>; CMOV32R2-NEXT: movf.s $f0, $f12, $fcc0<br>;<br>@@ -372,10 +367,9 @@ define float @tst_select_fcmp_ogt_float(<br>;<br>; M3-LABEL: tst_select_fcmp_ogt_float:<br>; M3: # %bb.0: # %entry<br>-; M3-NEXT: mov.s $f0, $f12<br>-; M3-NEXT: c.ule.s $f0, $f13<br>+; M3-NEXT: c.ule.s $f12, $f13<br>; M3-NEXT: bc1f .LBB4_2<br>-; M3-NEXT: nop<br>+; M3-NEXT: mov.s $f0, $f12<br>; M3-NEXT: # %bb.1: # %entry<br>; M3-NEXT: mov.s $f0, $f13<br>; M3-NEXT: .LBB4_2: # %entry<br>@@ -385,7 +379,7 @@ define float @tst_select_fcmp_ogt_float(<br>; CMOV64-LABEL: tst_select_fcmp_ogt_float:<br>; CMOV64: # %bb.0: # %entry<br>; CMOV64-NEXT: mov.s $f0, $f13<br>-; CMOV64-NEXT: c.ule.s $f12, $f0<br>+; CMOV64-NEXT: c.ule.s $f12, $f13<br>; CMOV64-NEXT: jr $ra<br>; CMOV64-NEXT: movf.s $f0, $f12, $fcc0<br>;<br>@@ -398,7 +392,7 @@ define float @tst_select_fcmp_ogt_float(<br>; MM32R3-LABEL: tst_select_fcmp_ogt_float:<br>; MM32R3: # %bb.0: # %entry<br>; MM32R3-NEXT: mov.s $f0, $f14<br>-; MM32R3-NEXT: c.ule.s $f12, $f0<br>+; MM32R3-NEXT: c.ule.s $f12, $f14<br>; MM32R3-NEXT: jr $ra<br>; MM32R3-NEXT: movf.s $f0, $f12, $fcc0<br>;<br>@@ -416,10 +410,9 @@ entry:<br>define float @tst_select_fcmp_oge_float(float %x, float %y) {<br>; M2-LABEL: tst_select_fcmp_oge_float:<br>; M2: # %bb.0: # %entry<br>-; M2-NEXT: mov.s $f0, $f12<br>-; M2-NEXT: c.ult.s $f0, $f14<br>+; M2-NEXT: c.ult.s $f12, $f14<br>; M2-NEXT: bc1f $BB5_2<br>-; M2-NEXT: nop<br>+; M2-NEXT: mov.s $f0, $f12<br>; M2-NEXT: # %bb.1: # %entry<br>; M2-NEXT: mov.s $f0, $f14<br>; M2-NEXT: $BB5_2: # %entry<br>@@ -429,14 +422,14 @@ define float @tst_select_fcmp_oge_float(<br>; CMOV32R1-LABEL: tst_select_fcmp_oge_float:<br>; CMOV32R1: # %bb.0: # %entry<br>; CMOV32R1-NEXT: mov.s $f0, $f14<br>-; CMOV32R1-NEXT: c.ult.s $f12, $f0<br>+; CMOV32R1-NEXT: c.ult.s $f12, $f14<br>; CMOV32R1-NEXT: jr $ra<br>; CMOV32R1-NEXT: movf.s $f0, $f12, $fcc0<br>;<br>; CMOV32R2-LABEL: tst_select_fcmp_oge_float:<br>; CMOV32R2: # %bb.0: # %entry<br>; CMOV32R2-NEXT: mov.s $f0, $f14<br>-; CMOV32R2-NEXT: c.ult.s $f12, $f0<br>+; CMOV32R2-NEXT: c.ult.s $f12, $f14<br>; CMOV32R2-NEXT: jr $ra<br>; CMOV32R2-NEXT: movf.s $f0, $f12, $fcc0<br>;<br>@@ -448,10 +441,9 @@ define float @tst_select_fcmp_oge_float(<br>;<br>; M3-LABEL: tst_select_fcmp_oge_float:<br>; M3: # %bb.0: # %entry<br>-; M3-NEXT: mov.s $f0, $f12<br>-; M3-NEXT: c.ult.s $f0, $f13<br>+; M3-NEXT: c.ult.s $f12, $f13<br>; M3-NEXT: bc1f .LBB5_2<br>-; M3-NEXT: nop<br>+; M3-NEXT: mov.s $f0, $f12<br>; M3-NEXT: # %bb.1: # %entry<br>; M3-NEXT: mov.s $f0, $f13<br>; M3-NEXT: .LBB5_2: # %entry<br>@@ -461,7 +453,7 @@ define float @tst_select_fcmp_oge_float(<br>; CMOV64-LABEL: tst_select_fcmp_oge_float:<br>; CMOV64: # %bb.0: # %entry<br>; CMOV64-NEXT: mov.s $f0, $f13<br>-; CMOV64-NEXT: c.ult.s $f12, $f0<br>+; CMOV64-NEXT: c.ult.s $f12, $f13<br>; CMOV64-NEXT: jr $ra<br>; CMOV64-NEXT: movf.s $f0, $f12, $fcc0<br>;<br>@@ -474,7 +466,7 @@ define float @tst_select_fcmp_oge_float(<br>; MM32R3-LABEL: tst_select_fcmp_oge_float:<br>; MM32R3: # %bb.0: # %entry<br>; MM32R3-NEXT: mov.s $f0, $f14<br>-; MM32R3-NEXT: c.ult.s $f12, $f0<br>+; MM32R3-NEXT: c.ult.s $f12, $f14<br>; MM32R3-NEXT: jr $ra<br>; MM32R3-NEXT: movf.s $f0, $f12, $fcc0<br>;<br>@@ -492,10 +484,9 @@ entry:<br>define float @tst_select_fcmp_oeq_float(float %x, float %y) {<br>; M2-LABEL: tst_select_fcmp_oeq_float:<br>; M2: # %bb.0: # %entry<br>-; M2-NEXT: mov.s $f0, $f12<br>-; M2-NEXT: c.eq.s $f0, $f14<br>+; M2-NEXT: c.eq.s $f12, $f14<br>; M2-NEXT: bc1t $BB6_2<br>-; M2-NEXT: nop<br>+; M2-NEXT: mov.s $f0, $f12<br>; M2-NEXT: # %bb.1: # %entry<br>; M2-NEXT: mov.s $f0, $f14<br>; M2-NEXT: $BB6_2: # %entry<br>@@ -505,14 +496,14 @@ define float @tst_select_fcmp_oeq_float(<br>; CMOV32R1-LABEL: tst_select_fcmp_oeq_float:<br>; CMOV32R1: # %bb.0: # %entry<br>; CMOV32R1-NEXT: mov.s $f0, $f14<br>-; CMOV32R1-NEXT: c.eq.s $f12, $f0<br>+; CMOV32R1-NEXT: c.eq.s $f12, $f14<br>; CMOV32R1-NEXT: jr $ra<br>; CMOV32R1-NEXT: movt.s $f0, $f12, $fcc0<br>;<br>; CMOV32R2-LABEL: tst_select_fcmp_oeq_float:<br>; CMOV32R2: # %bb.0: # %entry<br>; CMOV32R2-NEXT: mov.s $f0, $f14<br>-; CMOV32R2-NEXT: c.eq.s $f12, $f0<br>+; CMOV32R2-NEXT: c.eq.s $f12, $f14<br>; CMOV32R2-NEXT: jr $ra<br>; CMOV32R2-NEXT: movt.s $f0, $f12, $fcc0<br>;<br>@@ -524,10 +515,9 @@ define float @tst_select_fcmp_oeq_float(<br>;<br>; M3-LABEL: tst_select_fcmp_oeq_float:<br>; M3: # %bb.0: # %entry<br>-; M3-NEXT: mov.s $f0, $f12<br>-; M3-NEXT: c.eq.s $f0, $f13<br>+; M3-NEXT: c.eq.s $f12, $f13<br>; M3-NEXT: bc1t .LBB6_2<br>-; M3-NEXT: nop<br>+; M3-NEXT: mov.s $f0, $f12<br>; M3-NEXT: # %bb.1: # %entry<br>; M3-NEXT: mov.s $f0, $f13<br>; M3-NEXT: .LBB6_2: # %entry<br>@@ -537,7 +527,7 @@ define float @tst_select_fcmp_oeq_float(<br>; CMOV64-LABEL: tst_select_fcmp_oeq_float:<br>; CMOV64: # %bb.0: # %entry<br>; CMOV64-NEXT: mov.s $f0, $f13<br>-; CMOV64-NEXT: c.eq.s $f12, $f0<br>+; CMOV64-NEXT: c.eq.s $f12, $f13<br>; CMOV64-NEXT: jr $ra<br>; CMOV64-NEXT: movt.s $f0, $f12, $fcc0<br>;<br>@@ -550,7 +540,7 @@ define float @tst_select_fcmp_oeq_float(<br>; MM32R3-LABEL: tst_select_fcmp_oeq_float:<br>; MM32R3: # %bb.0: # %entry<br>; MM32R3-NEXT: mov.s $f0, $f14<br>-; MM32R3-NEXT: c.eq.s $f12, $f0<br>+; MM32R3-NEXT: c.eq.s $f12, $f14<br>; MM32R3-NEXT: jr $ra<br>; MM32R3-NEXT: movt.s $f0, $f12, $fcc0<br>;<br>@@ -568,10 +558,9 @@ entry:<br>define float @tst_select_fcmp_one_float(float %x, float %y) {<br>; M2-LABEL: tst_select_fcmp_one_float:<br>; M2: # %bb.0: # %entry<br>-; M2-NEXT: mov.s $f0, $f12<br>-; M2-NEXT: c.ueq.s $f0, $f14<br>+; M2-NEXT: c.ueq.s $f12, $f14<br>; M2-NEXT: bc1f $BB7_2<br>-; M2-NEXT: nop<br>+; M2-NEXT: mov.s $f0, $f12<br>; M2-NEXT: # %bb.1: # %entry<br>; M2-NEXT: mov.s $f0, $f14<br>; M2-NEXT: $BB7_2: # %entry<br>@@ -581,14 +570,14 @@ define float @tst_select_fcmp_one_float(<br>; CMOV32R1-LABEL: tst_select_fcmp_one_float:<br>; CMOV32R1: # %bb.0: # %entry<br>; CMOV32R1-NEXT: mov.s $f0, $f14<br>-; CMOV32R1-NEXT: c.ueq.s $f12, $f0<br>+; CMOV32R1-NEXT: c.ueq.s $f12, $f14<br>; CMOV32R1-NEXT: jr $ra<br>; CMOV32R1-NEXT: movf.s $f0, $f12, $fcc0<br>;<br>; CMOV32R2-LABEL: tst_select_fcmp_one_float:<br>; CMOV32R2: # %bb.0: # %entry<br>; CMOV32R2-NEXT: mov.s $f0, $f14<br>-; CMOV32R2-NEXT: c.ueq.s $f12, $f0<br>+; CMOV32R2-NEXT: c.ueq.s $f12, $f14<br>; CMOV32R2-NEXT: jr $ra<br>; CMOV32R2-NEXT: movf.s $f0, $f12, $fcc0<br>;<br>@@ -603,10 +592,9 @@ define float @tst_select_fcmp_one_float(<br>;<br>; M3-LABEL: tst_select_fcmp_one_float:<br>; M3: # %bb.0: # %entry<br>-; M3-NEXT: mov.s $f0, $f12<br>-; M3-NEXT: c.ueq.s $f0, $f13<br>+; M3-NEXT: c.ueq.s $f12, $f13<br>; M3-NEXT: bc1f .LBB7_2<br>-; M3-NEXT: nop<br>+; M3-NEXT: mov.s $f0, $f12<br>; M3-NEXT: # %bb.1: # %entry<br>; M3-NEXT: mov.s $f0, $f13<br>; M3-NEXT: .LBB7_2: # %entry<br>@@ -616,7 +604,7 @@ define float @tst_select_fcmp_one_float(<br>; CMOV64-LABEL: tst_select_fcmp_one_float:<br>; CMOV64: # %bb.0: # %entry<br>; CMOV64-NEXT: mov.s $f0, $f13<br>-; CMOV64-NEXT: c.ueq.s $f12, $f0<br>+; CMOV64-NEXT: c.ueq.s $f12, $f13<br>; CMOV64-NEXT: jr $ra<br>; CMOV64-NEXT: movf.s $f0, $f12, $fcc0<br>;<br>@@ -632,7 +620,7 @@ define float @tst_select_fcmp_one_float(<br>; MM32R3-LABEL: tst_select_fcmp_one_float:<br>; MM32R3: # %bb.0: # %entry<br>; MM32R3-NEXT: mov.s $f0, $f14<br>-; MM32R3-NEXT: c.ueq.s $f12, $f0<br>+; MM32R3-NEXT: c.ueq.s $f12, $f14<br>; MM32R3-NEXT: jr $ra<br>; MM32R3-NEXT: movf.s $f0, $f12, $fcc0<br>;<br><br>Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll (original)<br>+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll Tue Feb 27 08:59:10 2018<br>@@ -857,7 +857,7 @@ define signext i128 @shl_i128(i128 signe<br>; MMR3-NEXT: sw $5, 32($sp) # 4-byte Folded Spill<br>; MMR3-NEXT: move $1, $4<br>; MMR3-NEXT: lw $16, 76($sp)<br>-; MMR3-NEXT: sllv $2, $1, $16<br>+; MMR3-NEXT: sllv $2, $4, $16<br>; MMR3-NEXT: not16 $4, $16<br>; MMR3-NEXT: sw $4, 24($sp) # 4-byte Folded Spill<br>; MMR3-NEXT: srl16 $3, $5, 1<br>@@ -945,7 +945,7 @@ define signext i128 @shl_i128(i128 signe<br>; MMR6-NEXT: .cfi_offset 16, -8<br>; MMR6-NEXT: move $11, $4<br>; MMR6-NEXT: lw $3, 44($sp)<br>-; MMR6-NEXT: sllv $1, $11, $3<br>+; MMR6-NEXT: sllv $1, $4, $3<br>; MMR6-NEXT: not16 $2, $3<br>; MMR6-NEXT: sw $2, 4($sp) # 4-byte Folded Spill<br>; MMR6-NEXT: srl16 $16, $5, 1<br><br>Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll (original)<br>+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll Tue Feb 27 08:59:10 2018<br>@@ -163,7 +163,7 @@ entry:<br>; MMR3: subu16 $5, $[[T19]], $[[T20]]<br><br>; MMR6: move $[[T0:[0-9]+]], $7<br>-; MMR6: sw $[[T0]], 8($sp)<br>+; MMR6: sw $7, 8($sp)<br>; MMR6: move $[[T1:[0-9]+]], $5<br>; MMR6: sw $4, 12($sp)<br>; MMR6: lw $[[T2:[0-9]+]], 48($sp)<br><br>Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll (original)<br>+++ llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll Tue Feb 27 08:59:10 2018<br>@@ -193,7 +193,7 @@ define void @f4(float %f, %struct.S3* no<br>; CHECK-NEXT: move $4, $7<br>; CHECK-NEXT: sw $5, 52($sp)<br>; CHECK-NEXT: sw $6, 56($sp)<br>-; CHECK-NEXT: sw $4, 60($sp)<br>+; CHECK-NEXT: sw $7, 60($sp)<br>; CHECK-NEXT: lw $1, 80($sp)<br>; CHECK-NEXT: lb $2, 52($sp)<br>; CHECK-NEXT: addiu $3, $zero, 4<br><br>Modified: llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll (original)<br>+++ llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll Tue Feb 27 08:59:10 2018<br>@@ -20,9 +20,9 @@ define noalias i8* @_ZN2CC3funEv(%class.<br>; CHECK-NEXT: .cfi_def_cfa_offset 48<br>; CHECK-NEXT: .cfi_offset lr, 16<br>; CHECK-NEXT: .cfi_offset r30, -16<br>+; CHECK-NEXT: ld 12, 0(3)<br>; CHECK-NEXT: std 30, 32(1)<br>; CHECK-NEXT: mr 30, 3<br>-; CHECK-NEXT: ld 12, 0(30)<br>; CHECK-NEXT: std 2, 24(1)<br>; CHECK-NEXT: mtctr 12<br>; CHECK-NEXT: bctrl<br><br>Modified: llvm/trunk/test/CodeGen/PowerPC/fma-mutate.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fma-mutate.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fma-mutate.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/PowerPC/fma-mutate.ll (original)<br>+++ llvm/trunk/test/CodeGen/PowerPC/fma-mutate.ll Tue Feb 27 08:59:10 2018<br>@@ -14,7 +14,8 @@ define double @foo3(double %a) nounwind<br> ret double %r<br><br>; CHECK: @foo3<br>-; CHECK: xsnmsubadp [[REG:[0-9]+]], {{[0-9]+}}, [[REG]]<br>+; CHECK: fmr [[REG:[0-9]+]], [[REG2:[0-9]+]]<br>+; CHECK: xsnmsubadp [[REG]], {{[0-9]+}}, [[REG2]]<br>; CHECK: xsmaddmdp<br>; CHECK: xsmaddadp<br>}<br><br>Modified: llvm/trunk/test/CodeGen/PowerPC/gpr-vsr-spill.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/gpr-vsr-spill.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/gpr-vsr-spill.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/PowerPC/gpr-vsr-spill.ll (original)<br>+++ llvm/trunk/test/CodeGen/PowerPC/gpr-vsr-spill.ll Tue Feb 27 08:59:10 2018<br>@@ -16,8 +16,8 @@ if.end:<br> ret i32 %e.0<br>; CHECK: @foo<br>; CHECK: mr [[NEWREG:[0-9]+]], 3<br>+; CHECK: mr [[REG1:[0-9]+]], 4<br>; CHECK: mtvsrd [[NEWREG2:[0-9]+]], 4<br>-; CHECK: mffprd [[REG1:[0-9]+]], [[NEWREG2]]<br>; CHECK: add {{[0-9]+}}, [[NEWREG]], [[REG1]]<br>; CHECK: mffprd [[REG2:[0-9]+]], [[NEWREG2]]<br>; CHECK: add {{[0-9]+}}, [[REG2]], [[NEWREG]]<br><br>Modified: llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll (original)<br>+++ llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll Tue Feb 27 08:59:10 2018<br>@@ -20,8 +20,8 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(<br>define linkonce_odr void @ZN6snappyDecompressor_(%"class.snappy::SnappyDecompressor"* %this, %"class.snappy::SnappyIOVecWriter"* %writer) {<br>; CHECK-LABEL: ZN6snappyDecompressor_:<br>; CHECK: # %bb.0: # %entry<br>-; CHECK: addis 3, 2, _ZN6snappy8internalL8wordmaskE@toc@ha<br>-; CHECK-DAG: addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l<br>+; CHECK: addis 23, 2, _ZN6snappy8internalL8wordmaskE@toc@ha<br>+; CHECK-DAG: addi 25, 23, _ZN6snappy8internalL8wordmaskE@toc@l<br>; CHECK-DAG: addis 5, 2, _ZN6snappy8internalL10char_tableE@toc@ha<br>; CHECK-DAG: addi 24, 5, _ZN6snappy8internalL10char_tableE@toc@l<br>; CHECK: b .LBB0_2<br><br>Modified: llvm/trunk/test/CodeGen/PowerPC/opt-li-add-to-addi.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/opt-li-add-to-addi.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/opt-li-add-to-addi.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/PowerPC/opt-li-add-to-addi.ll (original)<br>+++ llvm/trunk/test/CodeGen/PowerPC/opt-li-add-to-addi.ll Tue Feb 27 08:59:10 2018<br>@@ -3,7 +3,7 @@<br><br>define i64 @testOptimizeLiAddToAddi(i64 %a) {<br>; CHECK-LABEL: testOptimizeLiAddToAddi:<br>-; CHECK: addi 3, 30, 2444<br>+; CHECK: addi 3, 3, 2444<br>; CHECK: bl callv<br>; CHECK: addi 3, 30, 234<br>; CHECK: bl call<br><br>Modified: llvm/trunk/test/CodeGen/PowerPC/tail-dup-layout.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tail-dup-layout.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tail-dup-layout.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/PowerPC/tail-dup-layout.ll (original)<br>+++ llvm/trunk/test/CodeGen/PowerPC/tail-dup-layout.ll Tue Feb 27 08:59:10 2018<br>@@ -25,7 +25,7 @@ target triple = "powerpc64le-grtev4-linu<br>;CHECK-LABEL: straight_test:<br>; test1 may have been merged with entry<br>;CHECK: mr [[TAGREG:[0-9]+]], 3<br>-;CHECK: andi. {{[0-9]+}}, [[TAGREG]], 1<br>+;CHECK: andi. {{[0-9]+}}, [[TAGREG:[0-9]+]], 1<br>;CHECK-NEXT: bc 12, 1, .[[OPT1LABEL:[_0-9A-Za-z]+]]<br>;CHECK-NEXT: # %test2<br>;CHECK-NEXT: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 30, 30<br><br>Modified: llvm/trunk/test/CodeGen/SPARC/32abi.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/32abi.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/32abi.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/SPARC/32abi.ll (original)<br>+++ llvm/trunk/test/CodeGen/SPARC/32abi.ll Tue Feb 27 08:59:10 2018<br>@@ -148,9 +148,9 @@ define double @floatarg(double %a0, ;<br>; HARD-NEXT: std %o0, [%sp+96]<br>; HARD-NEXT: st %o1, [%sp+92]<br>; HARD-NEXT: mov %i0, %o2<br>-; HARD-NEXT: mov %o0, %o3<br>+; HARD-NEXT: mov %i1, %o3<br>; HARD-NEXT: mov %o1, %o4<br>-; HARD-NEXT: mov %o0, %o5<br>+; HARD-NEXT: mov %i1, %o5<br>; HARD-NEXT: call floatarg<br>; HARD: std %f0, [%i4]<br>; SOFT: st %i0, [%sp+104]<br><br>Modified: llvm/trunk/test/CodeGen/SPARC/atomics.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/atomics.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/atomics.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/SPARC/atomics.ll (original)<br>+++ llvm/trunk/test/CodeGen/SPARC/atomics.ll Tue Feb 27 08:59:10 2018<br>@@ -235,8 +235,9 @@ entry:<br><br>; CHECK-LABEL: test_load_add_i32<br>; CHECK: membar<br>-; CHECK: add [[V:%[gilo][0-7]]], %o1, [[U:%[gilo][0-7]]]<br>-; CHECK: cas [%o0], [[V]], [[U]]<br>+; CHECK: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]<br>+; CHECK: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]<br>+; CHECK: cas [%o0], [[V]], [[V2]]<br>; CHECK: membar<br>define zeroext i32 @test_load_add_i32(i32* %p, i32 zeroext %v) {<br>entry:<br><br>Modified: llvm/trunk/test/CodeGen/SystemZ/vec-sub-01.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-sub-01.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-sub-01.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/SystemZ/vec-sub-01.ll (original)<br>+++ llvm/trunk/test/CodeGen/SystemZ/vec-sub-01.ll Tue Feb 27 08:59:10 2018<br>@@ -46,12 +46,12 @@ define <4 x float> @f5(<4 x float> %val1<br>; CHECK-LABEL: f5:<br>; CHECK-DAG: vlr %v[[A1:[0-5]]], %v24<br>; CHECK-DAG: vlr %v[[A2:[0-5]]], %v26<br>-; CHECK-DAG: vrepf %v[[B1:[0-5]]], %v[[A1]], 1<br>-; CHECK-DAG: vrepf %v[[B2:[0-5]]], %v[[A2]], 1<br>-; CHECK-DAG: vrepf %v[[C1:[0-5]]], %v[[A1]], 2<br>-; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v[[A2]], 2<br>-; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v[[A1]], 3<br>-; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v[[A2]], 3<br>+; CHECK-DAG: vrepf %v[[B1:[0-5]]], %v24, 1<br>+; CHECK-DAG: vrepf %v[[B2:[0-5]]], %v26, 1<br>+; CHECK-DAG: vrepf %v[[C1:[0-5]]], %v24, 2<br>+; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v26, 2<br>+; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v24, 3<br>+; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v26, 3<br>; CHECK-DAG: sebr %f[[A1]], %f[[A2]]<br>; CHECK-DAG: sebr %f[[B1]], %f[[B2]]<br>; CHECK-DAG: sebr %f[[C1]], %f[[C2]]<br><br>Modified: llvm/trunk/test/CodeGen/Thumb/pr35836.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/pr35836.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/pr35836.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Thumb/pr35836.ll (original)<br>+++ llvm/trunk/test/CodeGen/Thumb/pr35836.ll Tue Feb 27 08:59:10 2018<br>@@ -37,13 +37,13 @@ while.body:<br>; CHECK: adds<span class=apple-tab-span> </span><span class=apple-converted-space> </span>r3, r0, r1<br>; CHECK: push<span class=apple-tab-span> </span><span class=apple-converted-space> </span>{r5}<br>; CHECK: pop<span class=apple-tab-span> </span><span class=apple-converted-space> </span>{r1}<br>-; CHECK: adcs<span class=apple-converted-space> </span>r1, r1<br>+; CHECK: adcs<span class=apple-converted-space> </span>r1, r5<br>; CHECK: ldr<span class=apple-tab-span> </span><span class=apple-converted-space> </span>r0, [sp, #12] @ 4-byte Reload<br>; CHECK: ldr<span class=apple-tab-span> </span><span class=apple-converted-space> </span>r2, [sp, #8] @ 4-byte Reload<br>; CHECK: adds<span class=apple-tab-span> </span><span class=apple-converted-space> </span>r2, r0, r2<br>; CHECK: push<span class=apple-tab-span> </span><span class=apple-converted-space> </span>{r5}<br>; CHECK: pop<span class=apple-tab-span> </span><span class=apple-converted-space> </span>{r4}<br>-; CHECK: adcs<span class=apple-converted-space> </span>r4, r4<br>+; CHECK: adcs<span class=apple-converted-space> </span>r4, r5<br>; CHECK: adds<span class=apple-tab-span> </span><span class=apple-converted-space> </span>r0, r2, r5<br>; CHECK: push<span class=apple-tab-span> </span><span class=apple-converted-space> </span>{r3}<br>; CHECK: pop<span class=apple-tab-span> </span><span class=apple-converted-space> </span>{r0}<br><br>Modified: llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll (original)<br>+++ llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll Tue Feb 27 08:59:10 2018<br>@@ -598,7 +598,7 @@ declare void @abort() #0<br>define i32 @b_to_bx(i32 %value) {<br>; CHECK-LABEL: b_to_bx:<br>; DISABLE: push {r7, lr}<br>-; CHECK: cmp r1, #49<br>+; CHECK: cmp r0, #49<br>; CHECK-NEXT: bgt [[ELSE_LABEL:LBB[0-9_]+]]<br>; ENABLE: push {r7, lr}<br><br><br>Modified: llvm/trunk/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll Tue Feb 27 08:59:10 2018<br>@@ -7,7 +7,7 @@ define i32 @f(i32 %a, i32 %b) {<br>; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx<br>; CHECK-NEXT: movl %ecx, %edx<br>-; CHECK-NEXT: imull %edx, %edx<br>+; CHECK-NEXT: imull %ecx, %edx<br>; CHECK-NEXT: imull %eax, %ecx<br>; CHECK-NEXT: imull %eax, %eax<br>; CHECK-NEXT: addl %edx, %eax<br><br>Modified: llvm/trunk/test/CodeGen/X86/arg-copy-elide.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/arg-copy-elide.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/arg-copy-elide.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/arg-copy-elide.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/arg-copy-elide.ll Tue Feb 27 08:59:10 2018<br>@@ -106,7 +106,7 @@ entry:<br>; CHECK-DAG: movl %edx, %[[r1:[^ ]*]]<br>; CHECK-DAG: movl 8(%ebp), %[[r2:[^ ]*]]<br>; CHECK-DAG: movl %[[r2]], 4(%esp)<br>-; CHECK-DAG: movl %[[r1]], (%esp)<br>+; CHECK-DAG: movl %edx, (%esp)<br>; CHECK: movl %esp, %[[reg:[^ ]*]]<br>; CHECK: pushl %[[reg]]<br>; CHECK: calll _addrof_i64<br><br>Modified: llvm/trunk/test/CodeGen/X86/avg.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avg.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avg.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/avg.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/avg.ll Tue Feb 27 08:59:10 2018<br>@@ -2222,7 +2222,7 @@ define void @not_avg_v16i8_wide_constant<br>; SSE2-NEXT: movq %rax, %xmm11<br>; SSE2-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload<br>; SSE2-NEXT: movq %rbp, %rcx<br>-; SSE2-NEXT: shrdq $1, %rcx, %rax<br>+; SSE2-NEXT: shrdq $1, %rbp, %rax<br>; SSE2-NEXT: pslldq {{.*#+}} xmm13 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm13[0,1,2]<br>; SSE2-NEXT: punpcklqdq {{.*#+}} xmm15 = xmm15[0],xmm8[0]<br>; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255]<br><br>Modified: llvm/trunk/test/CodeGen/X86/avx-load-store.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-load-store.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-load-store.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/avx-load-store.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/avx-load-store.ll Tue Feb 27 08:59:10 2018<br>@@ -12,11 +12,11 @@ define void @test_256_load(double* nocap<br>; CHECK-NEXT: movq %rdx, %r14<br>; CHECK-NEXT: movq %rsi, %r15<br>; CHECK-NEXT: movq %rdi, %rbx<br>-; CHECK-NEXT: vmovaps (%rbx), %ymm0<br>+; CHECK-NEXT: vmovaps (%rdi), %ymm0<br>; CHECK-NEXT: vmovups %ymm0, {{[0-9]+}}(%rsp) # 32-byte Spill<br>-; CHECK-NEXT: vmovaps (%r15), %ymm1<br>+; CHECK-NEXT: vmovaps (%rsi), %ymm1<br>; CHECK-NEXT: vmovups %ymm1, {{[0-9]+}}(%rsp) # 32-byte Spill<br>-; CHECK-NEXT: vmovaps (%r14), %ymm2<br>+; CHECK-NEXT: vmovaps (%rdx), %ymm2<br>; CHECK-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill<br>; CHECK-NEXT: callq dummy<br>; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload<br><br>Modified: llvm/trunk/test/CodeGen/X86/avx512-bugfix-25270.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-bugfix-25270.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-bugfix-25270.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/avx512-bugfix-25270.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/avx512-bugfix-25270.ll Tue Feb 27 08:59:10 2018<br>@@ -9,10 +9,10 @@ define void @bar__512(<16 x i32>* %var)<br>; CHECK-NEXT: pushq %rbx<br>; CHECK-NEXT: subq $112, %rsp<br>; CHECK-NEXT: movq %rdi, %rbx<br>-; CHECK-NEXT: vmovups (%rbx), %zmm0<br>+; CHECK-NEXT: vmovups (%rdi), %zmm0<br>; CHECK-NEXT: vmovups %zmm0, (%rsp) ## 64-byte Spill<br>; CHECK-NEXT: vbroadcastss {{.*}}(%rip), %zmm1<br>-; CHECK-NEXT: vmovaps %zmm1, (%rbx)<br>+; CHECK-NEXT: vmovaps %zmm1, (%rdi)<br>; CHECK-NEXT: callq _Print__512<br>; CHECK-NEXT: vmovups (%rsp), %zmm0 ## 64-byte Reload<br>; CHECK-NEXT: callq _Print__512<br><br>Modified: llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll Tue Feb 27 08:59:10 2018<br>@@ -355,7 +355,7 @@ define i32 @test12(i32 %a1, i32 %a2, i32<br>; KNL_X32-NEXT: movl %edi, (%esp)<br>; KNL_X32-NEXT: calll _test11<br>; KNL_X32-NEXT: movl %eax, %ebx<br>-; KNL_X32-NEXT: movzbl %bl, %eax<br>+; KNL_X32-NEXT: movzbl %al, %eax<br>; KNL_X32-NEXT: movl %eax, {{[0-9]+}}(%esp)<br>; KNL_X32-NEXT: movl %esi, {{[0-9]+}}(%esp)<br>; KNL_X32-NEXT: movl %edi, (%esp)<br><br>Modified: llvm/trunk/test/CodeGen/X86/avx512-intel-ocl.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intel-ocl.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intel-ocl.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/avx512-intel-ocl.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/avx512-intel-ocl.ll Tue Feb 27 08:59:10 2018<br>@@ -148,7 +148,7 @@ define <16 x float> @testf16_regs(<16 x<br>; X64-NEXT: andq $-64, %rsp<br>; X64-NEXT: subq $128, %rsp<br>; X64-NEXT: vmovaps %zmm1, %zmm16<br>-; X64-NEXT: vaddps %zmm16, %zmm0, %zmm0<br>+; X64-NEXT: vaddps %zmm1, %zmm0, %zmm0<br>; X64-NEXT: movq %rsp, %rdi<br>; X64-NEXT: callq _func_float16_ptr<br>; X64-NEXT: vaddps %zmm16, %zmm0, %zmm0<br><br>Modified: llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll Tue Feb 27 08:59:10 2018<br>@@ -650,7 +650,7 @@ define x86_regcallcc <4 x i32> @test_Cal<br>; X32-NEXT: subl $24, %esp<br>; X32-NEXT: vmovups %xmm4, (%esp) # 16-byte Spill<br>; X32-NEXT: vmovdqa %xmm0, %xmm4<br>-; X32-NEXT: vmovdqa %xmm4, %xmm1<br>+; X32-NEXT: vmovdqa %xmm0, %xmm1<br>; X32-NEXT: calll _test_argRet128Vector<br>; X32-NEXT: vmovdqa32 %xmm4, %xmm0 {%k1}<br>; X32-NEXT: vmovups (%esp), %xmm4 # 16-byte Reload<br>@@ -668,7 +668,7 @@ define x86_regcallcc <4 x i32> @test_Cal<br>; WIN64-NEXT: .seh_savexmm 8, 0<br>; WIN64-NEXT: .seh_endprologue<br>; WIN64-NEXT: vmovdqa %xmm0, %xmm8<br>-; WIN64-NEXT: vmovdqa %xmm8, %xmm1<br>+; WIN64-NEXT: vmovdqa %xmm0, %xmm1<br>; WIN64-NEXT: callq test_argRet128Vector<br>; WIN64-NEXT: vmovdqa32 %xmm8, %xmm0 {%k1}<br>; WIN64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload<br>@@ -689,7 +689,7 @@ define x86_regcallcc <4 x i32> @test_Cal<br>; LINUXOSX64-NEXT: .cfi_offset %rsp, -16<br>; LINUXOSX64-NEXT: .cfi_offset %xmm8, -32<br>; LINUXOSX64-NEXT: vmovdqa %xmm0, %xmm8<br>-; LINUXOSX64-NEXT: vmovdqa %xmm8, %xmm1<br>+; LINUXOSX64-NEXT: vmovdqa %xmm0, %xmm1<br>; LINUXOSX64-NEXT: callq test_argRet128Vector<br>; LINUXOSX64-NEXT: vmovdqa32 %xmm8, %xmm0 {%k1}<br>; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload<br>@@ -908,12 +908,12 @@ define x86_regcallcc i32 @testi32_inp(i3<br>; X32-NEXT: subl $20, %esp<br>; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl %edi, %esi<br>-; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill<br>+; X32-NEXT: movl %edi, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl %edx, %ebx<br>-; X32-NEXT: movl %ebx, (%esp) # 4-byte Spill<br>+; X32-NEXT: movl %edx, (%esp) # 4-byte Spill<br>; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl %eax, %edx<br>-; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill<br>+; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: subl %ecx, %edx<br>; X32-NEXT: movl {{[0-9]+}}(%esp), %edi<br>; X32-NEXT: movl %edi, %ebp<br><br>Modified: llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll Tue Feb 27 08:59:10 2018<br>@@ -38,7 +38,7 @@ define <4 x float> @test_negative_zero_1<br>; SSE2-LABEL: test_negative_zero_1:<br>; SSE2: # %bb.0: # %entry<br>; SSE2-NEXT: movaps %xmm0, %xmm1<br>-; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]<br>+; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]<br>; SSE2-NEXT: xorps %xmm2, %xmm2<br>; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]<br>; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero<br><br>Modified: llvm/trunk/test/CodeGen/X86/combine-fcopysign.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-fcopysign.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-fcopysign.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/combine-fcopysign.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/combine-fcopysign.ll Tue Feb 27 08:59:10 2018<br>@@ -197,8 +197,8 @@ define <4 x double> @combine_vec_fcopysi<br>; SSE-NEXT: cvtss2sd %xmm2, %xmm4<br>; SSE-NEXT: movshdup {{.*#+}} xmm5 = xmm2[1,1,3,3]<br>; SSE-NEXT: movaps %xmm2, %xmm6<br>-; SSE-NEXT: movhlps {{.*#+}} xmm6 = xmm6[1,1]<br>-; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm6 = xmm2[1],xmm6[1]<br>+; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1],xmm2[2,3]<br>; SSE-NEXT: movaps {{.*#+}} xmm7<br>; SSE-NEXT: movaps %xmm0, %xmm2<br>; SSE-NEXT: andps %xmm7, %xmm2<br>@@ -213,7 +213,7 @@ define <4 x double> @combine_vec_fcopysi<br>; SSE-NEXT: orps %xmm0, %xmm4<br>; SSE-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm4[0]<br>; SSE-NEXT: movaps %xmm1, %xmm0<br>-; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]<br>; SSE-NEXT: andps %xmm7, %xmm0<br>; SSE-NEXT: cvtss2sd %xmm3, %xmm3<br>; SSE-NEXT: andps %xmm8, %xmm3<br>@@ -260,7 +260,7 @@ define <4 x float> @combine_vec_fcopysig<br>; SSE-NEXT: orps %xmm6, %xmm1<br>; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]<br>; SSE-NEXT: movaps %xmm3, %xmm1<br>-; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]<br>; SSE-NEXT: andps %xmm5, %xmm1<br>; SSE-NEXT: xorps %xmm6, %xmm6<br>; SSE-NEXT: cvtsd2ss %xmm2, %xmm6<br><br>Modified: llvm/trunk/test/CodeGen/X86/combine-shl.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-shl.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-shl.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/combine-shl.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/combine-shl.ll Tue Feb 27 08:59:10 2018<br>@@ -188,7 +188,7 @@ define <8 x i32> @combine_vec_shl_ext_sh<br>; SSE-LABEL: combine_vec_shl_ext_shl0:<br>; SSE: # %bb.0:<br>; SSE-NEXT: movdqa %xmm0, %xmm1<br>-; SSE-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero<br>+; SSE-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero<br>; SSE-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]<br>; SSE-NEXT: pslld $20, %xmm1<br>; SSE-NEXT: pslld $20, %xmm0<br><br>Modified: llvm/trunk/test/CodeGen/X86/complex-fastmath.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/complex-fastmath.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/complex-fastmath.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/complex-fastmath.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/complex-fastmath.ll Tue Feb 27 08:59:10 2018<br>@@ -14,7 +14,7 @@ define <2 x float> @complex_square_f32(<<br>; SSE: # %bb.0:<br>; SSE-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]<br>; SSE-NEXT: movaps %xmm0, %xmm2<br>-; SSE-NEXT: addss %xmm2, %xmm2<br>+; SSE-NEXT: addss %xmm0, %xmm2<br>; SSE-NEXT: mulss %xmm1, %xmm2<br>; SSE-NEXT: mulss %xmm0, %xmm0<br>; SSE-NEXT: mulss %xmm1, %xmm1<br>@@ -58,9 +58,9 @@ define <2 x double> @complex_square_f64(<br>; SSE-LABEL: complex_square_f64:<br>; SSE: # %bb.0:<br>; SSE-NEXT: movaps %xmm0, %xmm1<br>-; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]<br>; SSE-NEXT: movaps %xmm0, %xmm2<br>-; SSE-NEXT: addsd %xmm2, %xmm2<br>+; SSE-NEXT: addsd %xmm0, %xmm2<br>; SSE-NEXT: mulsd %xmm1, %xmm2<br>; SSE-NEXT: mulsd %xmm0, %xmm0<br>; SSE-NEXT: mulsd %xmm1, %xmm1<br>@@ -161,9 +161,9 @@ define <2 x double> @complex_mul_f64(<2<br>; SSE-LABEL: complex_mul_f64:<br>; SSE: # %bb.0:<br>; SSE-NEXT: movaps %xmm0, %xmm2<br>-; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]<br>; SSE-NEXT: movaps %xmm1, %xmm3<br>-; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm3[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]<br>; SSE-NEXT: movaps %xmm3, %xmm4<br>; SSE-NEXT: mulsd %xmm0, %xmm4<br>; SSE-NEXT: mulsd %xmm1, %xmm0<br><br>Modified: llvm/trunk/test/CodeGen/X86/divide-by-constant.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divide-by-constant.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divide-by-constant.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/divide-by-constant.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/divide-by-constant.ll Tue Feb 27 08:59:10 2018<br>@@ -312,7 +312,7 @@ define i64 @PR23590(i64 %x) nounwind {<br>; X64: # %bb.0: # %entry<br>; X64-NEXT: movq %rdi, %rcx<br>; X64-NEXT: movabsq $6120523590596543007, %rdx # imm = 0x54F077C718E7C21F<br>-; X64-NEXT: movq %rcx, %rax<br>+; X64-NEXT: movq %rdi, %rax<br>; X64-NEXT: mulq %rdx<br>; X64-NEXT: shrq $12, %rdx<br>; X64-NEXT: imulq $12345, %rdx, %rax # imm = 0x3039<br><br>Modified: llvm/trunk/test/CodeGen/X86/fmaxnum.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fmaxnum.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fmaxnum.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/fmaxnum.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/fmaxnum.ll Tue Feb 27 08:59:10 2018<br>@@ -18,7 +18,7 @@ declare <8 x double> @llvm.maxnum.v8f64(<br><br>; CHECK-LABEL: @test_fmaxf<br>; SSE: movaps %xmm0, %xmm2<br>-; SSE-NEXT: cmpunordss %xmm2, %xmm2<br>+; SSE-NEXT: cmpunordss %xmm0, %xmm2<br>; SSE-NEXT: movaps %xmm2, %xmm3<br>; SSE-NEXT: andps %xmm1, %xmm3<br>; SSE-NEXT: maxss %xmm0, %xmm1<br>@@ -47,7 +47,7 @@ define float @test_fmaxf_minsize(float %<br><br>; CHECK-LABEL: @test_fmax<br>; SSE: movapd %xmm0, %xmm2<br>-; SSE-NEXT: cmpunordsd %xmm2, %xmm2<br>+; SSE-NEXT: cmpunordsd %xmm0, %xmm2<br>; SSE-NEXT: movapd %xmm2, %xmm3<br>; SSE-NEXT: andpd %xmm1, %xmm3<br>; SSE-NEXT: maxsd %xmm0, %xmm1<br>@@ -74,7 +74,7 @@ define x86_fp80 @test_fmaxl(x86_fp80 %x,<br><br>; CHECK-LABEL: @test_intrinsic_fmaxf<br>; SSE: movaps %xmm0, %xmm2<br>-; SSE-NEXT: cmpunordss %xmm2, %xmm2<br>+; SSE-NEXT: cmpunordss %xmm0, %xmm2<br>; SSE-NEXT: movaps %xmm2, %xmm3<br>; SSE-NEXT: andps %xmm1, %xmm3<br>; SSE-NEXT: maxss %xmm0, %xmm1<br>@@ -95,7 +95,7 @@ define float @test_intrinsic_fmaxf(float<br><br>; CHECK-LABEL: @test_intrinsic_fmax<br>; SSE: movapd %xmm0, %xmm2<br>-; SSE-NEXT: cmpunordsd %xmm2, %xmm2<br>+; SSE-NEXT: cmpunordsd %xmm0, %xmm2<br>; SSE-NEXT: movapd %xmm2, %xmm3<br>; SSE-NEXT: andpd %xmm1, %xmm3<br>; SSE-NEXT: maxsd %xmm0, %xmm1<br><br>Modified: llvm/trunk/test/CodeGen/X86/fmf-flags.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fmf-flags.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fmf-flags.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/fmf-flags.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/fmf-flags.ll Tue Feb 27 08:59:10 2018<br>@@ -30,7 +30,7 @@ define float @fast_fmuladd_opts(float %a<br>; X64-LABEL: fast_fmuladd_opts:<br>; X64: # %bb.0:<br>; X64-NEXT: movaps %xmm0, %xmm1<br>-; X64-NEXT: addss %xmm1, %xmm1<br>+; X64-NEXT: addss %xmm0, %xmm1<br>; X64-NEXT: addss %xmm0, %xmm1<br>; X64-NEXT: movaps %xmm1, %xmm0<br>; X64-NEXT: retq<br><br>Modified: llvm/trunk/test/CodeGen/X86/fminnum.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fminnum.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fminnum.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/fminnum.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/fminnum.ll Tue Feb 27 08:59:10 2018<br>@@ -18,7 +18,7 @@ declare <8 x double> @llvm.minnum.v8f64(<br><br>; CHECK-LABEL: @test_fminf<br>; SSE: movaps %xmm0, %xmm2<br>-; SSE-NEXT: cmpunordss %xmm2, %xmm2<br>+; SSE-NEXT: cmpunordss %xmm0, %xmm2<br>; SSE-NEXT: movaps %xmm2, %xmm3<br>; SSE-NEXT: andps %xmm1, %xmm3<br>; SSE-NEXT: minss %xmm0, %xmm1<br>@@ -40,7 +40,7 @@ define float @test_fminf(float %x, float<br><br>; CHECK-LABEL: @test_fmin<br>; SSE: movapd %xmm0, %xmm2<br>-; SSE-NEXT: cmpunordsd %xmm2, %xmm2<br>+; SSE-NEXT: cmpunordsd %xmm0, %xmm2<br>; SSE-NEXT: movapd %xmm2, %xmm3<br>; SSE-NEXT: andpd %xmm1, %xmm3<br>; SSE-NEXT: minsd %xmm0, %xmm1<br>@@ -67,7 +67,7 @@ define x86_fp80 @test_fminl(x86_fp80 %x,<br><br>; CHECK-LABEL: @test_intrinsic_fminf<br>; SSE: movaps %xmm0, %xmm2<br>-; SSE-NEXT: cmpunordss %xmm2, %xmm2<br>+; SSE-NEXT: cmpunordss %xmm0, %xmm2<br>; SSE-NEXT: movaps %xmm2, %xmm3<br>; SSE-NEXT: andps %xmm1, %xmm3<br>; SSE-NEXT: minss %xmm0, %xmm1<br>@@ -87,7 +87,7 @@ define float @test_intrinsic_fminf(float<br><br>; CHECK-LABEL: @test_intrinsic_fmin<br>; SSE: movapd %xmm0, %xmm2<br>-; SSE-NEXT: cmpunordsd %xmm2, %xmm2<br>+; SSE-NEXT: cmpunordsd %xmm0, %xmm2<br>; SSE-NEXT: movapd %xmm2, %xmm3<br>; SSE-NEXT: andpd %xmm1, %xmm3<br>; SSE-NEXT: minsd %xmm0, %xmm1<br><br>Modified: llvm/trunk/test/CodeGen/X86/fp128-i128.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp128-i128.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp128-i128.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/fp128-i128.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/fp128-i128.ll Tue Feb 27 08:59:10 2018<br>@@ -227,7 +227,7 @@ define fp128 @TestI128_4(fp128 %x) #0 {<br>; CHECK: # %bb.0: # %entry<br>; CHECK-NEXT: subq $40, %rsp<br>; CHECK-NEXT: movaps %xmm0, %xmm1<br>-; CHECK-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)<br>+; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)<br>; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax<br>; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)<br>; CHECK-NEXT: movq $0, (%rsp)<br>@@ -275,7 +275,7 @@ define fp128 @acosl(fp128 %x) #0 {<br>; CHECK: # %bb.0: # %entry<br>; CHECK-NEXT: subq $40, %rsp<br>; CHECK-NEXT: movaps %xmm0, %xmm1<br>-; CHECK-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)<br>+; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)<br>; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax<br>; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)<br>; CHECK-NEXT: movq $0, (%rsp)<br><br>Modified: llvm/trunk/test/CodeGen/X86/h-registers-1.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/h-registers-1.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/h-registers-1.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/h-registers-1.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/h-registers-1.ll Tue Feb 27 08:59:10 2018<br>@@ -32,8 +32,7 @@ define i64 @foo(i64 %a, i64 %b, i64 %c,<br>; CHECK-NEXT: movzbl %ah, %eax<br>; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %ebx<br>; CHECK-NEXT: movzbl %bh, %edi<br>-; CHECK-NEXT: movq %r10, %r8<br>-; CHECK-NEXT: addq %r8, %rsi<br>+; CHECK-NEXT: addq %r10, %rsi<br>; CHECK-NEXT: addq %r11, %rdx<br>; CHECK-NEXT: addq %rsi, %rdx<br>; CHECK-NEXT: addq %rbp, %rcx<br>@@ -68,8 +67,7 @@ define i64 @foo(i64 %a, i64 %b, i64 %c,<br>; GNUX32-NEXT: movzbl %ah, %eax<br>; GNUX32-NEXT: movl {{[0-9]+}}(%esp), %ebx<br>; GNUX32-NEXT: movzbl %bh, %edi<br>-; GNUX32-NEXT: movq %r10, %r8<br>-; GNUX32-NEXT: addq %r8, %rsi<br>+; GNUX32-NEXT: addq %r10, %rsi<br>; GNUX32-NEXT: addq %r11, %rdx<br>; GNUX32-NEXT: addq %rsi, %rdx<br>; GNUX32-NEXT: addq %rbp, %rcx<br><br>Modified: llvm/trunk/test/CodeGen/X86/haddsub-2.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/haddsub-2.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/haddsub-2.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/haddsub-2.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/haddsub-2.ll Tue Feb 27 08:59:10 2018<br>@@ -896,16 +896,16 @@ define <4 x float> @not_a_hsub_2(<4 x fl<br>; SSE-LABEL: not_a_hsub_2:<br>; SSE: # %bb.0:<br>; SSE-NEXT: movaps %xmm0, %xmm2<br>-; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]<br>; SSE-NEXT: movaps %xmm0, %xmm3<br>-; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]<br>+; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1],xmm0[2,3]<br>; SSE-NEXT: subss %xmm3, %xmm2<br>; SSE-NEXT: movshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]<br>; SSE-NEXT: subss %xmm3, %xmm0<br>; SSE-NEXT: movaps %xmm1, %xmm3<br>-; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]<br>+; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1],xmm1[2,3]<br>; SSE-NEXT: movaps %xmm1, %xmm4<br>-; SSE-NEXT: movhlps {{.*#+}} xmm4 = xmm4[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm4 = xmm1[1],xmm4[1]<br>; SSE-NEXT: subss %xmm4, %xmm3<br>; SSE-NEXT: movshdup {{.*#+}} xmm4 = xmm1[1,1,3,3]<br>; SSE-NEXT: subss %xmm4, %xmm1<br>@@ -953,10 +953,10 @@ define <2 x double> @not_a_hsub_3(<2 x d<br>; SSE-LABEL: not_a_hsub_3:<br>; SSE: # %bb.0:<br>; SSE-NEXT: movaps %xmm1, %xmm2<br>-; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]<br>; SSE-NEXT: subsd %xmm2, %xmm1<br>; SSE-NEXT: movaps %xmm0, %xmm2<br>-; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]<br>; SSE-NEXT: subsd %xmm0, %xmm2<br>; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm1[0]<br>; SSE-NEXT: movapd %xmm2, %xmm0<br><br>Modified: llvm/trunk/test/CodeGen/X86/haddsub-3.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/haddsub-3.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/haddsub-3.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/haddsub-3.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/haddsub-3.ll Tue Feb 27 08:59:10 2018<br>@@ -7,10 +7,10 @@ define float @pr26491(<4 x float> %a0) {<br>; SSE2-LABEL: pr26491:<br>; SSE2: # %bb.0:<br>; SSE2-NEXT: movaps %xmm0, %xmm1<br>-; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,3,3]<br>+; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3]<br>; SSE2-NEXT: addps %xmm0, %xmm1<br>; SSE2-NEXT: movaps %xmm1, %xmm0<br>-; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]<br>+; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]<br>; SSE2-NEXT: addss %xmm1, %xmm0<br>; SSE2-NEXT: retq<br>;<br>@@ -19,7 +19,7 @@ define float @pr26491(<4 x float> %a0) {<br>; SSSE3-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]<br>; SSSE3-NEXT: addps %xmm0, %xmm1<br>; SSSE3-NEXT: movaps %xmm1, %xmm0<br>-; SSSE3-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]<br>+; SSSE3-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]<br>; SSSE3-NEXT: addss %xmm1, %xmm0<br>; SSSE3-NEXT: retq<br>;<br><br>Modified: llvm/trunk/test/CodeGen/X86/haddsub-undef.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/haddsub-undef.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/haddsub-undef.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/haddsub-undef.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/haddsub-undef.ll Tue Feb 27 08:59:10 2018<br>@@ -103,7 +103,7 @@ define <2 x double> @test5_undef(<2 x do<br>; SSE-LABEL: test5_undef:<br>; SSE: # %bb.0:<br>; SSE-NEXT: movaps %xmm0, %xmm1<br>-; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]<br>; SSE-NEXT: addsd %xmm0, %xmm1<br>; SSE-NEXT: movapd %xmm1, %xmm0<br>; SSE-NEXT: retq<br>@@ -168,7 +168,7 @@ define <4 x float> @test8_undef(<4 x flo<br>; SSE-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]<br>; SSE-NEXT: addss %xmm0, %xmm1<br>; SSE-NEXT: movaps %xmm0, %xmm2<br>-; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]<br>; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]<br>; SSE-NEXT: addss %xmm2, %xmm0<br>; SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]<br><br>Modified: llvm/trunk/test/CodeGen/X86/half.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/half.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/half.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/half.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/half.ll Tue Feb 27 08:59:10 2018<br>@@ -386,7 +386,7 @@ define <4 x float> @test_extend32_vec4(<<br>; CHECK-LIBCALL-NEXT: pushq %rbx<br>; CHECK-LIBCALL-NEXT: subq $48, %rsp<br>; CHECK-LIBCALL-NEXT: movq %rdi, %rbx<br>-; CHECK-LIBCALL-NEXT: movzwl (%rbx), %edi<br>+; CHECK-LIBCALL-NEXT: movzwl (%rdi), %edi<br>; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee<br>; CHECK-LIBCALL-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp) # 16-byte Spill<br>; CHECK-LIBCALL-NEXT: movzwl 2(%rbx), %edi<br>@@ -472,7 +472,7 @@ define <4 x double> @test_extend64_vec4(<br>; CHECK-LIBCALL-NEXT: pushq %rbx<br>; CHECK-LIBCALL-NEXT: subq $16, %rsp<br>; CHECK-LIBCALL-NEXT: movq %rdi, %rbx<br>-; CHECK-LIBCALL-NEXT: movzwl 4(%rbx), %edi<br>+; CHECK-LIBCALL-NEXT: movzwl 4(%rdi), %edi<br>; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee<br>; CHECK-LIBCALL-NEXT: movss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill<br>; CHECK-LIBCALL-NEXT: movzwl 6(%rbx), %edi<br>@@ -657,7 +657,7 @@ define void @test_trunc32_vec4(<4 x floa<br>; CHECK-I686-NEXT: movaps %xmm0, {{[0-9]+}}(%esp) # 16-byte Spill<br>; CHECK-I686-NEXT: movl {{[0-9]+}}(%esp), %ebp<br>; CHECK-I686-NEXT: movaps %xmm0, %xmm1<br>-; CHECK-I686-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]<br>+; CHECK-I686-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[2,3]<br>; CHECK-I686-NEXT: movss %xmm1, (%esp)<br>; CHECK-I686-NEXT: calll __gnu_f2h_ieee<br>; CHECK-I686-NEXT: movw %ax, %si<br><br>Modified: llvm/trunk/test/CodeGen/X86/horizontal-reduce-smax.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/horizontal-reduce-smax.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/horizontal-reduce-smax.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/horizontal-reduce-smax.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/horizontal-reduce-smax.ll Tue Feb 27 08:59:10 2018<br>@@ -40,7 +40,7 @@ define i64 @test_reduce_v2i64(<2 x i64><br>; X86-SSE42-LABEL: test_reduce_v2i64:<br>; X86-SSE42: ## %bb.0:<br>; X86-SSE42-NEXT: movdqa %xmm0, %xmm1<br>-; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]<br>+; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]<br>; X86-SSE42-NEXT: pcmpgtq %xmm2, %xmm0<br>; X86-SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm2<br>; X86-SSE42-NEXT: movd %xmm2, %eax<br>@@ -80,7 +80,7 @@ define i64 @test_reduce_v2i64(<2 x i64><br>; X64-SSE42-LABEL: test_reduce_v2i64:<br>; X64-SSE42: ## %bb.0:<br>; X64-SSE42-NEXT: movdqa %xmm0, %xmm1<br>-; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]<br>+; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]<br>; X64-SSE42-NEXT: pcmpgtq %xmm2, %xmm0<br>; X64-SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm2<br>; X64-SSE42-NEXT: movq %xmm2, %rax<br><br>Modified: llvm/trunk/test/CodeGen/X86/horizontal-reduce-smin.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/horizontal-reduce-smin.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/horizontal-reduce-smin.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/horizontal-reduce-smin.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/horizontal-reduce-smin.ll Tue Feb 27 08:59:10 2018<br>@@ -40,7 +40,7 @@ define i64 @test_reduce_v2i64(<2 x i64><br>; X86-SSE42-LABEL: test_reduce_v2i64:<br>; X86-SSE42: ## %bb.0:<br>; X86-SSE42-NEXT: movdqa %xmm0, %xmm1<br>-; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]<br>+; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]<br>; X86-SSE42-NEXT: movdqa %xmm2, %xmm0<br>; X86-SSE42-NEXT: pcmpgtq %xmm1, %xmm0<br>; X86-SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm2<br>@@ -81,7 +81,7 @@ define i64 @test_reduce_v2i64(<2 x i64><br>; X64-SSE42-LABEL: test_reduce_v2i64:<br>; X64-SSE42: ## %bb.0:<br>; X64-SSE42-NEXT: movdqa %xmm0, %xmm1<br>-; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]<br>+; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]<br>; X64-SSE42-NEXT: movdqa %xmm2, %xmm0<br>; X64-SSE42-NEXT: pcmpgtq %xmm1, %xmm0<br>; X64-SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm2<br><br>Modified: llvm/trunk/test/CodeGen/X86/horizontal-reduce-umax.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/horizontal-reduce-umax.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/horizontal-reduce-umax.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/horizontal-reduce-umax.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/horizontal-reduce-umax.ll Tue Feb 27 08:59:10 2018<br>@@ -40,7 +40,7 @@ define i64 @test_reduce_v2i64(<2 x i64><br>; X86-SSE42-LABEL: test_reduce_v2i64:<br>; X86-SSE42: ## %bb.0:<br>; X86-SSE42-NEXT: movdqa %xmm0, %xmm1<br>-; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]<br>+; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]<br>; X86-SSE42-NEXT: movdqa {{.*#+}} xmm3 = [0,2147483648,0,2147483648]<br>; X86-SSE42-NEXT: pxor %xmm3, %xmm0<br>; X86-SSE42-NEXT: pxor %xmm2, %xmm3<br>@@ -86,7 +86,7 @@ define i64 @test_reduce_v2i64(<2 x i64><br>; X64-SSE42-LABEL: test_reduce_v2i64:<br>; X64-SSE42: ## %bb.0:<br>; X64-SSE42-NEXT: movdqa %xmm0, %xmm1<br>-; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]<br>+; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]<br>; X64-SSE42-NEXT: movdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808]<br>; X64-SSE42-NEXT: pxor %xmm3, %xmm0<br>; X64-SSE42-NEXT: pxor %xmm2, %xmm3<br>@@ -1693,7 +1693,7 @@ define i16 @test_reduce_v32i16(<32 x i16<br>; X86-SSE2-NEXT: pxor %xmm4, %xmm1<br>; X86-SSE2-NEXT: pmaxsw %xmm3, %xmm1<br>; X86-SSE2-NEXT: movdqa %xmm4, %xmm2<br>-; X86-SSE2-NEXT: pxor %xmm2, %xmm2<br>+; X86-SSE2-NEXT: pxor %xmm4, %xmm2<br>; X86-SSE2-NEXT: pxor %xmm2, %xmm1<br>; X86-SSE2-NEXT: pxor %xmm0, %xmm2<br>; X86-SSE2-NEXT: pmaxsw %xmm1, %xmm2<br>@@ -1771,7 +1771,7 @@ define i16 @test_reduce_v32i16(<32 x i16<br>; X64-SSE2-NEXT: pxor %xmm4, %xmm1<br>; X64-SSE2-NEXT: pmaxsw %xmm3, %xmm1<br>; X64-SSE2-NEXT: movdqa %xmm4, %xmm2<br>-; X64-SSE2-NEXT: pxor %xmm2, %xmm2<br>+; X64-SSE2-NEXT: pxor %xmm4, %xmm2<br>; X64-SSE2-NEXT: pxor %xmm2, %xmm1<br>; X64-SSE2-NEXT: pxor %xmm0, %xmm2<br>; X64-SSE2-NEXT: pmaxsw %xmm1, %xmm2<br><br>Modified: llvm/trunk/test/CodeGen/X86/horizontal-reduce-umin.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/horizontal-reduce-umin.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/horizontal-reduce-umin.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/horizontal-reduce-umin.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/horizontal-reduce-umin.ll Tue Feb 27 08:59:10 2018<br>@@ -40,7 +40,7 @@ define i64 @test_reduce_v2i64(<2 x i64><br>; X86-SSE42-LABEL: test_reduce_v2i64:<br>; X86-SSE42: ## %bb.0:<br>; X86-SSE42-NEXT: movdqa %xmm0, %xmm1<br>-; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]<br>+; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]<br>; X86-SSE42-NEXT: movdqa {{.*#+}} xmm0 = [0,2147483648,0,2147483648]<br>; X86-SSE42-NEXT: movdqa %xmm1, %xmm3<br>; X86-SSE42-NEXT: pxor %xmm0, %xmm3<br>@@ -87,7 +87,7 @@ define i64 @test_reduce_v2i64(<2 x i64><br>; X64-SSE42-LABEL: test_reduce_v2i64:<br>; X64-SSE42: ## %bb.0:<br>; X64-SSE42-NEXT: movdqa %xmm0, %xmm1<br>-; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]<br>+; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]<br>; X64-SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808]<br>; X64-SSE42-NEXT: movdqa %xmm1, %xmm3<br>; X64-SSE42-NEXT: pxor %xmm0, %xmm3<br>@@ -444,7 +444,7 @@ define i64 @test_reduce_v4i64(<4 x i64><br>; X86-SSE42: ## %bb.0:<br>; X86-SSE42-NEXT: movdqa %xmm0, %xmm2<br>; X86-SSE42-NEXT: movdqa {{.*#+}} xmm3 = [0,2147483648,0,2147483648]<br>-; X86-SSE42-NEXT: movdqa %xmm2, %xmm4<br>+; X86-SSE42-NEXT: movdqa %xmm0, %xmm4<br>; X86-SSE42-NEXT: pxor %xmm3, %xmm4<br>; X86-SSE42-NEXT: movdqa %xmm1, %xmm0<br>; X86-SSE42-NEXT: pxor %xmm3, %xmm0<br>@@ -543,7 +543,7 @@ define i64 @test_reduce_v4i64(<4 x i64><br>; X64-SSE42: ## %bb.0:<br>; X64-SSE42-NEXT: movdqa %xmm0, %xmm2<br>; X64-SSE42-NEXT: movdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808]<br>-; X64-SSE42-NEXT: movdqa %xmm2, %xmm4<br>+; X64-SSE42-NEXT: movdqa %xmm0, %xmm4<br>; X64-SSE42-NEXT: pxor %xmm3, %xmm4<br>; X64-SSE42-NEXT: movdqa %xmm1, %xmm0<br>; X64-SSE42-NEXT: pxor %xmm3, %xmm0<br>@@ -1597,7 +1597,7 @@ define i16 @test_reduce_v32i16(<32 x i16<br>; X86-SSE2-NEXT: pxor %xmm4, %xmm1<br>; X86-SSE2-NEXT: pminsw %xmm3, %xmm1<br>; X86-SSE2-NEXT: movdqa %xmm4, %xmm2<br>-; X86-SSE2-NEXT: pxor %xmm2, %xmm2<br>+; X86-SSE2-NEXT: pxor %xmm4, %xmm2<br>; X86-SSE2-NEXT: pxor %xmm2, %xmm1<br>; X86-SSE2-NEXT: pxor %xmm0, %xmm2<br>; X86-SSE2-NEXT: pminsw %xmm1, %xmm2<br>@@ -1666,7 +1666,7 @@ define i16 @test_reduce_v32i16(<32 x i16<br>; X64-SSE2-NEXT: pxor %xmm4, %xmm1<br>; X64-SSE2-NEXT: pminsw %xmm3, %xmm1<br>; X64-SSE2-NEXT: movdqa %xmm4, %xmm2<br>-; X64-SSE2-NEXT: pxor %xmm2, %xmm2<br>+; X64-SSE2-NEXT: pxor %xmm4, %xmm2<br>; X64-SSE2-NEXT: pxor %xmm2, %xmm1<br>; X64-SSE2-NEXT: pxor %xmm0, %xmm2<br>; X64-SSE2-NEXT: pminsw %xmm1, %xmm2<br><br>Modified: llvm/trunk/test/CodeGen/X86/i128-mul.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i128-mul.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i128-mul.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/i128-mul.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/i128-mul.ll Tue Feb 27 08:59:10 2018<br>@@ -145,8 +145,8 @@ define i64 @mul1(i64 %n, i64* nocapture<br>; X86-NOBMI-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax<br>; X86-NOBMI-NEXT: movl %eax, %ecx<br>-; X86-NOBMI-NEXT: movl (%ecx,%ebx,8), %ebp<br>-; X86-NOBMI-NEXT: movl 4(%ecx,%ebx,8), %esi<br>+; X86-NOBMI-NEXT: movl (%eax,%ebx,8), %ebp<br>+; X86-NOBMI-NEXT: movl 4(%eax,%ebx,8), %esi<br>; X86-NOBMI-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X86-NOBMI-NEXT: movl %ebp, %eax<br>; X86-NOBMI-NEXT: movl %ebp, {{[0-9]+}}(%esp) # 4-byte Spill<br>@@ -245,7 +245,7 @@ define i64 @mul1(i64 %n, i64* nocapture<br>; X86-BMI-NEXT: movl %ecx, %edx<br>; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %eax<br>; X86-BMI-NEXT: movl %eax, %esi<br>-; X86-BMI-NEXT: mulxl %esi, %eax, %ebp<br>+; X86-BMI-NEXT: mulxl %eax, %eax, %ebp<br>; X86-BMI-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X86-BMI-NEXT: movl %ebx, %edx<br>; X86-BMI-NEXT: mulxl %esi, %eax, %esi<br><br>Modified: llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll Tue Feb 27 08:59:10 2018<br>@@ -161,6 +161,7 @@ define void @testPR4459(x86_fp80 %a) {<br>; CHECK-NEXT: fstpt (%esp)<br>; CHECK-NEXT: calll _ceil<br>; CHECK-NEXT: fld %st(0)<br>+; CHECK-NEXT: fxch %st(1)<br>; CHECK-NEXT: ## InlineAsm Start<br>; CHECK-NEXT: fistpl %st(0)<br>; CHECK-NEXT: ## InlineAsm End<br><br>Modified: llvm/trunk/test/CodeGen/X86/ipra-local-linkage.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ipra-local-linkage.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ipra-local-linkage.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/ipra-local-linkage.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/ipra-local-linkage.ll Tue Feb 27 08:59:10 2018<br>@@ -24,7 +24,7 @@ define void @bar(i32 %X) {<br> call void @foo()<br> ; CHECK-LABEL: bar:<br> ; CHECK: callq foo<br>- ; CHECK-NEXT: movl %eax, %r15d<br>+ ; CHECK-NEXT: movl %edi, %r15d<br> call void asm sideeffect "movl $0, %r12d", "{r15}~{r12}"(i32 %X)<br> ret void<br>}<br><br>Modified: llvm/trunk/test/CodeGen/X86/legalize-shift.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/legalize-shift.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/legalize-shift.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/legalize-shift.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/legalize-shift.ll Tue Feb 27 08:59:10 2018<br>@@ -10,7 +10,7 @@ define void @PR36250() {<br>; X86-NEXT: roll %ecx<br>; X86-NEXT: addl %eax, %eax<br>; X86-NEXT: movl %ecx, %edx<br>-; X86-NEXT: orl %edx, %edx<br>+; X86-NEXT: orl %ecx, %edx<br>; X86-NEXT: orl %ecx, %edx<br>; X86-NEXT: orl %eax, %edx<br>; X86-NEXT: orl %ecx, %edx<br>@@ -24,7 +24,7 @@ define void @PR36250() {<br>; X64-NEXT: rolq %rcx<br>; X64-NEXT: addq %rax, %rax<br>; X64-NEXT: movq %rcx, %rdx<br>-; X64-NEXT: orq %rdx, %rdx<br>+; X64-NEXT: orq %rcx, %rdx<br>; X64-NEXT: orq %rax, %rdx<br>; X64-NEXT: orq %rcx, %rdx<br>; X64-NEXT: sete (%rax)<br><br>Modified: llvm/trunk/test/CodeGen/X86/localescape.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/localescape.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/localescape.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/localescape.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/localescape.ll Tue Feb 27 08:59:10 2018<br>@@ -27,7 +27,7 @@ define void @print_framealloc_from_fp(i8<br><br>; X64-LABEL: print_framealloc_from_fp:<br>; X64: movq %rcx, %[[parent_fp:[a-z]+]]<br>-; X64: movl .Lalloc_func$frame_escape_0(%[[parent_fp]]), %edx<br>+; X64: movl .Lalloc_func$frame_escape_0(%rcx), %edx<br>; X64: leaq {{.*}}(%rip), %[[str:[a-z]+]]<br>; X64: movq %[[str]], %rcx<br>; X64: callq printf<br><br>Modified: llvm/trunk/test/CodeGen/X86/machine-cp.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-cp.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-cp.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/machine-cp.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/machine-cp.ll Tue Feb 27 08:59:10 2018<br>@@ -8,7 +8,7 @@ define i32 @t1(i32 %a, i32 %b) nounwind<br>; CHECK: ## %bb.0: ## %entry<br>; CHECK-NEXT: movl %esi, %edx<br>; CHECK-NEXT: movl %edi, %eax<br>-; CHECK-NEXT: testl %edx, %edx<br>+; CHECK-NEXT: testl %esi, %esi<br>; CHECK-NEXT: je LBB0_1<br>; CHECK-NEXT: .p2align 4, 0x90<br>; CHECK-NEXT: LBB0_2: ## %while.body<br>@@ -59,7 +59,7 @@ define i32 @t3(i64 %a, i64 %b) nounwind<br>; CHECK: ## %bb.0: ## %entry<br>; CHECK-NEXT: movq %rsi, %rdx<br>; CHECK-NEXT: movq %rdi, %rax<br>-; CHECK-NEXT: testq %rdx, %rdx<br>+; CHECK-NEXT: testq %rsi, %rsi<br>; CHECK-NEXT: je LBB2_1<br>; CHECK-NEXT: .p2align 4, 0x90<br>; CHECK-NEXT: LBB2_2: ## %while.body<br><br>Modified: llvm/trunk/test/CodeGen/X86/mmx-arith.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-arith.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-arith.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/mmx-arith.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/mmx-arith.ll Tue Feb 27 08:59:10 2018<br>@@ -580,7 +580,7 @@ define <1 x i64> @test3(<1 x i64>* %a, <<br>; X32-NEXT: # =>This Inner Loop Header: Depth=1<br>; X32-NEXT: movl 8(%ebp), %ecx<br>; X32-NEXT: movl %ecx, %esi<br>-; X32-NEXT: movl (%esi,%ebx,8), %ecx<br>+; X32-NEXT: movl (%ecx,%ebx,8), %ecx<br>; X32-NEXT: movl 4(%esi,%ebx,8), %esi<br>; X32-NEXT: movl 12(%ebp), %edi<br>; X32-NEXT: addl (%edi,%ebx,8), %ecx<br><br>Modified: llvm/trunk/test/CodeGen/X86/mul-i1024.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mul-i1024.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mul-i1024.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/mul-i1024.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/mul-i1024.ll Tue Feb 27 08:59:10 2018<br>@@ -38,7 +38,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movl %edx, %eax<br>; X32-NEXT: adcl %edi, %eax<br>; X32-NEXT: movl %edi, %ecx<br>-; X32-NEXT: movl %ecx, -204(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %edi, -204(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %eax, -892(%ebp) # 4-byte Spill<br>; X32-NEXT: movl 12(%ebp), %eax<br>; X32-NEXT: movl 36(%eax), %eax<br>@@ -47,7 +47,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: mull %edx<br>; X32-NEXT: movl %edx, -236(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %eax, %edi<br>-; X32-NEXT: movl %edi, -304(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %eax, -304(%ebp) # 4-byte Spill<br>; X32-NEXT: addl %ecx, %edi<br>; X32-NEXT: movl %edi, -80(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %edx, %eax<br>@@ -58,7 +58,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: xorl %ecx, %ecx<br>; X32-NEXT: mull %ecx<br>; X32-NEXT: movl %edx, %ecx<br>-; X32-NEXT: movl %ecx, -124(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %edx, -124(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %eax, -184(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %eax, %edx<br>; X32-NEXT: movl -400(%ebp), %esi # 4-byte Reload<br>@@ -72,7 +72,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movl %eax, -656(%ebp) # 4-byte Spill<br>; X32-NEXT: leal (%ebx,%edi), %eax<br>; X32-NEXT: movl %edx, %edi<br>-; X32-NEXT: leal (%ecx,%edi), %edx<br>+; X32-NEXT: leal (%ecx,%edx), %edx<br>; X32-NEXT: adcl %eax, %edx<br>; X32-NEXT: movl %edx, -700(%ebp) # 4-byte Spill<br>; X32-NEXT: seto %al<br>@@ -123,7 +123,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: adcl %edi, %ebx<br>; X32-NEXT: movl %ebx, -424(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %edi, %ebx<br>-; X32-NEXT: movl %ebx, -256(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %edi, -256(%ebp) # 4-byte Spill<br>; X32-NEXT: movl -100(%ebp), %eax # 4-byte Reload<br>; X32-NEXT: addl %eax, -80(%ebp) # 4-byte Folded Spill<br>; X32-NEXT: movl -204(%ebp), %eax # 4-byte Reload<br>@@ -148,7 +148,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movzbl %bh, %eax<br>; X32-NEXT: adcl %edx, %eax<br>; X32-NEXT: movl %eax, %edi<br>-; X32-NEXT: movl %edi, -72(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %eax, -72(%ebp) # 4-byte Spill<br>; X32-NEXT: movl 12(%ebp), %eax<br>; X32-NEXT: movl 8(%eax), %eax<br>; X32-NEXT: movl %eax, -108(%ebp) # 4-byte Spill<br>@@ -220,7 +220,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: mull %ecx<br>; X32-NEXT: movl %eax, -364(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %edx, %ebx<br>-; X32-NEXT: movl %ebx, -396(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %edx, -396(%ebp) # 4-byte Spill<br>; X32-NEXT: movl -324(%ebp), %edx # 4-byte Reload<br>; X32-NEXT: movl %edx, %edi<br>; X32-NEXT: addl %eax, %edi<br>@@ -252,7 +252,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: mull %ebx<br>; X32-NEXT: movl %eax, %edi<br>; X32-NEXT: movl %edx, %esi<br>-; X32-NEXT: movl %esi, -84(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %edx, -84(%ebp) # 4-byte Spill<br>; X32-NEXT: movl 20(%ecx), %eax<br>; X32-NEXT: movl %eax, -252(%ebp) # 4-byte Spill<br>; X32-NEXT: mull %ebx<br>@@ -303,7 +303,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movl -52(%ebp), %eax # 4-byte Reload<br>; X32-NEXT: adcl %edx, %eax<br>; X32-NEXT: movl %edx, %ebx<br>-; X32-NEXT: movl %ebx, -56(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %edx, -56(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %eax, -780(%ebp) # 4-byte Spill<br>; X32-NEXT: movl -132(%ebp), %edx # 4-byte Reload<br>; X32-NEXT: movl %edx, %eax<br>@@ -393,10 +393,10 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: xorl %ecx, %ecx<br>; X32-NEXT: mull %ecx<br>; X32-NEXT: movl %eax, %ecx<br>-; X32-NEXT: movl %ecx, -160(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %eax, -160(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %edx, -268(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %ebx, %esi<br>-; X32-NEXT: movl %esi, %eax<br>+; X32-NEXT: movl %ebx, %eax<br>; X32-NEXT: addl %ecx, %eax<br>; X32-NEXT: movl -264(%ebp), %ebx # 4-byte Reload<br>; X32-NEXT: movl %ebx, %ecx<br>@@ -425,7 +425,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: adcl -60(%ebp), %eax # 4-byte Folded Reload<br>; X32-NEXT: movl %eax, -592(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %esi, %edx<br>-; X32-NEXT: movl %edx, %eax<br>+; X32-NEXT: movl %esi, %eax<br>; X32-NEXT: movl -116(%ebp), %esi # 4-byte Reload<br>; X32-NEXT: addl %esi, %eax<br>; X32-NEXT: movl %ebx, %eax<br>@@ -533,7 +533,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: xorl %ecx, %ecx<br>; X32-NEXT: mull %ecx<br>; X32-NEXT: movl %eax, %ebx<br>-; X32-NEXT: movl %ebx, -336(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %eax, -336(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %edx, %edi<br>; X32-NEXT: movl 52(%esi), %eax<br>; X32-NEXT: movl %eax, -144(%ebp) # 4-byte Spill<br>@@ -559,7 +559,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movl -336(%ebp), %ebx # 4-byte Reload<br>; X32-NEXT: addl %eax, %ebx<br>; X32-NEXT: movl %edi, %edx<br>-; X32-NEXT: movl %edx, -176(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %edi, -176(%ebp) # 4-byte Spill<br>; X32-NEXT: adcl -360(%ebp), %edi # 4-byte Folded Reload<br>; X32-NEXT: addl %ecx, %ebx<br>; X32-NEXT: movl %ebx, -472(%ebp) # 4-byte Spill<br>@@ -590,12 +590,12 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: xorl %ecx, %ecx<br>; X32-NEXT: mull %ecx<br>; X32-NEXT: movl %edx, %esi<br>-; X32-NEXT: movl %esi, -384(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %edx, -384(%ebp) # 4-byte Spill<br>; X32-NEXT: movl -116(%ebp), %edi # 4-byte Reload<br>; X32-NEXT: movl %edi, %ecx<br>; X32-NEXT: movl %eax, %edx<br>-; X32-NEXT: movl %edx, -480(%ebp) # 4-byte Spill<br>-; X32-NEXT: addl %edx, %ecx<br>+; X32-NEXT: movl %eax, -480(%ebp) # 4-byte Spill<br>+; X32-NEXT: addl %eax, %ecx<br>; X32-NEXT: movl -84(%ebp), %ebx # 4-byte Reload<br>; X32-NEXT: movl %ebx, %eax<br>; X32-NEXT: adcl %esi, %eax<br>@@ -642,8 +642,8 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movl %eax, %ecx<br>; X32-NEXT: addl %esi, %ecx<br>; X32-NEXT: movl %edx, %esi<br>-; X32-NEXT: movl %esi, -496(%ebp) # 4-byte Spill<br>-; X32-NEXT: movl %esi, %ecx<br>+; X32-NEXT: movl %edx, -496(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %edx, %ecx<br>; X32-NEXT: adcl %edi, %ecx<br>; X32-NEXT: movl %ecx, -992(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %eax, %ecx<br>@@ -761,7 +761,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: xorl %edx, %edx<br>; X32-NEXT: mull %edx<br>; X32-NEXT: movl %eax, %esi<br>-; X32-NEXT: movl %esi, -484(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %eax, -484(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %edx, -488(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %ebx, %eax<br>; X32-NEXT: addl %esi, %eax<br>@@ -793,8 +793,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: adcl -60(%ebp), %ebx # 4-byte Folded Reload<br>; X32-NEXT: movl %ebx, -928(%ebp) # 4-byte Spill<br>; X32-NEXT: movl 8(%ebp), %ecx<br>-; X32-NEXT: movl %ecx, %eax<br>-; X32-NEXT: movl 84(%eax), %eax<br>+; X32-NEXT: movl 84(%ecx), %eax<br>; X32-NEXT: movl %eax, -544(%ebp) # 4-byte Spill<br>; X32-NEXT: xorl %ecx, %ecx<br>; X32-NEXT: mull %ecx<br>@@ -871,7 +870,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: xorl %edx, %edx<br>; X32-NEXT: mull %edx<br>; X32-NEXT: movl %eax, %esi<br>-; X32-NEXT: movl %esi, -556(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %eax, -556(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %edx, -560(%ebp) # 4-byte Spill<br>; X32-NEXT: movl -524(%ebp), %eax # 4-byte Reload<br>; X32-NEXT: movl %eax, %ebx<br>@@ -882,7 +881,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movl %ebx, -732(%ebp) # 4-byte Spill<br>; X32-NEXT: adcl %edi, %esi<br>; X32-NEXT: movl %esi, %edx<br>-; X32-NEXT: movl %edx, -728(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %esi, -728(%ebp) # 4-byte Spill<br>; X32-NEXT: addl -136(%ebp), %eax # 4-byte Folded Reload<br>; X32-NEXT: movl %eax, -712(%ebp) # 4-byte Spill<br>; X32-NEXT: movl -668(%ebp), %ecx # 4-byte Reload<br>@@ -917,7 +916,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: mull %ebx<br>; X32-NEXT: movl %eax, -564(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %edx, %ebx<br>-; X32-NEXT: movl %ebx, -568(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %edx, -568(%ebp) # 4-byte Spill<br>; X32-NEXT: movl -500(%ebp), %edx # 4-byte Reload<br>; X32-NEXT: movl %edx, %edi<br>; X32-NEXT: addl %eax, %edi<br>@@ -983,7 +982,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movzbl -88(%ebp), %eax # 1-byte Folded Reload<br>; X32-NEXT: adcl %edx, %eax<br>; X32-NEXT: movl %ecx, %edx<br>-; X32-NEXT: addl %edx, %ebx<br>+; X32-NEXT: addl %ecx, %ebx<br>; X32-NEXT: adcl %esi, %eax<br>; X32-NEXT: movl %eax, -88(%ebp) # 4-byte Spill<br>; X32-NEXT: movl -28(%ebp), %edi # 4-byte Reload<br>@@ -1038,7 +1037,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: mull %ecx<br>; X32-NEXT: movl %edx, %edi<br>; X32-NEXT: movl %eax, %ebx<br>-; X32-NEXT: movl %ebx, %ecx<br>+; X32-NEXT: movl %eax, %ecx<br>; X32-NEXT: movl -396(%ebp), %esi # 4-byte Reload<br>; X32-NEXT: addl %esi, %ecx<br>; X32-NEXT: adcl $0, %edx<br>@@ -1052,7 +1051,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movzbl -16(%ebp), %ebx # 1-byte Folded Reload<br>; X32-NEXT: adcl %edi, %ebx<br>; X32-NEXT: movl %eax, %esi<br>-; X32-NEXT: addl %esi, %edx<br>+; X32-NEXT: addl %eax, %edx<br>; X32-NEXT: adcl %ecx, %ebx<br>; X32-NEXT: movl -64(%ebp), %eax # 4-byte Reload<br>; X32-NEXT: addl -324(%ebp), %eax # 4-byte Folded Reload<br>@@ -1143,7 +1142,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movzbl %cl, %eax<br>; X32-NEXT: adcl %esi, %eax<br>; X32-NEXT: movl %edi, %esi<br>-; X32-NEXT: addl %esi, %edx<br>+; X32-NEXT: addl %edi, %edx<br>; X32-NEXT: adcl %ebx, %eax<br>; X32-NEXT: movl %eax, -112(%ebp) # 4-byte Spill<br>; X32-NEXT: movl -136(%ebp), %edi # 4-byte Reload<br>@@ -1223,7 +1222,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movzbl %bl, %eax<br>; X32-NEXT: adcl %edx, %eax<br>; X32-NEXT: movl %ecx, %edx<br>-; X32-NEXT: addl %edx, %esi<br>+; X32-NEXT: addl %ecx, %esi<br>; X32-NEXT: adcl %edi, %eax<br>; X32-NEXT: movl %eax, -48(%ebp) # 4-byte Spill<br>; X32-NEXT: movl -100(%ebp), %edi # 4-byte Reload<br>@@ -1697,7 +1696,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movl %esi, %eax<br>; X32-NEXT: mull %ebx<br>; X32-NEXT: movl %ebx, %esi<br>-; X32-NEXT: movl %esi, -48(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %ebx, -48(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %edx, %ebx<br>; X32-NEXT: addl %ecx, %eax<br>; X32-NEXT: movl %eax, -64(%ebp) # 4-byte Spill<br>@@ -4479,7 +4478,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movl %esi, %eax<br>; X32-NEXT: mull %ebx<br>; X32-NEXT: movl %ebx, %esi<br>-; X32-NEXT: movl %esi, -140(%ebp) # 4-byte Spill<br>+; X32-NEXT: movl %ebx, -140(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %edx, %ebx<br>; X32-NEXT: addl %ecx, %eax<br>; X32-NEXT: movl %eax, -56(%ebp) # 4-byte Spill<br>@@ -5199,7 +5198,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: addl %edi, %edx<br>; X32-NEXT: movl 124(%ebx), %ebx<br>; X32-NEXT: movl %ecx, %eax<br>-; X32-NEXT: imull %eax, %ebx<br>+; X32-NEXT: imull %ecx, %ebx<br>; X32-NEXT: addl %edx, %ebx<br>; X32-NEXT: movl -144(%ebp), %ecx # 4-byte Reload<br>; X32-NEXT: addl %ecx, -96(%ebp) # 4-byte Folded Spill<br>@@ -6073,8 +6072,8 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movl 108(%eax), %edx<br>; X32-NEXT: movl %ebx, %eax<br>; X32-NEXT: movl %edx, %ebx<br>-; X32-NEXT: movl %ebx, -112(%ebp) # 4-byte Spill<br>-; X32-NEXT: mull %ebx<br>+; X32-NEXT: movl %edx, -112(%ebp) # 4-byte Spill<br>+; X32-NEXT: mull %edx<br>; X32-NEXT: movl %edx, %esi<br>; X32-NEXT: addl %ecx, %eax<br>; X32-NEXT: movl %eax, -128(%ebp) # 4-byte Spill<br>@@ -6113,7 +6112,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X32-NEXT: movl -184(%ebp), %ecx # 4-byte Reload<br>; X32-NEXT: movl %ecx, %eax<br>; X32-NEXT: movl %ebx, %esi<br>-; X32-NEXT: mull %esi<br>+; X32-NEXT: mull %ebx<br>; X32-NEXT: movl %edx, -144(%ebp) # 4-byte Spill<br>; X32-NEXT: movl %eax, -280(%ebp) # 4-byte Spill<br>; X32-NEXT: movl -60(%ebp), %ebx # 4-byte Reload<br>@@ -6754,7 +6753,6 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: adcq $0, %rbp<br>; X64-NEXT: addq %rcx, %rbx<br>; X64-NEXT: movq %rbx, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>-; X64-NEXT: movq %rcx, %r11<br>; X64-NEXT: adcq %rdi, %rbp<br>; X64-NEXT: setb %bl<br>; X64-NEXT: movzbl %bl, %ebx<br>@@ -6764,12 +6762,12 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: mulq %r8<br>; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq %rdx, {{[0-9]+}}(%rsp) # 8-byte Spill<br>-; X64-NEXT: movq %r11, %r12<br>-; X64-NEXT: movq %r11, %r8<br>+; X64-NEXT: movq %rcx, %r12<br>+; X64-NEXT: movq %rcx, %r8<br>; X64-NEXT: addq %rax, %r12<br>; X64-NEXT: movq %rdi, %rax<br>; X64-NEXT: movq %rdi, %r9<br>-; X64-NEXT: movq %r9, (%rsp) # 8-byte Spill<br>+; X64-NEXT: movq %rdi, (%rsp) # 8-byte Spill<br>; X64-NEXT: adcq %rdx, %rax<br>; X64-NEXT: addq %rbp, %r12<br>; X64-NEXT: movq %r12, {{[0-9]+}}(%rsp) # 8-byte Spill<br>@@ -6798,7 +6796,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: adcq %rdx, %rbx<br>; X64-NEXT: movq 16(%rsi), %rax<br>; X64-NEXT: movq %rsi, %r13<br>-; X64-NEXT: movq %r13, {{[0-9]+}}(%rsp) # 8-byte Spill<br>+; X64-NEXT: movq %rsi, {{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: mulq %r11<br>; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>@@ -6811,7 +6809,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: adcq %rbx, %r11<br>; X64-NEXT: movq %r8, %rax<br>; X64-NEXT: movq %r8, %rbp<br>-; X64-NEXT: movq %rbp, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>+; X64-NEXT: movq %r8, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: addq %rdi, %rax<br>; X64-NEXT: movq %r9, %rax<br>; X64-NEXT: adcq %rcx, %rax<br>@@ -6824,7 +6822,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: movq %rax, %rbx<br>; X64-NEXT: addq %rdi, %rax<br>; X64-NEXT: movq %rdi, %r9<br>-; X64-NEXT: movq %rsi, %rax<br>+; X64-NEXT: movq %rdx, %rax<br>; X64-NEXT: adcq %rcx, %rax<br>; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq 32(%r13), %rax<br>@@ -6840,9 +6838,9 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: adcq %rdx, %rax<br>; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq %rbp, %rax<br>-; X64-NEXT: addq %r9, %rax<br>+; X64-NEXT: addq %rdi, %rax<br>; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>-; X64-NEXT: movq %r9, {{[0-9]+}}(%rsp) # 8-byte Spill<br>+; X64-NEXT: movq %rdi, {{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload<br>; X64-NEXT: adcq %r15, %rax<br>; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>@@ -6860,7 +6858,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: addq %rsi, %r11<br>; X64-NEXT: movq %rdx, %rbp<br>; X64-NEXT: adcq $0, %rbp<br>-; X64-NEXT: addq %rcx, %r11<br>+; X64-NEXT: addq %rbx, %r11<br>; X64-NEXT: adcq %rsi, %rbp<br>; X64-NEXT: movq %rsi, {{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: setb %bl<br>@@ -6881,11 +6879,11 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: adcq %rbx, %r10<br>; X64-NEXT: movq %rcx, %rdx<br>; X64-NEXT: movq %rcx, %r12<br>-; X64-NEXT: movq %r12, {{[0-9]+}}(%rsp) # 8-byte Spill<br>+; X64-NEXT: movq %rcx, {{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: addq %r9, %rdx<br>; X64-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq %r11, %r8<br>-; X64-NEXT: adcq %r8, %r15<br>+; X64-NEXT: adcq %r11, %r15<br>; X64-NEXT: movq %r15, {{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: adcq %rax, %r14<br>; X64-NEXT: movq %r14, {{[0-9]+}}(%rsp) # 8-byte Spill<br>@@ -6981,13 +6979,12 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: adcq %rdx, %r12<br>; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload<br>; X64-NEXT: movq %rcx, %rax<br>-; X64-NEXT: movq %r10, %rbp<br>-; X64-NEXT: mulq %rbp<br>+; X64-NEXT: mulq %r10<br>; X64-NEXT: movq %rdx, %rsi<br>; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload<br>; X64-NEXT: movq %rdi, %rax<br>-; X64-NEXT: mulq %rbp<br>+; X64-NEXT: mulq %r10<br>; X64-NEXT: movq %rdx, %rbp<br>; X64-NEXT: movq %rax, %rbx<br>; X64-NEXT: addq %rsi, %rbx<br>@@ -7014,7 +7011,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: adcq $0, %r15<br>; X64-NEXT: adcq $0, %r12<br>; X64-NEXT: movq %r10, %rbx<br>-; X64-NEXT: movq %rbx, %rax<br>+; X64-NEXT: movq %r10, %rax<br>; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r11 # 8-byte Reload<br>; X64-NEXT: mulq %r11<br>; X64-NEXT: movq %rdx, %rcx<br>@@ -7031,7 +7028,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: movq %rbx, %rax<br>; X64-NEXT: mulq %rcx<br>; X64-NEXT: movq %rcx, %rbx<br>-; X64-NEXT: movq %rbx, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>+; X64-NEXT: movq %rcx, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq %rdx, %rcx<br>; X64-NEXT: movq %rax, %r8<br>; X64-NEXT: addq %rbp, %r8<br>@@ -7062,7 +7059,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload<br>; X64-NEXT: movq %rcx, %rax<br>; X64-NEXT: movq %r11, %rsi<br>-; X64-NEXT: mulq %rsi<br>+; X64-NEXT: mulq %r11<br>; X64-NEXT: movq %rdx, %r11<br>; X64-NEXT: movq %rax, %r13<br>; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r12 # 8-byte Reload<br>@@ -7142,13 +7139,12 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: adcq %rdx, %r10<br>; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload<br>; X64-NEXT: movq %rcx, %rax<br>-; X64-NEXT: movq %r11, %rbp<br>-; X64-NEXT: mulq %rbp<br>+; X64-NEXT: mulq %r11<br>; X64-NEXT: movq %rdx, %rdi<br>; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload<br>; X64-NEXT: movq %rsi, %rax<br>-; X64-NEXT: mulq %rbp<br>+; X64-NEXT: mulq %r11<br>; X64-NEXT: movq %rdx, %rbp<br>; X64-NEXT: movq %rax, %rbx<br>; X64-NEXT: addq %rdi, %rbx<br>@@ -7278,7 +7274,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: movq %rdx, %rsi<br>; X64-NEXT: movq %rax, %r14<br>; X64-NEXT: movq %r8, %rbp<br>-; X64-NEXT: movq %rbp, %rax<br>+; X64-NEXT: movq %r8, %rax<br>; X64-NEXT: mulq %rcx<br>; X64-NEXT: movq %rcx, %r11<br>; X64-NEXT: movq %rdx, %rbx<br>@@ -7338,7 +7334,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: adcq $0, %r9<br>; X64-NEXT: adcq $0, %r10<br>; X64-NEXT: movq %rbp, %rsi<br>-; X64-NEXT: movq %rsi, %rax<br>+; X64-NEXT: movq %rbp, %rax<br>; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload<br>; X64-NEXT: mulq %rcx<br>; X64-NEXT: movq %rdx, %r14<br>@@ -7395,8 +7391,8 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: adcq $0, %r15<br>; X64-NEXT: movq %rbp, %rax<br>; X64-NEXT: movq %r8, %rdi<br>-; X64-NEXT: movq %rdi, {{[0-9]+}}(%rsp) # 8-byte Spill<br>-; X64-NEXT: mulq %rdi<br>+; X64-NEXT: movq %r8, {{[0-9]+}}(%rsp) # 8-byte Spill<br>+; X64-NEXT: mulq %r8<br>; X64-NEXT: movq %rdx, %r9<br>; X64-NEXT: movq %rax, %r8<br>; X64-NEXT: addq %rbx, %r8<br>@@ -7479,13 +7475,12 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: movq %rcx, %r14<br>; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload<br>; X64-NEXT: movq %rcx, %rax<br>-; X64-NEXT: movq %r10, %rdi<br>-; X64-NEXT: mulq %rdi<br>+; X64-NEXT: mulq %r10<br>; X64-NEXT: movq %rdx, %r11<br>; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload<br>; X64-NEXT: movq %rsi, %rax<br>-; X64-NEXT: mulq %rdi<br>+; X64-NEXT: mulq %r10<br>; X64-NEXT: movq %rdx, %rdi<br>; X64-NEXT: movq %rax, %rbx<br>; X64-NEXT: addq %r11, %rbx<br>@@ -7513,8 +7508,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: movq %r8, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: adcq $0, %r14<br>; X64-NEXT: movq %r14, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>-; X64-NEXT: movq %r13, %rbx<br>-; X64-NEXT: movq %rbx, %rax<br>+; X64-NEXT: movq %r13, %rax<br>; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload<br>; X64-NEXT: mulq %rcx<br>; X64-NEXT: movq %rdx, %r8<br>@@ -7527,7 +7521,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: movq %rax, %rcx<br>; X64-NEXT: addq %r8, %rcx<br>; X64-NEXT: adcq $0, %rsi<br>-; X64-NEXT: movq %rbx, %rax<br>+; X64-NEXT: movq %r13, %rax<br>; X64-NEXT: movq {{[0-9]+}}(%rsp), %r13 # 8-byte Reload<br>; X64-NEXT: mulq %r13<br>; X64-NEXT: movq %rdx, %rbx<br>@@ -7561,13 +7555,12 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: setb -{{[0-9]+}}(%rsp) # 1-byte Folded Spill<br>; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbx # 8-byte Reload<br>; X64-NEXT: movq %rbx, %rax<br>-; X64-NEXT: movq %r10, %rsi<br>-; X64-NEXT: mulq %rsi<br>+; X64-NEXT: mulq %r10<br>; X64-NEXT: movq %rdx, %rcx<br>; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r8 # 8-byte Reload<br>; X64-NEXT: movq %r8, %rax<br>-; X64-NEXT: mulq %rsi<br>+; X64-NEXT: mulq %r10<br>; X64-NEXT: movq %rdx, %rsi<br>; X64-NEXT: movq %rax, %rdi<br>; X64-NEXT: addq %rcx, %rdi<br>@@ -7643,7 +7636,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: movq %r9, %rax<br>; X64-NEXT: mulq %rcx<br>; X64-NEXT: movq %rcx, %r10<br>-; X64-NEXT: movq %r10, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>+; X64-NEXT: movq %rcx, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq %rdx, %rcx<br>; X64-NEXT: movq %rax, %rdi<br>; X64-NEXT: addq %rsi, %rdi<br>@@ -7655,16 +7648,16 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: movq %rax, %rbx<br>; X64-NEXT: movq %rdx, %r14<br>; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r12 # 8-byte Reload<br>-; X64-NEXT: addq %rbx, %r12<br>+; X64-NEXT: addq %rax, %r12<br>; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r15 # 8-byte Reload<br>-; X64-NEXT: adcq %r14, %r15<br>+; X64-NEXT: adcq %rdx, %r15<br>; X64-NEXT: addq %rdi, %r12<br>; X64-NEXT: adcq %rcx, %r15<br>; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload<br>; X64-NEXT: movq %rcx, %rax<br>; X64-NEXT: movq %r11, %rsi<br>-; X64-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>-; X64-NEXT: mulq %rsi<br>+; X64-NEXT: movq %r11, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>+; X64-NEXT: mulq %r11<br>; X64-NEXT: movq %rdx, %r11<br>; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq {{[0-9]+}}(%rsp), %r9 # 8-byte Reload<br>@@ -7728,7 +7721,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq %rax, %r9<br>; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbp # 8-byte Reload<br>-; X64-NEXT: addq %r9, %rbp<br>+; X64-NEXT: addq %rax, %rbp<br>; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload<br>; X64-NEXT: adcq %rdx, %rax<br>; X64-NEXT: addq %rsi, %rbp<br>@@ -7906,7 +7899,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: movq 88(%rsi), %rax<br>; X64-NEXT: movq %rsi, %r9<br>; X64-NEXT: movq %rax, %rsi<br>-; X64-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>+; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: mulq %rcx<br>; X64-NEXT: movq %rcx, %r11<br>; X64-NEXT: movq %rdx, %rbp<br>@@ -7942,13 +7935,12 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: adcq %r8, %r10<br>; X64-NEXT: addq %rbx, %rsi<br>; X64-NEXT: adcq %rbp, %r10<br>-; X64-NEXT: movq %r9, %rdi<br>-; X64-NEXT: movq 64(%rdi), %r13<br>+; X64-NEXT: movq 64(%r9), %r13<br>; X64-NEXT: movq %r13, %rax<br>; X64-NEXT: mulq %r11<br>; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq %rdx, %rcx<br>-; X64-NEXT: movq 72(%rdi), %r9<br>+; X64-NEXT: movq 72(%r9), %r9<br>; X64-NEXT: movq %r9, %rax<br>; X64-NEXT: mulq %r11<br>; X64-NEXT: movq %rdx, %rbp<br>@@ -7976,8 +7968,8 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: movq %rdx, %r11<br>; X64-NEXT: movq %rax, %r15<br>; X64-NEXT: movq %r12, %rcx<br>-; X64-NEXT: addq %r15, %rcx<br>-; X64-NEXT: adcq %r11, %r8<br>+; X64-NEXT: addq %rax, %rcx<br>+; X64-NEXT: adcq %rdx, %r8<br>; X64-NEXT: addq %rbp, %rcx<br>; X64-NEXT: adcq %rbx, %r8<br>; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload<br>@@ -8029,14 +8021,13 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: setb %r10b<br>; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload<br>; X64-NEXT: movq %rsi, %rax<br>-; X64-NEXT: movq %r8, %rdi<br>-; X64-NEXT: mulq %rdi<br>+; X64-NEXT: mulq %r8<br>; X64-NEXT: movq %rdx, %rcx<br>; X64-NEXT: movq %rax, %r9<br>; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbp # 8-byte Reload<br>; X64-NEXT: movq %rbp, %rax<br>-; X64-NEXT: mulq %rdi<br>-; X64-NEXT: movq %rdi, %r12<br>+; X64-NEXT: mulq %r8<br>+; X64-NEXT: movq %r8, %r12<br>; X64-NEXT: movq %rdx, %rdi<br>; X64-NEXT: movq %rax, %rbx<br>; X64-NEXT: addq %rcx, %rbx<br>@@ -8075,7 +8066,7 @@ define void @test_1024(i1024* %a, i1024*<br>; X64-NEXT: imulq %rcx, %rdi<br>; X64-NEXT: movq %rcx, %rax<br>; X64-NEXT: movq %r12, %rsi<br>-; X64-NEXT: mulq %rsi<br>+; X64-NEXT: mulq %r12<br>; X64-NEXT: movq %rax, %r9<br>; X64-NEXT: addq %rdi, %rdx<br>; X64-NEXT: movq 104(%rbp), %r8<br><br>Modified: llvm/trunk/test/CodeGen/X86/mul-i256.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mul-i256.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mul-i256.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/mul-i256.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/mul-i256.ll Tue Feb 27 08:59:10 2018<br>@@ -44,7 +44,7 @@ define void @test(i256* %a, i256* %b, i2<br>; X32-NEXT: movl %edi, %eax<br>; X32-NEXT: mull %ecx<br>; X32-NEXT: movl %ecx, %edi<br>-; X32-NEXT: movl %edi, {{[0-9]+}}(%esp) # 4-byte Spill<br>+; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl %edx, %ecx<br>; X32-NEXT: addl %ebx, %eax<br>; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill<br>@@ -62,9 +62,9 @@ define void @test(i256* %a, i256* %b, i2<br>; X32-NEXT: movl %ecx, %eax<br>; X32-NEXT: mull %edx<br>; X32-NEXT: movl %edx, %ebp<br>-; X32-NEXT: movl %ebp, {{[0-9]+}}(%esp) # 4-byte Spill<br>+; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl %eax, %esi<br>-; X32-NEXT: movl %esi, (%esp) # 4-byte Spill<br>+; X32-NEXT: movl %eax, (%esp) # 4-byte Spill<br>; X32-NEXT: movl {{[0-9]+}}(%esp), %eax # 4-byte Reload<br>; X32-NEXT: xorl %edx, %edx<br>; X32-NEXT: mull %edx<br>@@ -127,7 +127,7 @@ define void @test(i256* %a, i256* %b, i2<br>; X32-NEXT: adcl $0, {{[0-9]+}}(%esp) # 4-byte Folded Spill<br>; X32-NEXT: movl {{[0-9]+}}(%esp), %eax<br>; X32-NEXT: movl %eax, %ecx<br>-; X32-NEXT: movl 8(%ecx), %ebx<br>+; X32-NEXT: movl 8(%eax), %ebx<br>; X32-NEXT: movl %esi, %eax<br>; X32-NEXT: movl %esi, %edi<br>; X32-NEXT: mull %ebx<br>@@ -156,7 +156,7 @@ define void @test(i256* %a, i256* %b, i2<br>; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax # 1-byte Folded Reload<br>; X32-NEXT: adcl %eax, %esi<br>; X32-NEXT: movl %ebx, %edi<br>-; X32-NEXT: movl %edi, %eax<br>+; X32-NEXT: movl %ebx, %eax<br>; X32-NEXT: xorl %ecx, %ecx<br>; X32-NEXT: mull %ecx<br>; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill<br><br>Modified: llvm/trunk/test/CodeGen/X86/mul-i512.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mul-i512.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mul-i512.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/mul-i512.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/mul-i512.ll Tue Feb 27 08:59:10 2018<br>@@ -31,7 +31,7 @@ define void @test_512(i512* %a, i512* %b<br>; X32-NEXT: movl %edi, (%esp) # 4-byte Spill<br>; X32-NEXT: adcl %ecx, %ebx<br>; X32-NEXT: movl %ecx, %edi<br>-; X32-NEXT: movl %edi, {{[0-9]+}}(%esp) # 4-byte Spill<br>+; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: setb %cl<br>; X32-NEXT: addl %eax, %ebx<br>; X32-NEXT: movzbl %cl, %ecx<br>@@ -55,7 +55,7 @@ define void @test_512(i512* %a, i512* %b<br>; X32-NEXT: mull %ebx<br>; X32-NEXT: movl %eax, %ebp<br>; X32-NEXT: movl %edx, %edi<br>-; X32-NEXT: movl %edi, {{[0-9]+}}(%esp) # 4-byte Spill<br>+; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl 4(%ecx), %eax<br>; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl %ecx, %esi<br>@@ -92,14 +92,13 @@ define void @test_512(i512* %a, i512* %b<br>; X32-NEXT: adcl %edi, %eax<br>; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx<br>-; X32-NEXT: movl %ecx, %eax<br>-; X32-NEXT: movl (%eax), %eax<br>+; X32-NEXT: movl (%ecx), %eax<br>; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: xorl %ebp, %ebp<br>; X32-NEXT: mull %ebp<br>; X32-NEXT: movl %edx, %ebx<br>; X32-NEXT: movl %eax, %ecx<br>-; X32-NEXT: movl %ecx, %edx<br>+; X32-NEXT: movl %eax, %edx<br>; X32-NEXT: addl %esi, %edx<br>; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl %ebx, %eax<br>@@ -113,7 +112,7 @@ define void @test_512(i512* %a, i512* %b<br>; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl %ecx, %edi<br>; X32-NEXT: movl %ecx, %ebp<br>-; X32-NEXT: movl %ebp, {{[0-9]+}}(%esp) # 4-byte Spill<br>+; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: addl %eax, %edi<br>; X32-NEXT: movl %ebx, %eax<br>; X32-NEXT: adcl %edx, %eax<br>@@ -143,7 +142,7 @@ define void @test_512(i512* %a, i512* %b<br>; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: adcl %ebx, %ecx<br>; X32-NEXT: movl %ebx, %esi<br>-; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill<br>+; X32-NEXT: movl %ebx, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: setb %bl<br>; X32-NEXT: addl %eax, %ecx<br>; X32-NEXT: movzbl %bl, %ebx<br>@@ -278,7 +277,7 @@ define void @test_512(i512* %a, i512* %b<br>; X32-NEXT: adcl %ebx, %ecx<br>; X32-NEXT: setb {{[0-9]+}}(%esp) # 1-byte Folded Spill<br>; X32-NEXT: movl %edi, %ebp<br>-; X32-NEXT: movl %ebp, %eax<br>+; X32-NEXT: movl %edi, %eax<br>; X32-NEXT: mull %esi<br>; X32-NEXT: movl %edx, %edi<br>; X32-NEXT: movl %eax, %ebx<br>@@ -433,7 +432,7 @@ define void @test_512(i512* %a, i512* %b<br>; X32-NEXT: adcl %edi, %ecx<br>; X32-NEXT: setb {{[0-9]+}}(%esp) # 1-byte Folded Spill<br>; X32-NEXT: movl %ebx, %edi<br>-; X32-NEXT: movl %edi, %eax<br>+; X32-NEXT: movl %ebx, %eax<br>; X32-NEXT: mull %esi<br>; X32-NEXT: movl %eax, %ebp<br>; X32-NEXT: addl %ecx, %ebp<br>@@ -899,7 +898,7 @@ define void @test_512(i512* %a, i512* %b<br>; X32-NEXT: movl %ecx, %eax<br>; X32-NEXT: mull %esi<br>; X32-NEXT: movl %esi, %ecx<br>-; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill<br>+; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl %edx, %esi<br>; X32-NEXT: addl %ebx, %eax<br>; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill<br>@@ -929,7 +928,7 @@ define void @test_512(i512* %a, i512* %b<br>; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx # 4-byte Reload<br>; X32-NEXT: movl %ecx, %eax<br>; X32-NEXT: movl %ebx, %esi<br>-; X32-NEXT: mull %esi<br>+; X32-NEXT: mull %ebx<br>; X32-NEXT: movl %edx, %edi<br>; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx # 4-byte Reload<br>@@ -1077,7 +1076,7 @@ define void @test_512(i512* %a, i512* %b<br>; X32-NEXT: addl %esi, %edx<br>; X32-NEXT: movl {{[0-9]+}}(%esp), %esi # 4-byte Reload<br>; X32-NEXT: movl %edi, %eax<br>-; X32-NEXT: imull %eax, %esi<br>+; X32-NEXT: imull %edi, %esi<br>; X32-NEXT: addl %edx, %esi<br>; X32-NEXT: addl {{[0-9]+}}(%esp), %ecx # 4-byte Folded Reload<br>; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill<br>@@ -1177,7 +1176,7 @@ define void @test_512(i512* %a, i512* %b<br>; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl {{[0-9]+}}(%esp), %esi<br>; X32-NEXT: movl %esi, %ecx<br>-; X32-NEXT: movl 40(%ecx), %ebx<br>+; X32-NEXT: movl 40(%esi), %ebx<br>; X32-NEXT: movl %ebx, %eax<br>; X32-NEXT: movl %ebx, {{[0-9]+}}(%esp) # 4-byte Spill<br>; X32-NEXT: movl {{[0-9]+}}(%esp), %esi # 4-byte Reload<br>@@ -1374,7 +1373,7 @@ define void @test_512(i512* %a, i512* %b<br>; X32-NEXT: addl %edi, %edx<br>; X32-NEXT: movl 60(%ebx), %ebx<br>; X32-NEXT: movl %ecx, %eax<br>-; X32-NEXT: imull %eax, %ebx<br>+; X32-NEXT: imull %ecx, %ebx<br>; X32-NEXT: addl %edx, %ebx<br>; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx # 4-byte Reload<br>; X32-NEXT: addl %ecx, {{[0-9]+}}(%esp) # 4-byte Folded Spill<br>@@ -1546,7 +1545,7 @@ define void @test_512(i512* %a, i512* %b<br>; X64-NEXT: movq 8(%rsi), %rbp<br>; X64-NEXT: movq %r15, %rax<br>; X64-NEXT: movq %rdx, %rsi<br>-; X64-NEXT: mulq %rsi<br>+; X64-NEXT: mulq %rdx<br>; X64-NEXT: movq %rdx, %r9<br>; X64-NEXT: movq %rax, %r8<br>; X64-NEXT: movq %r11, %rax<br>@@ -1569,15 +1568,15 @@ define void @test_512(i512* %a, i512* %b<br>; X64-NEXT: movq %r11, %rax<br>; X64-NEXT: mulq %rbp<br>; X64-NEXT: movq %rbp, %r14<br>-; X64-NEXT: movq %r14, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>+; X64-NEXT: movq %rbp, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq %rdx, %rsi<br>; X64-NEXT: movq %rax, %rbp<br>; X64-NEXT: addq %rcx, %rbp<br>; X64-NEXT: adcq %rbx, %rsi<br>; X64-NEXT: xorl %ecx, %ecx<br>; X64-NEXT: movq %r10, %rbx<br>-; X64-NEXT: movq %rbx, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>-; X64-NEXT: movq %rbx, %rax<br>+; X64-NEXT: movq %r10, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>+; X64-NEXT: movq %r10, %rax<br>; X64-NEXT: mulq %rcx<br>; X64-NEXT: movq %rdx, %r13<br>; X64-NEXT: movq %rax, %r10<br>@@ -1585,7 +1584,7 @@ define void @test_512(i512* %a, i512* %b<br>; X64-NEXT: mulq %rcx<br>; X64-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq %rax, %r15<br>-; X64-NEXT: movq %r15, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>+; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: addq %r10, %r15<br>; X64-NEXT: adcq %r13, %rdx<br>; X64-NEXT: addq %rbp, %r15<br>@@ -1624,8 +1623,8 @@ define void @test_512(i512* %a, i512* %b<br>; X64-NEXT: mulq %rdx<br>; X64-NEXT: movq %rdx, %r14<br>; X64-NEXT: movq %rax, %r11<br>-; X64-NEXT: addq %r11, %r10<br>-; X64-NEXT: adcq %r14, %r13<br>+; X64-NEXT: addq %rax, %r10<br>+; X64-NEXT: adcq %rdx, %r13<br>; X64-NEXT: addq %rbp, %r10<br>; X64-NEXT: adcq %rsi, %r13<br>; X64-NEXT: addq %r8, %r10<br>@@ -1637,7 +1636,7 @@ define void @test_512(i512* %a, i512* %b<br>; X64-NEXT: movq 16(%rsi), %r8<br>; X64-NEXT: movq %rcx, %rax<br>; X64-NEXT: movq %rcx, %r9<br>-; X64-NEXT: movq %r9, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>+; X64-NEXT: movq %rcx, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: mulq %r8<br>; X64-NEXT: movq %rdx, %rdi<br>; X64-NEXT: movq %rax, %r12<br>@@ -1668,7 +1667,7 @@ define void @test_512(i512* %a, i512* %b<br>; X64-NEXT: mulq %rcx<br>; X64-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>; X64-NEXT: movq %rax, %rbp<br>-; X64-NEXT: addq %rbp, %r11<br>+; X64-NEXT: addq %rax, %r11<br>; X64-NEXT: adcq %rdx, %r14<br>; X64-NEXT: addq %r9, %r11<br>; X64-NEXT: adcq %rbx, %r14<br><br>Modified: llvm/trunk/test/CodeGen/X86/mul128.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mul128.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mul128.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/mul128.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/mul128.ll Tue Feb 27 08:59:10 2018<br>@@ -8,7 +8,7 @@ define i128 @foo(i128 %t, i128 %u) {<br>; X64-NEXT: movq %rdx, %r8<br>; X64-NEXT: imulq %rdi, %rcx<br>; X64-NEXT: movq %rdi, %rax<br>-; X64-NEXT: mulq %r8<br>+; X64-NEXT: mulq %rdx<br>; X64-NEXT: addq %rcx, %rdx<br>; X64-NEXT: imulq %r8, %rsi<br>; X64-NEXT: addq %rsi, %rdx<br><br>Modified: llvm/trunk/test/CodeGen/X86/mulvi32.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mulvi32.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mulvi32.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/mulvi32.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/mulvi32.ll Tue Feb 27 08:59:10 2018<br>@@ -234,7 +234,7 @@ define <4 x i64> @_mul4xi32toi64b(<4 x i<br>; SSE-LABEL: _mul4xi32toi64b:<br>; SSE: # %bb.0:<br>; SSE-NEXT: movdqa %xmm0, %xmm2<br>-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]<br>+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]<br>; SSE-NEXT: pmuludq %xmm1, %xmm2<br>; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]<br>; SSE-NEXT: pmuludq %xmm0, %xmm1<br><br>Modified: llvm/trunk/test/CodeGen/X86/musttail-varargs.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/musttail-varargs.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/musttail-varargs.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/musttail-varargs.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/musttail-varargs.ll Tue Feb 27 08:59:10 2018<br>@@ -209,9 +209,9 @@ define void @f_thunk(i8* %this, ...) {<br>; WINDOWS-NEXT: movq %r8, %rdi<br>; WINDOWS-NEXT: movq %rdx, %rbx<br>; WINDOWS-NEXT: movq %rcx, %rbp<br>-; WINDOWS-NEXT: movq %rsi, {{[0-9]+}}(%rsp)<br>-; WINDOWS-NEXT: movq %rdi, {{[0-9]+}}(%rsp)<br>-; WINDOWS-NEXT: movq %rbx, {{[0-9]+}}(%rsp)<br>+; WINDOWS-NEXT: movq %r9, {{[0-9]+}}(%rsp)<br>+; WINDOWS-NEXT: movq %r8, {{[0-9]+}}(%rsp)<br>+; WINDOWS-NEXT: movq %rdx, {{[0-9]+}}(%rsp)<br>; WINDOWS-NEXT: leaq {{[0-9]+}}(%rsp), %rax<br>; WINDOWS-NEXT: movq %rax, {{[0-9]+}}(%rsp)<br>; WINDOWS-NEXT: callq get_f<br><br>Modified: llvm/trunk/test/CodeGen/X86/pmul.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pmul.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pmul.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/pmul.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/pmul.ll Tue Feb 27 08:59:10 2018<br>@@ -9,7 +9,7 @@ define <16 x i8> @mul_v16i8c(<16 x i8> %<br>; SSE2-LABEL: mul_v16i8c:<br>; SSE2: # %bb.0: # %entry<br>; SSE2-NEXT: movdqa %xmm0, %xmm1<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]<br>; SSE2-NEXT: psraw $8, %xmm1<br>; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [117,117,117,117,117,117,117,117]<br>; SSE2-NEXT: pmullw %xmm2, %xmm1<br>@@ -143,10 +143,10 @@ define <16 x i8> @mul_v16i8(<16 x i8> %i<br>; SSE2-LABEL: mul_v16i8:<br>; SSE2: # %bb.0: # %entry<br>; SSE2-NEXT: movdqa %xmm1, %xmm2<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]<br>; SSE2-NEXT: psraw $8, %xmm2<br>; SSE2-NEXT: movdqa %xmm0, %xmm3<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm0[8],xmm3[9],xmm0[9],xmm3[10],xmm0[10],xmm3[11],xmm0[11],xmm3[12],xmm0[12],xmm3[13],xmm0[13],xmm3[14],xmm0[14],xmm3[15],xmm0[15]<br>; SSE2-NEXT: psraw $8, %xmm3<br>; SSE2-NEXT: pmullw %xmm2, %xmm3<br>; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]<br>@@ -386,7 +386,7 @@ define <32 x i8> @mul_v32i8c(<32 x i8> %<br>; SSE2-LABEL: mul_v32i8c:<br>; SSE2: # %bb.0: # %entry<br>; SSE2-NEXT: movdqa %xmm0, %xmm2<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]<br>; SSE2-NEXT: psraw $8, %xmm2<br>; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [117,117,117,117,117,117,117,117]<br>; SSE2-NEXT: pmullw %xmm3, %xmm2<br>@@ -398,7 +398,7 @@ define <32 x i8> @mul_v32i8c(<32 x i8> %<br>; SSE2-NEXT: pand %xmm4, %xmm0<br>; SSE2-NEXT: packuswb %xmm2, %xmm0<br>; SSE2-NEXT: movdqa %xmm1, %xmm2<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]<br>; SSE2-NEXT: psraw $8, %xmm2<br>; SSE2-NEXT: pmullw %xmm3, %xmm2<br>; SSE2-NEXT: pand %xmm4, %xmm2<br>@@ -567,10 +567,10 @@ define <32 x i8> @mul_v32i8(<32 x i8> %i<br>; SSE2-LABEL: mul_v32i8:<br>; SSE2: # %bb.0: # %entry<br>; SSE2-NEXT: movdqa %xmm2, %xmm4<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm2[8],xmm4[9],xmm2[9],xmm4[10],xmm2[10],xmm4[11],xmm2[11],xmm4[12],xmm2[12],xmm4[13],xmm2[13],xmm4[14],xmm2[14],xmm4[15],xmm2[15]<br>; SSE2-NEXT: psraw $8, %xmm4<br>; SSE2-NEXT: movdqa %xmm0, %xmm5<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8],xmm0[8],xmm5[9],xmm0[9],xmm5[10],xmm0[10],xmm5[11],xmm0[11],xmm5[12],xmm0[12],xmm5[13],xmm0[13],xmm5[14],xmm0[14],xmm5[15],xmm0[15]<br>; SSE2-NEXT: psraw $8, %xmm5<br>; SSE2-NEXT: pmullw %xmm4, %xmm5<br>; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [255,255,255,255,255,255,255,255]<br>@@ -583,10 +583,10 @@ define <32 x i8> @mul_v32i8(<32 x i8> %i<br>; SSE2-NEXT: pand %xmm4, %xmm0<br>; SSE2-NEXT: packuswb %xmm5, %xmm0<br>; SSE2-NEXT: movdqa %xmm3, %xmm2<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm3[8],xmm2[9],xmm3[9],xmm2[10],xmm3[10],xmm2[11],xmm3[11],xmm2[12],xmm3[12],xmm2[13],xmm3[13],xmm2[14],xmm3[14],xmm2[15],xmm3[15]<br>; SSE2-NEXT: psraw $8, %xmm2<br>; SSE2-NEXT: movdqa %xmm1, %xmm5<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8],xmm1[8],xmm5[9],xmm1[9],xmm5[10],xmm1[10],xmm5[11],xmm1[11],xmm5[12],xmm1[12],xmm5[13],xmm1[13],xmm5[14],xmm1[14],xmm5[15],xmm1[15]<br>; SSE2-NEXT: psraw $8, %xmm5<br>; SSE2-NEXT: pmullw %xmm2, %xmm5<br>; SSE2-NEXT: pand %xmm4, %xmm5<br>@@ -774,7 +774,7 @@ define <64 x i8> @mul_v64i8c(<64 x i8> %<br>; SSE2-LABEL: mul_v64i8c:<br>; SSE2: # %bb.0: # %entry<br>; SSE2-NEXT: movdqa %xmm0, %xmm6<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm0[8],xmm6[9],xmm0[9],xmm6[10],xmm0[10],xmm6[11],xmm0[11],xmm6[12],xmm0[12],xmm6[13],xmm0[13],xmm6[14],xmm0[14],xmm6[15],xmm0[15]<br>; SSE2-NEXT: psraw $8, %xmm6<br>; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [117,117,117,117,117,117,117,117]<br>; SSE2-NEXT: pmullw %xmm4, %xmm6<br>@@ -786,7 +786,7 @@ define <64 x i8> @mul_v64i8c(<64 x i8> %<br>; SSE2-NEXT: pand %xmm5, %xmm0<br>; SSE2-NEXT: packuswb %xmm6, %xmm0<br>; SSE2-NEXT: movdqa %xmm1, %xmm6<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm1[8],xmm6[9],xmm1[9],xmm6[10],xmm1[10],xmm6[11],xmm1[11],xmm6[12],xmm1[12],xmm6[13],xmm1[13],xmm6[14],xmm1[14],xmm6[15],xmm1[15]<br>; SSE2-NEXT: psraw $8, %xmm6<br>; SSE2-NEXT: pmullw %xmm4, %xmm6<br>; SSE2-NEXT: pand %xmm5, %xmm6<br>@@ -796,7 +796,7 @@ define <64 x i8> @mul_v64i8c(<64 x i8> %<br>; SSE2-NEXT: pand %xmm5, %xmm1<br>; SSE2-NEXT: packuswb %xmm6, %xmm1<br>; SSE2-NEXT: movdqa %xmm2, %xmm6<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm2[8],xmm6[9],xmm2[9],xmm6[10],xmm2[10],xmm6[11],xmm2[11],xmm6[12],xmm2[12],xmm6[13],xmm2[13],xmm6[14],xmm2[14],xmm6[15],xmm2[15]<br>; SSE2-NEXT: psraw $8, %xmm6<br>; SSE2-NEXT: pmullw %xmm4, %xmm6<br>; SSE2-NEXT: pand %xmm5, %xmm6<br>@@ -806,7 +806,7 @@ define <64 x i8> @mul_v64i8c(<64 x i8> %<br>; SSE2-NEXT: pand %xmm5, %xmm2<br>; SSE2-NEXT: packuswb %xmm6, %xmm2<br>; SSE2-NEXT: movdqa %xmm3, %xmm6<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm3[8],xmm6[9],xmm3[9],xmm6[10],xmm3[10],xmm6[11],xmm3[11],xmm6[12],xmm3[12],xmm6[13],xmm3[13],xmm6[14],xmm3[14],xmm6[15],xmm3[15]<br>; SSE2-NEXT: psraw $8, %xmm6<br>; SSE2-NEXT: pmullw %xmm4, %xmm6<br>; SSE2-NEXT: pand %xmm5, %xmm6<br>@@ -821,7 +821,7 @@ define <64 x i8> @mul_v64i8c(<64 x i8> %<br>; SSE41: # %bb.0: # %entry<br>; SSE41-NEXT: movdqa %xmm1, %xmm4<br>; SSE41-NEXT: movdqa %xmm0, %xmm1<br>-; SSE41-NEXT: pmovsxbw %xmm1, %xmm0<br>+; SSE41-NEXT: pmovsxbw %xmm0, %xmm0<br>; SSE41-NEXT: movdqa {{.*#+}} xmm6 = [117,117,117,117,117,117,117,117]<br>; SSE41-NEXT: pmullw %xmm6, %xmm0<br>; SSE41-NEXT: movdqa {{.*#+}} xmm7 = [255,255,255,255,255,255,255,255]<br>@@ -939,10 +939,10 @@ define <64 x i8> @mul_v64i8(<64 x i8> %i<br>; SSE2-LABEL: mul_v64i8:<br>; SSE2: # %bb.0: # %entry<br>; SSE2-NEXT: movdqa %xmm4, %xmm8<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm8 = xmm8[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm8 = xmm8[8],xmm4[8],xmm8[9],xmm4[9],xmm8[10],xmm4[10],xmm8[11],xmm4[11],xmm8[12],xmm4[12],xmm8[13],xmm4[13],xmm8[14],xmm4[14],xmm8[15],xmm4[15]<br>; SSE2-NEXT: psraw $8, %xmm8<br>; SSE2-NEXT: movdqa %xmm0, %xmm9<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm9 = xmm9[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm9 = xmm9[8],xmm0[8],xmm9[9],xmm0[9],xmm9[10],xmm0[10],xmm9[11],xmm0[11],xmm9[12],xmm0[12],xmm9[13],xmm0[13],xmm9[14],xmm0[14],xmm9[15],xmm0[15]<br>; SSE2-NEXT: psraw $8, %xmm9<br>; SSE2-NEXT: pmullw %xmm8, %xmm9<br>; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [255,255,255,255,255,255,255,255]<br>@@ -955,10 +955,10 @@ define <64 x i8> @mul_v64i8(<64 x i8> %i<br>; SSE2-NEXT: pand %xmm8, %xmm0<br>; SSE2-NEXT: packuswb %xmm9, %xmm0<br>; SSE2-NEXT: movdqa %xmm5, %xmm9<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm9 = xmm9[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm9 = xmm9[8],xmm5[8],xmm9[9],xmm5[9],xmm9[10],xmm5[10],xmm9[11],xmm5[11],xmm9[12],xmm5[12],xmm9[13],xmm5[13],xmm9[14],xmm5[14],xmm9[15],xmm5[15]<br>; SSE2-NEXT: psraw $8, %xmm9<br>; SSE2-NEXT: movdqa %xmm1, %xmm4<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm1[8],xmm4[9],xmm1[9],xmm4[10],xmm1[10],xmm4[11],xmm1[11],xmm4[12],xmm1[12],xmm4[13],xmm1[13],xmm4[14],xmm1[14],xmm4[15],xmm1[15]<br>; SSE2-NEXT: psraw $8, %xmm4<br>; SSE2-NEXT: pmullw %xmm9, %xmm4<br>; SSE2-NEXT: pand %xmm8, %xmm4<br>@@ -970,10 +970,10 @@ define <64 x i8> @mul_v64i8(<64 x i8> %i<br>; SSE2-NEXT: pand %xmm8, %xmm1<br>; SSE2-NEXT: packuswb %xmm4, %xmm1<br>; SSE2-NEXT: movdqa %xmm6, %xmm4<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm6[8],xmm4[9],xmm6[9],xmm4[10],xmm6[10],xmm4[11],xmm6[11],xmm4[12],xmm6[12],xmm4[13],xmm6[13],xmm4[14],xmm6[14],xmm4[15],xmm6[15]<br>; SSE2-NEXT: psraw $8, %xmm4<br>; SSE2-NEXT: movdqa %xmm2, %xmm5<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8],xmm2[8],xmm5[9],xmm2[9],xmm5[10],xmm2[10],xmm5[11],xmm2[11],xmm5[12],xmm2[12],xmm5[13],xmm2[13],xmm5[14],xmm2[14],xmm5[15],xmm2[15]<br>; SSE2-NEXT: psraw $8, %xmm5<br>; SSE2-NEXT: pmullw %xmm4, %xmm5<br>; SSE2-NEXT: pand %xmm8, %xmm5<br>@@ -985,10 +985,10 @@ define <64 x i8> @mul_v64i8(<64 x i8> %i<br>; SSE2-NEXT: pand %xmm8, %xmm2<br>; SSE2-NEXT: packuswb %xmm5, %xmm2<br>; SSE2-NEXT: movdqa %xmm7, %xmm4<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm7[8],xmm4[9],xmm7[9],xmm4[10],xmm7[10],xmm4[11],xmm7[11],xmm4[12],xmm7[12],xmm4[13],xmm7[13],xmm4[14],xmm7[14],xmm4[15],xmm7[15]<br>; SSE2-NEXT: psraw $8, %xmm4<br>; SSE2-NEXT: movdqa %xmm3, %xmm5<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8],xmm3[8],xmm5[9],xmm3[9],xmm5[10],xmm3[10],xmm5[11],xmm3[11],xmm5[12],xmm3[12],xmm5[13],xmm3[13],xmm5[14],xmm3[14],xmm5[15],xmm3[15]<br>; SSE2-NEXT: psraw $8, %xmm5<br>; SSE2-NEXT: pmullw %xmm4, %xmm5<br>; SSE2-NEXT: pand %xmm8, %xmm5<br>@@ -1006,7 +1006,7 @@ define <64 x i8> @mul_v64i8(<64 x i8> %i<br>; SSE41-NEXT: movdqa %xmm1, %xmm8<br>; SSE41-NEXT: movdqa %xmm0, %xmm1<br>; SSE41-NEXT: pmovsxbw %xmm4, %xmm9<br>-; SSE41-NEXT: pmovsxbw %xmm1, %xmm0<br>+; SSE41-NEXT: pmovsxbw %xmm0, %xmm0<br>; SSE41-NEXT: pmullw %xmm9, %xmm0<br>; SSE41-NEXT: movdqa {{.*#+}} xmm9 = [255,255,255,255,255,255,255,255]<br>; SSE41-NEXT: pand %xmm9, %xmm0<br>@@ -1383,7 +1383,7 @@ define <8 x i64> @mul_v8i64_sext(<8 x i1<br>; SSE2: # %bb.0:<br>; SSE2-NEXT: movdqa %xmm1, %xmm4<br>; SSE2-NEXT: movdqa %xmm0, %xmm1<br>-; SSE2-NEXT: punpckhwd {{.*#+}} xmm9 = xmm9[4],xmm1[4],xmm9[5],xmm1[5],xmm9[6],xmm1[6],xmm9[7],xmm1[7]<br>+; SSE2-NEXT: punpckhwd {{.*#+}} xmm9 = xmm9[4],xmm0[4],xmm9[5],xmm0[5],xmm9[6],xmm0[6],xmm9[7],xmm0[7]<br>; SSE2-NEXT: movdqa %xmm9, %xmm0<br>; SSE2-NEXT: psrad $31, %xmm0<br>; SSE2-NEXT: psrad $16, %xmm9<br><br>Modified: llvm/trunk/test/CodeGen/X86/powi.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/powi.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/powi.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/powi.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/powi.ll Tue Feb 27 08:59:10 2018<br>@@ -5,7 +5,7 @@ define double @pow_wrapper(double %a) no<br>; CHECK-LABEL: pow_wrapper:<br>; CHECK: # %bb.0:<br>; CHECK-NEXT: movapd %xmm0, %xmm1<br>-; CHECK-NEXT: mulsd %xmm1, %xmm1<br>+; CHECK-NEXT: mulsd %xmm0, %xmm1<br>; CHECK-NEXT: mulsd %xmm1, %xmm0<br>; CHECK-NEXT: mulsd %xmm1, %xmm1<br>; CHECK-NEXT: mulsd %xmm1, %xmm0<br><br>Modified: llvm/trunk/test/CodeGen/X86/pr11334.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr11334.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr11334.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/pr11334.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/pr11334.ll Tue Feb 27 08:59:10 2018<br>@@ -25,7 +25,7 @@ define <3 x double> @v3f2d_ext_vec(<3 x<br>; SSE-NEXT: cvtps2pd %xmm0, %xmm0<br>; SSE-NEXT: movlps %xmm0, -{{[0-9]+}}(%rsp)<br>; SSE-NEXT: movaps %xmm2, %xmm1<br>-; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]<br>; SSE-NEXT: fldl -{{[0-9]+}}(%rsp)<br>; SSE-NEXT: movaps %xmm2, %xmm0<br>; SSE-NEXT: retq<br><br>Modified: llvm/trunk/test/CodeGen/X86/pr29112.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr29112.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr29112.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/pr29112.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/pr29112.ll Tue Feb 27 08:59:10 2018<br>@@ -49,13 +49,13 @@ define <4 x float> @bar(<4 x float>* %a1<br>; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm12[0]<br>; CHECK-NEXT: vaddps %xmm3, %xmm2, %xmm2<br>; CHECK-NEXT: vmovaps %xmm15, %xmm1<br>-; CHECK-NEXT: vmovaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill<br>-; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm9<br>+; CHECK-NEXT: vmovaps %xmm15, {{[0-9]+}}(%rsp) # 16-byte Spill<br>+; CHECK-NEXT: vaddps %xmm0, %xmm15, %xmm9<br>; CHECK-NEXT: vaddps %xmm14, %xmm10, %xmm0<br>-; CHECK-NEXT: vaddps %xmm1, %xmm1, %xmm8<br>+; CHECK-NEXT: vaddps %xmm15, %xmm15, %xmm8<br>; CHECK-NEXT: vaddps %xmm11, %xmm3, %xmm3<br>; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0<br>-; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0<br>+; CHECK-NEXT: vaddps %xmm0, %xmm15, %xmm0<br>; CHECK-NEXT: vmovaps %xmm8, {{[0-9]+}}(%rsp)<br>; CHECK-NEXT: vmovaps %xmm9, (%rsp)<br>; CHECK-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm3 # 16-byte Reload<br><br>Modified: llvm/trunk/test/CodeGen/X86/pr34080-2.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr34080-2.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr34080-2.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/pr34080-2.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/pr34080-2.ll Tue Feb 27 08:59:10 2018<br>@@ -23,7 +23,7 @@ define void @computeJD(%struct.DateTime*<br>; CHECK-NEXT: movl %esi, %eax<br>; CHECK-NEXT: imull %ecx<br>; CHECK-NEXT: movl %edx, %ecx<br>-; CHECK-NEXT: movl %ecx, %eax<br>+; CHECK-NEXT: movl %edx, %eax<br>; CHECK-NEXT: shrl $31, %eax<br>; CHECK-NEXT: sarl $5, %ecx<br>; CHECK-NEXT: addl %eax, %ecx<br>@@ -31,7 +31,7 @@ define void @computeJD(%struct.DateTime*<br>; CHECK-NEXT: movl %esi, %eax<br>; CHECK-NEXT: imull %edx<br>; CHECK-NEXT: movl %edx, %edi<br>-; CHECK-NEXT: movl %edi, %eax<br>+; CHECK-NEXT: movl %edx, %eax<br>; CHECK-NEXT: shrl $31, %eax<br>; CHECK-NEXT: sarl $7, %edi<br>; CHECK-NEXT: addl %eax, %edi<br><br>Modified: llvm/trunk/test/CodeGen/X86/retpoline-external.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/retpoline-external.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/retpoline-external.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/retpoline-external.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/retpoline-external.ll Tue Feb 27 08:59:10 2018<br>@@ -19,7 +19,7 @@ entry:<br>; X64-LABEL: icall_reg:<br>; X64-DAG: movq %rdi, %[[fp:[^ ]*]]<br>; X64-DAG: movl %esi, %[[x:[^ ]*]]<br>-; X64: movl %[[x]], %edi<br>+; X64: movl %esi, %edi<br>; X64: callq bar<br>; X64-DAG: movl %[[x]], %edi<br>; X64-DAG: movq %[[fp]], %r11<br>@@ -111,7 +111,7 @@ define void @vcall(%struct.Foo* %obj) #0<br><br>; X64-LABEL: vcall:<br>; X64: movq %rdi, %[[obj:[^ ]*]]<br>-; X64: movq (%[[obj]]), %[[vptr:[^ ]*]]<br>+; X64: movq (%rdi), %[[vptr:[^ ]*]]<br>; X64: movq 8(%[[vptr]]), %[[fp:[^ ]*]]<br>; X64: movq %[[fp]], %r11<br>; X64: callq __x86_indirect_thunk_r11<br><br>Modified: llvm/trunk/test/CodeGen/X86/retpoline.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/retpoline.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/retpoline.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/retpoline.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/retpoline.ll Tue Feb 27 08:59:10 2018<br>@@ -19,7 +19,7 @@ entry:<br>; X64-LABEL: icall_reg:<br>; X64-DAG: movq %rdi, %[[fp:[^ ]*]]<br>; X64-DAG: movl %esi, %[[x:[^ ]*]]<br>-; X64: movl %[[x]], %edi<br>+; X64: movl %esi, %edi<br>; X64: callq bar<br>; X64-DAG: movl %[[x]], %edi<br>; X64-DAG: movq %[[fp]], %r11<br>@@ -111,7 +111,7 @@ define void @vcall(%struct.Foo* %obj) #0<br><br>; X64-LABEL: vcall:<br>; X64: movq %rdi, %[[obj:[^ ]*]]<br>-; X64: movq (%[[obj]]), %[[vptr:[^ ]*]]<br>+; X64: movq (%rdi), %[[vptr:[^ ]*]]<br>; X64: movq 8(%[[vptr]]), %[[fp:[^ ]*]]<br>; X64: movq %[[fp]], %r11<br>; X64: callq __llvm_retpoline_r11<br><br>Modified: llvm/trunk/test/CodeGen/X86/sad.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sad.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sad.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/sad.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/sad.ll Tue Feb 27 08:59:10 2018<br>@@ -670,7 +670,7 @@ define i32 @sad_avx64i8() nounwind {<br>; SSE2-NEXT: paddd %xmm7, %xmm0<br>; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp) # 16-byte Spill<br>; SSE2-NEXT: movdqa %xmm13, %xmm1<br>-; SSE2-NEXT: movdqa %xmm1, %xmm0<br>+; SSE2-NEXT: movdqa %xmm13, %xmm0<br>; SSE2-NEXT: psrad $31, %xmm0<br>; SSE2-NEXT: paddd %xmm0, %xmm1<br>; SSE2-NEXT: pxor %xmm0, %xmm1<br><br>Modified: llvm/trunk/test/CodeGen/X86/safestack.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/safestack.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/safestack.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/safestack.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/safestack.ll Tue Feb 27 08:59:10 2018<br>@@ -40,6 +40,6 @@ declare void @_Z7CapturePi(i32*)<br><br>; LINUX-I386-PA: calll __safestack_pointer_address<br>; LINUX-I386-PA: movl %eax, %[[A:.*]]<br>-; LINUX-I386-PA: movl (%[[A]]), %[[B:.*]]<br>+; LINUX-I386-PA: movl (%eax), %[[B:.*]]<br>; LINUX-I386-PA: leal -16(%[[B]]), %[[C:.*]]<br>; LINUX-I386-PA: movl %[[C]], (%[[A]])<br><br>Modified: llvm/trunk/test/CodeGen/X86/safestack_inline.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/safestack_inline.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/safestack_inline.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/safestack_inline.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/safestack_inline.ll Tue Feb 27 08:59:10 2018<br>@@ -25,6 +25,6 @@ declare void @_Z7CapturePi(i32*)<br><br>; CALL: callq __safestack_pointer_address<br>; CALL: movq %rax, %[[A:.*]]<br>-; CALL: movq (%[[A]]), %[[B:.*]]<br>+; CALL: movq (%rax), %[[B:.*]]<br>; CALL: leaq -16(%[[B]]), %[[C:.*]]<br>; CALL: movq %[[C]], (%[[A]])<br><br>Modified: llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll Tue Feb 27 08:59:10 2018<br>@@ -11,7 +11,7 @@ define void @vectorDiv (<2 x i32> addrsp<br>; CHECK-NEXT: movq %rdx, %r8<br>; CHECK-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)<br>; CHECK-NEXT: movq %rsi, -{{[0-9]+}}(%rsp)<br>-; CHECK-NEXT: movq %r8, -{{[0-9]+}}(%rsp)<br>+; CHECK-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)<br>; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rcx<br>; CHECK-NEXT: pmovsxdq (%rdi,%rcx,8), %xmm0<br>; CHECK-NEXT: pmovsxdq (%rsi,%rcx,8), %xmm1<br>@@ -403,7 +403,7 @@ define void @test_int_div(<3 x i32>* %de<br>; CHECK-LABEL: test_int_div:<br>; CHECK: # %bb.0: # %entry<br>; CHECK-NEXT: movl %edx, %r9d<br>-; CHECK-NEXT: testl %r9d, %r9d<br>+; CHECK-NEXT: testl %edx, %edx<br>; CHECK-NEXT: jle .LBB12_3<br>; CHECK-NEXT: # %bb.1: # %bb.nph<br>; CHECK-NEXT: xorl %ecx, %ecx<br><br>Modified: llvm/trunk/test/CodeGen/X86/select.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/select.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/select.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/select.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/select.ll Tue Feb 27 08:59:10 2018<br>@@ -22,8 +22,7 @@ define i32 @test1(%0* %p, %0* %q, i1 %r)<br>; MCU-NEXT: jne .LBB0_1<br>; MCU-NEXT: # %bb.2:<br>; MCU-NEXT: addl $8, %edx<br>-; MCU-NEXT: movl %edx, %eax<br>-; MCU-NEXT: movl (%eax), %eax<br>+; MCU-NEXT: movl (%edx), %eax<br>; MCU-NEXT: retl<br>; MCU-NEXT: .LBB0_1:<br>; MCU-NEXT: addl $8, %eax<br><br>Modified: llvm/trunk/test/CodeGen/X86/shrink-wrap-chkstk.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shrink-wrap-chkstk.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shrink-wrap-chkstk.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/shrink-wrap-chkstk.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/shrink-wrap-chkstk.ll Tue Feb 27 08:59:10 2018<br>@@ -61,7 +61,7 @@ false:<br><br>; CHECK-LABEL: @use_eax_before_prologue@8: # @use_eax_before_prologue<br>; CHECK: movl %ecx, %eax<br>-; CHECK: cmpl %edx, %eax<br>+; CHECK: cmpl %edx, %ecx<br>; CHECK: jge LBB1_2<br>; CHECK: pushl %eax<br>; CHECK: movl $4092, %eax<br><br>Modified: llvm/trunk/test/CodeGen/X86/slow-pmulld.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/slow-pmulld.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/slow-pmulld.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/slow-pmulld.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/slow-pmulld.ll Tue Feb 27 08:59:10 2018<br>@@ -614,7 +614,7 @@ define <16 x i32> @test_mul_v16i32_v16i1<br>; SLOW32-NEXT: movdqa %xmm1, %xmm3<br>; SLOW32-NEXT: movdqa %xmm0, %xmm1<br>; SLOW32-NEXT: movdqa {{.*#+}} xmm2 = [18778,18778,18778,18778,18778,18778,18778,18778]<br>-; SLOW32-NEXT: movdqa %xmm1, %xmm4<br>+; SLOW32-NEXT: movdqa %xmm0, %xmm4<br>; SLOW32-NEXT: pmulhuw %xmm2, %xmm4<br>; SLOW32-NEXT: pmullw %xmm2, %xmm1<br>; SLOW32-NEXT: movdqa %xmm1, %xmm0<br>@@ -633,7 +633,7 @@ define <16 x i32> @test_mul_v16i32_v16i1<br>; SLOW64-NEXT: movdqa %xmm1, %xmm3<br>; SLOW64-NEXT: movdqa %xmm0, %xmm1<br>; SLOW64-NEXT: movdqa {{.*#+}} xmm2 = [18778,18778,18778,18778,18778,18778,18778,18778]<br>-; SLOW64-NEXT: movdqa %xmm1, %xmm4<br>+; SLOW64-NEXT: movdqa %xmm0, %xmm4<br>; SLOW64-NEXT: pmulhuw %xmm2, %xmm4<br>; SLOW64-NEXT: pmullw %xmm2, %xmm1<br>; SLOW64-NEXT: movdqa %xmm1, %xmm0<br><br>Modified: llvm/trunk/test/CodeGen/X86/sqrt-fastmath.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sqrt-fastmath.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sqrt-fastmath.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/sqrt-fastmath.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/sqrt-fastmath.ll Tue Feb 27 08:59:10 2018<br>@@ -201,7 +201,7 @@ define float @f32_estimate(float %x) #1<br>; SSE: # %bb.0:<br>; SSE-NEXT: rsqrtss %xmm0, %xmm1<br>; SSE-NEXT: movaps %xmm1, %xmm2<br>-; SSE-NEXT: mulss %xmm2, %xmm2<br>+; SSE-NEXT: mulss %xmm1, %xmm2<br>; SSE-NEXT: mulss %xmm0, %xmm2<br>; SSE-NEXT: addss {{.*}}(%rip), %xmm2<br>; SSE-NEXT: mulss {{.*}}(%rip), %xmm1<br>@@ -247,7 +247,7 @@ define <4 x float> @v4f32_estimate(<4 x<br>; SSE: # %bb.0:<br>; SSE-NEXT: rsqrtps %xmm0, %xmm1<br>; SSE-NEXT: movaps %xmm1, %xmm2<br>-; SSE-NEXT: mulps %xmm2, %xmm2<br>+; SSE-NEXT: mulps %xmm1, %xmm2<br>; SSE-NEXT: mulps %xmm0, %xmm2<br>; SSE-NEXT: addps {{.*}}(%rip), %xmm2<br>; SSE-NEXT: mulps {{.*}}(%rip), %xmm1<br>@@ -297,7 +297,7 @@ define <8 x float> @v8f32_estimate(<8 x<br>; SSE-NEXT: rsqrtps %xmm0, %xmm3<br>; SSE-NEXT: movaps {{.*#+}} xmm4 = [-5.000000e-01,-5.000000e-01,-5.000000e-01,-5.000000e-01]<br>; SSE-NEXT: movaps %xmm3, %xmm2<br>-; SSE-NEXT: mulps %xmm2, %xmm2<br>+; SSE-NEXT: mulps %xmm3, %xmm2<br>; SSE-NEXT: mulps %xmm0, %xmm2<br>; SSE-NEXT: movaps {{.*#+}} xmm0 = [-3.000000e+00,-3.000000e+00,-3.000000e+00,-3.000000e+00]<br>; SSE-NEXT: addps %xmm0, %xmm2<br>@@ -305,7 +305,7 @@ define <8 x float> @v8f32_estimate(<8 x<br>; SSE-NEXT: mulps %xmm3, %xmm2<br>; SSE-NEXT: rsqrtps %xmm1, %xmm5<br>; SSE-NEXT: movaps %xmm5, %xmm3<br>-; SSE-NEXT: mulps %xmm3, %xmm3<br>+; SSE-NEXT: mulps %xmm5, %xmm3<br>; SSE-NEXT: mulps %xmm1, %xmm3<br>; SSE-NEXT: addps %xmm0, %xmm3<br>; SSE-NEXT: mulps %xmm4, %xmm3<br><br>Modified: llvm/trunk/test/CodeGen/X86/sse-scalar-fp-arith.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-scalar-fp-arith.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-scalar-fp-arith.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/sse-scalar-fp-arith.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/sse-scalar-fp-arith.ll Tue Feb 27 08:59:10 2018<br>@@ -1084,8 +1084,7 @@ define <4 x float> @add_ss_mask(<4 x flo<br>; SSE2-NEXT: testb $1, %dil<br>; SSE2-NEXT: jne .LBB62_1<br>; SSE2-NEXT: # %bb.2:<br>-; SSE2-NEXT: movaps %xmm2, %xmm1<br>-; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]<br>+; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]<br>; SSE2-NEXT: retq<br>; SSE2-NEXT: .LBB62_1:<br>; SSE2-NEXT: addss %xmm0, %xmm1<br>@@ -1097,8 +1096,7 @@ define <4 x float> @add_ss_mask(<4 x flo<br>; SSE41-NEXT: testb $1, %dil<br>; SSE41-NEXT: jne .LBB62_1<br>; SSE41-NEXT: # %bb.2:<br>-; SSE41-NEXT: movaps %xmm2, %xmm1<br>-; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]<br>+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]<br>; SSE41-NEXT: retq<br>; SSE41-NEXT: .LBB62_1:<br>; SSE41-NEXT: addss %xmm0, %xmm1<br>@@ -1138,8 +1136,7 @@ define <2 x double> @add_sd_mask(<2 x do<br>; SSE2-NEXT: testb $1, %dil<br>; SSE2-NEXT: jne .LBB63_1<br>; SSE2-NEXT: # %bb.2:<br>-; SSE2-NEXT: movapd %xmm2, %xmm1<br>-; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]<br>+; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]<br>; SSE2-NEXT: retq<br>; SSE2-NEXT: .LBB63_1:<br>; SSE2-NEXT: addsd %xmm0, %xmm1<br>@@ -1151,8 +1148,7 @@ define <2 x double> @add_sd_mask(<2 x do<br>; SSE41-NEXT: testb $1, %dil<br>; SSE41-NEXT: jne .LBB63_1<br>; SSE41-NEXT: # %bb.2:<br>-; SSE41-NEXT: movaps %xmm2, %xmm1<br>-; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]<br>+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3]<br>; SSE41-NEXT: retq<br>; SSE41-NEXT: .LBB63_1:<br>; SSE41-NEXT: addsd %xmm0, %xmm1<br><br>Modified: llvm/trunk/test/CodeGen/X86/sse1.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse1.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse1.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/sse1.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/sse1.ll Tue Feb 27 08:59:10 2018<br>@@ -16,7 +16,7 @@ define <2 x float> @test4(<2 x float> %A<br>; X32-LABEL: test4:<br>; X32: # %bb.0: # %entry<br>; X32-NEXT: movaps %xmm0, %xmm2<br>-; X32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]<br>+; X32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[2,3]<br>; X32-NEXT: addss %xmm1, %xmm0<br>; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]<br>; X32-NEXT: subss %xmm1, %xmm2<br>@@ -26,7 +26,7 @@ define <2 x float> @test4(<2 x float> %A<br>; X64-LABEL: test4:<br>; X64: # %bb.0: # %entry<br>; X64-NEXT: movaps %xmm0, %xmm2<br>-; X64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]<br>+; X64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[2,3]<br>; X64-NEXT: addss %xmm1, %xmm0<br>; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]<br>; X64-NEXT: subss %xmm1, %xmm2<br><br>Modified: llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll Tue Feb 27 08:59:10 2018<br>@@ -406,9 +406,9 @@ define <4 x float> @test16(<4 x float> %<br>; SSE-NEXT: movaps %xmm0, %xmm2<br>; SSE-NEXT: subss %xmm0, %xmm2<br>; SSE-NEXT: movaps %xmm0, %xmm3<br>-; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm3[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]<br>; SSE-NEXT: movaps %xmm1, %xmm4<br>-; SSE-NEXT: movhlps {{.*#+}} xmm4 = xmm4[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm4 = xmm1[1],xmm4[1]<br>; SSE-NEXT: subss %xmm4, %xmm3<br>; SSE-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]<br>; SSE-NEXT: addss %xmm0, %xmm4<br><br>Modified: llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll Tue Feb 27 08:59:10 2018<br>@@ -114,7 +114,7 @@ define void @test6(i32 %a) gc "statepoin<br>; CHECK-NEXT: .cfi_def_cfa_offset 32<br>; CHECK-NEXT: .cfi_offset %rbx, -16<br>; CHECK-NEXT: movl %edi, %ebx<br>-; CHECK-NEXT: movl %ebx, {{[0-9]+}}(%rsp)<br>+; CHECK-NEXT: movl %edi, {{[0-9]+}}(%rsp)<br>; CHECK-NEXT: callq _baz<br>; CHECK-NEXT: Ltmp6:<br>; CHECK-NEXT: callq _bar<br><br>Modified: llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll Tue Feb 27 08:59:10 2018<br>@@ -61,9 +61,9 @@ define i32 @back_to_back_deopt(i32 %a, i<br> gc "statepoint-example" {<br>; CHECK-LABEL: back_to_back_deopt<br>; The exact stores don't matter, but there need to be three stack slots created<br>-; CHECK-DAG: movl<span class=apple-tab-span> </span><span class=apple-converted-space> </span>%ebx, 12(%rsp)<br>-; CHECK-DAG: movl<span class=apple-tab-span> </span><span class=apple-converted-space> </span>%ebp, 8(%rsp)<br>-; CHECK-DAG: movl<span class=apple-tab-span> </span><span class=apple-converted-space> </span>%r14d, 4(%rsp)<br>+; CHECK-DAG: movl<span class=apple-tab-span> </span><span class=apple-converted-space> </span>%edi, 12(%rsp)<br>+; CHECK-DAG: movl<span class=apple-tab-span> </span><span class=apple-converted-space> </span>%esi, 8(%rsp)<br>+; CHECK-DAG: movl<span class=apple-tab-span> </span><span class=apple-converted-space> </span>%edx, 4(%rsp)<br>; CHECK: callq<br>; CHECK-DAG: movl<span class=apple-tab-span> </span><span class=apple-converted-space> </span>%ebx, 12(%rsp)<br>; CHECK-DAG: movl<span class=apple-tab-span> </span><span class=apple-converted-space> </span>%ebp, 8(%rsp)<br><br>Modified: llvm/trunk/test/CodeGen/X86/vec_fp_to_int.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_fp_to_int.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_fp_to_int.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vec_fp_to_int.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vec_fp_to_int.ll Tue Feb 27 08:59:10 2018<br>@@ -1016,12 +1016,12 @@ define <4 x i64> @fptosi_4f32_to_4i64(<8<br>; SSE-NEXT: cvttss2si %xmm0, %rax<br>; SSE-NEXT: movq %rax, %xmm2<br>; SSE-NEXT: movaps %xmm0, %xmm1<br>-; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]<br>+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[2,3]<br>; SSE-NEXT: cvttss2si %xmm1, %rax<br>; SSE-NEXT: movq %rax, %xmm1<br>; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]<br>; SSE-NEXT: movaps %xmm0, %xmm1<br>-; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1,2,3]<br>+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1],xmm0[2,3]<br>; SSE-NEXT: cvttss2si %xmm1, %rax<br>; SSE-NEXT: movq %rax, %xmm3<br>; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]<br>@@ -1124,12 +1124,12 @@ define <4 x i64> @fptosi_8f32_to_4i64(<8<br>; SSE-NEXT: cvttss2si %xmm0, %rax<br>; SSE-NEXT: movq %rax, %xmm2<br>; SSE-NEXT: movaps %xmm0, %xmm1<br>-; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]<br>+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[2,3]<br>; SSE-NEXT: cvttss2si %xmm1, %rax<br>; SSE-NEXT: movq %rax, %xmm1<br>; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]<br>; SSE-NEXT: movaps %xmm0, %xmm1<br>-; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1,2,3]<br>+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1],xmm0[2,3]<br>; SSE-NEXT: cvttss2si %xmm1, %rax<br>; SSE-NEXT: movq %rax, %xmm3<br>; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]<br>@@ -1314,11 +1314,11 @@ define <4 x i32> @fptoui_4f32_to_4i32(<4<br>; SSE-LABEL: fptoui_4f32_to_4i32:<br>; SSE: # %bb.0:<br>; SSE-NEXT: movaps %xmm0, %xmm1<br>-; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1,2,3]<br>+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1],xmm0[2,3]<br>; SSE-NEXT: cvttss2si %xmm1, %rax<br>; SSE-NEXT: movd %eax, %xmm1<br>; SSE-NEXT: movaps %xmm0, %xmm2<br>-; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]<br>; SSE-NEXT: cvttss2si %xmm2, %rax<br>; SSE-NEXT: movd %eax, %xmm2<br>; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]<br>@@ -1556,7 +1556,7 @@ define <8 x i32> @fptoui_8f32_to_8i32(<8<br>; SSE-NEXT: cvttss2si %xmm0, %rax<br>; SSE-NEXT: movd %eax, %xmm0<br>; SSE-NEXT: movaps %xmm2, %xmm3<br>-; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm3[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm2[1],xmm3[1]<br>; SSE-NEXT: cvttss2si %xmm3, %rax<br>; SSE-NEXT: movd %eax, %xmm3<br>; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]<br>@@ -1568,11 +1568,11 @@ define <8 x i32> @fptoui_8f32_to_8i32(<8<br>; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]<br>; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]<br>; SSE-NEXT: movaps %xmm1, %xmm2<br>-; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,1,2,3]<br>+; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,1],xmm1[2,3]<br>; SSE-NEXT: cvttss2si %xmm2, %rax<br>; SSE-NEXT: movd %eax, %xmm2<br>; SSE-NEXT: movaps %xmm1, %xmm3<br>-; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm3[1,1]<br>+; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]<br>; SSE-NEXT: cvttss2si %xmm3, %rax<br>; SSE-NEXT: movd %eax, %xmm3<br>; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]<br>@@ -1683,7 +1683,7 @@ define <4 x i64> @fptoui_4f32_to_4i64(<8<br>; SSE-NEXT: cmovaeq %rcx, %rdx<br>; SSE-NEXT: movq %rdx, %xmm2<br>; SSE-NEXT: movaps %xmm0, %xmm3<br>-; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,2,3]<br>+; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[2,3]<br>; SSE-NEXT: movaps %xmm3, %xmm4<br>; SSE-NEXT: subss %xmm1, %xmm4<br>; SSE-NEXT: cvttss2si %xmm4, %rcx<br>@@ -1694,7 +1694,7 @@ define <4 x i64> @fptoui_4f32_to_4i64(<8<br>; SSE-NEXT: movq %rdx, %xmm3<br>; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]<br>; SSE-NEXT: movaps %xmm0, %xmm3<br>-; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]<br>+; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1],xmm0[2,3]<br>; SSE-NEXT: movaps %xmm3, %xmm4<br>; SSE-NEXT: subss %xmm1, %xmm4<br>; SSE-NEXT: cvttss2si %xmm4, %rcx<br>@@ -1861,7 +1861,7 @@ define <4 x i64> @fptoui_8f32_to_4i64(<8<br>; SSE-NEXT: cmovaeq %rcx, %rdx<br>; SSE-NEXT: movq %rdx, %xmm2<br>; SSE-NEXT: movaps %xmm0, %xmm3<br>-; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,2,3]<br>+; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[2,3]<br>; SSE-NEXT: movaps %xmm3, %xmm4<br>; SSE-NEXT: subss %xmm1, %xmm4<br>; SSE-NEXT: cvttss2si %xmm4, %rcx<br>@@ -1872,7 +1872,7 @@ define <4 x i64> @fptoui_8f32_to_4i64(<8<br>; SSE-NEXT: movq %rdx, %xmm3<br>; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]<br>; SSE-NEXT: movaps %xmm0, %xmm3<br>-; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]<br>+; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1],xmm0[2,3]<br>; SSE-NEXT: movaps %xmm3, %xmm4<br>; SSE-NEXT: subss %xmm1, %xmm4<br>; SSE-NEXT: cvttss2si %xmm4, %rcx<br><br>Modified: llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll Tue Feb 27 08:59:10 2018<br>@@ -1591,7 +1591,7 @@ define <4 x float> @uitofp_2i64_to_4f32(<br>; SSE-LABEL: uitofp_2i64_to_4f32:<br>; SSE: # %bb.0:<br>; SSE-NEXT: movdqa %xmm0, %xmm1<br>-; SSE-NEXT: movq %xmm1, %rax<br>+; SSE-NEXT: movq %xmm0, %rax<br>; SSE-NEXT: testq %rax, %rax<br>; SSE-NEXT: js .LBB39_1<br>; SSE-NEXT: # %bb.2:<br>@@ -1819,7 +1819,7 @@ define <4 x float> @uitofp_4i64_to_4f32_<br>; SSE-LABEL: uitofp_4i64_to_4f32_undef:<br>; SSE: # %bb.0:<br>; SSE-NEXT: movdqa %xmm0, %xmm1<br>-; SSE-NEXT: movq %xmm1, %rax<br>+; SSE-NEXT: movq %xmm0, %rax<br>; SSE-NEXT: testq %rax, %rax<br>; SSE-NEXT: js .LBB41_1<br>; SSE-NEXT: # %bb.2:<br><br>Modified: llvm/trunk/test/CodeGen/X86/vec_minmax_uint.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_minmax_uint.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_minmax_uint.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vec_minmax_uint.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vec_minmax_uint.ll Tue Feb 27 08:59:10 2018<br>@@ -1006,7 +1006,7 @@ define <4 x i64> @min_lt_v4i64(<4 x i64><br>; SSE42: # %bb.0:<br>; SSE42-NEXT: movdqa %xmm0, %xmm4<br>; SSE42-NEXT: movdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808]<br>-; SSE42-NEXT: movdqa %xmm4, %xmm6<br>+; SSE42-NEXT: movdqa %xmm0, %xmm6<br>; SSE42-NEXT: pxor %xmm5, %xmm6<br>; SSE42-NEXT: movdqa %xmm2, %xmm0<br>; SSE42-NEXT: pxor %xmm5, %xmm0<br>@@ -1426,7 +1426,7 @@ define <4 x i64> @min_le_v4i64(<4 x i64><br>; SSE42: # %bb.0:<br>; SSE42-NEXT: movdqa %xmm0, %xmm4<br>; SSE42-NEXT: movdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808]<br>-; SSE42-NEXT: movdqa %xmm4, %xmm6<br>+; SSE42-NEXT: movdqa %xmm0, %xmm6<br>; SSE42-NEXT: pxor %xmm5, %xmm6<br>; SSE42-NEXT: movdqa %xmm2, %xmm0<br>; SSE42-NEXT: pxor %xmm5, %xmm0<br><br>Modified: llvm/trunk/test/CodeGen/X86/vec_shift4.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shift4.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shift4.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vec_shift4.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vec_shift4.ll Tue Feb 27 08:59:10 2018<br>@@ -35,7 +35,7 @@ define <2 x i64> @shl2(<16 x i8> %r, <16<br>; X32: # %bb.0: # %entry<br>; X32-NEXT: movdqa %xmm0, %xmm2<br>; X32-NEXT: psllw $5, %xmm1<br>-; X32-NEXT: movdqa %xmm2, %xmm3<br>+; X32-NEXT: movdqa %xmm0, %xmm3<br>; X32-NEXT: psllw $4, %xmm3<br>; X32-NEXT: pand {{\.LCPI.*}}, %xmm3<br>; X32-NEXT: movdqa %xmm1, %xmm0<br>@@ -47,7 +47,7 @@ define <2 x i64> @shl2(<16 x i8> %r, <16<br>; X32-NEXT: movdqa %xmm1, %xmm0<br>; X32-NEXT: pblendvb %xmm0, %xmm3, %xmm2<br>; X32-NEXT: movdqa %xmm2, %xmm3<br>-; X32-NEXT: paddb %xmm3, %xmm3<br>+; X32-NEXT: paddb %xmm2, %xmm3<br>; X32-NEXT: paddb %xmm1, %xmm1<br>; X32-NEXT: movdqa %xmm1, %xmm0<br>; X32-NEXT: pblendvb %xmm0, %xmm3, %xmm2<br>@@ -58,7 +58,7 @@ define <2 x i64> @shl2(<16 x i8> %r, <16<br>; X64: # %bb.0: # %entry<br>; X64-NEXT: movdqa %xmm0, %xmm2<br>; X64-NEXT: psllw $5, %xmm1<br>-; X64-NEXT: movdqa %xmm2, %xmm3<br>+; X64-NEXT: movdqa %xmm0, %xmm3<br>; X64-NEXT: psllw $4, %xmm3<br>; X64-NEXT: pand {{.*}}(%rip), %xmm3<br>; X64-NEXT: movdqa %xmm1, %xmm0<br>@@ -70,7 +70,7 @@ define <2 x i64> @shl2(<16 x i8> %r, <16<br>; X64-NEXT: movdqa %xmm1, %xmm0<br>; X64-NEXT: pblendvb %xmm0, %xmm3, %xmm2<br>; X64-NEXT: movdqa %xmm2, %xmm3<br>-; X64-NEXT: paddb %xmm3, %xmm3<br>+; X64-NEXT: paddb %xmm2, %xmm3<br>; X64-NEXT: paddb %xmm1, %xmm1<br>; X64-NEXT: movdqa %xmm1, %xmm0<br>; X64-NEXT: pblendvb %xmm0, %xmm3, %xmm2<br><br>Modified: llvm/trunk/test/CodeGen/X86/vector-blend.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-blend.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-blend.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vector-blend.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vector-blend.ll Tue Feb 27 08:59:10 2018<br>@@ -954,7 +954,7 @@ define <4 x i32> @blend_neg_logic_v4i32_<br>; SSE41: # %bb.0: # %entry<br>; SSE41-NEXT: movdqa %xmm0, %xmm2<br>; SSE41-NEXT: pxor %xmm3, %xmm3<br>-; SSE41-NEXT: psubd %xmm2, %xmm3<br>+; SSE41-NEXT: psubd %xmm0, %xmm3<br>; SSE41-NEXT: movaps %xmm1, %xmm0<br>; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm3<br>; SSE41-NEXT: movaps %xmm3, %xmm0<br><br>Modified: llvm/trunk/test/CodeGen/X86/vector-idiv-sdiv-128.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-idiv-sdiv-128.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-idiv-sdiv-128.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vector-idiv-sdiv-128.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vector-idiv-sdiv-128.ll Tue Feb 27 08:59:10 2018<br>@@ -177,13 +177,13 @@ define <16 x i8> @test_div7_16i8(<16 x i<br>; SSE2-LABEL: test_div7_16i8:<br>; SSE2: # %bb.0:<br>; SSE2-NEXT: movdqa %xmm0, %xmm2<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]<br>; SSE2-NEXT: psraw $8, %xmm2<br>; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [65427,65427,65427,65427,65427,65427,65427,65427]<br>; SSE2-NEXT: pmullw %xmm3, %xmm2<br>; SSE2-NEXT: psrlw $8, %xmm2<br>; SSE2-NEXT: movdqa %xmm0, %xmm1<br>-; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]<br>+; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]<br>; SSE2-NEXT: psraw $8, %xmm1<br>; SSE2-NEXT: pmullw %xmm3, %xmm1<br>; SSE2-NEXT: psrlw $8, %xmm1<br>@@ -501,13 +501,13 @@ define <16 x i8> @test_rem7_16i8(<16 x i<br>; SSE2-LABEL: test_rem7_16i8:<br>; SSE2: # %bb.0:<br>; SSE2-NEXT: movdqa %xmm0, %xmm2<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]<br>; SSE2-NEXT: psraw $8, %xmm2<br>; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [65427,65427,65427,65427,65427,65427,65427,65427]<br>; SSE2-NEXT: pmullw %xmm3, %xmm2<br>; SSE2-NEXT: psrlw $8, %xmm2<br>; SSE2-NEXT: movdqa %xmm0, %xmm1<br>-; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]<br>+; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]<br>; SSE2-NEXT: psraw $8, %xmm1<br>; SSE2-NEXT: pmullw %xmm3, %xmm1<br>; SSE2-NEXT: psrlw $8, %xmm1<br>@@ -523,7 +523,7 @@ define <16 x i8> @test_rem7_16i8(<16 x i<br>; SSE2-NEXT: pand {{.*}}(%rip), %xmm1<br>; SSE2-NEXT: paddb %xmm2, %xmm1<br>; SSE2-NEXT: movdqa %xmm1, %xmm2<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]<br>; SSE2-NEXT: psraw $8, %xmm2<br>; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [7,7,7,7,7,7,7,7]<br>; SSE2-NEXT: pmullw %xmm3, %xmm2<br><br>Modified: llvm/trunk/test/CodeGen/X86/vector-idiv-udiv-128.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-idiv-udiv-128.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-idiv-udiv-128.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vector-idiv-udiv-128.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vector-idiv-udiv-128.ll Tue Feb 27 08:59:10 2018<br>@@ -497,7 +497,7 @@ define <16 x i8> @test_rem7_16i8(<16 x i<br>; SSE2-NEXT: psrlw $2, %xmm1<br>; SSE2-NEXT: pand {{.*}}(%rip), %xmm1<br>; SSE2-NEXT: movdqa %xmm1, %xmm2<br>-; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]<br>+; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]<br>; SSE2-NEXT: psraw $8, %xmm2<br>; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [7,7,7,7,7,7,7,7]<br>; SSE2-NEXT: pmullw %xmm3, %xmm2<br><br>Modified: llvm/trunk/test/CodeGen/X86/vector-mul.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-mul.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-mul.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vector-mul.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vector-mul.ll Tue Feb 27 08:59:10 2018<br>@@ -178,7 +178,7 @@ define <16 x i8> @mul_v16i8_1_2_4_8_1_2_<br>; X86-LABEL: mul_v16i8_1_2_4_8_1_2_4_8_1_2_4_8_1_2_4_8:<br>; X86: # %bb.0:<br>; X86-NEXT: movdqa %xmm0, %xmm1<br>-; X86-NEXT: movdqa %xmm1, %xmm2<br>+; X86-NEXT: movdqa %xmm0, %xmm2<br>; X86-NEXT: psllw $4, %xmm2<br>; X86-NEXT: pand {{\.LCPI.*}}, %xmm2<br>; X86-NEXT: movdqa {{.*#+}} xmm0 = [8192,24640,8192,24640,8192,24640,8192,24640]<br>@@ -189,7 +189,7 @@ define <16 x i8> @mul_v16i8_1_2_4_8_1_2_<br>; X86-NEXT: paddb %xmm0, %xmm0<br>; X86-NEXT: pblendvb %xmm0, %xmm2, %xmm1<br>; X86-NEXT: movdqa %xmm1, %xmm2<br>-; X86-NEXT: paddb %xmm2, %xmm2<br>+; X86-NEXT: paddb %xmm1, %xmm2<br>; X86-NEXT: paddb %xmm0, %xmm0<br>; X86-NEXT: pblendvb %xmm0, %xmm2, %xmm1<br>; X86-NEXT: movdqa %xmm1, %xmm0<br>@@ -198,7 +198,7 @@ define <16 x i8> @mul_v16i8_1_2_4_8_1_2_<br>; X64-LABEL: mul_v16i8_1_2_4_8_1_2_4_8_1_2_4_8_1_2_4_8:<br>; X64: # %bb.0:<br>; X64-NEXT: movdqa %xmm0, %xmm1<br>-; X64-NEXT: movdqa %xmm1, %xmm2<br>+; X64-NEXT: movdqa %xmm0, %xmm2<br>; X64-NEXT: psllw $4, %xmm2<br>; X64-NEXT: pand {{.*}}(%rip), %xmm2<br>; X64-NEXT: movdqa {{.*#+}} xmm0 = [8192,24640,8192,24640,8192,24640,8192,24640]<br>@@ -209,7 +209,7 @@ define <16 x i8> @mul_v16i8_1_2_4_8_1_2_<br>; X64-NEXT: paddb %xmm0, %xmm0<br>; X64-NEXT: pblendvb %xmm0, %xmm2, %xmm1<br>; X64-NEXT: movdqa %xmm1, %xmm2<br>-; X64-NEXT: paddb %xmm2, %xmm2<br>+; X64-NEXT: paddb %xmm1, %xmm2<br>; X64-NEXT: paddb %xmm0, %xmm0<br>; X64-NEXT: pblendvb %xmm0, %xmm2, %xmm1<br>; X64-NEXT: movdqa %xmm1, %xmm0<br><br>Modified: llvm/trunk/test/CodeGen/X86/vector-rotate-128.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-rotate-128.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-rotate-128.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vector-rotate-128.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vector-rotate-128.ll Tue Feb 27 08:59:10 2018<br>@@ -359,7 +359,7 @@ define <8 x i16> @var_rotate_v8i16(<8 x<br>; SSE41-NEXT: psllw $4, %xmm1<br>; SSE41-NEXT: por %xmm0, %xmm1<br>; SSE41-NEXT: movdqa %xmm1, %xmm4<br>-; SSE41-NEXT: paddw %xmm4, %xmm4<br>+; SSE41-NEXT: paddw %xmm1, %xmm4<br>; SSE41-NEXT: movdqa %xmm3, %xmm6<br>; SSE41-NEXT: psllw $8, %xmm6<br>; SSE41-NEXT: movdqa %xmm3, %xmm5<br>@@ -384,7 +384,7 @@ define <8 x i16> @var_rotate_v8i16(<8 x<br>; SSE41-NEXT: psllw $4, %xmm2<br>; SSE41-NEXT: por %xmm0, %xmm2<br>; SSE41-NEXT: movdqa %xmm2, %xmm1<br>-; SSE41-NEXT: paddw %xmm1, %xmm1<br>+; SSE41-NEXT: paddw %xmm2, %xmm1<br>; SSE41-NEXT: movdqa %xmm3, %xmm4<br>; SSE41-NEXT: psrlw $8, %xmm4<br>; SSE41-NEXT: movdqa %xmm2, %xmm0<br>@@ -629,10 +629,10 @@ define <16 x i8> @var_rotate_v16i8(<16 x<br>; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]<br>; SSE41-NEXT: psubb %xmm3, %xmm2<br>; SSE41-NEXT: psllw $5, %xmm3<br>-; SSE41-NEXT: movdqa %xmm1, %xmm5<br>+; SSE41-NEXT: movdqa %xmm0, %xmm5<br>; SSE41-NEXT: psllw $4, %xmm5<br>; SSE41-NEXT: pand {{.*}}(%rip), %xmm5<br>-; SSE41-NEXT: movdqa %xmm1, %xmm4<br>+; SSE41-NEXT: movdqa %xmm0, %xmm4<br>; SSE41-NEXT: movdqa %xmm3, %xmm0<br>; SSE41-NEXT: pblendvb %xmm0, %xmm5, %xmm4<br>; SSE41-NEXT: movdqa %xmm4, %xmm5<br>@@ -642,13 +642,13 @@ define <16 x i8> @var_rotate_v16i8(<16 x<br>; SSE41-NEXT: movdqa %xmm3, %xmm0<br>; SSE41-NEXT: pblendvb %xmm0, %xmm5, %xmm4<br>; SSE41-NEXT: movdqa %xmm4, %xmm5<br>-; SSE41-NEXT: paddb %xmm5, %xmm5<br>+; SSE41-NEXT: paddb %xmm4, %xmm5<br>; SSE41-NEXT: paddb %xmm3, %xmm3<br>; SSE41-NEXT: movdqa %xmm3, %xmm0<br>; SSE41-NEXT: pblendvb %xmm0, %xmm5, %xmm4<br>; SSE41-NEXT: psllw $5, %xmm2<br>; SSE41-NEXT: movdqa %xmm2, %xmm3<br>-; SSE41-NEXT: paddb %xmm3, %xmm3<br>+; SSE41-NEXT: paddb %xmm2, %xmm3<br>; SSE41-NEXT: movdqa %xmm1, %xmm5<br>; SSE41-NEXT: psrlw $4, %xmm5<br>; SSE41-NEXT: pand {{.*}}(%rip), %xmm5<br>@@ -1202,7 +1202,7 @@ define <16 x i8> @constant_rotate_v16i8(<br>; SSE41-LABEL: constant_rotate_v16i8:<br>; SSE41: # %bb.0:<br>; SSE41-NEXT: movdqa %xmm0, %xmm1<br>-; SSE41-NEXT: movdqa %xmm1, %xmm3<br>+; SSE41-NEXT: movdqa %xmm0, %xmm3<br>; SSE41-NEXT: psllw $4, %xmm3<br>; SSE41-NEXT: pand {{.*}}(%rip), %xmm3<br>; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [8192,24640,41088,57536,57600,41152,24704,8256]<br>@@ -1214,7 +1214,7 @@ define <16 x i8> @constant_rotate_v16i8(<br>; SSE41-NEXT: paddb %xmm0, %xmm0<br>; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2<br>; SSE41-NEXT: movdqa %xmm2, %xmm3<br>-; SSE41-NEXT: paddb %xmm3, %xmm3<br>+; SSE41-NEXT: paddb %xmm2, %xmm3<br>; SSE41-NEXT: paddb %xmm0, %xmm0<br>; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2<br>; SSE41-NEXT: movdqa %xmm1, %xmm3<br><br>Modified: llvm/trunk/test/CodeGen/X86/vector-sext.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-sext.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-sext.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vector-sext.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vector-sext.ll Tue Feb 27 08:59:10 2018<br>@@ -243,7 +243,7 @@ define <8 x i32> @sext_16i8_to_8i32(<16<br>; SSSE3-LABEL: sext_16i8_to_8i32:<br>; SSSE3: # %bb.0: # %entry<br>; SSSE3-NEXT: movdqa %xmm0, %xmm1<br>-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]<br>+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]<br>; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]<br>; SSSE3-NEXT: psrad $24, %xmm0<br>; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[u,u,u,4,u,u,u,5,u,u,u,6,u,u,u,7]<br>@@ -312,7 +312,7 @@ define <16 x i32> @sext_16i8_to_16i32(<1<br>; SSSE3-LABEL: sext_16i8_to_16i32:<br>; SSSE3: # %bb.0: # %entry<br>; SSSE3-NEXT: movdqa %xmm0, %xmm3<br>-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7]<br>+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]<br>; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]<br>; SSSE3-NEXT: psrad $24, %xmm0<br>; SSSE3-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm3[8],xmm1[9],xmm3[9],xmm1[10],xmm3[10],xmm1[11],xmm3[11],xmm1[12],xmm3[12],xmm1[13],xmm3[13],xmm1[14],xmm3[14],xmm1[15],xmm3[15]<br>@@ -443,7 +443,7 @@ define <4 x i64> @sext_16i8_to_4i64(<16<br>; SSSE3-LABEL: sext_16i8_to_4i64:<br>; SSSE3: # %bb.0: # %entry<br>; SSSE3-NEXT: movdqa %xmm0, %xmm1<br>-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]<br>+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]<br>; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]<br>; SSSE3-NEXT: movdqa %xmm0, %xmm2<br>; SSSE3-NEXT: psrad $31, %xmm2<br>@@ -499,7 +499,7 @@ define <8 x i64> @sext_16i8_to_8i64(<16<br>; SSE2-LABEL: sext_16i8_to_8i64:<br>; SSE2: # %bb.0: # %entry<br>; SSE2-NEXT: movdqa %xmm0, %xmm1<br>-; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]<br>+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]<br>; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]<br>; SSE2-NEXT: movdqa %xmm0, %xmm2<br>; SSE2-NEXT: psrad $31, %xmm2<br>@@ -1108,7 +1108,7 @@ define <8 x i64> @sext_8i32_to_8i64(<8 x<br>; SSE2-NEXT: movdqa %xmm1, %xmm2<br>; SSE2-NEXT: movdqa %xmm0, %xmm3<br>; SSE2-NEXT: psrad $31, %xmm3<br>-; SSE2-NEXT: movdqa %xmm2, %xmm4<br>+; SSE2-NEXT: movdqa %xmm1, %xmm4<br>; SSE2-NEXT: psrad $31, %xmm4<br>; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]<br>; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]<br>@@ -1127,7 +1127,7 @@ define <8 x i64> @sext_8i32_to_8i64(<8 x<br>; SSSE3-NEXT: movdqa %xmm1, %xmm2<br>; SSSE3-NEXT: movdqa %xmm0, %xmm3<br>; SSSE3-NEXT: psrad $31, %xmm3<br>-; SSSE3-NEXT: movdqa %xmm2, %xmm4<br>+; SSSE3-NEXT: movdqa %xmm1, %xmm4<br>; SSSE3-NEXT: psrad $31, %xmm4<br>; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]<br>; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]<br><br>Modified: llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll Tue Feb 27 08:59:10 2018<br>@@ -273,7 +273,7 @@ define <8 x i16> @var_shift_v8i16(<8 x i<br>; SSE41-NEXT: psllw $4, %xmm1<br>; SSE41-NEXT: por %xmm0, %xmm1<br>; SSE41-NEXT: movdqa %xmm1, %xmm3<br>-; SSE41-NEXT: paddw %xmm3, %xmm3<br>+; SSE41-NEXT: paddw %xmm1, %xmm3<br>; SSE41-NEXT: movdqa %xmm2, %xmm4<br>; SSE41-NEXT: psraw $8, %xmm4<br>; SSE41-NEXT: movdqa %xmm1, %xmm0<br><br>Modified: llvm/trunk/test/CodeGen/X86/vector-shift-lshr-128.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shift-lshr-128.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shift-lshr-128.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vector-shift-lshr-128.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vector-shift-lshr-128.ll Tue Feb 27 08:59:10 2018<br>@@ -243,7 +243,7 @@ define <8 x i16> @var_shift_v8i16(<8 x i<br>; SSE41-NEXT: psllw $4, %xmm1<br>; SSE41-NEXT: por %xmm0, %xmm1<br>; SSE41-NEXT: movdqa %xmm1, %xmm3<br>-; SSE41-NEXT: paddw %xmm3, %xmm3<br>+; SSE41-NEXT: paddw %xmm1, %xmm3<br>; SSE41-NEXT: movdqa %xmm2, %xmm4<br>; SSE41-NEXT: psrlw $8, %xmm4<br>; SSE41-NEXT: movdqa %xmm1, %xmm0<br>@@ -408,7 +408,7 @@ define <16 x i8> @var_shift_v16i8(<16 x<br>; SSE41: # %bb.0:<br>; SSE41-NEXT: movdqa %xmm0, %xmm2<br>; SSE41-NEXT: psllw $5, %xmm1<br>-; SSE41-NEXT: movdqa %xmm2, %xmm3<br>+; SSE41-NEXT: movdqa %xmm0, %xmm3<br>; SSE41-NEXT: psrlw $4, %xmm3<br>; SSE41-NEXT: pand {{.*}}(%rip), %xmm3<br>; SSE41-NEXT: movdqa %xmm1, %xmm0<br>@@ -701,7 +701,7 @@ define <16 x i8> @splatvar_shift_v16i8(<<br>; SSE41-NEXT: pshufb %xmm0, %xmm1<br>; SSE41-NEXT: psllw $5, %xmm1<br>; SSE41-NEXT: movdqa %xmm1, %xmm3<br>-; SSE41-NEXT: paddb %xmm3, %xmm3<br>+; SSE41-NEXT: paddb %xmm1, %xmm3<br>; SSE41-NEXT: movdqa %xmm2, %xmm4<br>; SSE41-NEXT: psrlw $4, %xmm4<br>; SSE41-NEXT: pand {{.*}}(%rip), %xmm4<br>@@ -1147,7 +1147,7 @@ define <16 x i8> @constant_shift_v16i8(<<br>; SSE41-LABEL: constant_shift_v16i8:<br>; SSE41: # %bb.0:<br>; SSE41-NEXT: movdqa %xmm0, %xmm1<br>-; SSE41-NEXT: movdqa %xmm1, %xmm2<br>+; SSE41-NEXT: movdqa %xmm0, %xmm2<br>; SSE41-NEXT: psrlw $4, %xmm2<br>; SSE41-NEXT: pand {{.*}}(%rip), %xmm2<br>; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [8192,24640,41088,57536,49376,32928,16480,32]<br><br>Modified: llvm/trunk/test/CodeGen/X86/vector-shift-shl-128.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shift-shl-128.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shift-shl-128.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vector-shift-shl-128.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vector-shift-shl-128.ll Tue Feb 27 08:59:10 2018<br>@@ -200,7 +200,7 @@ define <8 x i16> @var_shift_v8i16(<8 x i<br>; SSE41-NEXT: psllw $4, %xmm1<br>; SSE41-NEXT: por %xmm0, %xmm1<br>; SSE41-NEXT: movdqa %xmm1, %xmm3<br>-; SSE41-NEXT: paddw %xmm3, %xmm3<br>+; SSE41-NEXT: paddw %xmm1, %xmm3<br>; SSE41-NEXT: movdqa %xmm2, %xmm4<br>; SSE41-NEXT: psllw $8, %xmm4<br>; SSE41-NEXT: movdqa %xmm1, %xmm0<br>@@ -362,7 +362,7 @@ define <16 x i8> @var_shift_v16i8(<16 x<br>; SSE41: # %bb.0:<br>; SSE41-NEXT: movdqa %xmm0, %xmm2<br>; SSE41-NEXT: psllw $5, %xmm1<br>-; SSE41-NEXT: movdqa %xmm2, %xmm3<br>+; SSE41-NEXT: movdqa %xmm0, %xmm3<br>; SSE41-NEXT: psllw $4, %xmm3<br>; SSE41-NEXT: pand {{.*}}(%rip), %xmm3<br>; SSE41-NEXT: movdqa %xmm1, %xmm0<br>@@ -374,7 +374,7 @@ define <16 x i8> @var_shift_v16i8(<16 x<br>; SSE41-NEXT: movdqa %xmm1, %xmm0<br>; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2<br>; SSE41-NEXT: movdqa %xmm2, %xmm3<br>-; SSE41-NEXT: paddb %xmm3, %xmm3<br>+; SSE41-NEXT: paddb %xmm2, %xmm3<br>; SSE41-NEXT: paddb %xmm1, %xmm1<br>; SSE41-NEXT: movdqa %xmm1, %xmm0<br>; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2<br>@@ -649,7 +649,7 @@ define <16 x i8> @splatvar_shift_v16i8(<<br>; SSE41-NEXT: pshufb %xmm0, %xmm1<br>; SSE41-NEXT: psllw $5, %xmm1<br>; SSE41-NEXT: movdqa %xmm1, %xmm3<br>-; SSE41-NEXT: paddb %xmm3, %xmm3<br>+; SSE41-NEXT: paddb %xmm1, %xmm3<br>; SSE41-NEXT: movdqa %xmm2, %xmm4<br>; SSE41-NEXT: psllw $4, %xmm4<br>; SSE41-NEXT: pand {{.*}}(%rip), %xmm4<br>@@ -661,7 +661,7 @@ define <16 x i8> @splatvar_shift_v16i8(<<br>; SSE41-NEXT: movdqa %xmm3, %xmm0<br>; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm2<br>; SSE41-NEXT: movdqa %xmm2, %xmm1<br>-; SSE41-NEXT: paddb %xmm1, %xmm1<br>+; SSE41-NEXT: paddb %xmm2, %xmm1<br>; SSE41-NEXT: paddb %xmm3, %xmm3<br>; SSE41-NEXT: movdqa %xmm3, %xmm0<br>; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm2<br>@@ -1001,7 +1001,7 @@ define <16 x i8> @constant_shift_v16i8(<<br>; SSE41-LABEL: constant_shift_v16i8:<br>; SSE41: # %bb.0:<br>; SSE41-NEXT: movdqa %xmm0, %xmm1<br>-; SSE41-NEXT: movdqa %xmm1, %xmm2<br>+; SSE41-NEXT: movdqa %xmm0, %xmm2<br>; SSE41-NEXT: psllw $4, %xmm2<br>; SSE41-NEXT: pand {{.*}}(%rip), %xmm2<br>; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [8192,24640,41088,57536,49376,32928,16480,32]<br>@@ -1012,7 +1012,7 @@ define <16 x i8> @constant_shift_v16i8(<<br>; SSE41-NEXT: paddb %xmm0, %xmm0<br>; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1<br>; SSE41-NEXT: movdqa %xmm1, %xmm2<br>-; SSE41-NEXT: paddb %xmm2, %xmm2<br>+; SSE41-NEXT: paddb %xmm1, %xmm2<br>; SSE41-NEXT: paddb %xmm0, %xmm0<br>; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1<br>; SSE41-NEXT: movdqa %xmm1, %xmm0<br><br>Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll Tue Feb 27 08:59:10 2018<br>@@ -2703,7 +2703,7 @@ define <4 x float> @PR22377(<4 x float><br>; SSE-LABEL: PR22377:<br>; SSE: # %bb.0: # %entry<br>; SSE-NEXT: movaps %xmm0, %xmm1<br>-; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3,1,3]<br>+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm0[1,3]<br>; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,0,2]<br>; SSE-NEXT: addps %xmm0, %xmm1<br>; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]<br><br>Modified: llvm/trunk/test/CodeGen/X86/vector-trunc-math.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-trunc-math.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-trunc-math.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vector-trunc-math.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vector-trunc-math.ll Tue Feb 27 08:59:10 2018<br>@@ -5511,7 +5511,7 @@ define <4 x i32> @mul_add_const_v4i64_v4<br>; SSE-LABEL: mul_add_const_v4i64_v4i32:<br>; SSE: # %bb.0:<br>; SSE-NEXT: movdqa %xmm0, %xmm2<br>-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,1,1,3]<br>+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]<br>; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,1,3,3]<br>; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[0,1,1,3]<br>; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]<br><br>Modified: llvm/trunk/test/CodeGen/X86/vector-zext.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-zext.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-zext.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vector-zext.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vector-zext.ll Tue Feb 27 08:59:10 2018<br>@@ -247,7 +247,7 @@ define <16 x i32> @zext_16i8_to_16i32(<1<br>; SSE2: # %bb.0: # %entry<br>; SSE2-NEXT: movdqa %xmm0, %xmm3<br>; SSE2-NEXT: pxor %xmm4, %xmm4<br>-; SSE2-NEXT: movdqa %xmm3, %xmm1<br>+; SSE2-NEXT: movdqa %xmm0, %xmm1<br>; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]<br>; SSE2-NEXT: movdqa %xmm1, %xmm0<br>; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]<br>@@ -262,7 +262,7 @@ define <16 x i32> @zext_16i8_to_16i32(<1<br>; SSSE3: # %bb.0: # %entry<br>; SSSE3-NEXT: movdqa %xmm0, %xmm3<br>; SSSE3-NEXT: pxor %xmm4, %xmm4<br>-; SSSE3-NEXT: movdqa %xmm3, %xmm1<br>+; SSSE3-NEXT: movdqa %xmm0, %xmm1<br>; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]<br>; SSSE3-NEXT: movdqa %xmm1, %xmm0<br>; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]<br>@@ -400,7 +400,7 @@ define <8 x i64> @zext_16i8_to_8i64(<16<br>; SSE2: # %bb.0: # %entry<br>; SSE2-NEXT: movdqa %xmm0, %xmm1<br>; SSE2-NEXT: pxor %xmm4, %xmm4<br>-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,2,3]<br>+; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,2,3]<br>; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]<br>; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]<br>; SSE2-NEXT: movdqa %xmm1, %xmm0<br>@@ -701,7 +701,7 @@ define <8 x i64> @zext_8i16_to_8i64(<8 x<br>; SSE2: # %bb.0: # %entry<br>; SSE2-NEXT: movdqa %xmm0, %xmm3<br>; SSE2-NEXT: pxor %xmm4, %xmm4<br>-; SSE2-NEXT: movdqa %xmm3, %xmm1<br>+; SSE2-NEXT: movdqa %xmm0, %xmm1<br>; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]<br>; SSE2-NEXT: movdqa %xmm1, %xmm0<br>; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]<br>@@ -716,7 +716,7 @@ define <8 x i64> @zext_8i16_to_8i64(<8 x<br>; SSSE3: # %bb.0: # %entry<br>; SSSE3-NEXT: movdqa %xmm0, %xmm3<br>; SSSE3-NEXT: pxor %xmm4, %xmm4<br>-; SSSE3-NEXT: movdqa %xmm3, %xmm1<br>+; SSSE3-NEXT: movdqa %xmm0, %xmm1<br>; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]<br>; SSSE3-NEXT: movdqa %xmm1, %xmm0<br>; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]<br>@@ -1583,7 +1583,7 @@ define <8 x i32> @shuf_zext_8i16_to_8i32<br>; SSE41: # %bb.0: # %entry<br>; SSE41-NEXT: movdqa %xmm0, %xmm1<br>; SSE41-NEXT: pxor %xmm2, %xmm2<br>-; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero<br>+; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero<br>; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]<br>; SSE41-NEXT: retq<br>;<br>@@ -1631,7 +1631,7 @@ define <4 x i64> @shuf_zext_4i32_to_4i64<br>; SSE41: # %bb.0: # %entry<br>; SSE41-NEXT: movdqa %xmm0, %xmm1<br>; SSE41-NEXT: pxor %xmm2, %xmm2<br>-; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero<br>+; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero<br>; SSE41-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]<br>; SSE41-NEXT: retq<br>;<br><br>Modified: llvm/trunk/test/CodeGen/X86/vselect-minmax.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vselect-minmax.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vselect-minmax.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vselect-minmax.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vselect-minmax.ll Tue Feb 27 08:59:10 2018<br>@@ -5015,7 +5015,7 @@ define <8 x i64> @test125(<8 x i64> %a,<br>; SSE4: # %bb.0: # %entry<br>; SSE4-NEXT: movdqa %xmm0, %xmm9<br>; SSE4-NEXT: movdqa {{.*#+}} xmm8 = [9223372036854775808,9223372036854775808]<br>-; SSE4-NEXT: movdqa %xmm9, %xmm10<br>+; SSE4-NEXT: movdqa %xmm0, %xmm10<br>; SSE4-NEXT: pxor %xmm8, %xmm10<br>; SSE4-NEXT: movdqa %xmm4, %xmm0<br>; SSE4-NEXT: pxor %xmm8, %xmm0<br>@@ -5162,7 +5162,7 @@ define <8 x i64> @test126(<8 x i64> %a,<br>; SSE4: # %bb.0: # %entry<br>; SSE4-NEXT: movdqa %xmm0, %xmm9<br>; SSE4-NEXT: movdqa {{.*#+}} xmm8 = [9223372036854775808,9223372036854775808]<br>-; SSE4-NEXT: movdqa %xmm9, %xmm10<br>+; SSE4-NEXT: movdqa %xmm0, %xmm10<br>; SSE4-NEXT: pxor %xmm8, %xmm10<br>; SSE4-NEXT: movdqa %xmm4, %xmm0<br>; SSE4-NEXT: pxor %xmm8, %xmm0<br>@@ -7483,7 +7483,7 @@ define <8 x i64> @test159(<8 x i64> %a,<br>; SSE4: # %bb.0: # %entry<br>; SSE4-NEXT: movdqa %xmm0, %xmm9<br>; SSE4-NEXT: movdqa {{.*#+}} xmm8 = [9223372036854775808,9223372036854775808]<br>-; SSE4-NEXT: movdqa %xmm9, %xmm10<br>+; SSE4-NEXT: movdqa %xmm0, %xmm10<br>; SSE4-NEXT: pxor %xmm8, %xmm10<br>; SSE4-NEXT: movdqa %xmm4, %xmm0<br>; SSE4-NEXT: pxor %xmm8, %xmm0<br>@@ -7630,7 +7630,7 @@ define <8 x i64> @test160(<8 x i64> %a,<br>; SSE4: # %bb.0: # %entry<br>; SSE4-NEXT: movdqa %xmm0, %xmm9<br>; SSE4-NEXT: movdqa {{.*#+}} xmm8 = [9223372036854775808,9223372036854775808]<br>-; SSE4-NEXT: movdqa %xmm9, %xmm10<br>+; SSE4-NEXT: movdqa %xmm0, %xmm10<br>; SSE4-NEXT: pxor %xmm8, %xmm10<br>; SSE4-NEXT: movdqa %xmm4, %xmm0<br>; SSE4-NEXT: pxor %xmm8, %xmm0<br>@@ -8041,7 +8041,7 @@ define <4 x i64> @test165(<4 x i64> %a,<br>; SSE4: # %bb.0: # %entry<br>; SSE4-NEXT: movdqa %xmm0, %xmm4<br>; SSE4-NEXT: movdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808]<br>-; SSE4-NEXT: movdqa %xmm4, %xmm6<br>+; SSE4-NEXT: movdqa %xmm0, %xmm6<br>; SSE4-NEXT: pxor %xmm5, %xmm6<br>; SSE4-NEXT: movdqa %xmm2, %xmm0<br>; SSE4-NEXT: pxor %xmm5, %xmm0<br>@@ -8130,7 +8130,7 @@ define <4 x i64> @test166(<4 x i64> %a,<br>; SSE4: # %bb.0: # %entry<br>; SSE4-NEXT: movdqa %xmm0, %xmm4<br>; SSE4-NEXT: movdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808]<br>-; SSE4-NEXT: movdqa %xmm4, %xmm6<br>+; SSE4-NEXT: movdqa %xmm0, %xmm6<br>; SSE4-NEXT: pxor %xmm5, %xmm6<br>; SSE4-NEXT: movdqa %xmm2, %xmm0<br>; SSE4-NEXT: pxor %xmm5, %xmm0<br>@@ -8865,7 +8865,7 @@ define <4 x i64> @test175(<4 x i64> %a,<br>; SSE4: # %bb.0: # %entry<br>; SSE4-NEXT: movdqa %xmm0, %xmm4<br>; SSE4-NEXT: movdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808]<br>-; SSE4-NEXT: movdqa %xmm4, %xmm6<br>+; SSE4-NEXT: movdqa %xmm0, %xmm6<br>; SSE4-NEXT: pxor %xmm5, %xmm6<br>; SSE4-NEXT: movdqa %xmm2, %xmm0<br>; SSE4-NEXT: pxor %xmm5, %xmm0<br>@@ -8954,7 +8954,7 @@ define <4 x i64> @test176(<4 x i64> %a,<br>; SSE4: # %bb.0: # %entry<br>; SSE4-NEXT: movdqa %xmm0, %xmm4<br>; SSE4-NEXT: movdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808]<br>-; SSE4-NEXT: movdqa %xmm4, %xmm6<br>+; SSE4-NEXT: movdqa %xmm0, %xmm6<br>; SSE4-NEXT: pxor %xmm5, %xmm6<br>; SSE4-NEXT: movdqa %xmm2, %xmm0<br>; SSE4-NEXT: pxor %xmm5, %xmm0<br><br>Modified: llvm/trunk/test/CodeGen/X86/widen_conv-3.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_conv-3.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_conv-3.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/widen_conv-3.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/widen_conv-3.ll Tue Feb 27 08:59:10 2018<br>@@ -74,7 +74,7 @@ define void @convert_v3i8_to_v3f32(<3 x<br>; X86-SSE2-NEXT: cvtdq2ps %xmm0, %xmm0<br>; X86-SSE2-NEXT: movss %xmm0, (%eax)<br>; X86-SSE2-NEXT: movaps %xmm0, %xmm1<br>-; X86-SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]<br>+; X86-SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]<br>; X86-SSE2-NEXT: movss %xmm1, 8(%eax)<br>; X86-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]<br>; X86-SSE2-NEXT: movss %xmm0, 4(%eax)<br><br>Modified: llvm/trunk/test/CodeGen/X86/widen_conv-4.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_conv-4.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_conv-4.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/widen_conv-4.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/widen_conv-4.ll Tue Feb 27 08:59:10 2018<br>@@ -19,7 +19,7 @@ define void @convert_v7i16_v7f32(<7 x fl<br>; X86-SSE2-NEXT: movups %xmm0, (%eax)<br>; X86-SSE2-NEXT: movss %xmm2, 16(%eax)<br>; X86-SSE2-NEXT: movaps %xmm2, %xmm0<br>-; X86-SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]<br>+; X86-SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm2[1],xmm0[1]<br>; X86-SSE2-NEXT: movss %xmm0, 24(%eax)<br>; X86-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]<br>; X86-SSE2-NEXT: movss %xmm2, 20(%eax)<br>@@ -100,7 +100,7 @@ define void @convert_v3i8_to_v3f32(<3 x<br>; X86-SSE2-NEXT: cvtdq2ps %xmm0, %xmm0<br>; X86-SSE2-NEXT: movss %xmm0, (%eax)<br>; X86-SSE2-NEXT: movaps %xmm0, %xmm1<br>-; X86-SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]<br>+; X86-SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]<br>; X86-SSE2-NEXT: movss %xmm1, 8(%eax)<br>; X86-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]<br>; X86-SSE2-NEXT: movss %xmm0, 4(%eax)<br><br>Modified: llvm/trunk/test/CodeGen/X86/win64_frame.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_frame.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_frame.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/win64_frame.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/win64_frame.ll Tue Feb 27 08:59:10 2018<br>@@ -238,7 +238,7 @@ define i64 @f10(i64* %foo, i64 %bar, i64<br>; PUSHF-NEXT: .seh_setframe 5, 32<br>; PUSHF-NEXT: .seh_endprologue<br>; PUSHF-NEXT: movq %rdx, %rsi<br>-; PUSHF-NEXT: movq %rsi, %rax<br>+; PUSHF-NEXT: movq %rdx, %rax<br>; PUSHF-NEXT: lock cmpxchgq %r8, (%rcx)<br>; PUSHF-NEXT: pushfq<br>; PUSHF-NEXT: popq %rdi<br>@@ -269,7 +269,7 @@ define i64 @f10(i64* %foo, i64 %bar, i64<br>; SAHF-NEXT: .seh_setframe 5, 32<br>; SAHF-NEXT: .seh_endprologue<br>; SAHF-NEXT: movq %rdx, %rsi<br>-; SAHF-NEXT: movq %rsi, %rax<br>+; SAHF-NEXT: movq %rdx, %rax<br>; SAHF-NEXT: lock cmpxchgq %r8, (%rcx)<br>; SAHF-NEXT: seto %al<br>; SAHF-NEXT: lahf<br><br>Modified: llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll Tue Feb 27 08:59:10 2018<br>@@ -1757,7 +1757,7 @@ define void @interleaved_store_vf64_i8_s<br>; AVX1-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp) # 32-byte Spill<br>; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm9[0],xmm12[0],xmm9[1],xmm12[1],xmm9[2],xmm12[2],xmm9[3],xmm12[3]<br>; AVX1-NEXT: vmovdqa %xmm8, %xmm2<br>-; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm2[0],xmm14[0],xmm2[1],xmm14[1],xmm2[2],xmm14[2],xmm2[3],xmm14[3]<br>+; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm8[0],xmm14[0],xmm8[1],xmm14[1],xmm8[2],xmm14[2],xmm8[3],xmm14[3]<br>; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm8, %ymm13<br>; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm15[4],xmm5[4],xmm15[5],xmm5[5],xmm15[6],xmm5[6],xmm15[7],xmm5[7]<br>; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm10 = xmm10[4],xmm0[4],xmm10[5],xmm0[5],xmm10[6],xmm0[6],xmm10[7],xmm0[7]<br><br>Modified: llvm/trunk/test/CodeGen/X86/x86-shrink-wrap-unwind.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-shrink-wrap-unwind.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-shrink-wrap-unwind.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/x86-shrink-wrap-unwind.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/x86-shrink-wrap-unwind.ll Tue Feb 27 08:59:10 2018<br>@@ -23,7 +23,7 @@ target triple = "x86_64-apple-macosx"<br>; Compare the arguments and jump to exit.<br>; After the prologue is set.<br>; CHECK: movl %edi, [[ARG0CPY:%e[a-z]+]]<br>-; CHECK-NEXT: cmpl %esi, [[ARG0CPY]]<br>+; CHECK-NEXT: cmpl %esi, %edi<br>; CHECK-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]<br>;<br>; Store %a in the alloca.<br>@@ -69,7 +69,7 @@ attributes #0 = { "no-frame-pointer-elim<br>; Compare the arguments and jump to exit.<br>; After the prologue is set.<br>; CHECK: movl %edi, [[ARG0CPY:%e[a-z]+]]<br>-; CHECK-NEXT: cmpl %esi, [[ARG0CPY]]<br>+; CHECK-NEXT: cmpl %esi, %edi<br>; CHECK-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]<br>;<br>; Prologue code.<br>@@ -115,7 +115,7 @@ attributes #1 = { "no-frame-pointer-elim<br>; Compare the arguments and jump to exit.<br>; After the prologue is set.<br>; CHECK: movl %edi, [[ARG0CPY:%e[a-z]+]]<br>-; CHECK-NEXT: cmpl %esi, [[ARG0CPY]]<br>+; CHECK-NEXT: cmpl %esi, %edi<br>; CHECK-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]<br>;<br>; Prologue code.<br><br>Modified: llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll Tue Feb 27 08:59:10 2018<br>@@ -17,7 +17,7 @@ target triple = "x86_64-apple-macosx"<br>; Compare the arguments and jump to exit.<br>; No prologue needed.<br>; ENABLE: movl %edi, [[ARG0CPY:%e[a-z]+]]<br>-; ENABLE-NEXT: cmpl %esi, [[ARG0CPY]]<br>+; ENABLE-NEXT: cmpl %esi, %edi<br>; ENABLE-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]<br>;<br>; Prologue code.<br>@@ -27,7 +27,7 @@ target triple = "x86_64-apple-macosx"<br>; Compare the arguments and jump to exit.<br>; After the prologue is set.<br>; DISABLE: movl %edi, [[ARG0CPY:%e[a-z]+]]<br>-; DISABLE-NEXT: cmpl %esi, [[ARG0CPY]]<br>+; DISABLE-NEXT: cmpl %esi, %edi<br>; DISABLE-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]<br>;<br>; Store %a in the alloca.<br><br>Modified: llvm/trunk/test/DebugInfo/COFF/fpo-shrink-wrap.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/COFF/fpo-shrink-wrap.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/COFF/fpo-shrink-wrap.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/DebugInfo/COFF/fpo-shrink-wrap.ll (original)<br>+++ llvm/trunk/test/DebugInfo/COFF/fpo-shrink-wrap.ll Tue Feb 27 08:59:10 2018<br>@@ -15,7 +15,7 @@<br>; ASM: .cv_fpo_proc @shrink_wrap_basic@16 8<br>; ASM: .cv_loc 0 1 3 9 # t.c:3:9<br>; ASM: movl %ecx, %eax<br>-; ASM: cmpl %edx, %eax<br>+; ASM: cmpl %edx, %ecx<br>; ASM: jl [[EPILOGUE:LBB0_[0-9]+]]<br><br>; ASM: pushl %ebx<br><br>Modified: llvm/trunk/test/DebugInfo/X86/spill-nospill.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/spill-nospill.ll?rev=326208&r1=326207&r2=326208&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/spill-nospill.ll?rev=326208&r1=326207&r2=326208&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/DebugInfo/X86/spill-nospill.ll (original)<br>+++ llvm/trunk/test/DebugInfo/X86/spill-nospill.ll Tue Feb 27 08:59:10 2018<br>@@ -30,7 +30,7 @@<br>; CHECK: callq g<br>; CHECK: movl %eax, %[[CSR:[^ ]*]]<br>; CHECK: #DEBUG_VALUE: f:y <- $esi<br>-; CHECK: movl %[[CSR]], %ecx<br>+; CHECK: movl %eax, %ecx<br>; CHECK: callq g<br>; CHECK: movl %[[CSR]], %ecx<br>; CHECK: callq g<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@lists.llvm.org"><span style='color:purple'>llvm-commits@lists.llvm.org</span></a><br><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits"><span style='color:purple'>http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</span></a><o:p></o:p></p></div></div></div></blockquote></div></div></div></div></blockquote></div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><br>_______________________________________________<br>llvm-commits mailing list<br></span><a href="mailto:llvm-commits@lists.llvm.org"><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>llvm-commits@lists.llvm.org</span></a><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><br></span><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits"><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</span></a><o:p></o:p></p></div></blockquote></div><p class=MsoNormal><o:p> </o:p></p></div></body></html>