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<p class="MsoNormal"><a name="_MailEndCompose">Hi Galina,<o:p></o:p></a></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose">Sure. I was assuming I’d have Linux pipes and added a file redirect to the RUN command. This is obviously breaking on Windows.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose">I’ll see how to fix this. Thanks for the heads up!<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose">Cheers,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose">Pablo<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose"><b><span style="color:#006FC9">Pablo Barrio
</span></b><span style="color:#757B80">| Software Engineer | </span><b><span style="color:#006FC9">Arm<o:p></o:p></span></b></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose"><i><span style="color:#757B80">. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
</span></i><span style="color:black"><o:p></o:p></span></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose"><span style="color:black"><o:p> </o:p></span></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose"><span style="color:#757B80">m. +44 1223 405 149<o:p></o:p></span></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose"><span style="color:#757B80">CPC1, Capital Park, Cambridge Road, Fulbourn, CB21 5XE<o:p></o:p></span></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose"><span style="color:#757B80">Arm.com</span><span style="color:black"><o:p></o:p></span></span></p>
<p class="MsoNormal"><span style="mso-bookmark:_MailEndCompose"><o:p> </o:p></span></p>
<span style="mso-bookmark:_MailEndCompose"></span>
<p class="MsoNormal"><b><span lang="EN-US">From:</span></b><span lang="EN-US"> Galina Kistanova [mailto:gkistanova@gmail.com]
<br>
<b>Sent:</b> 15 February 2018 17:42<br>
<b>To:</b> Pablo Barrio <Pablo.Barrio@arm.com><br>
<b>Cc:</b> Artur Pilipenko via llvm-commits <llvm-commits@lists.llvm.org><br>
<b>Subject:</b> Re: [llvm] r325244 - [ARM] Allow 64- and 128-bit types with 't' inline asm constraint<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<p class="MsoNormal">Hello Pablo,<br>
<br>
This commits added broken test to one of our builders:<br>
<a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/7937">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/7937</a><br>
<br>
. . .<br>
LLVM :: CodeGen/ARM/inlineasm-error-t-toofewregs.ll<br>
<br>
The builder was already red and did not send notifications on the changes.<br>
Please have a look?<br>
<br>
Thanks<br>
<br>
Galina<o:p></o:p></p>
</div>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Thu, Feb 15, 2018 at 6:44 AM, Pablo Barrio via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<o:p></o:p></p>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-right:0cm">
<p class="MsoNormal">Author: pabbar01<br>
Date: Thu Feb 15 06:44:22 2018<br>
New Revision: 325244<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=325244&view=rev" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=325244&view=rev</a><br>
Log:<br>
[ARM] Allow 64- and 128-bit types with 't' inline asm constraint<br>
<br>
Summary:<br>
In LLVM, 't' selects a floating-point/SIMD register and only supports<br>
32-bit values. This is appropriately documented in the LLVM Language<br>
Reference Manual. However, this behaviour diverges from that of GCC, where<br>
't' selects the s0-s31 registers and its qX and dX variants depending on<br>
additional operand modifiers (q/P).<br>
<br>
For example, the following C code:<br>
<br>
#include <arm_neon.h><br>
float32x4_t a, b, x;<br>
asm("vadd.f32 %0, %1, %2" : "=t" (x) : "t" (a), "t" (b))<br>
<br>
results in the following assembly if compiled with GCC:<br>
<br>
vadd.f32 s0, s0, s1<br>
<br>
whereas LLVM will show "error: couldn't allocate output register for<br>
constraint 't'", since a, b, x are 128-bit variables, not 32-bit.<br>
<br>
This patch extends the use of 't' to mean that of GCC, thus allowing<br>
selection of the lower Q vector regs and their D/S variants. For example,<br>
the earlier code will now compile as:<br>
<br>
vadd.f32 q0, q0, q1<br>
<br>
This behaviour still differs from that of GCC but I think it is actually<br>
more correct, since LLVM picks up the right register type based on the<br>
datatype of x, while GCC would need an extra operand modifier to achieve<br>
the same result, as follows:<br>
<br>
asm("vadd.f32 %q0, %q1, %q2" : "=t" (x) : "t" (a), "t" (b))<br>
<br>
Since this is only an extension of functionality, existing code should not<br>
be affected by this change. Note that operand modifiers q/P are already<br>
supported by LLVM, so this patch should suffice to support inline<br>
assembly with constraint 't' originally built for GCC.<br>
<br>
Reviewers: grosbach, rengolin<br>
<br>
Reviewed By: rengolin<br>
<br>
Subscribers: rogfer01, efriedma, olista01, aemerson, javed.absar, eraman, kristof.beyls, llvm-commits<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D42962" target="_blank">
https://reviews.llvm.org/D42962</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/ARM/inlineasm-error-t-toofewregs.ll<br>
Modified:<br>
llvm/trunk/docs/LangRef.rst<br>
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>
llvm/trunk/test/CodeGen/ARM/inlineasm.ll<br>
<br>
Modified: llvm/trunk/docs/LangRef.rst<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.rst?rev=325244&r1=325243&r2=325244&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.rst?rev=325244&r1=325243&r2=325244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/docs/LangRef.rst (original)<br>
+++ llvm/trunk/docs/LangRef.rst Thu Feb 15 06:44:22 2018<br>
@@ -3654,8 +3654,8 @@ ARM and ARM's Thumb2 mode:<br>
``d0-d31``, or ``q0-q15``.<br>
- ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``,<br>
``d0-d7``, or ``q0-q3``.<br>
-- ``t``: A floating-point/SIMD register, only supports 32-bit values:<br>
- ``s0-s31``.<br>
+- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or<br>
+ ``q0-q8``.<br>
<br>
ARM's Thumb1 mode:<br>
<br>
@@ -3674,8 +3674,8 @@ ARM's Thumb1 mode:<br>
``d0-d31``, or ``q0-q15``.<br>
- ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``,<br>
``d0-d7``, or ``q0-q3``.<br>
-- ``t``: A floating-point/SIMD register, only supports 32-bit values:<br>
- ``s0-s31``.<br>
+- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or<br>
+ ``q0-q8``.<br>
<br>
<br>
Hexagon:<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=325244&r1=325243&r2=325244&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=325244&r1=325243&r2=325244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Feb 15 06:44:22 2018<br>
@@ -13467,8 +13467,14 @@ RCPair ARMTargetLowering::getRegForInlin<br>
return RCPair(0U, &ARM::QPR_8RegClass);<br>
break;<br>
case 't':<br>
+ if (VT == MVT::Other)<br>
+ break;<br>
if (VT == MVT::f32 || VT == MVT::i32)<br>
return RCPair(0U, &ARM::SPRRegClass);<br>
+ if (VT.getSizeInBits() == 64)<br>
+ return RCPair(0U, &ARM::DPR_VFP2RegClass);<br>
+ if (VT.getSizeInBits() == 128)<br>
+ return RCPair(0U, &ARM::QPR_VFP2RegClass);<br>
break;<br>
}<br>
}<br>
<br>
Added: llvm/trunk/test/CodeGen/ARM/inlineasm-error-t-toofewregs.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm-error-t-toofewregs.ll?rev=325244&view=auto" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm-error-t-toofewregs.ll?rev=325244&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/inlineasm-error-t-toofewregs.ll (added)<br>
+++ llvm/trunk/test/CodeGen/ARM/inlineasm-error-t-toofewregs.ll Thu Feb 15 06:44:22 2018<br>
@@ -0,0 +1,9 @@<br>
+; RUN: not llc -mtriple=armv8-eabi -mattr=+neon %s -o /dev/null 2<&1 | FileCheck %s<br>
+<br>
+; CHECK: inline assembly requires more registers than available<br>
+define <4 x float> @t-constraint-float-vectors-too-few-regs(<4 x float> %a, <4 x float> %b) {<br>
+entry:<br>
+ %0 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } asm "vadd.F32 $0, $9, $10\0A\09vadd.F32 $1, $9, $10\0A\09vadd.F32 $2, $9, $10\0A\09vadd.F32 $3, $9, $10\0A\09vadd.F32
$4, $9, $10\0A\09vadd.F32 $5, $9, $10\0A\09vadd.F32 $6, $9, $10\0A\09vadd.F32 $7, $9, $10\0A\09vadd.F32 $8, $9, $10", "=t,=t,=t,=t,=t,=t,=t,=t,=t,=t,t,t"(<4 x float> %a, <4 x float> %b)<br>
+ %asmresult = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %0, 0<br>
+ ret <4 x float> %asmresult<br>
+}<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/inlineasm.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm.ll?rev=325244&r1=325243&r2=325244&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm.ll?rev=325244&r1=325243&r2=325244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/inlineasm.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/inlineasm.ll Thu Feb 15 06:44:22 2018<br>
@@ -16,3 +16,35 @@ define float @t-constraint-int(i32 %i) {<br>
%ret = call float asm "vcvt.f32.s32 $0, $1\0A", "=t,t"(i32 %i)<br>
ret float %ret<br>
}<br>
+<br>
+define <2 x i32> @t-constraint-int-vector-64bit(<2 x float> %x) {<br>
+entry:<br>
+ ; CHECK-LABEL: t-constraint-int-vector-64bit<br>
+ ; CHECK: vcvt.s32.f32 {{d[0-9]+}}, {{d[0-9]+}}<br>
+ %0 = tail call <2 x i32> asm "vcvt.s32.f32 $0, $1", "=t,t"(<2 x float> %x)<br>
+ ret <2 x i32> %0<br>
+}<br>
+<br>
+define <4 x i32> @t-constraint-int-vector-128bit(<4 x float> %x) {<br>
+entry:<br>
+ ; CHECK-LABEL: t-constraint-int-vector-128bit<br>
+ ; CHECK: vcvt.s32.f32 {{q[0-7]}}, {{q[0-7]}}<br>
+ %0 = tail call <4 x i32> asm "vcvt.s32.f32 $0, $1", "=t,t"(<4 x float> %x)<br>
+ ret <4 x i32> %0<br>
+}<br>
+<br>
+define <2 x float> @t-constraint-float-vector-64bit(<2 x float> %a, <2 x float> %b) {<br>
+entry:<br>
+ ; CHECK-LABEL: t-constraint-float-vector-64bit<br>
+ ; CHECK: vadd.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}<br>
+ %0 = tail call <2 x float> asm "vadd.f32 $0, $1, $2", "=t,t,t"(<2 x float> %a, <2 x float> %b)<br>
+ ret <2 x float> %0<br>
+}<br>
+<br>
+define <4 x float> @t-constraint-float-vector-128bit(<4 x float> %a, <4 x float> %b) {<br>
+entry:<br>
+ ; CHECK-LABEL: t-constraint-float-vector-128bit<br>
+ ; CHECK: vadd.f32 q{{[0-7]}}, q{{[0-7]}}, q{{[0-7]}}<br>
+ %0 = tail call <4 x float> asm "vadd.f32 $0, $1, $2", "=t,t,t"(<4 x float> %a, <4 x float> %b)<br>
+ ret <4 x float> %0<br>
+}<br>
<br>
<br>
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