<div dir="ltr">I'm having trouble reproducing this. Did the bot somehow fail to rebuild/run tablegen to generate lib/Target/X86/X86GenEVEX2VEXTables.inc?</div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br><div class="gmail_quote">On Tue, Feb 13, 2018 at 9:49 AM, Galina Kistanova via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hello Craig,<br><br>This commit broke tests on one of our builders:<br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/7884" target="_blank">http://lab.llvm.org:8011/<wbr>builders/llvm-clang-x86_64-<wbr>expensive-checks-win/builds/<wbr>7884</a><br><br>. . . <br>Failing Tests (10):<br> LLVM :: CodeGen/X86/avx-intrinsics-<wbr>x86.ll<br> LLVM :: CodeGen/X86/avx-schedule.ll<br> LLVM :: CodeGen/X86/avx512-intrinsics.<wbr>ll<br> LLVM :: CodeGen/X86/avx512-scalar.ll<br> LLVM :: CodeGen/X86/avx512vl-<wbr>intrinsics.ll<br> LLVM :: CodeGen/X86/rounding-ops.ll<br> LLVM :: CodeGen/X86/sse41-intrinsics-<wbr>x86.ll<br> LLVM :: CodeGen/X86/sse41-schedule.ll<br> LLVM :: CodeGen/X86/vec_floor.ll<br> LLVM :: CodeGen/X86/vec_ss_load_fold.<wbr>ll<br><br>Please have a look?<br><br>Thanks<br><br>Galina<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Feb 12, 2018 at 8:19 PM, Craig Topper via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ctopper<br>
Date: Mon Feb 12 20:19:26 2018<br>
New Revision: 324985<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=324985&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=324985&view=rev</a><br>
Log:<br>
[X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass.<br>
<br>
Bits 7:4 control the scale part of the operation. If the scale is 0 the behavior is equivalent to VROUND.<br>
<br>
Fixes PR36246<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86E<wbr>vexToVex.cpp<br>
llvm/trunk/test/CodeGen/X86/av<wbr>x-intrinsics-x86.ll<br>
llvm/trunk/test/CodeGen/X86/av<wbr>x-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/av<wbr>x512-intrinsics.ll<br>
llvm/trunk/test/CodeGen/X86/av<wbr>x512-scalar.ll<br>
llvm/trunk/test/CodeGen/X86/av<wbr>x512vl-intrinsics.ll<br>
llvm/trunk/test/CodeGen/X86/ro<wbr>unding-ops.ll<br>
llvm/trunk/test/CodeGen/X86/ss<wbr>e41-intrinsics-x86.ll<br>
llvm/trunk/test/CodeGen/X86/ss<wbr>e41-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/ve<wbr>c_floor.ll<br>
llvm/trunk/test/CodeGen/X86/ve<wbr>c_ss_load_fold.ll<br>
llvm/trunk/utils/TableGen/X86E<wbr>VEX2VEXTablesEmitter.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86E<wbr>vexToVex.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86EvexToVex.cpp?rev=324985&r1=324984&r2=324985&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86EvexToVex.cpp?rev=324985&<wbr>r1=324984&r2=324985&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86E<wbr>vexToVex.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86E<wbr>vexToVex.cpp Mon Feb 12 20:19:26 2018<br>
@@ -164,7 +164,7 @@ static bool usesExtendedRegister(const M<br>
}<br>
<br>
// Do any custom cleanup needed to finalize the conversion.<br>
-static void performCustomAdjustments(Machi<wbr>neInstr &MI, unsigned NewOpc) {<br>
+static bool performCustomAdjustments(Machi<wbr>neInstr &MI, unsigned NewOpc) {<br>
(void)NewOpc;<br>
unsigned Opc = MI.getOpcode();<br>
switch (Opc) {<br>
@@ -197,7 +197,31 @@ static void performCustomAdjustments(Mac<br>
Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1));<br>
break;<br>
}<br>
+ case X86::VRNDSCALEPDZ128rri:<br>
+ case X86::VRNDSCALEPDZ128rmi:<br>
+ case X86::VRNDSCALEPSZ128rri:<br>
+ case X86::VRNDSCALEPSZ128rmi:<br>
+ case X86::VRNDSCALEPDZ256rri:<br>
+ case X86::VRNDSCALEPDZ256rmi:<br>
+ case X86::VRNDSCALEPSZ256rri:<br>
+ case X86::VRNDSCALEPSZ256rmi:<br>
+ case X86::VRNDSCALESDr:<br>
+ case X86::VRNDSCALESDm:<br>
+ case X86::VRNDSCALESSr:<br>
+ case X86::VRNDSCALESSm:<br>
+ case X86::VRNDSCALESDr_Int:<br>
+ case X86::VRNDSCALESDm_Int:<br>
+ case X86::VRNDSCALESSr_Int:<br>
+ case X86::VRNDSCALESSm_Int:<br>
+ const MachineOperand &Imm = MI.getOperand(MI.getNumExplici<wbr>tOperands()-1);<br>
+ int64_t ImmVal = Imm.getImm();<br>
+ // Ensure that only bits 3:0 of the immediate are used.<br>
+ if ((ImmVal & 0xf) != ImmVal)<br>
+ return false;<br>
+ break;<br>
}<br>
+<br>
+ return true;<br>
}<br>
<br>
<br>
@@ -260,7 +284,8 @@ bool EvexToVexInstPass::CompressEve<wbr>xToVe<br>
if (usesExtendedRegister(MI))<br>
return false;<br>
<br>
- performCustomAdjustments(MI, NewOpc);<br>
+ if (!performCustomAdjustments(MI, NewOpc))<br>
+ return false;<br>
<br>
MI.setDesc(TII->get(NewOpc));<br>
MI.setAsmPrinterFlag(AC_EVEX_<wbr>2_VEX);<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/av<wbr>x-intrinsics-x86.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=324985&r1=324984&r2=324985&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/avx-intrinsics-x86.ll?rev=<wbr>324985&r1=324984&r2=324985&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/av<wbr>x-intrinsics-x86.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/av<wbr>x-intrinsics-x86.ll Mon Feb 12 20:19:26 2018<br>
@@ -599,7 +599,7 @@ define <4 x double> @test_x86_avx_round_<br>
;<br>
; AVX512VL-LABEL: test_x86_avx_round_pd_256:<br>
; AVX512VL: # %bb.0:<br>
-; AVX512VL-NEXT: vrndscalepd $7, %ymm0, %ymm0 # encoding: [0x62,0xf3,0xfd,0x28,0x09,0xc0<wbr>,0x07]<br>
+; AVX512VL-NEXT: vroundpd $7, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x09,0xc0,0x07<wbr>]<br>
; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]<br>
%res = call <4 x double> @llvm.x86.avx.round.pd.256(<4 x double> %a0, i32 7) ; <<4 x double>> [#uses=1]<br>
ret <4 x double> %res<br>
@@ -615,7 +615,7 @@ define <8 x float> @test_x86_avx_round_p<br>
;<br>
; AVX512VL-LABEL: test_x86_avx_round_ps_256:<br>
; AVX512VL: # %bb.0:<br>
-; AVX512VL-NEXT: vrndscaleps $7, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7d,0x28,0x08,0xc0<wbr>,0x07]<br>
+; AVX512VL-NEXT: vroundps $7, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x08,0xc0,0x07<wbr>]<br>
; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]<br>
%res = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> %a0, i32 7) ; <<8 x float>> [#uses=1]<br>
ret <8 x float> %res<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/av<wbr>x-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-schedule.ll?rev=324985&r1=324984&r2=324985&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/avx-schedule.ll?rev=<wbr>324985&r1=324984&r2=324985&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/av<wbr>x-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/av<wbr>x-schedule.ll Mon Feb 12 20:19:26 2018<br>
@@ -4118,8 +4118,8 @@ define <4 x double> @test_roundpd(<4 x d<br>
;<br>
; SKX-LABEL: test_roundpd:<br>
; SKX: # %bb.0:<br>
-; SKX-NEXT: vrndscalepd $7, %ymm0, %ymm0 # sched: [8:0.67]<br>
-; SKX-NEXT: vrndscalepd $7, (%rdi), %ymm1 # sched: [15:0.67]<br>
+; SKX-NEXT: vroundpd $7, %ymm0, %ymm0 # sched: [8:0.67]<br>
+; SKX-NEXT: vroundpd $7, (%rdi), %ymm1 # sched: [15:0.67]<br>
; SKX-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
; SKX-NEXT: retq # sched: [7:1.00]<br>
;<br>
@@ -4182,8 +4182,8 @@ define <8 x float> @test_roundps(<8 x fl<br>
;<br>
; SKX-LABEL: test_roundps:<br>
; SKX: # %bb.0:<br>
-; SKX-NEXT: vrndscaleps $7, %ymm0, %ymm0 # sched: [8:0.67]<br>
-; SKX-NEXT: vrndscaleps $7, (%rdi), %ymm1 # sched: [15:0.67]<br>
+; SKX-NEXT: vroundps $7, %ymm0, %ymm0 # sched: [8:0.67]<br>
+; SKX-NEXT: vroundps $7, (%rdi), %ymm1 # sched: [15:0.67]<br>
; SKX-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
; SKX-NEXT: retq # sched: [7:1.00]<br>
;<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/av<wbr>x512-intrinsics.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=324985&r1=324984&r2=324985&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/avx512-intrinsics.ll?rev=<wbr>324985&r1=324984&r2=324985&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/av<wbr>x512-intrinsics.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/av<wbr>x512-intrinsics.ll Mon Feb 12 20:19:26 2018<br>
@@ -26,7 +26,7 @@ declare <2 x double> @<a href="http://llvm.x86.avx512.ma" rel="noreferrer" target="_blank">llvm.x86.avx512.ma</a><br>
define <2 x double> @test_rndscale_sd(<2 x double> %a, <2 x double> %b) {<br>
; CHECK-LABEL: test_rndscale_sd:<br>
; CHECK: ## %bb.0:<br>
-; CHECK-NEXT: vrndscalesd $11, %xmm1, %xmm0, %xmm0<br>
+; CHECK-NEXT: vroundsd $11, %xmm1, %xmm0, %xmm0<br>
; CHECK-NEXT: retq<br>
%res = call <2 x double> @<a href="http://llvm.x86.avx512.mask.rndscale.sd" rel="noreferrer" target="_blank">llvm.x86.avx512.mask.rndscale<wbr>.sd</a>(<2 x double> %a, <2 x double> %b, <2 x double> undef, i8 -1, i32 11, i32 4)<br>
ret <2 x double>%res<br>
@@ -70,7 +70,7 @@ declare <4 x float> @llvm.x86.avx512.mas<br>
define <4 x float> @test_rndscale_ss(<4 x float> %a, <4 x float> %b) {<br>
; CHECK-LABEL: test_rndscale_ss:<br>
; CHECK: ## %bb.0:<br>
-; CHECK-NEXT: vrndscaless $11, %xmm1, %xmm0, %xmm0<br>
+; CHECK-NEXT: vroundss $11, %xmm1, %xmm0, %xmm0<br>
; CHECK-NEXT: retq<br>
%res = call <4 x float> @llvm.x86.avx512.mask.rndscale<wbr>.ss(<4 x float> %a, <4 x float> %b, <4 x float> undef, i8 -1, i32 11, i32 4)<br>
ret <4 x float>%res<br>
@@ -79,7 +79,7 @@ define <4 x float> @test_rndscale_ss(<4<br>
define <4 x float> @test_rndscale_ss_load(<4 x float> %a, <4 x float>* %bptr) {<br>
; CHECK-LABEL: test_rndscale_ss_load:<br>
; CHECK: ## %bb.0:<br>
-; CHECK-NEXT: vrndscaless $11, (%rdi), %xmm0, %xmm0<br>
+; CHECK-NEXT: vroundss $11, (%rdi), %xmm0, %xmm0<br>
; CHECK-NEXT: retq<br>
%b = load <4 x float>, <4 x float>* %bptr<br>
%res = call <4 x float> @llvm.x86.avx512.mask.rndscale<wbr>.ss(<4 x float> %a, <4 x float> %b, <4 x float> undef, i8 -1, i32 11, i32 4)<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/av<wbr>x512-scalar.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-scalar.ll?rev=324985&r1=324984&r2=324985&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/avx512-scalar.ll?rev=<wbr>324985&r1=324984&r2=324985&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/av<wbr>x512-scalar.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/av<wbr>x512-scalar.ll Mon Feb 12 20:19:26 2018<br>
@@ -55,7 +55,7 @@ declare float @llvm.sqrt.f32(float<br>
define float @test_trunc(float %a) {<br>
; AVX512-LABEL: test_trunc:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscaless $11, %xmm0, %xmm0, %xmm0 ## encoding: [0x62,0xf3,0x7d,0x08,0x0a,0xc0<wbr>,0x0b]<br>
+; AVX512-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x0a,0xc0,0x0b<wbr>]<br>
; AVX512-NEXT: retq ## encoding: [0xc3]<br>
;<br>
; AVX-LABEL: test_trunc:<br>
@@ -83,7 +83,7 @@ define double @test_sqrt(double %a) {<br>
define float @test_rint(float %a) {<br>
; AVX512-LABEL: test_rint:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscaless $4, %xmm0, %xmm0, %xmm0 ## encoding: [0x62,0xf3,0x7d,0x08,0x0a,0xc0<wbr>,0x04]<br>
+; AVX512-NEXT: vroundss $4, %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x0a,0xc0,0x04<wbr>]<br>
; AVX512-NEXT: retq ## encoding: [0xc3]<br>
;<br>
; AVX-LABEL: test_rint:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/av<wbr>x512vl-intrinsics.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll?rev=324985&r1=324984&r2=324985&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/avx512vl-intrinsics.ll?<wbr>rev=324985&r1=324984&r2=<wbr>324985&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/av<wbr>x512vl-intrinsics.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/av<wbr>x512vl-intrinsics.ll Mon Feb 12 20:19:26 2018<br>
@@ -2701,7 +2701,7 @@ define <4 x float>@test_int_x86_avx512_m<br>
; CHECK: ## %bb.0:<br>
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]<br>
; CHECK-NEXT: vrndscaleps $88, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf3,0x7d,0x09,0x08,0xc8<wbr>,0x58]<br>
-; CHECK-NEXT: vrndscaleps $4, %xmm0, %xmm0 ## encoding: [0x62,0xf3,0x7d,0x08,0x08,0xc0<wbr>,0x04]<br>
+; CHECK-NEXT: vroundps $4, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x08,0xc0,0x04<wbr>]<br>
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf0,0x58,0xc0]<br>
; CHECK-NEXT: retq ## encoding: [0xc3]<br>
%res = call <4 x float> @llvm.x86.avx512.mask.rndscale<wbr>.ps.128(<4 x float> %x0, i32 88, <4 x float> %x2, i8 %x3)<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/ro<wbr>unding-ops.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/rounding-ops.ll?rev=324985&r1=324984&r2=324985&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/rounding-ops.ll?rev=<wbr>324985&r1=324984&r2=324985&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/ro<wbr>unding-ops.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/ro<wbr>unding-ops.ll Mon Feb 12 20:19:26 2018<br>
@@ -16,7 +16,7 @@ define float @test1(float %x) nounwind<br>
;<br>
; CHECK-AVX512-LABEL: test1:<br>
; CHECK-AVX512: ## %bb.0:<br>
-; CHECK-AVX512-NEXT: vrndscaless $9, %xmm0, %xmm0, %xmm0<br>
+; CHECK-AVX512-NEXT: vroundss $9, %xmm0, %xmm0, %xmm0<br>
; CHECK-AVX512-NEXT: retq<br>
%call = tail call float @floorf(float %x) nounwind readnone<br>
ret float %call<br>
@@ -37,7 +37,7 @@ define double @test2(double %x) nounwind<br>
;<br>
; CHECK-AVX512-LABEL: test2:<br>
; CHECK-AVX512: ## %bb.0:<br>
-; CHECK-AVX512-NEXT: vrndscalesd $9, %xmm0, %xmm0, %xmm0<br>
+; CHECK-AVX512-NEXT: vroundsd $9, %xmm0, %xmm0, %xmm0<br>
; CHECK-AVX512-NEXT: retq<br>
%call = tail call double @floor(double %x) nounwind readnone<br>
ret double %call<br>
@@ -58,7 +58,7 @@ define float @test3(float %x) nounwind<br>
;<br>
; CHECK-AVX512-LABEL: test3:<br>
; CHECK-AVX512: ## %bb.0:<br>
-; CHECK-AVX512-NEXT: vrndscaless $12, %xmm0, %xmm0, %xmm0<br>
+; CHECK-AVX512-NEXT: vroundss $12, %xmm0, %xmm0, %xmm0<br>
; CHECK-AVX512-NEXT: retq<br>
%call = tail call float @nearbyintf(float %x) nounwind readnone<br>
ret float %call<br>
@@ -79,7 +79,7 @@ define double @test4(double %x) nounwind<br>
;<br>
; CHECK-AVX512-LABEL: test4:<br>
; CHECK-AVX512: ## %bb.0:<br>
-; CHECK-AVX512-NEXT: vrndscalesd $12, %xmm0, %xmm0, %xmm0<br>
+; CHECK-AVX512-NEXT: vroundsd $12, %xmm0, %xmm0, %xmm0<br>
; CHECK-AVX512-NEXT: retq<br>
%call = tail call double @nearbyint(double %x) nounwind readnone<br>
ret double %call<br>
@@ -100,7 +100,7 @@ define float @test5(float %x) nounwind<br>
;<br>
; CHECK-AVX512-LABEL: test5:<br>
; CHECK-AVX512: ## %bb.0:<br>
-; CHECK-AVX512-NEXT: vrndscaless $10, %xmm0, %xmm0, %xmm0<br>
+; CHECK-AVX512-NEXT: vroundss $10, %xmm0, %xmm0, %xmm0<br>
; CHECK-AVX512-NEXT: retq<br>
%call = tail call float @ceilf(float %x) nounwind readnone<br>
ret float %call<br>
@@ -121,7 +121,7 @@ define double @test6(double %x) nounwind<br>
;<br>
; CHECK-AVX512-LABEL: test6:<br>
; CHECK-AVX512: ## %bb.0:<br>
-; CHECK-AVX512-NEXT: vrndscalesd $10, %xmm0, %xmm0, %xmm0<br>
+; CHECK-AVX512-NEXT: vroundsd $10, %xmm0, %xmm0, %xmm0<br>
; CHECK-AVX512-NEXT: retq<br>
%call = tail call double @ceil(double %x) nounwind readnone<br>
ret double %call<br>
@@ -142,7 +142,7 @@ define float @test7(float %x) nounwind<br>
;<br>
; CHECK-AVX512-LABEL: test7:<br>
; CHECK-AVX512: ## %bb.0:<br>
-; CHECK-AVX512-NEXT: vrndscaless $4, %xmm0, %xmm0, %xmm0<br>
+; CHECK-AVX512-NEXT: vroundss $4, %xmm0, %xmm0, %xmm0<br>
; CHECK-AVX512-NEXT: retq<br>
%call = tail call float @rintf(float %x) nounwind readnone<br>
ret float %call<br>
@@ -163,7 +163,7 @@ define double @test8(double %x) nounwind<br>
;<br>
; CHECK-AVX512-LABEL: test8:<br>
; CHECK-AVX512: ## %bb.0:<br>
-; CHECK-AVX512-NEXT: vrndscalesd $4, %xmm0, %xmm0, %xmm0<br>
+; CHECK-AVX512-NEXT: vroundsd $4, %xmm0, %xmm0, %xmm0<br>
; CHECK-AVX512-NEXT: retq<br>
%call = tail call double @rint(double %x) nounwind readnone<br>
ret double %call<br>
@@ -184,7 +184,7 @@ define float @test9(float %x) nounwind<br>
;<br>
; CHECK-AVX512-LABEL: test9:<br>
; CHECK-AVX512: ## %bb.0:<br>
-; CHECK-AVX512-NEXT: vrndscaless $11, %xmm0, %xmm0, %xmm0<br>
+; CHECK-AVX512-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0<br>
; CHECK-AVX512-NEXT: retq<br>
%call = tail call float @truncf(float %x) nounwind readnone<br>
ret float %call<br>
@@ -205,7 +205,7 @@ define double @test10(double %x) nounwin<br>
;<br>
; CHECK-AVX512-LABEL: test10:<br>
; CHECK-AVX512: ## %bb.0:<br>
-; CHECK-AVX512-NEXT: vrndscalesd $11, %xmm0, %xmm0, %xmm0<br>
+; CHECK-AVX512-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0<br>
; CHECK-AVX512-NEXT: retq<br>
%call = tail call double @trunc(double %x) nounwind readnone<br>
ret double %call<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/ss<wbr>e41-intrinsics-x86.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-intrinsics-x86.ll?rev=324985&r1=324984&r2=324985&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/sse41-intrinsics-x86.ll?<wbr>rev=324985&r1=324984&r2=<wbr>324985&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/ss<wbr>e41-intrinsics-x86.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/ss<wbr>e41-intrinsics-x86.ll Mon Feb 12 20:19:26 2018<br>
@@ -458,7 +458,7 @@ define <2 x double> @test_x86_sse41_roun<br>
;<br>
; SKX-LABEL: test_x86_sse41_round_pd:<br>
; SKX: ## %bb.0:<br>
-; SKX-NEXT: vrndscalepd $7, %xmm0, %xmm0 ## encoding: [0x62,0xf3,0xfd,0x08,0x09,0xc0<wbr>,0x07]<br>
+; SKX-NEXT: vroundpd $7, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x09,0xc0,0x07<wbr>]<br>
; SKX-NEXT: retl ## encoding: [0xc3]<br>
%res = call <2 x double> @llvm.x86.sse41.round.pd(<2 x double> %a0, i32 7) ; <<2 x double>> [#uses=1]<br>
ret <2 x double> %res<br>
@@ -479,7 +479,7 @@ define <4 x float> @test_x86_sse41_round<br>
;<br>
; SKX-LABEL: test_x86_sse41_round_ps:<br>
; SKX: ## %bb.0:<br>
-; SKX-NEXT: vrndscaleps $7, %xmm0, %xmm0 ## encoding: [0x62,0xf3,0x7d,0x08,0x08,0xc0<wbr>,0x07]<br>
+; SKX-NEXT: vroundps $7, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x08,0xc0,0x07<wbr>]<br>
; SKX-NEXT: retl ## encoding: [0xc3]<br>
%res = call <4 x float> @<a href="http://llvm.x86.sse41.round.ps" rel="noreferrer" target="_blank">llvm.x86.sse41.round.ps</a>(<4 x float> %a0, i32 7) ; <<4 x float>> [#uses=1]<br>
ret <4 x float> %res<br>
@@ -500,7 +500,7 @@ define <2 x double> @test_x86_sse41_roun<br>
;<br>
; SKX-LABEL: test_x86_sse41_round_sd:<br>
; SKX: ## %bb.0:<br>
-; SKX-NEXT: vrndscalesd $7, %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf3,0xfd,0x08,0x0b,0xc1<wbr>,0x07]<br>
+; SKX-NEXT: vroundsd $7, %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x0b,0xc1,0x07<wbr>]<br>
; SKX-NEXT: retl ## encoding: [0xc3]<br>
%res = call <2 x double> @<a href="http://llvm.x86.sse41.round.sd" rel="noreferrer" target="_blank">llvm.x86.sse41.round.sd</a>(<2 x double> %a0, <2 x double> %a1, i32 7) ; <<2 x double>> [#uses=1]<br>
ret <2 x double> %res<br>
@@ -524,7 +524,7 @@ define <2 x double> @test_x86_sse41_roun<br>
; SKX-LABEL: test_x86_sse41_round_sd_load:<br>
; SKX: ## %bb.0:<br>
; SKX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]<br>
-; SKX-NEXT: vrndscalesd $7, (%eax), %xmm0, %xmm0 ## encoding: [0x62,0xf3,0xfd,0x08,0x0b,0x00<wbr>,0x07]<br>
+; SKX-NEXT: vroundsd $7, (%eax), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x0b,0x00,0x07<wbr>]<br>
; SKX-NEXT: retl ## encoding: [0xc3]<br>
%a1b = load <2 x double>, <2 x double>* %a1<br>
%res = call <2 x double> @<a href="http://llvm.x86.sse41.round.sd" rel="noreferrer" target="_blank">llvm.x86.sse41.round.sd</a>(<2 x double> %a0, <2 x double> %a1b, i32 7) ; <<2 x double>> [#uses=1]<br>
@@ -545,7 +545,7 @@ define <4 x float> @test_x86_sse41_round<br>
;<br>
; SKX-LABEL: test_x86_sse41_round_ss:<br>
; SKX: ## %bb.0:<br>
-; SKX-NEXT: vrndscaless $7, %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf3,0x7d,0x08,0x0a,0xc1<wbr>,0x07]<br>
+; SKX-NEXT: vroundss $7, %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x0a,0xc1,0x07<wbr>]<br>
; SKX-NEXT: retl ## encoding: [0xc3]<br>
%res = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %a0, <4 x float> %a1, i32 7) ; <<4 x float>> [#uses=1]<br>
ret <4 x float> %res<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/ss<wbr>e41-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-schedule.ll?rev=324985&r1=324984&r2=324985&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/sse41-schedule.ll?rev=<wbr>324985&r1=324984&r2=324985&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/ss<wbr>e41-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/ss<wbr>e41-schedule.ll Mon Feb 12 20:19:26 2018<br>
@@ -3024,8 +3024,8 @@ define <2 x double> @test_roundpd(<2 x d<br>
;<br>
; SKX-LABEL: test_roundpd:<br>
; SKX: # %bb.0:<br>
-; SKX-NEXT: vrndscalepd $7, %xmm0, %xmm0 # sched: [8:0.67]<br>
-; SKX-NEXT: vrndscalepd $7, (%rdi), %xmm1 # sched: [14:0.67]<br>
+; SKX-NEXT: vroundpd $7, %xmm0, %xmm0 # sched: [8:0.67]<br>
+; SKX-NEXT: vroundpd $7, (%rdi), %xmm1 # sched: [14:0.67]<br>
; SKX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
; SKX-NEXT: retq # sched: [7:1.00]<br>
;<br>
@@ -3096,8 +3096,8 @@ define <4 x float> @test_roundps(<4 x fl<br>
;<br>
; SKX-LABEL: test_roundps:<br>
; SKX: # %bb.0:<br>
-; SKX-NEXT: vrndscaleps $7, %xmm0, %xmm0 # sched: [8:0.67]<br>
-; SKX-NEXT: vrndscaleps $7, (%rdi), %xmm1 # sched: [14:0.67]<br>
+; SKX-NEXT: vroundps $7, %xmm0, %xmm0 # sched: [8:0.67]<br>
+; SKX-NEXT: vroundps $7, (%rdi), %xmm1 # sched: [14:0.67]<br>
; SKX-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
; SKX-NEXT: retq # sched: [7:1.00]<br>
;<br>
@@ -3169,8 +3169,8 @@ define <2 x double> @test_roundsd(<2 x d<br>
;<br>
; SKX-LABEL: test_roundsd:<br>
; SKX: # %bb.0:<br>
-; SKX-NEXT: vrndscalesd $7, %xmm1, %xmm0, %xmm1 # sched: [8:0.67]<br>
-; SKX-NEXT: vrndscalesd $7, (%rdi), %xmm0, %xmm0 # sched: [14:0.67]<br>
+; SKX-NEXT: vroundsd $7, %xmm1, %xmm0, %xmm1 # sched: [8:0.67]<br>
+; SKX-NEXT: vroundsd $7, (%rdi), %xmm0, %xmm0 # sched: [14:0.67]<br>
; SKX-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.33]<br>
; SKX-NEXT: retq # sched: [7:1.00]<br>
;<br>
@@ -3242,8 +3242,8 @@ define <4 x float> @test_roundss(<4 x fl<br>
;<br>
; SKX-LABEL: test_roundss:<br>
; SKX: # %bb.0:<br>
-; SKX-NEXT: vrndscaless $7, %xmm1, %xmm0, %xmm1 # sched: [8:0.67]<br>
-; SKX-NEXT: vrndscaless $7, (%rdi), %xmm0, %xmm0 # sched: [14:0.67]<br>
+; SKX-NEXT: vroundss $7, %xmm1, %xmm0, %xmm1 # sched: [8:0.67]<br>
+; SKX-NEXT: vroundss $7, (%rdi), %xmm0, %xmm0 # sched: [14:0.67]<br>
; SKX-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [4:0.33]<br>
; SKX-NEXT: retq # sched: [7:1.00]<br>
;<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/ve<wbr>c_floor.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_floor.ll?rev=324985&r1=324984&r2=324985&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/vec_floor.ll?rev=324985&<wbr>r1=324984&r2=324985&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/ve<wbr>c_floor.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/ve<wbr>c_floor.ll Mon Feb 12 20:19:26 2018<br>
@@ -16,7 +16,7 @@ define <2 x double> @floor_v2f64(<2 x do<br>
;<br>
; AVX512-LABEL: floor_v2f64:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscalepd $9, %xmm0, %xmm0<br>
+; AVX512-NEXT: vroundpd $9, %xmm0, %xmm0<br>
; AVX512-NEXT: retq<br>
%t = call <2 x double> @llvm.floor.v2f64(<2 x double> %p)<br>
ret <2 x double> %t<br>
@@ -36,7 +36,7 @@ define <4 x float> @floor_v4f32(<4 x flo<br>
;<br>
; AVX512-LABEL: floor_v4f32:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscaleps $9, %xmm0, %xmm0<br>
+; AVX512-NEXT: vroundps $9, %xmm0, %xmm0<br>
; AVX512-NEXT: retq<br>
%t = call <4 x float> @llvm.floor.v4f32(<4 x float> %p)<br>
ret <4 x float> %t<br>
@@ -57,7 +57,7 @@ define <4 x double> @floor_v4f64(<4 x do<br>
;<br>
; AVX512-LABEL: floor_v4f64:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscalepd $9, %ymm0, %ymm0<br>
+; AVX512-NEXT: vroundpd $9, %ymm0, %ymm0<br>
; AVX512-NEXT: retq<br>
%t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p)<br>
ret <4 x double> %t<br>
@@ -78,7 +78,7 @@ define <8 x float> @floor_v8f32(<8 x flo<br>
;<br>
; AVX512-LABEL: floor_v8f32:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscaleps $9, %ymm0, %ymm0<br>
+; AVX512-NEXT: vroundps $9, %ymm0, %ymm0<br>
; AVX512-NEXT: retq<br>
%t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)<br>
ret <8 x float> %t<br>
@@ -146,7 +146,7 @@ define <2 x double> @ceil_v2f64(<2 x dou<br>
;<br>
; AVX512-LABEL: ceil_v2f64:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscalepd $10, %xmm0, %xmm0<br>
+; AVX512-NEXT: vroundpd $10, %xmm0, %xmm0<br>
; AVX512-NEXT: retq<br>
%t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p)<br>
ret <2 x double> %t<br>
@@ -166,7 +166,7 @@ define <4 x float> @ceil_v4f32(<4 x floa<br>
;<br>
; AVX512-LABEL: ceil_v4f32:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscaleps $10, %xmm0, %xmm0<br>
+; AVX512-NEXT: vroundps $10, %xmm0, %xmm0<br>
; AVX512-NEXT: retq<br>
%t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p)<br>
ret <4 x float> %t<br>
@@ -187,7 +187,7 @@ define <4 x double> @ceil_v4f64(<4 x dou<br>
;<br>
; AVX512-LABEL: ceil_v4f64:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscalepd $10, %ymm0, %ymm0<br>
+; AVX512-NEXT: vroundpd $10, %ymm0, %ymm0<br>
; AVX512-NEXT: retq<br>
%t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p)<br>
ret <4 x double> %t<br>
@@ -208,7 +208,7 @@ define <8 x float> @ceil_v8f32(<8 x floa<br>
;<br>
; AVX512-LABEL: ceil_v8f32:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscaleps $10, %ymm0, %ymm0<br>
+; AVX512-NEXT: vroundps $10, %ymm0, %ymm0<br>
; AVX512-NEXT: retq<br>
%t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)<br>
ret <8 x float> %t<br>
@@ -276,7 +276,7 @@ define <2 x double> @trunc_v2f64(<2 x do<br>
;<br>
; AVX512-LABEL: trunc_v2f64:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscalepd $11, %xmm0, %xmm0<br>
+; AVX512-NEXT: vroundpd $11, %xmm0, %xmm0<br>
; AVX512-NEXT: retq<br>
%t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p)<br>
ret <2 x double> %t<br>
@@ -296,7 +296,7 @@ define <4 x float> @trunc_v4f32(<4 x flo<br>
;<br>
; AVX512-LABEL: trunc_v4f32:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscaleps $11, %xmm0, %xmm0<br>
+; AVX512-NEXT: vroundps $11, %xmm0, %xmm0<br>
; AVX512-NEXT: retq<br>
%t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p)<br>
ret <4 x float> %t<br>
@@ -317,7 +317,7 @@ define <4 x double> @trunc_v4f64(<4 x do<br>
;<br>
; AVX512-LABEL: trunc_v4f64:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscalepd $11, %ymm0, %ymm0<br>
+; AVX512-NEXT: vroundpd $11, %ymm0, %ymm0<br>
; AVX512-NEXT: retq<br>
%t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p)<br>
ret <4 x double> %t<br>
@@ -338,7 +338,7 @@ define <8 x float> @trunc_v8f32(<8 x flo<br>
;<br>
; AVX512-LABEL: trunc_v8f32:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscaleps $11, %ymm0, %ymm0<br>
+; AVX512-NEXT: vroundps $11, %ymm0, %ymm0<br>
; AVX512-NEXT: retq<br>
%t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)<br>
ret <8 x float> %t<br>
@@ -406,7 +406,7 @@ define <2 x double> @rint_v2f64(<2 x dou<br>
;<br>
; AVX512-LABEL: rint_v2f64:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscalepd $4, %xmm0, %xmm0<br>
+; AVX512-NEXT: vroundpd $4, %xmm0, %xmm0<br>
; AVX512-NEXT: retq<br>
%t = call <2 x double> @llvm.rint.v2f64(<2 x double> %p)<br>
ret <2 x double> %t<br>
@@ -426,7 +426,7 @@ define <4 x float> @rint_v4f32(<4 x floa<br>
;<br>
; AVX512-LABEL: rint_v4f32:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscaleps $4, %xmm0, %xmm0<br>
+; AVX512-NEXT: vroundps $4, %xmm0, %xmm0<br>
; AVX512-NEXT: retq<br>
%t = call <4 x float> @llvm.rint.v4f32(<4 x float> %p)<br>
ret <4 x float> %t<br>
@@ -447,7 +447,7 @@ define <4 x double> @rint_v4f64(<4 x dou<br>
;<br>
; AVX512-LABEL: rint_v4f64:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscalepd $4, %ymm0, %ymm0<br>
+; AVX512-NEXT: vroundpd $4, %ymm0, %ymm0<br>
; AVX512-NEXT: retq<br>
%t = call <4 x double> @llvm.rint.v4f64(<4 x double> %p)<br>
ret <4 x double> %t<br>
@@ -468,7 +468,7 @@ define <8 x float> @rint_v8f32(<8 x floa<br>
;<br>
; AVX512-LABEL: rint_v8f32:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscaleps $4, %ymm0, %ymm0<br>
+; AVX512-NEXT: vroundps $4, %ymm0, %ymm0<br>
; AVX512-NEXT: retq<br>
%t = call <8 x float> @llvm.rint.v8f32(<8 x float> %p)<br>
ret <8 x float> %t<br>
@@ -536,7 +536,7 @@ define <2 x double> @nearbyint_v2f64(<2<br>
;<br>
; AVX512-LABEL: nearbyint_v2f64:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscalepd $12, %xmm0, %xmm0<br>
+; AVX512-NEXT: vroundpd $12, %xmm0, %xmm0<br>
; AVX512-NEXT: retq<br>
%t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p)<br>
ret <2 x double> %t<br>
@@ -556,7 +556,7 @@ define <4 x float> @nearbyint_v4f32(<4 x<br>
;<br>
; AVX512-LABEL: nearbyint_v4f32:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscaleps $12, %xmm0, %xmm0<br>
+; AVX512-NEXT: vroundps $12, %xmm0, %xmm0<br>
; AVX512-NEXT: retq<br>
%t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p)<br>
ret <4 x float> %t<br>
@@ -577,7 +577,7 @@ define <4 x double> @nearbyint_v4f64(<4<br>
;<br>
; AVX512-LABEL: nearbyint_v4f64:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscalepd $12, %ymm0, %ymm0<br>
+; AVX512-NEXT: vroundpd $12, %ymm0, %ymm0<br>
; AVX512-NEXT: retq<br>
%t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)<br>
ret <4 x double> %t<br>
@@ -598,7 +598,7 @@ define <8 x float> @nearbyint_v8f32(<8 x<br>
;<br>
; AVX512-LABEL: nearbyint_v8f32:<br>
; AVX512: ## %bb.0:<br>
-; AVX512-NEXT: vrndscaleps $12, %ymm0, %ymm0<br>
+; AVX512-NEXT: vroundps $12, %ymm0, %ymm0<br>
; AVX512-NEXT: retq<br>
%t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)<br>
ret <8 x float> %t<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/ve<wbr>c_ss_load_fold.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_ss_load_fold.ll?rev=324985&r1=324984&r2=324985&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/vec_ss_load_fold.ll?rev=<wbr>324985&r1=324984&r2=324985&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/ve<wbr>c_ss_load_fold.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/ve<wbr>c_ss_load_fold.ll Mon Feb 12 20:19:26 2018<br>
@@ -176,27 +176,16 @@ define <4 x float> @test3(<4 x float> %A<br>
; X64-NEXT: roundss $4, (%rdi), %xmm0<br>
; X64-NEXT: retq<br>
;<br>
-; X32_AVX1-LABEL: test3:<br>
-; X32_AVX1: ## %bb.0:<br>
-; X32_AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
-; X32_AVX1-NEXT: vroundss $4, (%eax), %xmm0, %xmm0<br>
-; X32_AVX1-NEXT: retl<br>
-;<br>
-; X64_AVX1-LABEL: test3:<br>
-; X64_AVX1: ## %bb.0:<br>
-; X64_AVX1-NEXT: vroundss $4, (%rdi), %xmm0, %xmm0<br>
-; X64_AVX1-NEXT: retq<br>
-;<br>
-; X32_AVX512-LABEL: test3:<br>
-; X32_AVX512: ## %bb.0:<br>
-; X32_AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
-; X32_AVX512-NEXT: vrndscaless $4, (%eax), %xmm0, %xmm0<br>
-; X32_AVX512-NEXT: retl<br>
-;<br>
-; X64_AVX512-LABEL: test3:<br>
-; X64_AVX512: ## %bb.0:<br>
-; X64_AVX512-NEXT: vrndscaless $4, (%rdi), %xmm0, %xmm0<br>
-; X64_AVX512-NEXT: retq<br>
+; X32_AVX-LABEL: test3:<br>
+; X32_AVX: ## %bb.0:<br>
+; X32_AVX-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
+; X32_AVX-NEXT: vroundss $4, (%eax), %xmm0, %xmm0<br>
+; X32_AVX-NEXT: retl<br>
+;<br>
+; X64_AVX-LABEL: test3:<br>
+; X64_AVX: ## %bb.0:<br>
+; X64_AVX-NEXT: vroundss $4, (%rdi), %xmm0, %xmm0<br>
+; X64_AVX-NEXT: retq<br>
%a = load float , float *%b<br>
%B = insertelement <4 x float> undef, float %a, i32 0<br>
%X = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %A, <4 x float> %B, i32 4)<br>
@@ -254,7 +243,7 @@ define <4 x float> @test4(<4 x float> %A<br>
; X32_AVX512-NEXT: vmovaps %xmm0, (%esp) ## 16-byte Spill<br>
; X32_AVX512-NEXT: calll _f<br>
; X32_AVX512-NEXT: vmovaps (%esp), %xmm1 ## 16-byte Reload<br>
-; X32_AVX512-NEXT: vrndscaless $4, %xmm1, %xmm0, %xmm0<br>
+; X32_AVX512-NEXT: vroundss $4, %xmm1, %xmm0, %xmm0<br>
; X32_AVX512-NEXT: addl $28, %esp<br>
; X32_AVX512-NEXT: retl<br>
;<br>
@@ -265,7 +254,7 @@ define <4 x float> @test4(<4 x float> %A<br>
; X64_AVX512-NEXT: vmovaps %xmm0, (%rsp) ## 16-byte Spill<br>
; X64_AVX512-NEXT: callq _f<br>
; X64_AVX512-NEXT: vmovaps (%rsp), %xmm1 ## 16-byte Reload<br>
-; X64_AVX512-NEXT: vrndscaless $4, %xmm1, %xmm0, %xmm0<br>
+; X64_AVX512-NEXT: vroundss $4, %xmm1, %xmm0, %xmm0<br>
; X64_AVX512-NEXT: addq $24, %rsp<br>
; X64_AVX512-NEXT: retq<br>
%a = load float , float *%b<br>
<br>
Modified: llvm/trunk/utils/TableGen/X86E<wbr>VEX2VEXTablesEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp?rev=324985&r1=324984&r2=324985&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/utils/TableGe<wbr>n/X86EVEX2VEXTablesEmitter.<wbr>cpp?rev=324985&r1=324984&r2=32<wbr>4985&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/X86E<wbr>VEX2VEXTablesEmitter.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/X86E<wbr>VEX2VEXTablesEmitter.cpp Mon Feb 12 20:19:26 2018<br>
@@ -67,7 +67,6 @@ private:<br>
"VPMULLQ",<br>
"VPSRAQ",<br>
"VDBPSADBW",<br>
- "VRNDSCALE",<br>
"VSCALEFPS"<br>
};<br>
// Instruction's name starts with one of the entries in the exception list<br>
@@ -163,6 +162,25 @@ void X86EVEX2VEXTablesEmitter::prin<wbr>tTabl<br>
{"VSHUFI32X4Z256rri", "VPERM2I128rr", false},<br>
{"VSHUFI64X2Z256rmi", "VPERM2I128rm", false},<br>
{"VSHUFI64X2Z256rri", "VPERM2I128rr", false},<br>
+<br>
+ // These can be replaced if we verify the scale part of the immediate is<br>
+ // zero.<br>
+ {"VRNDSCALEPDZ128rri", "VROUNDPDr", true},<br>
+ {"VRNDSCALEPDZ128rmi", "VROUNDPDm", true},<br>
+ {"VRNDSCALEPSZ128rri", "VROUNDPSr", true},<br>
+ {"VRNDSCALEPSZ128rmi", "VROUNDPSm", true},<br>
+ {"VRNDSCALEPDZ256rri", "VROUNDYPDr", false},<br>
+ {"VRNDSCALEPDZ256rmi", "VROUNDYPDm", false},<br>
+ {"VRNDSCALEPSZ256rri", "VROUNDYPSr", false},<br>
+ {"VRNDSCALEPSZ256rmi", "VROUNDYPSm", false},<br>
+ {"VRNDSCALESDr", "VROUNDSDr", true},<br>
+ {"VRNDSCALESDm", "VROUNDSDm", true},<br>
+ {"VRNDSCALESSr", "VROUNDSSr", true},<br>
+ {"VRNDSCALESSm", "VROUNDSSm", true},<br>
+ {"VRNDSCALESDr_Int", "VROUNDSDr_Int", true},<br>
+ {"VRNDSCALESDm_Int", "VROUNDSDm_Int", true},<br>
+ {"VRNDSCALESSr_Int", "VROUNDSSr_Int", true},<br>
+ {"VRNDSCALESSm_Int", "VROUNDSSm_Int", true},<br>
};<br>
<br>
// Print the manually added entries<br>
<br>
<br>
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