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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><o:p> </o:p></p><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal style='margin-left:.5in'><b>From:</b> qcolombet@apple.com [mailto:qcolombet@apple.com] <br><b>Sent:</b> Friday, February 2, 2018 8:18 PM<br><br><o:p></o:p></p></div></div><div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><p class=MsoNormal style='margin-left:.5in'>On Feb 2, 2018, at 3:53 PM, Nemanja Ivanovic via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal style='margin-left:.5in'><o:p> </o:p></p><div><div><div><div><div><div><div><div><div><div><div><div><div><p class=MsoNormal style='margin-left:.5in'>Sorry, but it seems to me that we are working around the problem with the hasExtraRegAllocReq flag and this workaround is introducing new problems that then need to be solved.<o:p></o:p></p></div><p class=MsoNormal style='mso-margin-top-alt:0in;margin-right:0in;margin-bottom:12.0pt;margin-left:.5in'>Going back to the original problem that Escha reported, it seems to be that the back end ends up in the following state which arguably is probably not a reasonable state to be in (if register renaming is to be allowed):<o:p></o:p></p></div><p class=MsoNormal style='margin-left:.5in'>- There are constraints added to the virtual registers that restrict which register class the assigned physical register must come from<o:p></o:p></p></div><p class=MsoNormal style='margin-left:.5in'>- The register allocator respects those constraints and selects a register from the correct class<o:p></o:p></p></div><p class=MsoNormal style='margin-left:.5in'>- The selected physical register is marked as renamable<o:p></o:p></p></div><p class=MsoNormal style='mso-margin-top-alt:0in;margin-right:0in;margin-bottom:12.0pt;margin-left:.5in'>- Calling MachineInstr::getRegClassConstraint() on the machine instruction returns a register class that does not take into account the additional constraints<o:p></o:p></p></div><p class=MsoNormal style='margin-left:.5in'>Ultimately, anything that does register renaming with the back end in that state can potentially break the code since it doesn't know what actual class the register rename is allowed to come from.<o:p></o:p></p></div><p class=MsoNormal style='margin-left:.5in'><o:p> </o:p></p></div><p class=MsoNormal style='margin-left:.5in'>Wouldn't this mean that a target that can be in this state has at least these two reasonable options:<o:p></o:p></p></div><p class=MsoNormal style='margin-left:.5in'>1. Set some property that will ensure that the renamable flag is never set on any register - essentially what Geoff is suggesting in the latter part of his last email. I would just make it a property of TargetRegisterInfo (perhaps `virtual bool TargetRegisterInfo::allowRegisterRenaming()`).<o:p></o:p></p></div></div></div></div></blockquote><div><p class=MsoNormal style='margin-left:.5in'><o:p> </o:p></p></div><div><p class=MsoNormal style='margin-left:.5in'>Again, yes I think we need that.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Ok, I will put together a strawman proposal for adding this target global allowRegisterRenaming flag.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal style='margin-left:.5in'>More generally, I believe we want to step back with the renamable flag, think about its semantic and what in the infrastructure we would need to fix, if any, to make sure that semantic is preserved/preservable along the way.<o:p></o:p></p></div><p class=MsoNormal style='margin-left:.5in'><o:p> </o:p></p><p class=MsoNormal>My understanding of the renamable flag is: if I see an operand with it set, I can freely change the register to any other that is a member of the register class returned by MI->getRegClassConstraint(). The renamable flag can be set to 0 for several different reasons:<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><ul style='margin-top:0in' type=disc><li class=MsoListParagraph style='margin-left:0in;mso-list:l0 level1 lfo1'>ABI constraints (since liveness is not always precisely modeled). We conservatively handle these cases by setting all physical register operands that didn’t start out as virtual regs to not be renamable. Also any physical register operands created after register allocation will have renamable set to 0 as well.<o:p></o:p></li><li class=MsoListParagraph style='margin-left:0in;mso-list:l0 level1 lfo1'>Opcode/target constraints: for opcodes that have complex register class requirements (e.g. that depend on other operands/instructions), we set hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine description, and set renamable to 0 for these operands. We check this property in the verifier as well. The proposal discussed above would add a target flag that essentially says “all opcodes have these extra requirements”, so no operands would ever get marked as renamable.<o:p></o:p></li></ul><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>One issue that has come up a few times is keeping the renamable flag correct when modifying code after register allocation. In my first proposed change to add the renamable flag, I made setOpcode() and setReg() both conservative clear all renamable flags. I believe Matthias voiced some opposition to this (I don’t recall how strong), but perhaps this is another level of conservatism that would be useful. Taking this approach would mean that backend code would only need to change to set the renamable flag to 1 in cases where it knows it is safe to do so.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><div><p class=MsoNormal style='mso-margin-top-alt:0in;margin-right:0in;margin-bottom:12.0pt;margin-left:.5in'>2. We make TargetInstrInfo::getRegClass() virtual and allow the target to override it so that the extra constraints can be taken into account if it wants to allow renaming of registers<o:p></o:p></p></div><p class=MsoNormal style='margin-left:.5in'>Not to suggest that the two solutions are mutually exclusive.<o:p></o:p></p></div><div><p class=MsoNormal style='margin-left:.5in'><o:p> </o:p></p><div><p class=MsoNormal style='margin-left:.5in'>On Fri, Feb 2, 2018 at 5:57 PM, <<a href="mailto:gberry@codeaurora.org" target="_blank">gberry@codeaurora.org</a>> wrote:<o:p></o:p></p><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in'><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>I think the fix for this the way things are currently setup would be for the code that changes the COPY to the target opcode to clear the renamable bits on the operands.<o:p></o:p></p></div></div></blockquote></div></div></div></blockquote><div><p class=MsoNormal style='margin-left:.5in'><o:p> </o:p></p></div><div><p class=MsoNormal style='margin-left:.5in'>Although it would work, I think it hints that we didn’t think the handle of the renamable flag all the way. I feel like we are reproducing the same problems that the kill flag had whereas we are trying to kill the kill flag.<o:p></o:p></p></div><div><p class=MsoNormal style='margin-left:.5in'>Let us no repeat history :).<o:p></o:p></p></div><p class=MsoNormal style='margin-left:.5in'><br><br><o:p></o:p></p><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><div><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in'><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>If we add a target global “all opcodes are hasExtraRegAllocReq” setting, we could avoid setting any COPY operands as renamable in the first place.<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>-- <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>Geoff Berry<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>Employee of Qualcomm Datacenter Technologies, Inc.<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.<o:p></o:p></p></div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'><b>From:</b> <a href="mailto:fglaser@apple.com" target="_blank">fglaser@apple.com</a> [mailto:<a href="mailto:fglaser@apple.com" target="_blank">fglaser@apple.com</a>] <b>On Behalf Of </b><a href="mailto:escha@apple.com" target="_blank">escha@apple.com</a><br><b>Sent:</b> Friday, February 2, 2018 5:30 PM<br><b>To:</b> <a href="mailto:escha@apple.com" target="_blank">escha@apple.com</a><br><b>Cc:</b> <a href="mailto:gberry@codeaurora.org" target="_blank">gberry@codeaurora.org</a>; <a href="mailto:junbuml@codeaurora.org" target="_blank">junbuml@codeaurora.org</a>; <a href="mailto:marina.yatsina@intel.com" target="_blank">marina.yatsina@intel.com</a>; <a href="mailto:kannan.narayanan@amd.com" target="_blank">kannan.narayanan@amd.com</a>; <a href="mailto:nhaehnle@gmail.com" target="_blank">nhaehnle@gmail.com</a>; <a href="mailto:wei.ding2@amd.com" target="_blank">wei.ding2@amd.com</a>; Matthias Braun <<a href="mailto:matze@braunis.de" target="_blank">matze@braunis.de</a>>; Nemanja Ivanovic <<a href="mailto:nemanja.i.ibm@gmail.com" target="_blank">nemanja.i.ibm@gmail.com</a>>; llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>>; <a href="mailto:reviews%2BD41835%2Bpublic%2B9c1dec7fb6e75ce0@reviews.llvm.org" target="_blank">reviews+D41835+public+9c1dec7fb6e75ce0@reviews.llvm.org</a>; <a href="mailto:tpr.llvm@botech.co.uk" target="_blank">tpr.llvm@botech.co.uk</a>; <a href="mailto:javed.absar@arm.com" target="_blank">javed.absar@arm.com</a><o:p></o:p></p><div><div><p class=MsoNormal style='margin-left:.5in'><br><b>Subject:</b> Re: [PATCH] D41835: [MachineCopyPropagation] Extend pass to do COPY source forwarding<o:p></o:p></p></div></div><div><p class=MsoNormal style='margin-left:.5in'><o:p> </o:p></p></div></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>update: it gets worse. i can’t get the tests to pass because a lot of tests fail with this when the verifier is on:<o:p></o:p></p><div><pre style='margin-left:.5in;box-sizing:border-box;white-space:pre-wrap;word-wrap:break-word;font-variant-ligatures:normal'><span style='color:#333333'> </span><o:p></o:p></pre><pre style='margin-left:.5in'><span style='color:#333333'>*** Bad machine code: Illegal isRenamable setting for opcode with extra regalloc requirements ***</span><o:p></o:p></pre><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>This occurs on our copy instructions after we expand them into actual machine opcodes, because the machine opcode for the copy instruction isn’t Renamable (none of our instructions are).<o:p></o:p></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>—escha<o:p></o:p></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p><div><p class=MsoNormal style='mso-margin-top-alt:auto;margin-bottom:12.0pt;margin-left:.5in'><o:p> </o:p></p><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>On Feb 2, 2018, at 1:37 PM, via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>this is probably a reasonable solution. mostly, at this point, i’m worried about the fact that upstream now apparently has a different understanding of register classes than we do (in terms of what is “safe”), which could lead to other future issues for us.<o:p></o:p></p><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>—escha<o:p></o:p></p><div><p class=MsoNormal style='mso-margin-top-alt:auto;margin-bottom:12.0pt;margin-left:.5in'><o:p> </o:p></p><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>On Feb 2, 2018, at 1:36 PM, <a href="mailto:gberry@codeaurora.org" target="_blank">gberry@codeaurora.org</a> wrote:<o:p></o:p></p></div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>Ah, okay. So I assume you’re okay with disabling the post-RA run of this pass for this particular target to fix this particular issue?<o:p></o:p></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>--<span class=m4139097589071889215apple-converted-space> </span><o:p></o:p></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>Geoff Berry<o:p></o:p></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>Employee of Qualcomm Datacenter Technologies, Inc.<o:p></o:p></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.<o:p></o:p></p></div></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'><b>From:</b><span class=m4139097589071889215apple-converted-space> </span><a href="mailto:fglaser@apple.com" target="_blank">fglaser@apple.com</a> [<a href="mailto:fglaser@apple.com" target="_blank">mailto:fglaser@apple.com</a>]<span class=m4139097589071889215apple-converted-space> </span><b>On Behalf Of<span class=m4139097589071889215apple-converted-space> </span></b><a href="mailto:escha@apple.com" target="_blank">escha@apple.com</a><br><b>Sent:</b><span class=m4139097589071889215apple-converted-space> </span>Friday, February 2, 2018 4:32 PM<br><b>To:</b><span class=m4139097589071889215apple-converted-space> </span><a href="mailto:gberry@codeaurora.org" target="_blank">gberry@codeaurora.org</a><br><b>Cc:</b><span class=m4139097589071889215apple-converted-space> </span>Quentin Colombet <<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>>; <a href="mailto:reviews+D41835+public+9c1dec7fb6e75ce0@reviews.llvm.org" target="_blank">reviews+D41835+public+9c1dec7fb6e75ce0@reviews.llvm.org</a>; Geoff Berry via Phabricator <<a href="mailto:reviews@reviews.llvm.org" target="_blank">reviews@reviews.llvm.org</a>>; <a href="mailto:javed.absar@arm.com" target="_blank">javed.absar@arm.com</a>; Matthias Braun <<a href="mailto:matze@braunis.de" target="_blank">matze@braunis.de</a>>; Jonas Paulsson <<a href="mailto:paulsson@linux.vnet.ibm.com" target="_blank">paulsson@linux.vnet.ibm.com</a>>; <a href="mailto:tstellar@redhat.com" target="_blank">tstellar@redhat.com</a>; Matt Arsenault <<a href="mailto:Matthew.Arsenault@amd.com" target="_blank">Matthew.Arsenault@amd.com</a>>; <a href="mailto:junbuml@codeaurora.org" target="_blank">junbuml@codeaurora.org</a>; <a href="mailto:marina.yatsina@intel.com" target="_blank">marina.yatsina@intel.com</a>; <a href="mailto:wei.ding2@amd.com" target="_blank">wei.ding2@amd.com</a>; <a href="mailto:kannan.narayanan@amd.com" target="_blank">kannan.narayanan@amd.com</a>; <a href="mailto:nhaehnle@gmail.com" target="_blank">nhaehnle@gmail.com</a>; Nemanja Ivanovic <<a href="mailto:nemanja.i.ibm@gmail.com" target="_blank">nemanja.i.ibm@gmail.com</a>>; llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>>; <a href="mailto:tpr.llvm@botech.co.uk" target="_blank">tpr.llvm@botech.co.uk</a><br><b>Subject:</b><span class=m4139097589071889215apple-converted-space> </span>Re: [PATCH] D41835: [MachineCopyPropagation] Extend pass to do COPY source forwarding<o:p></o:p></p></div></div></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>looking at it again, it’s making more sense: your patch enabled MachineCopyPropagation in the RA pipeline. the pass might have *already* been broken, but it wasn’t running for us, and now it is, so it broke things in that way too.<o:p></o:p></p></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>—escha<o:p></o:p></p></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;margin-bottom:12.0pt;margin-left:.5in'><br><br><o:p></o:p></p></div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>On Feb 2, 2018, at 1:26 PM,<span class=m4139097589071889215apple-converted-space> </span><a href="mailto:gberry@codeaurora.org" target="_blank"><span style='color:purple'>gberry@codeaurora.org</span></a><span class=m4139097589071889215apple-converted-space> </span>wrote:<o:p></o:p></p></div></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>escha,<o:p></o:p></p></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>I’m confused by your comment about bundles. It was known that this patch doesn’t handle forwarding into bundles, but it sounds like to me you are seeing problems with the dead COPY removal part of this pass, which was not intentionally changed by this patch (other than adding a DEBUG statement when it happens).<o:p></o:p></p></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>--<span class=m4139097589071889215apple-converted-space> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>Geoff Berry<o:p></o:p></p></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>Employee of Qualcomm Datacenter Technologies, Inc.<o:p></o:p></p></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.<o:p></o:p></p></div></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'><b>From:</b><span class=m4139097589071889215apple-converted-space> </span><a href="mailto:fglaser@apple.com" target="_blank"><span style='color:purple'>fglaser@apple.com</span></a><span class=m4139097589071889215apple-converted-space> </span>[<a href="mailto:fglaser@apple.com" target="_blank"><span style='color:purple'>mailto:fglaser@apple.com</span></a>]<span class=m4139097589071889215apple-converted-space> </span><b>On Behalf Of<span class=m4139097589071889215apple-converted-space> </span></b><a href="mailto:escha@apple.com" target="_blank"><span style='color:purple'>escha@apple.com</span></a><br><b>Sent:</b><span class=m4139097589071889215apple-converted-space> </span>Friday, February 2, 2018 4:10 PM<br><b>To:</b><span class=m4139097589071889215apple-converted-space> </span>Quentin Colombet <<a href="mailto:qcolombet@apple.com" target="_blank"><span style='color:purple'>qcolombet@apple.com</span></a>><br><b>Cc:</b><span class=m4139097589071889215apple-converted-space> </span>Geoff Berry <<a href="mailto:gberry@codeaurora.org" target="_blank"><span style='color:purple'>gberry@codeaurora.org</span></a>>;<span class=m4139097589071889215apple-converted-space> </span><a href="mailto:reviews+D41835+public+9c1dec7fb6e75ce0@reviews.llvm.org" target="_blank"><span style='color:purple'>reviews+D41835+public+9c1dec7fb6e75ce0@reviews.llvm.org</span></a>; Geoff Berry via Phabricator <<a href="mailto:reviews@reviews.llvm.org" target="_blank"><span style='color:purple'>reviews@reviews.llvm.org</span></a>>;<span class=m4139097589071889215apple-converted-space> </span><a href="mailto:javed.absar@arm.com" target="_blank"><span style='color:purple'>javed.absar@arm.com</span></a>; Matthias Braun <<a href="mailto:matze@braunis.de" target="_blank"><span style='color:purple'>matze@braunis.de</span></a>>; Jonas Paulsson <<a href="mailto:paulsson@linux.vnet.ibm.com" target="_blank"><span style='color:purple'>paulsson@linux.vnet.ibm.com</span></a>>;<span class=m4139097589071889215apple-converted-space> </span><a href="mailto:tstellar@redhat.com" target="_blank"><span style='color:purple'>tstellar@redhat.com</span></a>; Matt Arsenault <<a href="mailto:Matthew.Arsenault@amd.com" target="_blank"><span style='color:purple'>Matthew.Arsenault@amd.com</span></a>>;<span class=m4139097589071889215apple-converted-space> </span><a href="mailto:junbuml@codeaurora.org" target="_blank"><span style='color:purple'>junbuml@codeaurora.org</span></a>;<span class=m4139097589071889215apple-converted-space> </span><a href="mailto:marina.yatsina@intel.com" target="_blank"><span style='color:purple'>marina.yatsina@intel.com</span></a>;<span class=m4139097589071889215apple-converted-space> </span><a href="mailto:wei.ding2@amd.com" target="_blank"><span style='color:purple'>wei.ding2@amd.com</span></a>;<span class=m4139097589071889215apple-converted-space> </span><a href="mailto:kannan.narayanan@amd.com" target="_blank"><span style='color:purple'>kannan.narayanan@amd.com</span></a>;<span class=m4139097589071889215apple-converted-space> </span><a href="mailto:nhaehnle@gmail.com" target="_blank"><span style='color:purple'>nhaehnle@gmail.com</span></a>; Nemanja Ivanovic <<a href="mailto:nemanja.i.ibm@gmail.com" target="_blank"><span style='color:purple'>nemanja.i.ibm@gmail.com</span></a>>; llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank"><span style='color:purple'>llvm-commits@lists.llvm.org</span></a>>;<span class=m4139097589071889215apple-converted-space> </span><a href="mailto:tpr.llvm@botech.co.uk" target="_blank"><span style='color:purple'>tpr.llvm@botech.co.uk</span></a><br><b>Subject:</b><span class=m4139097589071889215apple-converted-space> </span>Re: [PATCH] D41835: [MachineCopyPropagation] Extend pass to do COPY source forwarding<o:p></o:p></p></div></div></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;margin-bottom:12.0pt;margin-left:.5in'><br><br><br><o:p></o:p></p></div></div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>On Feb 2, 2018, at 12:55 PM, Quentin Colombet <<a href="mailto:qcolombet@apple.com" target="_blank"><span style='color:purple'>qcolombet@apple.com</span></a>> wrote:<o:p></o:p></p></div></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div><div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;margin-bottom:12.0pt;margin-left:.5in'><br><br><br><o:p></o:p></p></div></div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>On Feb 2, 2018, at 12:21 PM,<span class=m4139097589071889215apple-converted-space> </span><a href="mailto:escha@apple.com" target="_blank"><span style='color:purple'>escha@apple.com</span></a><span class=m4139097589071889215apple-converted-space> </span>wrote:<o:p></o:p></p></div></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div><div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>I mean, in that case we are likely to have to mark every single opcode (all 12,000 or so) with this requirement. At that point we might as well just opt out of the pass, I think? At least, it feels like a gross hack that papers over the fact that LLVM has changed how register classes work such that our entire approach is no longer valid.<o:p></o:p></p></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>Also, it seems very weird to make this constraint-violating behavior *opt-out*. Maybe it should be opt-in, i.e. put doesNotHaveExtraSrcRegAllocReq on all instructions it’s okay for?<o:p></o:p></p></div></div></div></div></div></blockquote><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>That sounds like a better approach to me.<o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>After talking with escha, I agree that TableGen is not necessarily expressive enough to model all the constraints that need to be met and I would err on the safe side of being opt-in instead of opt-out.<o:p></o:p></p></div></div></div></div></div></div></blockquote><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>this is actually worse than i initially realized. one of our targets is VLIW and is completely broken by this patch, *even if we opt out as described*, because it doesn’t iterate over the operands of a bundle. so for example:<o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>r3 = COPY foo<o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>BUNDLE_TYPE_FOO<o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'><thing that uses r3><o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>END<o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>it believes that r3 is dead because it doesn’t iterate over the bundle operands, so it never sees the use of r3.<o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>—escha<o:p></o:p></p></div></div></div></div></blockquote></div></div></div></div></blockquote></div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><o:p></o:p></p></div></blockquote></div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:.5in'> <o:p></o:p></p></div></div></div></div></div></blockquote></div><p class=MsoNormal style='margin-left:.5in'><o:p> </o:p></p></div><p class=MsoNormal style='margin-left:.5in'>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a><br><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><o:p></o:p></p></div></blockquote></div><p class=MsoNormal style='margin-left:.5in'><o:p> </o:p></p></div></body></html>