<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Feb 2, 2018, at 12:21 PM, <a href="mailto:escha@apple.com" class="">escha@apple.com</a> wrote:</div><br class="Apple-interchange-newline"><div class=""><meta http-equiv="Content-Type" content="text/html; charset=utf-8" class=""><div style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">I mean, in that case we are likely to have to mark every single opcode (all 12,000 or so) with this requirement. At that point we might as well just opt out of the pass, I think? At least, it feels like a gross hack that papers over the fact that LLVM has changed how register classes work such that our entire approach is no longer valid.<div class=""><br class=""></div><div class="">Also, it seems very weird to make this constraint-violating behavior *opt-out*. Maybe it should be opt-in, i.e. put doesNotHaveExtraSrcRegAllocReq on all instructions it’s okay for?</div></div></div></blockquote><div><br class=""></div><div>That sounds like a better approach to me.</div><div>After talking with escha, I agree that TableGen is not necessarily expressive enough to model all the constraints that need to be met and I would err on the safe side of being opt-in instead of opt-out.</div><br class=""><blockquote type="cite" class=""><div class=""><div style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div class=""><br class=""></div><div class="">—escha<br class=""><div class=""><br class=""><blockquote type="cite" class=""><div class="">On Feb 2, 2018, at 12:17 PM, <a href="mailto:gberry@codeaurora.org" class="">gberry@codeaurora.org</a> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="WordSection1" style="page: WordSection1; font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">Hi escha,<span class="Apple-converted-space"> </span><o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">This sounds very similar to the issues this change caused on AMDGPU. The way we worked around them for those effected targets was to mark the relevant opcodes with hasExtraSrcRegAllocReq, which will prevent the MachineOperands from being marked as isRenamable, which will in turn prevent MachineCopyPropagation from changing them. Is this a reasonable fix for your targets?<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">--<span class="Apple-converted-space"> </span><o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">Geoff Berry<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">Employee of Qualcomm Datacenter Technologies, Inc.<o:p class=""></o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.<o:p class=""></o:p></div></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div><div class=""><div style="border-style: solid none none; border-top-width: 1pt; border-top-color: rgb(225, 225, 225); padding: 3pt 0in 0in;" class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><b class="">From:</b><span class="Apple-converted-space"> </span><a href="mailto:fglaser@apple.com" class="">fglaser@apple.com</a> [<a href="mailto:fglaser@apple.com" class="">mailto:fglaser@apple.com</a>]<span class="Apple-converted-space"> </span><b class="">On Behalf Of<span class="Apple-converted-space"> </span></b><a href="mailto:escha@apple.com" class="">escha@apple.com</a><br class=""><b class="">Sent:</b><span class="Apple-converted-space"> </span>Friday, February 2, 2018 2:56 PM<br class=""><b class="">To:</b><span class="Apple-converted-space"> </span><a href="mailto:reviews+D41835+public+9c1dec7fb6e75ce0@reviews.llvm.org" class="">reviews+D41835+public+9c1dec7fb6e75ce0@reviews.llvm.org</a>; Geoff Berry via Phabricator <<a href="mailto:reviews@reviews.llvm.org" class="">reviews@reviews.llvm.org</a>><br class=""><b class="">Cc:</b><span class="Apple-converted-space"> </span><a href="mailto:gberry@codeaurora.org" class="">gberry@codeaurora.org</a>; <a href="mailto:qcolombet@apple.com" class="">qcolombet@apple.com</a>; <a href="mailto:javed.absar@arm.com" class="">javed.absar@arm.com</a>; <a href="mailto:matze@braunis.de" class="">matze@braunis.de</a>; <a href="mailto:paulsson@linux.vnet.ibm.com" class="">paulsson@linux.vnet.ibm.com</a>; <a href="mailto:tstellar@redhat.com" class="">tstellar@redhat.com</a>; <a href="mailto:Matthew.Arsenault@amd.com" class="">Matthew.Arsenault@amd.com</a>; <a href="mailto:junbuml@codeaurora.org" class="">junbuml@codeaurora.org</a>; <a href="mailto:marina.yatsina@intel.com" class="">marina.yatsina@intel.com</a>; <a href="mailto:wei.ding2@amd.com" class="">wei.ding2@amd.com</a>; <a href="mailto:kannan.narayanan@amd.com" class="">kannan.narayanan@amd.com</a>; <a href="mailto:nhaehnle@gmail.com" class="">nhaehnle@gmail.com</a>; <a href="mailto:nemanja.i.ibm@gmail.com" class="">nemanja.i.ibm@gmail.com</a>; <a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>; <a href="mailto:tpr.llvm@botech.co.uk" class="">tpr.llvm@botech.co.uk</a><br class=""><b class="">Subject:</b><span class="Apple-converted-space"> </span>Re: [PATCH] D41835: [MachineCopyPropagation] Extend pass to do COPY source forwarding<o:p class=""></o:p></div></div></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">FYI, this completely broke our (out-of-tree) backends in more ways than i can count. In particular, it seems to break the ability for us to enforce constraints on register classes at all: we heavily rely on this for a wide variety of instructions whose behavior cannot be fully expressed in tablegen, or really, anywhere that we need to say “X argument of Y instruction should be constrained to class Z”.<o:p class=""></o:p></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">Here is one particular example that illustrates this (but what breaks is potentially far more than this).<o:p class=""></o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">Suppose you have a machine in which instructions can have at most 2 arguments in the category {immediates, special registers}. We limit immediates to 2 in instruction selection, and then run a small pass after instruction selection that identifies any instructions with more than 2 {immediates, special registers} and marks the special register arguments as “no SR”. For example:<o:p class=""></o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif; background-color: white; background-position: initial initial; background-repeat: initial initial;" class="">%6:gpr32 = COPY $sr12</span><span style="font-size: 8.5pt; font-family: Menlo, serif;" class=""><o:p class=""></o:p></span></div></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif; background-color: white; background-position: initial initial; background-repeat: initial initial;" class=""><br class=""><br class=""></span><span style="font-size: 8.5pt; font-family: Menlo, serif;" class=""><o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">becomes<o:p class=""></o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif; background-color: white; background-position: initial initial; background-repeat: initial initial;" class="">%6:gpr32nosr = COPY $sr12</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">reasonably, this should mean the COPY cannot be folded into the instruction that uses it, because the argument is a “gpr32nosr”, which prohibits special registers.<o:p class=""></o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">however, with this patch…<o:p class=""></o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class=""># *** IR Dump After Greedy Register Allocator ***:<o:p class=""></o:p></span></div></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">%6:gpr32nosr = COPY $sr12<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">%12.sub2:gpr32tup3 = /* some instruction */ 0, 0, %6, 0, 4294967312, 0, 0<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class=""># *** IR Dump After Virtual Register Rewriter ***:<o:p class=""></o:p></span></div></div><div class=""><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">renamable $r2 = COPY $sr12<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">renamable $r2 = /* some instruction */ 0, 0, %6, 0, 4294967312, 0, 0<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">[…]<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class=""># *** IR Dump After Machine Copy Propagation Pass ***:<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">renamable $r2 = /* some instruction */ 0, 0, $sr12, 0, 4294967312, 0, 0<o:p class=""></o:p></span></div></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">in the second step the information that “%6” cannot be an SR is lost due to register allocation, and then copy propagation happily plows through and violates the constraint we set earlier.<o:p class=""></o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">this is the simplest example, but this entire patch makes me extremely nervous because we rely on register classes heavily in our backend and if the compiler is now free to violate our constraints, all bets are off.<o:p class=""></o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">—escha<o:p class=""></o:p></div><div class=""><div class=""><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><br class=""><br class=""><o:p class=""></o:p></div><blockquote style="margin-top: 5pt; margin-bottom: 5pt;" class="" type="cite"><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">On Feb 1, 2018, at 10:56 AM, Geoff Berry via Phabricator via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" style="color: purple; text-decoration: underline;" class="">llvm-commits@lists.llvm.org</a>> wrote:<o:p class=""></o:p></div></div><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><o:p class=""> </o:p></div><div class=""><div class=""><div style="margin: 0in 0in 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif;" class="">This revision was automatically updated to reflect the committed changes.<br class="">Closed by commit rL323991: [MachineCopyPropagation] Extend pass to do COPY source forwarding (authored by gberry, committed by ).<br class=""><br class="">Changed prior to commit:<br class=""> <a href="https://reviews.llvm.org/D41835?vs=131323&id=132429#toc" style="color: purple; text-decoration: underline;" class="">https://reviews.llvm.org/D41835?vs=131323&id=132429#toc</a><br class=""><br class="">Repository:<br class=""> rL LLVM<br class=""><br class=""><a href="https://reviews.llvm.org/D41835" style="color: purple; text-decoration: underline;" class="">https://reviews.llvm.org/D41835</a><br class=""><br class="">Files:<br class=""> llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp<br class=""> llvm/trunk/lib/CodeGen/TargetPassConfig.cpp<br class=""> llvm/trunk/test/CodeGen/AArch64/aarch64-fold-lslfast.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/copyprop.mir<br class=""> llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/flags-multiuse.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/ldst-opt.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/neg-imm.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/fix-vgpr-copies.mir<br class=""> llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/ret.ll<br class=""> llvm/trunk/test/CodeGen/ARM/atomic-op.ll<br class=""> llvm/trunk/test/CodeGen/ARM/intrinsics-overflow.ll<br class=""> llvm/trunk/test/CodeGen/ARM/select-imm.ll<br class=""> llvm/trunk/test/CodeGen/ARM/swifterror.ll<br class=""> llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll<br class=""> llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll<br class=""> llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll<br class=""> llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/fma-mutate.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/gpr-vsr-spill.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/opt-li-add-to-addi.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/tail-dup-layout.ll<br class=""> llvm/trunk/test/CodeGen/SPARC/32abi.ll<br class=""> llvm/trunk/test/CodeGen/SPARC/atomics.ll<br class=""> llvm/trunk/test/CodeGen/SystemZ/vec-sub-01.ll<br class=""> llvm/trunk/test/CodeGen/Thumb/pr35836.ll<br class=""> llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll<br class=""> llvm/trunk/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll<br class=""> llvm/trunk/test/CodeGen/X86/arg-copy-elide.ll<br class=""> llvm/trunk/test/CodeGen/X86/avx-load-store.ll<br class=""> llvm/trunk/test/CodeGen/X86/avx512-bugfix-25270.ll<br class=""> llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll<br class=""> llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll<br class=""> llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-fast-isel.ll<br class=""> llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll<br class=""> llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll<br class=""> llvm/trunk/test/CodeGen/X86/combine-fcopysign.ll<br class=""> llvm/trunk/test/CodeGen/X86/combine-shl.ll<br class=""> llvm/trunk/test/CodeGen/X86/complex-fastmath.ll<br class=""> llvm/trunk/test/CodeGen/X86/divide-by-constant.ll<br class=""> llvm/trunk/test/CodeGen/X86/fmaxnum.ll<br class=""> llvm/trunk/test/CodeGen/X86/fmf-flags.ll<br class=""> llvm/trunk/test/CodeGen/X86/fminnum.ll<br class=""> llvm/trunk/test/CodeGen/X86/fp128-i128.ll<br class=""> llvm/trunk/test/CodeGen/X86/h-registers-1.ll<br class=""> llvm/trunk/test/CodeGen/X86/haddsub-2.ll<br class=""> llvm/trunk/test/CodeGen/X86/haddsub-3.ll<br class=""> llvm/trunk/test/CodeGen/X86/haddsub-undef.ll<br class=""> llvm/trunk/test/CodeGen/X86/half.ll<br class=""> llvm/trunk/test/CodeGen/X86/horizontal-reduce-smax.ll<br class=""> llvm/trunk/test/CodeGen/X86/horizontal-reduce-smin.ll<br class=""> llvm/trunk/test/CodeGen/X86/horizontal-reduce-umax.ll<br class=""> llvm/trunk/test/CodeGen/X86/horizontal-reduce-umin.ll<br class=""> llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll<br class=""> llvm/trunk/test/CodeGen/X86/ipra-local-linkage.ll<br class=""> llvm/trunk/test/CodeGen/X86/localescape.ll<br class=""> llvm/trunk/test/CodeGen/X86/machine-cp.ll<br class=""> llvm/trunk/test/CodeGen/X86/mul-i1024.ll<br class=""> llvm/trunk/test/CodeGen/X86/mul-i256.ll<br class=""> llvm/trunk/test/CodeGen/X86/mul-i512.ll<br class=""> llvm/trunk/test/CodeGen/X86/mul128.ll<br class=""> llvm/trunk/test/CodeGen/X86/mulvi32.ll<br class=""> llvm/trunk/test/CodeGen/X86/pmul.ll<br class=""> llvm/trunk/test/CodeGen/X86/powi.ll<br class=""> llvm/trunk/test/CodeGen/X86/pr11334.ll<br class=""> llvm/trunk/test/CodeGen/X86/pr29112.ll<br class=""> llvm/trunk/test/CodeGen/X86/pr34080-2.ll<br class=""> llvm/trunk/test/CodeGen/X86/psubus.ll<br class=""> llvm/trunk/test/CodeGen/X86/retpoline-external.ll<br class=""> llvm/trunk/test/CodeGen/X86/retpoline.ll<br class=""> llvm/trunk/test/CodeGen/X86/sad.ll<br class=""> llvm/trunk/test/CodeGen/X86/safestack.ll<br class=""> llvm/trunk/test/CodeGen/X86/safestack_inline.ll<br class=""> llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll<br class=""> llvm/trunk/test/CodeGen/X86/select.ll<br class=""> llvm/trunk/test/CodeGen/X86/shrink-wrap-chkstk.ll<br class=""> llvm/trunk/test/CodeGen/X86/slow-pmulld.ll<br class=""> llvm/trunk/test/CodeGen/X86/sqrt-fastmath.ll<br class=""> llvm/trunk/test/CodeGen/X86/sse-scalar-fp-arith.ll<br class=""> llvm/trunk/test/CodeGen/X86/sse1.ll<br class=""> llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll<br class=""> llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll<br class=""> llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll<br class=""> llvm/trunk/test/CodeGen/X86/vec_fp_to_int.ll<br class=""> llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll<br class=""> llvm/trunk/test/CodeGen/X86/vec_minmax_sint.ll<br class=""> llvm/trunk/test/CodeGen/X86/vec_shift4.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-blend.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-idiv-sdiv-128.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-idiv-udiv-128.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-mul.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-rotate-128.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-sext.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-shift-lshr-128.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-shift-shl-128.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-trunc-math.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-trunc-packus.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-trunc-ssat.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-trunc-usat.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-zext.ll<br class=""> llvm/trunk/test/CodeGen/X86/vselect-minmax.ll<br class=""> llvm/trunk/test/CodeGen/X86/widen_conv-3.ll<br class=""> llvm/trunk/test/CodeGen/X86/widen_conv-4.ll<br class=""> llvm/trunk/test/CodeGen/X86/win64_frame.ll<br class=""> llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll<br class=""> llvm/trunk/test/CodeGen/X86/x86-shrink-wrap-unwind.ll<br class=""> llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll<br class=""> llvm/trunk/test/DebugInfo/COFF/fpo-shrink-wrap.ll<br class=""> llvm/trunk/test/DebugInfo/X86/spill-nospill.ll<br class=""><br class=""><D41835.132429.patch>_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" style="color: purple; text-decoration: underline;" class="">llvm-commits@lists.llvm.org</a><br class=""><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" style="color: purple; text-decoration: underline;" class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a></div></div></div></blockquote></div></div></div></div></div></div></blockquote></div><br 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