<div dir="ltr"><div><div>Forgive me if I am misinterpreting what the suggestion is, but
while I agree that a pass with the potential to break things should be
opt-in rather than opt-out, I'm curious about a couple of things:<br><br></div>1.
The granularity of the opt-in/opt-out. Seems that as Escha pointed out,
opting out for every instruction that could receive a result of a copy
can be prohibitive. But equivalently, opting in for every instruction
can be quite daunting as well. Would it make more sense for the pass
itself to be opt-in only and then instructions themselves to be opt-out?
That way targets that can just use the pass as-is can just go ahead and
opt-in (and fix any instructions that need to opt out) and targets for
which it would be prohibitive to do this per-instruction opt-out would
simply just not opt-in to the pass.<br></div><br>2. Seems like the issue that Escha describes can be handled in the pass by ensuring that the source is forwarded only if it is a register that is in the register class for the user of the copy. Isn't everything required for this available from MCInstrDesc and TargetRegisterClass? Or maybe I'm misinterpreting what the problem actually is...<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Feb 2, 2018 at 4:10 PM, <span dir="ltr"><<a href="mailto:gberry@codeaurora.org" target="_blank">gberry@codeaurora.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div link="blue" vlink="purple" lang="EN-US"><div class="m_5379822803082636775WordSection1"><p class="MsoNormal">In the case of AMDGPU there were just one or two opcode base classes in the td files that needed to have the hasExtraSrcRegAllocReq attribute added, so it wasn’t a big deal.<u></u><u></u></p><p class="MsoNormal">I don’t think flipping the default value of this opcode property makes sense, as that would involve changing all of the opcodes (or their base classes) in all of the in-tree targets (other than AMDGPU).<u></u><u></u></p><p class="MsoNormal">How about a target property that says “all opcodes are hasExtraSrcRegAllocReq”? <u></u><u></u></p><span class=""><p class="MsoNormal"><u></u> <u></u></p><div><p class="MsoNormal">-- <u></u><u></u></p><p class="MsoNormal">Geoff Berry<u></u><u></u></p><p class="MsoNormal">Employee of Qualcomm Datacenter Technologies, Inc.<u></u><u></u></p><p class="MsoNormal"> Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.<u></u><u></u></p></div><p class="MsoNormal"><u></u> <u></u></p></span><div><div style="border:none;border-top:solid #e1e1e1 1.0pt;padding:3.0pt 0in 0in 0in"><p class="MsoNormal"><b>From:</b> <a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a> [mailto:<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>] <br><b>Sent:</b> Friday, February 2, 2018 3:55 PM<br><b>To:</b> Geoff Berry <<a href="mailto:gberry@codeaurora.org" target="_blank">gberry@codeaurora.org</a>><br><b>Cc:</b> <a href="mailto:reviews%2BD41835%2Bpublic%2B9c1dec7fb6e75ce0@reviews.llvm.org" target="_blank">reviews+D41835+public+<wbr>9c1dec7fb6e75ce0@reviews.llvm.<wbr>org</a>; Geoff Berry via Phabricator <<a href="mailto:reviews@reviews.llvm.org" target="_blank">reviews@reviews.llvm.org</a>>; <a href="mailto:javed.absar@arm.com" target="_blank">javed.absar@arm.com</a>; Matthias Braun <<a href="mailto:matze@braunis.de" target="_blank">matze@braunis.de</a>>; Jonas Paulsson <<a href="mailto:paulsson@linux.vnet.ibm.com" target="_blank">paulsson@linux.vnet.ibm.com</a>>; <a href="mailto:tstellar@redhat.com" target="_blank">tstellar@redhat.com</a>; Matt Arsenault <<a href="mailto:Matthew.Arsenault@amd.com" target="_blank">Matthew.Arsenault@amd.com</a>>; <a href="mailto:junbuml@codeaurora.org" target="_blank">junbuml@codeaurora.org</a>; <a href="mailto:marina.yatsina@intel.com" target="_blank">marina.yatsina@intel.com</a>; <a href="mailto:wei.ding2@amd.com" target="_blank">wei.ding2@amd.com</a>; <a href="mailto:kannan.narayanan@amd.com" target="_blank">kannan.narayanan@amd.com</a>; <a href="mailto:nhaehnle@gmail.com" target="_blank">nhaehnle@gmail.com</a>; Nemanja Ivanovic <<a href="mailto:nemanja.i.ibm@gmail.com" target="_blank">nemanja.i.ibm@gmail.com</a>>; llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>>; <a href="mailto:tpr.llvm@botech.co.uk" target="_blank">tpr.llvm@botech.co.uk</a>; <a href="mailto:escha@apple.com" target="_blank">escha@apple.com</a></p><div><div class="h5"><br><b>Subject:</b> Re: [PATCH] D41835: [MachineCopyPropagation] Extend pass to do COPY source forwarding<u></u><u></u></div></div><p></p></div></div><div><div class="h5"><p class="MsoNormal"><u></u> <u></u></p><p class="MsoNormal"><u></u> <u></u></p><div><p class="MsoNormal"><br><br><u></u><u></u></p><blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"><div><p class="MsoNormal">On Feb 2, 2018, at 12:21 PM, <a href="mailto:escha@apple.com" target="_blank">escha@apple.com</a> wrote:<u></u><u></u></p></div><p class="MsoNormal"><u></u> <u></u></p><div><div><p class="MsoNormal">I mean, in that case we are likely to have to mark every single opcode (all 12,000 or so) with this requirement. At that point we might as well just opt out of the pass, I think? At least, it feels like a gross hack that papers over the fact that LLVM has changed how register classes work such that our entire approach is no longer valid.<u></u><u></u></p><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">Also, it seems very weird to make this constraint-violating behavior *opt-out*. Maybe it should be opt-in, i.e. put doesNotHaveExtraSrcRegAllocReq on all instructions it’s okay for?<u></u><u></u></p></div></div></div></blockquote><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">That sounds like a better approach to me.<u></u><u></u></p></div><div><p class="MsoNormal">After talking with escha, I agree that TableGen is not necessarily expressive enough to model all the constraints that need to be met and I would err on the safe side of being opt-in instead of opt-out.<u></u><u></u></p></div><p class="MsoNormal"><br><br><u></u><u></u></p><blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"><div><div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">—escha<u></u><u></u></p><div><p class="MsoNormal"><br><br><u></u><u></u></p><blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"><div><p class="MsoNormal">On Feb 2, 2018, at 12:17 PM, <a href="mailto:gberry@codeaurora.org" target="_blank">gberry@codeaurora.org</a> wrote:<u></u><u></u></p></div><p class="MsoNormal"><u></u> <u></u></p><div><div><p class="MsoNormal">Hi escha,<span class="m_5379822803082636775apple-converted-space"> </span><u></u><u></u></p></div><div><p class="MsoNormal"> <u></u><u></u></p></div><div><p class="MsoNormal">This sounds very similar to the issues this change caused on AMDGPU. The way we worked around them for those effected targets was to mark the relevant opcodes with hasExtraSrcRegAllocReq, which will prevent the MachineOperands from being marked as isRenamable, which will in turn prevent MachineCopyPropagation from changing them. Is this a reasonable fix for your targets?<u></u><u></u></p></div><div><p class="MsoNormal"> <u></u><u></u></p></div><div><div><p class="MsoNormal">--<span class="m_5379822803082636775apple-converted-space"> </span><u></u><u></u></p></div><div><p class="MsoNormal">Geoff Berry<u></u><u></u></p></div><div><p class="MsoNormal">Employee of Qualcomm Datacenter Technologies, Inc.<u></u><u></u></p></div><div><p class="MsoNormal">Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.<u></u><u></u></p></div></div><div><p class="MsoNormal"> <u></u><u></u></p></div><div><div style="border:none;border-top:solid #e1e1e1 1.0pt;padding:3.0pt 0in 0in 0in"><div><p class="MsoNormal"><b>From:</b><span class="m_5379822803082636775apple-converted-space"> </span><a href="mailto:fglaser@apple.com" target="_blank">fglaser@apple.com</a> [<a href="mailto:fglaser@apple.com" target="_blank">mailto:fglaser@apple.com</a>]<span class="m_5379822803082636775apple-converted-space"> </span><b>On Behalf Of<span class="m_5379822803082636775apple-converted-space"> </span></b><a href="mailto:escha@apple.com" target="_blank">escha@apple.com</a><br><b>Sent:</b><span class="m_5379822803082636775apple-converted-space"> </span>Friday, February 2, 2018 2:56 PM<br><b>To:</b><span class="m_5379822803082636775apple-converted-space"> </span><a href="mailto:reviews+D41835+public+9c1dec7fb6e75ce0@reviews.llvm.org" target="_blank">reviews+D41835+public+<wbr>9c1dec7fb6e75ce0@reviews.llvm.<wbr>org</a>; Geoff Berry via Phabricator <<a href="mailto:reviews@reviews.llvm.org" target="_blank">reviews@reviews.llvm.org</a>><br><b>Cc:</b><span class="m_5379822803082636775apple-converted-space"> </span><a href="mailto:gberry@codeaurora.org" target="_blank">gberry@codeaurora.org</a>; <a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>; <a href="mailto:javed.absar@arm.com" target="_blank">javed.absar@arm.com</a>; <a href="mailto:matze@braunis.de" target="_blank">matze@braunis.de</a>; <a href="mailto:paulsson@linux.vnet.ibm.com" target="_blank">paulsson@linux.vnet.ibm.com</a>; <a href="mailto:tstellar@redhat.com" target="_blank">tstellar@redhat.com</a>; <a href="mailto:Matthew.Arsenault@amd.com" target="_blank">Matthew.Arsenault@amd.com</a>; <a href="mailto:junbuml@codeaurora.org" target="_blank">junbuml@codeaurora.org</a>; <a href="mailto:marina.yatsina@intel.com" target="_blank">marina.yatsina@intel.com</a>; <a href="mailto:wei.ding2@amd.com" target="_blank">wei.ding2@amd.com</a>; <a href="mailto:kannan.narayanan@amd.com" target="_blank">kannan.narayanan@amd.com</a>; <a href="mailto:nhaehnle@gmail.com" target="_blank">nhaehnle@gmail.com</a>; <a href="mailto:nemanja.i.ibm@gmail.com" target="_blank">nemanja.i.ibm@gmail.com</a>; <a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>; <a href="mailto:tpr.llvm@botech.co.uk" target="_blank">tpr.llvm@botech.co.uk</a><br><b>Subject:</b><span class="m_5379822803082636775apple-converted-space"> </span>Re: [PATCH] D41835: [MachineCopyPropagation] Extend pass to do COPY source forwarding<u></u><u></u></p></div></div></div><div><p class="MsoNormal"> <u></u><u></u></p></div><div><p class="MsoNormal">FYI, this completely broke our (out-of-tree) backends in more ways than i can count. In particular, it seems to break the ability for us to enforce constraints on register classes at all: we heavily rely on this for a wide variety of instructions whose behavior cannot be fully expressed in tablegen, or really, anywhere that we need to say “X argument of Y instruction should be constrained to class Z”.<u></u><u></u></p></div><div><div><p class="MsoNormal"> <u></u><u></u></p></div></div><div><div><p class="MsoNormal">Here is one particular example that illustrates this (but what breaks is potentially far more than this).<u></u><u></u></p></div></div><div><div><p class="MsoNormal"> <u></u><u></u></p></div></div><div><div><p class="MsoNormal">Suppose you have a machine in which instructions can have at most 2 arguments in the category {immediates, special registers}. We limit immediates to 2 in instruction selection, and then run a small pass after instruction selection that identifies any instructions with more than 2 {immediates, special registers} and marks the special register arguments as “no SR”. For example:<u></u><u></u></p></div></div><div><div><p class="MsoNormal"> <u></u><u></u></p></div></div><div><div><div><p class="MsoNormal"><span style="font-size:8.5pt;font-family:"Menlo",serif;background:white">%6:gpr32 = COPY $sr12</span><u></u><u></u></p></div></div></div><div><div><p class="MsoNormal"><span style="font-size:8.5pt;font-family:"Menlo",serif;background:white"><br><br><br></span><u></u><u></u></p></div></div><div><div><p class="MsoNormal">becomes<u></u><u></u></p></div></div><div><div><p class="MsoNormal"> <u></u><u></u></p></div></div><div><div><p class="MsoNormal"><span style="font-size:8.5pt;font-family:"Menlo",serif;background:white">%6:gpr32nosr = COPY $sr12</span><u></u><u></u></p></div></div><div><div><p class="MsoNormal"> <u></u><u></u></p></div></div><div><div><p class="MsoNormal">reasonably, this should mean the COPY cannot be folded into the instruction that uses it, because the argument is a “gpr32nosr”, which prohibits special registers.<u></u><u></u></p></div></div><div><div><p class="MsoNormal"> <u></u><u></u></p></div></div><div><div><p class="MsoNormal">however, with this patch…<u></u><u></u></p></div></div><div><div><p class="MsoNormal"> <u></u><u></u></p></div></div><div><div><div><p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Menlo",serif"># *** IR Dump After Greedy Register Allocator ***:</span><u></u><u></u></p></div></div></div><div><div><p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Menlo",serif">%6:gpr32nosr = COPY $sr12</span><u></u><u></u></p></div></div><div><div><p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Menlo",serif">%12.sub2:gpr32tup3 = /* some instruction */ 0, 0, %6, 0, 4294967312, 0, 0</span><u></u><u></u></p></div></div><div><div><p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Menlo",serif"># *** IR Dump After Virtual Register Rewriter ***:</span><u></u><u></u></p></div></div><div><div><div><p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Menlo",serif">renamable $r2 = COPY $sr12</span><u></u><u></u></p></div></div><div><div><p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Menlo",serif">renamable $r2 = /* some instruction */ 0, 0, %6, 0, 4294967312, 0, 0</span><u></u><u></u></p></div></div><div><div><p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Menlo",serif">[…]</span><u></u><u></u></p></div></div><div><div><p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Menlo",serif"># *** IR Dump After Machine Copy Propagation Pass ***:</span><u></u><u></u></p></div></div><div><div><p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Menlo",serif">renamable $r2 = /* some instruction */ 0, 0, $sr12, 0, 4294967312, 0, 0</span><u></u><u></u></p></div></div></div><div><div><p class="MsoNormal"> <u></u><u></u></p></div></div><div><div><p class="MsoNormal">in the second step the information that “%6” cannot be an SR is lost due to register allocation, and then copy propagation happily plows through and violates the constraint we set earlier.<u></u><u></u></p></div></div><div><div><p class="MsoNormal"> <u></u><u></u></p></div></div><div><div><p class="MsoNormal">this is the simplest example, but this entire patch makes me extremely nervous because we rely on register classes heavily in our backend and if the compiler is now free to violate our constraints, all bets are off.<u></u><u></u></p></div></div><div><div><p class="MsoNormal"> <u></u><u></u></p></div></div><div><div><p class="MsoNormal">—escha<u></u><u></u></p></div><div><div><div><div><p class="MsoNormal"><br><br><br><u></u><u></u></p></div><blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"><div><div><p class="MsoNormal">On Feb 1, 2018, at 10:56 AM, Geoff Berry via Phabricator via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank"><span style="color:purple">llvm-commits@lists.llvm.org</span></a>> wrote:<u></u><u></u></p></div></div><div><p class="MsoNormal"> <u></u><u></u></p></div><div><div><div><p class="MsoNormal">This revision was automatically updated to reflect the committed changes.<br>Closed by commit rL323991: [MachineCopyPropagation] Extend pass to do COPY source forwarding (authored by gberry, committed by ).<br><br>Changed prior to commit:<br> <a href="https://reviews.llvm.org/D41835?vs=131323&id=132429#toc" target="_blank"><span style="color:purple">https://reviews.llvm.org/<wbr>D41835?vs=131323&id=132429#toc</span></a><br><br>Repository:<br> rL LLVM<br><br><a href="https://reviews.llvm.org/D41835" target="_blank"><span style="color:purple">https://reviews.llvm.org/<wbr>D41835</span></a><br><br>Files:<br> llvm/trunk/lib/CodeGen/<wbr>MachineCopyPropagation.cpp<br> llvm/trunk/lib/CodeGen/<wbr>TargetPassConfig.cpp<br> llvm/trunk/test/CodeGen/<wbr>AArch64/aarch64-fold-lslfast.<wbr>ll<br> llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-AdvSIMD-Scalar.<wbr>ll<br> llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-zero-cycle-<wbr>regmov.ll<br> llvm/trunk/test/CodeGen/<wbr>AArch64/cmpxchg-idioms.ll<br> llvm/trunk/test/CodeGen/<wbr>AArch64/copyprop.mir<br> llvm/trunk/test/CodeGen/<wbr>AArch64/f16-instructions.ll<br> llvm/trunk/test/CodeGen/<wbr>AArch64/flags-multiuse.ll<br> llvm/trunk/test/CodeGen/<wbr>AArch64/ldst-opt.ll<br> llvm/trunk/test/CodeGen/<wbr>AArch64/merge-store-<wbr>dependency.ll<br> llvm/trunk/test/CodeGen/<wbr>AArch64/neg-imm.ll<br> llvm/trunk/test/CodeGen/<wbr>AMDGPU/callee-special-input-<wbr>sgprs.ll<br> llvm/trunk/test/CodeGen/<wbr>AMDGPU/fix-vgpr-copies.mir<br> llvm/trunk/test/CodeGen/<wbr>AMDGPU/multilevel-break.ll<br> llvm/trunk/test/CodeGen/<wbr>AMDGPU/ret.ll<br> llvm/trunk/test/CodeGen/ARM/<wbr>atomic-op.ll<br> llvm/trunk/test/CodeGen/ARM/<wbr>intrinsics-overflow.ll<br> llvm/trunk/test/CodeGen/ARM/<wbr>select-imm.ll<br> llvm/trunk/test/CodeGen/ARM/<wbr>swifterror.ll<br> llvm/trunk/test/CodeGen/Mips/<wbr>llvm-ir/ashr.ll<br> llvm/trunk/test/CodeGen/Mips/<wbr>llvm-ir/lshr.ll<br> llvm/trunk/test/CodeGen/Mips/<wbr>llvm-ir/shl.ll<br> llvm/trunk/test/CodeGen/Mips/<wbr>llvm-ir/sub.ll<br> llvm/trunk/test/CodeGen/<wbr>PowerPC/MCSE-caller-preserved-<wbr>reg.ll<br> llvm/trunk/test/CodeGen/<wbr>PowerPC/fma-mutate.ll<br> llvm/trunk/test/CodeGen/<wbr>PowerPC/gpr-vsr-spill.ll<br> llvm/trunk/test/CodeGen/<wbr>PowerPC/licm-remat.ll<br> llvm/trunk/test/CodeGen/<wbr>PowerPC/opt-li-add-to-addi.ll<br> llvm/trunk/test/CodeGen/<wbr>PowerPC/tail-dup-layout.ll<br> llvm/trunk/test/CodeGen/<wbr>SPARC/32abi.ll<br> llvm/trunk/test/CodeGen/<wbr>SPARC/atomics.ll<br> llvm/trunk/test/CodeGen/<wbr>SystemZ/vec-sub-01.ll<br> llvm/trunk/test/CodeGen/<wbr>Thumb/pr35836.ll<br> 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llvm/trunk/test/CodeGen/X86/<wbr>vector-trunc-math.ll<br> llvm/trunk/test/CodeGen/X86/<wbr>vector-trunc-packus.ll<br> llvm/trunk/test/CodeGen/X86/<wbr>vector-trunc-ssat.ll<br> llvm/trunk/test/CodeGen/X86/<wbr>vector-trunc-usat.ll<br> llvm/trunk/test/CodeGen/X86/<wbr>vector-zext.ll<br> llvm/trunk/test/CodeGen/X86/<wbr>vselect-minmax.ll<br> llvm/trunk/test/CodeGen/X86/<wbr>widen_conv-3.ll<br> llvm/trunk/test/CodeGen/X86/<wbr>widen_conv-4.ll<br> llvm/trunk/test/CodeGen/X86/<wbr>win64_frame.ll<br> llvm/trunk/test/CodeGen/X86/<wbr>x86-interleaved-access.ll<br> llvm/trunk/test/CodeGen/X86/<wbr>x86-shrink-wrap-unwind.ll<br> llvm/trunk/test/CodeGen/X86/<wbr>x86-shrink-wrapping.ll<br> llvm/trunk/test/DebugInfo/<wbr>COFF/fpo-shrink-wrap.ll<br> llvm/trunk/test/DebugInfo/<wbr>X86/spill-nospill.ll<br><br><D41835.132429.patch>_________<wbr>______________________________<wbr>________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@lists.llvm.org" target="_blank"><span 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