<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">FYI, this completely broke our (out-of-tree) backends in more ways than i can count. In particular, it seems to break the ability for us to enforce constraints on register classes at all: we heavily rely on this for a wide variety of instructions whose behavior cannot be fully expressed in tablegen, or really, anywhere that we need to say “X argument of Y instruction should be constrained to class Z”.<div class=""><br class=""></div><div class="">Here is one particular example that illustrates this (but what breaks is potentially far more than this).</div><div class=""><br class=""></div><div class="">Suppose you have a machine in which instructions can have at most 2 arguments in the category {immediates, special registers}. We limit immediates to 2 in instruction selection, and then run a small pass after instruction selection that identifies any instructions with more than 2 {immediates, special registers} and marks the special register arguments as “no SR”. For example:</div><div class=""><br class=""></div><div class=""><div style="margin: 0px; font-stretch: normal; font-size: 11px; line-height: normal; font-family: Menlo;" class=""><span style="font-variant-ligatures: no-common-ligatures;" class=""><span style="background-color: rgb(255, 255, 255);" class="">%6:gpr32 = COPY $sr12</span></span></div></div><div style="margin: 0px; font-stretch: normal; font-size: 11px; line-height: normal; font-family: Menlo;" class=""><span style="font-variant-ligatures: no-common-ligatures;" class=""><span style="background-color: rgb(255, 255, 255);" class=""><br class=""></span></span></div><div class="">becomes</div><div class=""><br class=""></div><div class=""><span style="font-family: Menlo; font-size: 11px; background-color: rgb(255, 255, 255);" class="">%6:gpr32nosr = COPY $sr12</span></div><div class=""><br class=""></div><div class="">reasonably, this should mean the COPY cannot be folded into the instruction that uses it, because the argument is a “gpr32nosr”, which prohibits special registers.</div><div class=""><br class=""></div><div class="">however, with this patch…</div><div class=""><br class=""></div><div class=""><div style="margin: 0px; font-stretch: normal; font-size: 11px; line-height: normal; font-family: Menlo; background-color: rgb(255, 255, 255);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""># *** IR Dump After Greedy Register Allocator ***:</span></div></div><div style="margin: 0px; font-stretch: normal; font-size: 11px; line-height: normal; font-family: Menlo; background-color: rgb(255, 255, 255);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">%6:gpr32nosr = COPY $sr12</span></div><div style="margin: 0px; font-stretch: normal; font-size: 11px; line-height: normal; font-family: Menlo; background-color: rgb(255, 255, 255);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">%12.sub2:gpr32tup3 = /* some instruction */ </span>0, 0, %6, 0, 4294967312, 0, 0</div><div style="margin: 0px; font-stretch: normal; font-size: 11px; line-height: normal; font-family: Menlo; background-color: rgb(255, 255, 255);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""># *** IR Dump After Virtual Register Rewriter ***:</span></div><div style="margin: 0px; font-stretch: normal; font-size: 11px; line-height: normal; font-family: Menlo; background-color: rgb(255, 255, 255);" class=""><div style="margin: 0px; font-stretch: normal; line-height: normal;" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">renamable $r2 = COPY $sr12</span></div><div style="margin: 0px; font-stretch: normal; line-height: normal;" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">renamable $r2</span> = /* some instruction */ 0, 0, %6, 0, 4294967312, 0, 0</div><div style="margin: 0px; font-stretch: normal; line-height: normal;" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">[…]</span></div><div style="margin: 0px; font-stretch: normal; line-height: normal;" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""># *** IR Dump After Machine Copy Propagation Pass ***:</span></div><div style="margin: 0px; font-stretch: normal; line-height: normal;" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">renamable $r2 = /* some instruction */ 0, 0, $sr12, 0, 4294967312, 0, 0</span></div></div><div class=""><br class=""></div><div class="">in the second step the information that “%6” cannot be an SR is lost due to register allocation, and then copy propagation happily plows through and violates the constraint we set earlier.</div><div class=""><br class=""></div><div class="">this is the simplest example, but this entire patch makes me extremely nervous because we rely on register classes heavily in our backend and if the compiler is now free to violate our constraints, all bets are off.</div><div class=""><br class=""></div><div class="">—escha<br class=""><div class=""><div class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Feb 1, 2018, at 10:56 AM, Geoff Berry via Phabricator via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="">This revision was automatically updated to reflect the committed changes.<br class="">Closed by commit rL323991: [MachineCopyPropagation] Extend pass to do COPY source forwarding (authored by gberry, committed by ).<br class=""><br class="">Changed prior to commit:<br class=""> <a href="https://reviews.llvm.org/D41835?vs=131323&id=132429#toc" class="">https://reviews.llvm.org/D41835?vs=131323&id=132429#toc</a><br class=""><br class="">Repository:<br class=""> rL LLVM<br class=""><br class=""><a href="https://reviews.llvm.org/D41835" class="">https://reviews.llvm.org/D41835</a><br class=""><br class="">Files:<br class=""> llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp<br class=""> llvm/trunk/lib/CodeGen/TargetPassConfig.cpp<br class=""> llvm/trunk/test/CodeGen/AArch64/aarch64-fold-lslfast.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/copyprop.mir<br class=""> llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/flags-multiuse.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/ldst-opt.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/neg-imm.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/fix-vgpr-copies.mir<br class=""> llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/ret.ll<br class=""> llvm/trunk/test/CodeGen/ARM/atomic-op.ll<br class=""> llvm/trunk/test/CodeGen/ARM/intrinsics-overflow.ll<br class=""> llvm/trunk/test/CodeGen/ARM/select-imm.ll<br class=""> llvm/trunk/test/CodeGen/ARM/swifterror.ll<br class=""> llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll<br class=""> llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll<br class=""> llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll<br class=""> llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/fma-mutate.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/gpr-vsr-spill.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/opt-li-add-to-addi.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/tail-dup-layout.ll<br class=""> llvm/trunk/test/CodeGen/SPARC/32abi.ll<br class=""> llvm/trunk/test/CodeGen/SPARC/atomics.ll<br class=""> llvm/trunk/test/CodeGen/SystemZ/vec-sub-01.ll<br class=""> llvm/trunk/test/CodeGen/Thumb/pr35836.ll<br class=""> llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll<br class=""> llvm/trunk/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll<br class=""> llvm/trunk/test/CodeGen/X86/arg-copy-elide.ll<br class=""> llvm/trunk/test/CodeGen/X86/avx-load-store.ll<br class=""> llvm/trunk/test/CodeGen/X86/avx512-bugfix-25270.ll<br class=""> llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll<br class=""> llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll<br class=""> llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-fast-isel.ll<br class=""> llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll<br class=""> llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll<br class=""> llvm/trunk/test/CodeGen/X86/combine-fcopysign.ll<br class=""> llvm/trunk/test/CodeGen/X86/combine-shl.ll<br class=""> llvm/trunk/test/CodeGen/X86/complex-fastmath.ll<br class=""> llvm/trunk/test/CodeGen/X86/divide-by-constant.ll<br class=""> llvm/trunk/test/CodeGen/X86/fmaxnum.ll<br class=""> llvm/trunk/test/CodeGen/X86/fmf-flags.ll<br class=""> llvm/trunk/test/CodeGen/X86/fminnum.ll<br class=""> llvm/trunk/test/CodeGen/X86/fp128-i128.ll<br class=""> llvm/trunk/test/CodeGen/X86/h-registers-1.ll<br class=""> llvm/trunk/test/CodeGen/X86/haddsub-2.ll<br class=""> llvm/trunk/test/CodeGen/X86/haddsub-3.ll<br class=""> llvm/trunk/test/CodeGen/X86/haddsub-undef.ll<br class=""> llvm/trunk/test/CodeGen/X86/half.ll<br class=""> llvm/trunk/test/CodeGen/X86/horizontal-reduce-smax.ll<br class=""> llvm/trunk/test/CodeGen/X86/horizontal-reduce-smin.ll<br class=""> llvm/trunk/test/CodeGen/X86/horizontal-reduce-umax.ll<br class=""> llvm/trunk/test/CodeGen/X86/horizontal-reduce-umin.ll<br class=""> llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll<br class=""> llvm/trunk/test/CodeGen/X86/ipra-local-linkage.ll<br class=""> llvm/trunk/test/CodeGen/X86/localescape.ll<br class=""> llvm/trunk/test/CodeGen/X86/machine-cp.ll<br class=""> llvm/trunk/test/CodeGen/X86/mul-i1024.ll<br class=""> llvm/trunk/test/CodeGen/X86/mul-i256.ll<br class=""> llvm/trunk/test/CodeGen/X86/mul-i512.ll<br class=""> llvm/trunk/test/CodeGen/X86/mul128.ll<br class=""> llvm/trunk/test/CodeGen/X86/mulvi32.ll<br class=""> llvm/trunk/test/CodeGen/X86/pmul.ll<br class=""> llvm/trunk/test/CodeGen/X86/powi.ll<br class=""> llvm/trunk/test/CodeGen/X86/pr11334.ll<br class=""> llvm/trunk/test/CodeGen/X86/pr29112.ll<br class=""> llvm/trunk/test/CodeGen/X86/pr34080-2.ll<br class=""> llvm/trunk/test/CodeGen/X86/psubus.ll<br class=""> llvm/trunk/test/CodeGen/X86/retpoline-external.ll<br class=""> llvm/trunk/test/CodeGen/X86/retpoline.ll<br class=""> llvm/trunk/test/CodeGen/X86/sad.ll<br class=""> llvm/trunk/test/CodeGen/X86/safestack.ll<br class=""> llvm/trunk/test/CodeGen/X86/safestack_inline.ll<br class=""> llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll<br class=""> llvm/trunk/test/CodeGen/X86/select.ll<br class=""> llvm/trunk/test/CodeGen/X86/shrink-wrap-chkstk.ll<br class=""> llvm/trunk/test/CodeGen/X86/slow-pmulld.ll<br class=""> llvm/trunk/test/CodeGen/X86/sqrt-fastmath.ll<br class=""> llvm/trunk/test/CodeGen/X86/sse-scalar-fp-arith.ll<br class=""> llvm/trunk/test/CodeGen/X86/sse1.ll<br class=""> llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll<br class=""> llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll<br class=""> llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll<br class=""> llvm/trunk/test/CodeGen/X86/vec_fp_to_int.ll<br class=""> llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll<br class=""> llvm/trunk/test/CodeGen/X86/vec_minmax_sint.ll<br class=""> llvm/trunk/test/CodeGen/X86/vec_shift4.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-blend.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-idiv-sdiv-128.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-idiv-udiv-128.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-mul.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-rotate-128.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-sext.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-shift-lshr-128.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-shift-shl-128.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-trunc-math.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-trunc-packus.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-trunc-ssat.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-trunc-usat.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-zext.ll<br class=""> llvm/trunk/test/CodeGen/X86/vselect-minmax.ll<br class=""> llvm/trunk/test/CodeGen/X86/widen_conv-3.ll<br class=""> llvm/trunk/test/CodeGen/X86/widen_conv-4.ll<br class=""> llvm/trunk/test/CodeGen/X86/win64_frame.ll<br class=""> llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll<br class=""> llvm/trunk/test/CodeGen/X86/x86-shrink-wrap-unwind.ll<br class=""> llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll<br class=""> llvm/trunk/test/DebugInfo/COFF/fpo-shrink-wrap.ll<br class=""> llvm/trunk/test/DebugInfo/X86/spill-nospill.ll<br class=""><br class=""><span id="cid:FEC7C11B-26BC-45F7-A51E-AB9C7455EEF3"><D41835.132429.patch></span>_______________________________________________<br class="">llvm-commits mailing list<br class="">llvm-commits@lists.llvm.org<br class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits<br class=""></div></div></blockquote></div><br class=""></div></div></div></body></html>