<div dir="ltr">Hello Marek,<br><br>The test split-gep-and-gvn-addrspace-addressing-modes.ll failed on one of our builders:<br><br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/7641">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/7641</a><br><br>. . .<br>Failing Tests (4):<br> LLVM :: Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll<br> LLVM :: tools/llvm-cov/dir-with-filtering.test<br> LLVM :: tools/llvm-cov/hideUnexecutedSubviews.test<br> LLVM :: tools/llvm-cov/showLineExecutionCounts.cpp<br><br>The builder was already red and did not send notifications on the changes.<br>Please have a look?<br><br>Thanks<br><br>Galina<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jan 31, 2018 at 12:17 PM, Marek Olsak via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: mareko<br>
Date: Wed Jan 31 12:17:52 2018<br>
New Revision: 323907<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=323907&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=323907&view=rev</a><br>
Log:<br>
[SeparateConstOffsetFromGEP] Preserve metadata when splitting GEPs<br>
<br>
Summary:<br>
!amdgpu.uniform needs to be preserved for AMDGPU, otherwise bad things<br>
happen.<br>
<br>
Reviewers: arsenm, nhaehnle, jingyue, broune, majnemer, bjarke.roune, dblaikie<br>
<br>
Subscribers: wdng, tpr, llvm-commits<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D42744" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D42744</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Transforms/<wbr>Scalar/<wbr>SeparateConstOffsetFromGEP.cpp<br>
llvm/trunk/test/Transforms/<wbr>SeparateConstOffsetFromGEP/<wbr>AMDGPU/split-gep-and-gvn-<wbr>addrspace-addressing-modes.ll<br>
<br>
Modified: llvm/trunk/lib/Transforms/<wbr>Scalar/<wbr>SeparateConstOffsetFromGEP.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp?rev=323907&r1=323906&r2=323907&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>Transforms/Scalar/<wbr>SeparateConstOffsetFromGEP.<wbr>cpp?rev=323907&r1=323906&r2=<wbr>323907&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Transforms/<wbr>Scalar/<wbr>SeparateConstOffsetFromGEP.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/<wbr>Scalar/<wbr>SeparateConstOffsetFromGEP.cpp Wed Jan 31 12:17:52 2018<br>
@@ -1071,6 +1071,7 @@ bool SeparateConstOffsetFromGEP::<wbr>splitGE<br>
NewGEP = GetElementPtrInst::Create(GEP-<wbr>>getResultElementType(), NewGEP,<br>
ConstantInt::get(IntPtrTy, Index, true),<br>
GEP->getName(), GEP);<br>
+ NewGEP->copyMetadata(*GEP);<br>
// Inherit the inbounds attribute of the original GEP.<br>
cast<GetElementPtrInst>(<wbr>NewGEP)->setIsInBounds(<wbr>GEPWasInBounds);<br>
} else {<br>
@@ -1095,6 +1096,7 @@ bool SeparateConstOffsetFromGEP::<wbr>splitGE<br>
Type::getInt8Ty(GEP-><wbr>getContext()), NewGEP,<br>
ConstantInt::get(IntPtrTy, AccumulativeByteOffset, true), "uglygep",<br>
GEP);<br>
+ NewGEP->copyMetadata(*GEP);<br>
// Inherit the inbounds attribute of the original GEP.<br>
cast<GetElementPtrInst>(<wbr>NewGEP)->setIsInBounds(<wbr>GEPWasInBounds);<br>
if (GEP->getType() != I8PtrTy)<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>SeparateConstOffsetFromGEP/<wbr>AMDGPU/split-gep-and-gvn-<wbr>addrspace-addressing-modes.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll?rev=323907&r1=323906&r2=323907&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/<wbr>SeparateConstOffsetFromGEP/<wbr>AMDGPU/split-gep-and-gvn-<wbr>addrspace-addressing-modes.ll?<wbr>rev=323907&r1=323906&r2=<wbr>323907&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>SeparateConstOffsetFromGEP/<wbr>AMDGPU/split-gep-and-gvn-<wbr>addrspace-addressing-modes.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>SeparateConstOffsetFromGEP/<wbr>AMDGPU/split-gep-and-gvn-<wbr>addrspace-addressing-modes.ll Wed Jan 31 12:17:52 2018<br>
@@ -92,3 +92,48 @@ define amdgpu_kernel void @sum_of_lds_ar<br>
store float %tmp21, float addrspace(1)* %output, align 4<br>
ret void<br>
}<br>
+<br>
+; IR-LABEL: @keep_metadata(<br>
+; IR: getelementptr {{.*}} !amdgpu.uniform<br>
+; IR: getelementptr {{.*}} !amdgpu.uniform<br>
+; IR: getelementptr {{.*}} !amdgpu.uniform<br>
+define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @keep_metadata([0 x <4 x i32>] addrspace(6)* inreg noalias dereferenceable(<wbr>18446744073709551615), [0 x <8 x i32>] addrspace(6)* inreg noalias dereferenceable(<wbr>18446744073709551615), [0 x <4 x i32>] addrspace(6)* inreg noalias dereferenceable(<wbr>18446744073709551615), [0 x <8 x i32>] addrspace(6)* inreg noalias dereferenceable(<wbr>18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #5 {<br>
+main_body:<br>
+ %22 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %5) #8<br>
+ %23 = bitcast float %22 to i32<br>
+ %24 = shl i32 %23, 1<br>
+ %25 = getelementptr [0 x <8 x i32>], [0 x <8 x i32>] addrspace(6)* %1, i32 0, i32 %24, !amdgpu.uniform !0<br>
+ %26 = load <8 x i32>, <8 x i32> addrspace(6)* %25, align 32, !invariant.load !0<br>
+ %27 = shl i32 %23, 2<br>
+ %28 = or i32 %27, 3<br>
+ %29 = bitcast [0 x <8 x i32>] addrspace(6)* %1 to [0 x <4 x i32>] addrspace(6)*<br>
+ %30 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %29, i32 0, i32 %28, !amdgpu.uniform !0<br>
+ %31 = load <4 x i32>, <4 x i32> addrspace(6)* %30, align 16, !invariant.load !0<br>
+ %32 = call nsz <4 x float> @llvm.amdgcn.image.sample.<wbr>v4f32.v2f32.v8i32(<2 x float> zeroinitializer, <8 x i32> %26, <4 x i32> %31, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #8<br>
+ %33 = extractelement <4 x float> %32, i32 0<br>
+ %34 = extractelement <4 x float> %32, i32 1<br>
+ %35 = extractelement <4 x float> %32, i32 2<br>
+ %36 = extractelement <4 x float> %32, i32 3<br>
+ %37 = bitcast float %4 to i32<br>
+ %38 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %37, 4<br>
+ %39 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %33, 5<br>
+ %40 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %39, float %34, 6<br>
+ %41 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %40, float %35, 7<br>
+ %42 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %41, float %36, 8<br>
+ %43 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %42, float %20, 19<br>
+ ret <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %43<br>
+}<br>
+<br>
+; Function Attrs: nounwind readnone speculatable<br>
+declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #6<br>
+<br>
+; Function Attrs: nounwind readonly<br>
+declare <4 x float> @llvm.amdgcn.image.sample.<wbr>v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #7<br>
+<br>
+<br>
+!0 = !{}<br>
+<br>
+attributes #5 = { "InitialPSInputAddr"="45175" }<br>
+attributes #6 = { nounwind readnone speculatable }<br>
+attributes #7 = { nounwind readonly }<br>
+attributes #8 = { nounwind readnone }<br>
<br>
<br>
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</blockquote></div><br></div>