<div dir="ltr"><div>
Please do to revert it till the fix gets approved.<br>It is not good to keep the bot red for too long. This hides new problem which later hard to track down.<br><br>Thanks<br><br></div>Galina<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jan 31, 2018 at 10:46 AM, <span dir="ltr"><<a href="mailto:gberry@codeaurora.org" target="_blank">gberry@codeaurora.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div link="blue" vlink="purple" lang="EN-US"><div class="m_7287936843852574477WordSection1"><p class="MsoNormal">Fix up for review: <a href="https://reviews.llvm.org/D42749" target="_blank">https://reviews.llvm.org/<wbr>D42749</a><u></u><u></u></p><span class=""><p class="MsoNormal"><u></u> <u></u></p><p class="MsoNormal">-- <u></u><u></u></p><p class="MsoNormal">Geoff Berry<u></u><u></u></p><p class="MsoNormal">Employee of Qualcomm Datacenter Technologies, Inc.<u></u><u></u></p><p class="MsoNormal"> Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.<u></u><u></u></p><p class="MsoNormal"><u></u> <u></u></p></span><p class="MsoNormal"><span class=""><b>From:</b> Galina Kistanova [mailto:<a href="mailto:gkistanova@gmail.com" target="_blank">gkistanova@gmail.com</a>] <br><b>Sent:</b> Tuesday, January 30, 2018 6:00 PM<br><b>To:</b> Geoff Berry <<a href="mailto:gberry@codeaurora.org" target="_blank">gberry@codeaurora.org</a>><br><b>Cc:</b> Artur Pilipenko via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>><br></span><b>Subject:</b> Re: [llvm] r323676 - [MachineVerifier] Add check that renamable operands aren't reserved registers.<u></u><u></u></p><div><div class="h5"><p class="MsoNormal"><u></u> <u></u></p><div><p class="MsoNormal">Hello Geoff,<br><br>This commit broke the test CodeGen/AArch64/machine-<wbr>outliner.mir on one of our builders:<br>r323676<br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/7621" target="_blank">http://lab.llvm.org:8011/<wbr>builders/llvm-clang-x86_64-<wbr>expensive-checks-win/builds/<wbr>7621</a><br><br>. . .<br>Failing Tests (3):<br> LLVM :: CodeGen/AArch64/machine-<wbr>outliner.mir<br> LLVM :: CodeGen/ARM/pr25838.ll<br> LLVM :: DebugInfo/X86/string-offsets-<wbr>multiple-cus.ll<br><br>Previous revision:<br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/7624" target="_blank">http://lab.llvm.org:8011/<wbr>builders/llvm-clang-x86_64-<wbr>expensive-checks-win/builds/<wbr>7624</a><br><br>Please have a look?<br><br>Thanks<br><br>Galina<u></u><u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p><div><p class="MsoNormal">On Mon, Jan 29, 2018 at 10:57 AM, Geoff Berry via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<u></u><u></u></p><blockquote style="border:none;border-left:solid #cccccc 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in"><p class="MsoNormal">Author: gberry<br>Date: Mon Jan 29 10:57:07 2018<br>New Revision: 323676<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=323676&view=rev" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=323676&view=rev</a><br>Log:<br>[MachineVerifier] Add check that renamable operands aren't reserved registers.<br><br>Summary:<br><br>Reviewers: qcolombet, MatzeB<br><br>Subscribers: arsenm, sdardis, nhaehnle, mcrosier, llvm-commits<br><br>Differential Revision: <a href="https://reviews.llvm.org/D42449" target="_blank">https://reviews.llvm.org/<wbr>D42449</a><br><br>Modified:<br> llvm/trunk/lib/CodeGen/<wbr>MachineVerifier.cpp<br><br>Modified: llvm/trunk/lib/CodeGen/<wbr>MachineVerifier.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=323676&r1=323675&r2=323676&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/MachineVerifier.cpp?<wbr>rev=323676&r1=323675&r2=<wbr>323676&view=diff</a><br>==============================<wbr>==============================<wbr>==================<br>--- llvm/trunk/lib/CodeGen/<wbr>MachineVerifier.cpp (original)<br>+++ llvm/trunk/lib/CodeGen/<wbr>MachineVerifier.cpp Mon Jan 29 10:57:07 2018<br>@@ -1101,12 +1101,14 @@ MachineVerifier::<wbr>visitMachineOperand(con<br> }<br> }<br> }<br>- if (MO->isRenamable() &&<br>- ((MO->isDef() && MI->hasExtraDefRegAllocReq()) ||<br>- (MO->isUse() && MI->hasExtraSrcRegAllocReq()))<wbr>) {<br>- report("Illegal isRenamable setting for opcode with extra regalloc "<br>- "requirements",<br>- MO, MONum);<br>+ if (MO->isRenamable()) {<br>+ if ((MO->isDef() && MI->hasExtraDefRegAllocReq()) ||<br>+ (MO->isUse() && MI->hasExtraSrcRegAllocReq()))<br>+ report("Illegal isRenamable setting for opcode with extra regalloc "<br>+ "requirements",<br>+ MO, MONum);<br>+ if (MRI->isReserved(Reg))<br>+ report("isRenamable set on reserved register", MO, MONum);<br> return;<br> }<br> } else {<br><br><br>______________________________<wbr>_________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" target="_blank">http://lists.llvm.org/cgi-bin/<wbr>mailman/listinfo/llvm-commits</a><u></u><u></u></p></blockquote></div><p class="MsoNormal"><u></u> <u></u></p></div></div></div></div></div></blockquote></div><br></div>