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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal>Hi Galina, <o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Sorry about that. I’ll take a look shortly<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>-- <o:p></o:p></p><p class=MsoNormal>Geoff Berry<o:p></o:p></p><p class=MsoNormal>Employee of Qualcomm Datacenter Technologies, Inc.<o:p></o:p></p><p class=MsoNormal> Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><b>From:</b> Galina Kistanova [mailto:gkistanova@gmail.com] <br><b>Sent:</b> Tuesday, January 30, 2018 6:00 PM<br><b>To:</b> Geoff Berry <gberry@codeaurora.org><br><b>Cc:</b> Artur Pilipenko via llvm-commits <llvm-commits@lists.llvm.org><br><b>Subject:</b> Re: [llvm] r323676 - [MachineVerifier] Add check that renamable operands aren't reserved registers.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>Hello Geoff,<br><br>This commit broke the test CodeGen/AArch64/machine-outliner.mir on one of our builders:<br>r323676<br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/7621">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/7621</a><br><br>. . .<br>Failing Tests (3):<br> LLVM :: CodeGen/AArch64/machine-outliner.mir<br> LLVM :: CodeGen/ARM/pr25838.ll<br> LLVM :: DebugInfo/X86/string-offsets-multiple-cus.ll<br><br>Previous revision:<br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/7624">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/7624</a><br><br>Please have a look?<br><br>Thanks<br><br>Galina<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>On Mon, Jan 29, 2018 at 10:57 AM, Geoff Berry via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<o:p></o:p></p><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in'><p class=MsoNormal>Author: gberry<br>Date: Mon Jan 29 10:57:07 2018<br>New Revision: 323676<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=323676&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=323676&view=rev</a><br>Log:<br>[MachineVerifier] Add check that renamable operands aren't reserved registers.<br><br>Summary:<br><br>Reviewers: qcolombet, MatzeB<br><br>Subscribers: arsenm, sdardis, nhaehnle, mcrosier, llvm-commits<br><br>Differential Revision: <a href="https://reviews.llvm.org/D42449" target="_blank">https://reviews.llvm.org/D42449</a><br><br>Modified:<br> llvm/trunk/lib/CodeGen/MachineVerifier.cpp<br><br>Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=323676&r1=323675&r2=323676&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=323676&r1=323675&r2=323676&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)<br>+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Mon Jan 29 10:57:07 2018<br>@@ -1101,12 +1101,14 @@ MachineVerifier::visitMachineOperand(con<br> }<br> }<br> }<br>- if (MO->isRenamable() &&<br>- ((MO->isDef() && MI->hasExtraDefRegAllocReq()) ||<br>- (MO->isUse() && MI->hasExtraSrcRegAllocReq()))) {<br>- report("Illegal isRenamable setting for opcode with extra regalloc "<br>- "requirements",<br>- MO, MONum);<br>+ if (MO->isRenamable()) {<br>+ if ((MO->isDef() && MI->hasExtraDefRegAllocReq()) ||<br>+ (MO->isUse() && MI->hasExtraSrcRegAllocReq()))<br>+ report("Illegal isRenamable setting for opcode with extra regalloc "<br>+ "requirements",<br>+ MO, MONum);<br>+ if (MRI->isReserved(Reg))<br>+ report("isRenamable set on reserved register", MO, MONum);<br> return;<br> }<br> } else {<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a><br><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><o:p></o:p></p></blockquote></div><p class=MsoNormal><o:p> </o:p></p></div></div></body></html>