<div dir="ltr">Merged to 6.0 in r323772.</div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jan 30, 2018 at 12:19 AM, Marek Olsak via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: mareko<br>
Date: Mon Jan 29 15:19:10 2018<br>
New Revision: 323706<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=323706&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=323706&view=rev</a><br>
Log:<br>
AMDGPU: Allow a SGPR for the conditional KILL operand<br>
<br>
Patch by: Bas Nieuwenhuizen<br>
<br>
Just use the _e64 variant if needed. This should be possible as per<br>
<br>
def : Pat <<br>
(int_amdgcn_kill (i1 (setcc f32:$src, InlineFPImm<f32>:$imm, cond:$cond))),<br>
(SI_KILL_F32_COND_IMM_PSEUDO $src, (bitcast_fpimm_to_i32 $imm), (cond_as_i32imm $cond))<br>
> ;<br>
<br>
I don't think we can get an immediate for the other operand for which we<br>
need the second 32-bit word.<br>
<br>
<a href="https://reviews.llvm.org/D42302" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D42302</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AMDGPU/<wbr>SIInsertSkips.cpp<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.kill.ll<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/<wbr>SIInsertSkips.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInsertSkips.cpp?rev=323706&r1=323705&r2=323706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AMDGPU/SIInsertSkips.cpp?rev=<wbr>323706&r1=323705&r2=323706&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AMDGPU/<wbr>SIInsertSkips.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/<wbr>SIInsertSkips.cpp Mon Jan 29 15:19:10 2018<br>
@@ -210,65 +210,73 @@ void SIInsertSkips::kill(<wbr>MachineInstr &M<br>
switch (MI.getOperand(2).getImm()) {<br>
case ISD::SETOEQ:<br>
case ISD::SETEQ:<br>
- Opcode = AMDGPU::V_CMPX_EQ_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_EQ_F32_e64;<br>
break;<br>
case ISD::SETOGT:<br>
case ISD::SETGT:<br>
- Opcode = AMDGPU::V_CMPX_LT_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_LT_F32_e64;<br>
break;<br>
case ISD::SETOGE:<br>
case ISD::SETGE:<br>
- Opcode = AMDGPU::V_CMPX_LE_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_LE_F32_e64;<br>
break;<br>
case ISD::SETOLT:<br>
case ISD::SETLT:<br>
- Opcode = AMDGPU::V_CMPX_GT_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_GT_F32_e64;<br>
break;<br>
case ISD::SETOLE:<br>
case ISD::SETLE:<br>
- Opcode = AMDGPU::V_CMPX_GE_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_GE_F32_e64;<br>
break;<br>
case ISD::SETONE:<br>
case ISD::SETNE:<br>
- Opcode = AMDGPU::V_CMPX_LG_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_LG_F32_e64;<br>
break;<br>
case ISD::SETO:<br>
- Opcode = AMDGPU::V_CMPX_O_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_O_F32_e64;<br>
break;<br>
case ISD::SETUO:<br>
- Opcode = AMDGPU::V_CMPX_U_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_U_F32_e64;<br>
break;<br>
case ISD::SETUEQ:<br>
- Opcode = AMDGPU::V_CMPX_NLG_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_NLG_F32_e64;<br>
break;<br>
case ISD::SETUGT:<br>
- Opcode = AMDGPU::V_CMPX_NGE_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_NGE_F32_e64;<br>
break;<br>
case ISD::SETUGE:<br>
- Opcode = AMDGPU::V_CMPX_NGT_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_NGT_F32_e64;<br>
break;<br>
case ISD::SETULT:<br>
- Opcode = AMDGPU::V_CMPX_NLE_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_NLE_F32_e64;<br>
break;<br>
case ISD::SETULE:<br>
- Opcode = AMDGPU::V_CMPX_NLT_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_NLT_F32_e64;<br>
break;<br>
case ISD::SETUNE:<br>
- Opcode = AMDGPU::V_CMPX_NEQ_F32_e32;<br>
+ Opcode = AMDGPU::V_CMPX_NEQ_F32_e64;<br>
break;<br>
default:<br>
llvm_unreachable("invalid ISD:SET cond code");<br>
}<br>
<br>
- // TODO: Allow this:<br>
- if (!MI.getOperand(0).isReg() ||<br>
- !TRI->isVGPR(MBB.getParent()-><wbr>getRegInfo(),<br>
- MI.getOperand(0).getReg()))<br>
- llvm_unreachable("SI_KILL operand should be a VGPR");<br>
+ assert(MI.getOperand(0).isReg(<wbr>));<br>
<br>
- BuildMI(MBB, &MI, DL, TII->get(Opcode))<br>
- .add(MI.getOperand(1))<br>
- .add(MI.getOperand(0));<br>
+ if (TRI->isVGPR(MBB.getParent()-><wbr>getRegInfo(),<br>
+ MI.getOperand(0).getReg())) {<br>
+ Opcode = AMDGPU::getVOPe32(Opcode);<br>
+ BuildMI(MBB, &MI, DL, TII->get(Opcode))<br>
+ .add(MI.getOperand(1))<br>
+ .add(MI.getOperand(0));<br>
+ } else {<br>
+ BuildMI(MBB, &MI, DL, TII->get(Opcode))<br>
+ .addReg(AMDGPU::VCC, RegState::Define)<br>
+ .addImm(0) // src0 modifiers<br>
+ .add(MI.getOperand(1))<br>
+ .addImm(0) // src1 modifiers<br>
+ .add(MI.getOperand(0))<br>
+ .addImm(0); // omod<br>
+ }<br>
break;<br>
}<br>
case AMDGPU::SI_KILL_I1_TERMINATOR: {<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.kill.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll?rev=323706&r1=323705&r2=323706&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/llvm.amdgcn.<wbr>kill.ll?rev=323706&r1=323705&<wbr>r2=323706&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.kill.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.kill.ll Mon Jan 29 15:19:10 2018<br>
@@ -234,6 +234,23 @@ define amdgpu_ps void @wqm(float %a) {<br>
ret void<br>
}<br>
<br>
+; This checks that we use the 64-bit encoding when the operand is a SGPR.<br>
+; SI-LABEL: {{^}}test_sgpr:<br>
+; SI: v_cmpx_ge_f32_e64<br>
+define amdgpu_ps void @test_sgpr(float inreg %a) #0 {<br>
+ %c = fcmp ole float %a, 1.000000e+00<br>
+ call void @llvm.amdgcn.kill(i1 %c) #1<br>
+ ret void<br>
+}<br>
+<br>
+; SI-LABEL: {{^}}test_non_inline_imm_sgpr:<br>
+; SI-NOT: v_cmpx_ge_f32_e64<br>
+define amdgpu_ps void @test_non_inline_imm_sgpr(<wbr>float inreg %a) #0 {<br>
+ %c = fcmp ole float %a, 1.500000e+00<br>
+ call void @llvm.amdgcn.kill(i1 %c) #1<br>
+ ret void<br>
+}<br>
+<br>
declare void @llvm.amdgcn.kill(i1) #0<br>
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0<br>
declare i1 @llvm.amdgcn.wqm.vote(i1)<br>
<br>
<br>
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</blockquote></div><br></div>