<div dir="ltr">Merged in r323746.</div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jan 30, 2018 at 12:47 AM, Quentin Colombet <span dir="ltr"><<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Hans,<br>
<br>
Could we pull that commit in the release please?<br>
<br>
With GISel, this is a pattern that can come up more often.<br>
<br>
Cheers,<br>
-Quentin<br>
<div class="HOEnZb"><div class="h5"><br>
> On Jan 29, 2018, at 3:42 PM, Quentin Colombet via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br>
><br>
> Author: qcolombet<br>
> Date: Mon Jan 29 15:42:37 2018<br>
> New Revision: 323710<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=323710&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=323710&view=rev</a><br>
> Log:<br>
> [RAFast] Don't dereference MBB::end<br>
><br>
> When RAFast sees liveins in on a basic block, it uses that information<br>
> to initialize the availability of the registers. The called<br>
> method uses an instruction as one of its argument and in the liveins<br>
> case, RAFast was dereferencing MBB::begin which can be MBB::end for<br>
> empty basic block.<br>
><br>
> Change the API of definePhysReg to use MachineBasicBlock::iterator<br>
> instead of MachineInstr so that we don't dereference an<br>
> invalid iterator while making the call.<br>
><br>
> rdar://problem/36952401<br>
><br>
> Added:<br>
>    llvm/trunk/test/CodeGen/<wbr>AArch64/fast-regalloc-empty-<wbr>bb-with-liveins.mir<br>
> Modified:<br>
>    llvm/trunk/lib/CodeGen/<wbr>RegAllocFast.cpp<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/<wbr>RegAllocFast.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=323710&r1=323709&r2=323710&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/RegAllocFast.cpp?rev=<wbr>323710&r1=323709&r2=323710&<wbr>view=diff</a><br>
> ==============================<wbr>==============================<wbr>==================<br>
> --- llvm/trunk/lib/CodeGen/<wbr>RegAllocFast.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/<wbr>RegAllocFast.cpp Mon Jan 29 15:42:37 2018<br>
> @@ -193,9 +193,10 @@ namespace {<br>
>     void spillVirtReg(<wbr>MachineBasicBlock::iterator MI, unsigned VirtReg);<br>
><br>
>     void usePhysReg(MachineOperand &MO);<br>
> -    void definePhysReg(MachineInstr &MI, MCPhysReg PhysReg, RegState NewState);<br>
> +    void definePhysReg(<wbr>MachineBasicBlock::iterator MI, MCPhysReg PhysReg,<br>
> +                       RegState NewState);<br>
>     unsigned calcSpillCost(MCPhysReg PhysReg) const;<br>
> -    void assignVirtToPhysReg(LiveReg&, MCPhysReg PhysReg);<br>
> +    void assignVirtToPhysReg(LiveReg &, MCPhysReg PhysReg);<br>
><br>
>     LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {<br>
>       return LiveVirtRegs.find(<wbr>TargetRegisterInfo::<wbr>virtReg2Index(VirtReg));<br>
> @@ -434,8 +435,8 @@ void RegAllocFast::usePhysReg(<wbr>MachineOpe<br>
> /// Mark PhysReg as reserved or free after spilling any virtregs. This is very<br>
> /// similar to defineVirtReg except the physreg is reserved instead of<br>
> /// allocated.<br>
> -void RegAllocFast::definePhysReg(<wbr>MachineInstr &MI, MCPhysReg PhysReg,<br>
> -                                 RegState NewState) {<br>
> +void RegAllocFast::definePhysReg(<wbr>MachineBasicBlock::iterator MI,<br>
> +                                 MCPhysReg PhysReg, RegState NewState) {<br>
>   markRegUsedInInstr(PhysReg);<br>
>   switch (unsigned VirtReg = PhysRegState[PhysReg]) {<br>
>   case regDisabled:<br>
> @@ -857,7 +858,7 @@ void RegAllocFast::<wbr>allocateBasicBlock(Ma<br>
>   // Add live-in registers as live.<br>
>   for (const MachineBasicBlock::<wbr>RegisterMaskPair LI : MBB.liveins())<br>
>     if (MRI->isAllocatable(LI.<wbr>PhysReg))<br>
> -      definePhysReg(*MII, LI.PhysReg, regReserved);<br>
> +      definePhysReg(MII, LI.PhysReg, regReserved);<br>
><br>
>   VirtDead.clear();<br>
>   Coalesced.clear();<br>
><br>
> Added: llvm/trunk/test/CodeGen/<wbr>AArch64/fast-regalloc-empty-<wbr>bb-with-liveins.mir<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir?rev=323710&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/fast-regalloc-<wbr>empty-bb-with-liveins.mir?rev=<wbr>323710&view=auto</a><br>
> ==============================<wbr>==============================<wbr>==================<br>
> --- llvm/trunk/test/CodeGen/<wbr>AArch64/fast-regalloc-empty-<wbr>bb-with-liveins.mir (added)<br>
> +++ llvm/trunk/test/CodeGen/<wbr>AArch64/fast-regalloc-empty-<wbr>bb-with-liveins.mir Mon Jan 29 15:42:37 2018<br>
> @@ -0,0 +1,26 @@<br>
> +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.<wbr>py<br>
> +# RUN: llc -mtriple aarch64-apple-ios -run-pass regallocfast -o - %s | FileCheck %s<br>
> +# This test used to crash the fast register alloc.<br>
> +# Basically, when a basic block has liveins, the fast regalloc<br>
> +# was deferencing the begin iterator of this block. However,<br>
> +# when this block is empty and it will just crashed!<br>
> +---<br>
> +name:            crashing<br>
> +tracksRegLiveness: true<br>
> +body:             |<br>
> +  ; CHECK-LABEL: name: crashing<br>
> +  ; CHECK: bb.0:<br>
> +  ; CHECK:   successors: %bb.1(0x80000000)<br>
> +  ; CHECK:   liveins: %x0, %x1<br>
> +  ; CHECK: bb.1:<br>
> +  ; CHECK:   renamable %w0 = MOVi32imm -1<br>
> +  ; CHECK:   RET_ReallyLR implicit killed %w0<br>
> +  bb.1:<br>
> +    liveins: %x0, %x1<br>
> +<br>
> +  bb.2:<br>
> +    %0:gpr32 = MOVi32imm -1<br>
> +    %w0 = COPY %0<br>
> +    RET_ReallyLR implicit %w0<br>
> +<br>
> +...<br>
><br>
><br>
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</div></div></blockquote></div><br></div>