<div dir="ltr">It sounds like this was reverted in trunk at r323355 due to PR36015. I've also merged the revert to the release branch.<div><br></div><div>Please let me know if there's a new fix that I should merge.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jan 17, 2018 at 5:35 PM, Hans Wennborg <span dir="ltr"><<a href="mailto:hans@chromium.org" target="_blank">hans@chromium.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Merged to 6.0 in r322686 along with the follow-ups.<br>
<div class="HOEnZb"><div class="h5"><br>
On Wed, Jan 3, 2018 at 7:45 PM, Matt Arsenault via llvm-commits<br>
<<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br>
> Author: arsenm<br>
> Date: Wed Jan 3 10:45:37 2018<br>
> New Revision: 321751<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=321751&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=321751&view=rev</a><br>
> Log:<br>
> StructurizeCFG: Fix broken backedge detection<br>
><br>
> The work order was changed in r228186 from SCC order<br>
> to RPO with an arbitrary sorting function. The sorting<br>
> function attempted to move inner loop nodes earlier. This<br>
> was was apparently relying on an assumption that every block<br>
> in a given loop / the same loop depth would be seen before<br>
> visiting another loop. In the broken testcase, a block<br>
> outside of the loop was encountered before moving onto<br>
> another block in the same loop. The testcase would then<br>
> structurize such that one blocks unconditional successor<br>
> could never be reached.<br>
><br>
> Revert to plain RPO for the analysis phase. This fixes<br>
> detecting edges as backedges that aren't really.<br>
><br>
> The processing phase does use another visited set, and<br>
> I'm unclear on whether the order there is as important.<br>
> An arbitrary order doesn't work, and triggers some infinite<br>
> loops. The reversed RPO list seems to work and is closer<br>
> to the order that was used before, minus the arbitary<br>
> custom sorting.<br>
><br>
> A few of the changed tests now produce smaller code,<br>
> and a few are slightly worse looking.<br>
><br>
> Added:<br>
> llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/<br>
> llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/<wbr>backedge-id-bug.ll<br>
> llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/lit.<wbr>local.cfg<br>
> Modified:<br>
> llvm/trunk/lib/Transforms/<wbr>Scalar/StructurizeCFG.cpp<br>
> llvm/trunk/test/CodeGen/<wbr>AMDGPU/multilevel-break.ll<br>
> llvm/trunk/test/CodeGen/<wbr>AMDGPU/nested-loop-conditions.<wbr>ll<br>
> llvm/trunk/test/Transforms/<wbr>StructurizeCFG/nested-loop-<wbr>order.ll<br>
><br>
> Modified: llvm/trunk/lib/Transforms/<wbr>Scalar/StructurizeCFG.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/StructurizeCFG.cpp?rev=321751&r1=321750&r2=321751&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>Transforms/Scalar/<wbr>StructurizeCFG.cpp?rev=321751&<wbr>r1=321750&r2=321751&view=diff</a><br>
> ==============================<wbr>==============================<wbr>==================<br>
> --- llvm/trunk/lib/Transforms/<wbr>Scalar/StructurizeCFG.cpp (original)<br>
> +++ llvm/trunk/lib/Transforms/<wbr>Scalar/StructurizeCFG.cpp Wed Jan 3 10:45:37 2018<br>
> @@ -14,7 +14,6 @@<br>
> #include "llvm/ADT/SmallPtrSet.h"<br>
> #include "llvm/ADT/SmallVector.h"<br>
> #include "llvm/Analysis/<wbr>DivergenceAnalysis.h"<br>
> -#include "llvm/Analysis/LoopInfo.h"<br>
> #include "llvm/Analysis/RegionInfo.h"<br>
> #include "llvm/Analysis/RegionIterator.<wbr>h"<br>
> #include "llvm/Analysis/RegionPass.h"<br>
> @@ -177,9 +176,8 @@ class StructurizeCFG : public RegionPass<br>
> Region *ParentRegion;<br>
><br>
> DominatorTree *DT;<br>
> - LoopInfo *LI;<br>
><br>
> - SmallVector<RegionNode *, 8> Order;<br>
> + std::deque<RegionNode *> Order;<br>
> BBSet Visited;<br>
><br>
> BBPhiMap DeletedPhis;<br>
> @@ -204,7 +202,7 @@ class StructurizeCFG : public RegionPass<br>
><br>
> void gatherPredicates(RegionNode *N);<br>
><br>
> - void collectInfos();<br>
> + void analyzeNode(RegionNode *N);<br>
><br>
> void insertConditions(bool Loops);<br>
><br>
> @@ -258,7 +256,6 @@ public:<br>
> AU.addRequired<<wbr>DivergenceAnalysis>();<br>
> AU.addRequiredID(<wbr>LowerSwitchID);<br>
> AU.addRequired<<wbr>DominatorTreeWrapperPass>();<br>
> - AU.addRequired<<wbr>LoopInfoWrapperPass>();<br>
><br>
> AU.addPreserved<<wbr>DominatorTreeWrapperPass>();<br>
> RegionPass::getAnalysisUsage(<wbr>AU);<br>
> @@ -292,55 +289,17 @@ bool StructurizeCFG::<wbr>doInitialization(Re<br>
><br>
> /// \brief Build up the general order of nodes<br>
> void StructurizeCFG::orderNodes() {<br>
> - ReversePostOrderTraversal<<wbr>Region*> RPOT(ParentRegion);<br>
> - SmallDenseMap<Loop*, unsigned, 8> LoopBlocks;<br>
> -<br>
> - // The reverse post-order traversal of the list gives us an ordering close<br>
> - // to what we want. The only problem with it is that sometimes backedges<br>
> - // for outer loops will be visited before backedges for inner loops.<br>
> - for (RegionNode *RN : RPOT) {<br>
> - BasicBlock *BB = RN->getEntry();<br>
> - Loop *Loop = LI->getLoopFor(BB);<br>
> - ++LoopBlocks[Loop];<br>
> - }<br>
> -<br>
> - unsigned CurrentLoopDepth = 0;<br>
> - Loop *CurrentLoop = nullptr;<br>
> - for (auto I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {<br>
> - BasicBlock *BB = (*I)->getEntry();<br>
> - unsigned LoopDepth = LI->getLoopDepth(BB);<br>
> -<br>
> - if (is_contained(Order, *I))<br>
> - continue;<br>
> -<br>
> - if (LoopDepth < CurrentLoopDepth) {<br>
> - // Make sure we have visited all blocks in this loop before moving back to<br>
> - // the outer loop.<br>
> -<br>
> - auto LoopI = I;<br>
> - while (unsigned &BlockCount = LoopBlocks[CurrentLoop]) {<br>
> - LoopI++;<br>
> - BasicBlock *LoopBB = (*LoopI)->getEntry();<br>
> - if (LI->getLoopFor(LoopBB) == CurrentLoop) {<br>
> - --BlockCount;<br>
> - Order.push_back(*LoopI);<br>
> - }<br>
> - }<br>
> - }<br>
> -<br>
> - CurrentLoop = LI->getLoopFor(BB);<br>
> - if (CurrentLoop)<br>
> - LoopBlocks[CurrentLoop]--;<br>
> -<br>
> - CurrentLoopDepth = LoopDepth;<br>
> - Order.push_back(*I);<br>
> + assert(Visited.empty());<br>
> + assert(Predicates.empty());<br>
> + assert(Loops.empty());<br>
> + assert(LoopPreds.empty());<br>
> +<br>
> + // This must be RPO order for the back edge detection to work<br>
> + for (RegionNode *RN : ReversePostOrderTraversal<<wbr>Region*>(ParentRegion)) {<br>
> + // FIXME: Is there a better order to use for structurization?<br>
> + Order.push_back(RN);<br>
> + analyzeNode(RN);<br>
> }<br>
> -<br>
> - // This pass originally used a post-order traversal and then operated on<br>
> - // the list in reverse. Now that we are using a reverse post-order traversal<br>
> - // rather than re-working the whole pass to operate on the list in order,<br>
> - // we just reverse the list and continue to operate on it in reverse.<br>
> - std::reverse(Order.begin(), Order.end());<br>
> }<br>
><br>
> /// \brief Determine the end of the loops<br>
> @@ -466,32 +425,19 @@ void StructurizeCFG::<wbr>gatherPredicates(Re<br>
> }<br>
><br>
> /// \brief Collect various loop and predicate infos<br>
> -void StructurizeCFG::collectInfos() {<br>
> - // Reset predicate<br>
> - Predicates.clear();<br>
> -<br>
> - // and loop infos<br>
> - Loops.clear();<br>
> - LoopPreds.clear();<br>
> -<br>
> - // Reset the visited nodes<br>
> - Visited.clear();<br>
> +void StructurizeCFG::analyzeNode(<wbr>RegionNode *RN) {<br>
> + DEBUG(dbgs() << "Visiting: "<br>
> + << (RN->isSubRegion() ? "SubRegion with entry: " : "")<br>
> + << RN->getEntry()->getName() << '\n');<br>
><br>
> - for (RegionNode *RN : reverse(Order)) {<br>
> - DEBUG(dbgs() << "Visiting: "<br>
> - << (RN->isSubRegion() ? "SubRegion with entry: " : "")<br>
> - << RN->getEntry()->getName() << " Loop Depth: "<br>
> - << LI->getLoopDepth(RN->getEntry(<wbr>)) << "\n");<br>
> + // Analyze all the conditions leading to a node<br>
> + gatherPredicates(RN);<br>
><br>
> - // Analyze all the conditions leading to a node<br>
> - gatherPredicates(RN);<br>
> + // Remember that we've seen this node<br>
> + Visited.insert(RN->getEntry())<wbr>;<br>
><br>
> - // Remember that we've seen this node<br>
> - Visited.insert(RN->getEntry())<wbr>;<br>
> -<br>
> - // Find the last back edges<br>
> - analyzeLoops(RN);<br>
> - }<br>
> + // Find the last back edges<br>
> + analyzeLoops(RN);<br>
> }<br>
><br>
> /// \brief Insert the missing branch conditions<br>
> @@ -664,7 +610,7 @@ void StructurizeCFG::changeExit(<wbr>RegionNo<br>
> BasicBlock *StructurizeCFG::getNextFlow(<wbr>BasicBlock *Dominator) {<br>
> LLVMContext &Context = Func->getContext();<br>
> BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() :<br>
> - Order.back()->getEntry();<br>
> + Order.front()->getEntry();<br>
> BasicBlock *Flow = BasicBlock::Create(Context, FlowBlockName,<br>
> Func, Insert);<br>
> DT->addNewBlock(Flow, Dominator);<br>
> @@ -744,7 +690,8 @@ bool StructurizeCFG::<wbr>isPredictableTrue(R<br>
> /// Take one node from the order vector and wire it up<br>
> void StructurizeCFG::wireFlow(bool ExitUseAllowed,<br>
> BasicBlock *LoopEnd) {<br>
> - RegionNode *Node = Order.pop_back_val();<br>
> + RegionNode *Node = Order.front();<br>
> + Order.pop_front();<br>
> Visited.insert(Node->getEntry(<wbr>));<br>
><br>
> if (isPredictableTrue(Node)) {<br>
> @@ -768,7 +715,7 @@ void StructurizeCFG::wireFlow(bool ExitU<br>
><br>
> PrevNode = Node;<br>
> while (!Order.empty() && !Visited.count(LoopEnd) &&<br>
> - dominatesPredicates(Entry, Order.back())) {<br>
> + dominatesPredicates(Entry, Order.front())) {<br>
> handleLoops(false, LoopEnd);<br>
> }<br>
><br>
> @@ -779,7 +726,7 @@ void StructurizeCFG::wireFlow(bool ExitU<br>
><br>
> void StructurizeCFG::handleLoops(<wbr>bool ExitUseAllowed,<br>
> BasicBlock *LoopEnd) {<br>
> - RegionNode *Node = Order.back();<br>
> + RegionNode *Node = Order.front();<br>
> BasicBlock *LoopStart = Node->getEntry();<br>
><br>
> if (!Loops.count(LoopStart)) {<br>
> @@ -924,10 +871,9 @@ bool StructurizeCFG::runOnRegion(<wbr>Region<br>
> ParentRegion = R;<br>
><br>
> DT = &getAnalysis<<wbr>DominatorTreeWrapperPass>().<wbr>getDomTree();<br>
> - LI = &getAnalysis<<wbr>LoopInfoWrapperPass>().<wbr>getLoopInfo();<br>
><br>
> orderNodes();<br>
> - collectInfos();<br>
> +<br>
> createFlow();<br>
> insertConditions(false);<br>
> insertConditions(true);<br>
><br>
> Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/multilevel-break.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll?rev=321751&r1=321750&r2=321751&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/multilevel-<wbr>break.ll?rev=321751&r1=321750&<wbr>r2=321751&view=diff</a><br>
> ==============================<wbr>==============================<wbr>==================<br>
> --- llvm/trunk/test/CodeGen/<wbr>AMDGPU/multilevel-break.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/multilevel-break.ll Wed Jan 3 10:45:37 2018<br>
> @@ -66,9 +66,10 @@ ENDIF:<br>
><br>
> ; OPT-LABEL: define amdgpu_kernel void @multi_if_break_loop(<br>
> ; OPT: llvm.amdgcn.break<br>
> -; OPT: llvm.amdgcn.loop<br>
> +; OPT: llvm.amdgcn.break<br>
> ; OPT: llvm.amdgcn.if.break<br>
> ; OPT: llvm.amdgcn.if.break<br>
> +; OPT: llvm.amdgcn.loop<br>
> ; OPT: <a href="http://llvm.amdgcn.end.cf" rel="noreferrer" target="_blank">llvm.amdgcn.end.cf</a><br>
><br>
> ; GCN-LABEL: {{^}}multi_if_break_loop:<br>
><br>
> Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/nested-loop-conditions.<wbr>ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/nested-loop-conditions.ll?rev=321751&r1=321750&r2=321751&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/nested-loop-<wbr>conditions.ll?rev=321751&r1=<wbr>321750&r2=321751&view=diff</a><br>
> ==============================<wbr>==============================<wbr>==================<br>
> --- llvm/trunk/test/CodeGen/<wbr>AMDGPU/nested-loop-conditions.<wbr>ll (original)<br>
> +++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/nested-loop-conditions.<wbr>ll Wed Jan 3 10:45:37 2018<br>
> @@ -124,55 +124,100 @@ bb23:<br>
> ; Earlier version of above, before a run of the structurizer.<br>
> ; IR-LABEL: @nested_loop_conditions(<br>
><br>
> -; IR: Flow7:<br>
> -; IR-NEXT: call void @<a href="http://llvm.amdgcn.end.cf" rel="noreferrer" target="_blank">llvm.amdgcn.end.cf</a>(i64 %17)<br>
> -; IR-NEXT: %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %15)<br>
> -; IR-NEXT: %1 = extractvalue { i1, i64 } %0, 0<br>
> -; IR-NEXT: %2 = extractvalue { i1, i64 } %0, 1<br>
> -; IR-NEXT: br i1 %1, label %bb4.bb13_crit_edge, label %Flow8<br>
> +; IR: %tmp1235 = icmp slt i32 %tmp1134, 9<br>
> +; IR: br i1 %tmp1235, label %<a href="http://bb14.lr.ph" rel="noreferrer" target="_blank">bb14.lr.ph</a>, label %Flow<br>
> +<br>
> +; IR: <a href="http://bb14.lr.ph" rel="noreferrer" target="_blank">bb14.lr.ph</a>:<br>
> +; IR: br label %bb14<br>
> +<br>
> +; IR: Flow3:<br>
> +; IR: call void @<a href="http://llvm.amdgcn.end.cf" rel="noreferrer" target="_blank">llvm.amdgcn.end.cf</a>(i64 %18)<br>
> +; IR: %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %17)<br>
> +; IR: %1 = extractvalue { i1, i64 } %0, 0<br>
> +; IR: %2 = extractvalue { i1, i64 } %0, 1<br>
> +; IR: br i1 %1, label %bb4.bb13_crit_edge, label %Flow4<br>
> +<br>
> +; IR: bb4.bb13_crit_edge:<br>
> +; IR: br label %Flow4<br>
> +<br>
> +; IR: Flow4:<br>
> +; IR: %3 = phi i1 [ true, %bb4.bb13_crit_edge ], [ false, %Flow3 ]<br>
> +; IR: call void @<a href="http://llvm.amdgcn.end.cf" rel="noreferrer" target="_blank">llvm.amdgcn.end.cf</a>(i64 %2)<br>
> +; IR: br label %Flow<br>
> +<br>
> +; IR: bb13:<br>
> +; IR: br label %bb31<br>
> +<br>
> +; IR: Flow:<br>
> +; IR: %4 = phi i1 [ %3, %Flow4 ], [ true, %bb ]<br>
> +; IR: %5 = call { i1, i64 } @llvm.amdgcn.if(i1 %4)<br>
> +; IR: %6 = extractvalue { i1, i64 } %5, 0<br>
> +; IR: %7 = extractvalue { i1, i64 } %5, 1<br>
> +; IR: br i1 %6, label %bb13, label %bb31<br>
> +<br>
> +; IR: bb14:<br>
> +; IR: %phi.broken = phi i64 [ %18, %Flow2 ], [ 0, %<a href="http://bb14.lr.ph" rel="noreferrer" target="_blank">bb14.lr.ph</a> ]<br>
> +; IR: %tmp1037 = phi i32 [ %tmp1033, %<a href="http://bb14.lr.ph" rel="noreferrer" target="_blank">bb14.lr.ph</a> ], [ %16, %Flow2 ]<br>
> +; IR: %tmp936 = phi <4 x i32> [ %tmp932, %<a href="http://bb14.lr.ph" rel="noreferrer" target="_blank">bb14.lr.ph</a> ], [ %15, %Flow2 ]<br>
> +; IR: %tmp15 = icmp eq i32 %tmp1037, 1<br>
> +; IR: %8 = xor i1 %tmp15, true<br>
> +; IR: %9 = call { i1, i64 } @llvm.amdgcn.if(i1 %8)<br>
> +; IR: %10 = extractvalue { i1, i64 } %9, 0<br>
> +; IR: %11 = extractvalue { i1, i64 } %9, 1<br>
> +; IR: br i1 %10, label %bb31.loopexit, label %Flow1<br>
><br>
> ; IR: Flow1:<br>
> -; IR-NEXT: %loop.phi = phi i64 [ %loop.phi9, %Flow6 ], [ %phi.broken, %bb14 ]<br>
> -; IR-NEXT: %13 = phi <4 x i32> [ %29, %Flow6 ], [ undef, %bb14 ]<br>
> -; IR-NEXT: %14 = phi i32 [ %30, %Flow6 ], [ undef, %bb14 ]<br>
> -; IR-NEXT: %15 = phi i1 [ %31, %Flow6 ], [ false, %bb14 ]<br>
> -; IR-NEXT: %16 = phi i1 [ false, %Flow6 ], [ %8, %bb14 ]<br>
> -; IR-NEXT: %17 = call i64 @llvm.amdgcn.else.break(i64 %11, i64 %loop.phi)<br>
> -; IR-NEXT: call void @<a href="http://llvm.amdgcn.end.cf" rel="noreferrer" target="_blank">llvm.amdgcn.end.cf</a>(i64 %11)<br>
> -; IR-NEXT: %18 = call i1 @llvm.amdgcn.loop(i64 %17)<br>
> -; IR-NEXT: br i1 %18, label %Flow7, label %bb14<br>
> +; IR: %12 = call { i1, i64 } @llvm.amdgcn.else(i64 %11)<br>
> +; IR: %13 = extractvalue { i1, i64 } %12, 0<br>
> +; IR: %14 = extractvalue { i1, i64 } %12, 1<br>
> +; IR: br i1 %13, label %bb16, label %Flow2<br>
> +<br>
> +; IR: bb16:<br>
> +; IR: %tmp17 = bitcast i64 %tmp3 to <2 x i32><br>
> +; IR: br label %bb18<br>
><br>
> ; IR: Flow2:<br>
> -; IR-NEXT: %loop.phi10 = phi i64 [ %loop.phi11, %Flow5 ], [ %12, %bb16 ]<br>
> -; IR-NEXT: %19 = phi <4 x i32> [ %29, %Flow5 ], [ undef, %bb16 ]<br>
> -; IR-NEXT: %20 = phi i32 [ %30, %Flow5 ], [ undef, %bb16 ]<br>
> -; IR-NEXT: %21 = phi i1 [ %31, %Flow5 ], [ false, %bb16 ]<br>
> -; IR-NEXT: %22 = phi i1 [ false, %Flow5 ], [ false, %bb16 ]<br>
> -; IR-NEXT: %23 = phi i1 [ false, %Flow5 ], [ %8, %bb16 ]<br>
> -; IR-NEXT: %24 = call { i1, i64 } @llvm.amdgcn.if(i1 %23)<br>
> -; IR-NEXT: %25 = extractvalue { i1, i64 } %24, 0<br>
> -; IR-NEXT: %26 = extractvalue { i1, i64 } %24, 1<br>
> -; IR-NEXT: br i1 %25, label %bb21, label %Flow3<br>
> +; IR: %loop.phi = phi i64 [ %21, %bb21 ], [ %phi.broken, %Flow1 ]<br>
> +; IR: %15 = phi <4 x i32> [ %tmp9, %bb21 ], [ undef, %Flow1 ]<br>
> +; IR: %16 = phi i32 [ %tmp10, %bb21 ], [ undef, %Flow1 ]<br>
> +; IR: %17 = phi i1 [ %20, %bb21 ], [ false, %Flow1 ]<br>
> +; IR: %18 = call i64 @llvm.amdgcn.else.break(i64 %14, i64 %loop.phi)<br>
> +; IR: call void @<a href="http://llvm.amdgcn.end.cf" rel="noreferrer" target="_blank">llvm.amdgcn.end.cf</a>(i64 %14)<br>
> +; IR: %19 = call i1 @llvm.amdgcn.loop(i64 %18)<br>
> +; IR: br i1 %19, label %Flow3, label %bb14<br>
> +<br>
> +; IR: bb18:<br>
> +; IR: %tmp19 = load volatile i32, i32 addrspace(1)* undef<br>
> +; IR: %tmp20 = icmp slt i32 %tmp19, 9<br>
> +; IR: br i1 %tmp20, label %bb21, label %bb18<br>
><br>
> ; IR: bb21:<br>
> -; IR: %tmp12 = icmp slt i32 %tmp11, 9<br>
> -; IR-NEXT: %27 = xor i1 %tmp12, true<br>
> -; IR-NEXT: %28 = call i64 @llvm.amdgcn.if.break(i1 %27, i64 %phi.broken)<br>
> -; IR-NEXT: br label %Flow3<br>
> +; IR: %tmp22 = extractelement <2 x i32> %tmp17, i64 1<br>
> +; IR: %tmp23 = lshr i32 %tmp22, 16<br>
> +; IR: %tmp24 = select i1 undef, i32 undef, i32 %tmp23<br>
> +; IR: %tmp25 = uitofp i32 %tmp24 to float<br>
> +; IR: %tmp26 = fmul float %tmp25, 0x3EF0001000000000<br>
> +; IR: %tmp27 = fsub float %tmp26, undef<br>
> +; IR: %tmp28 = fcmp olt float %tmp27, 5.000000e-01<br>
> +; IR: %tmp29 = select i1 %tmp28, i64 1, i64 2<br>
> +; IR: %tmp30 = extractelement <4 x i32> %tmp936, i64 %tmp29<br>
> +; IR: %tmp7 = zext i32 %tmp30 to i64<br>
> +; IR: %tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* undef, i64 %tmp7<br>
> +; IR: %tmp9 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp8, align 16<br>
> +; IR: %tmp10 = extractelement <4 x i32> %tmp9, i64 0<br>
> +; IR: %tmp11 = load volatile i32, i32 addrspace(1)* undef<br>
> +; IR: %tmp12 = icmp slt i32 %tmp11, 9<br>
> +; IR: %20 = xor i1 %tmp12, true<br>
> +; IR: %21 = call i64 @llvm.amdgcn.if.break(i1 %20, i64 %phi.broken)<br>
> +; IR: br label %Flow2<br>
><br>
> -; IR: Flow3:<br>
> -; IR-NEXT: %loop.phi11 = phi i64 [ %phi.broken, %bb21 ], [ %phi.broken, %Flow2 ]<br>
> -; IR-NEXT: %loop.phi9 = phi i64 [ %28, %bb21 ], [ %loop.phi10, %Flow2 ]<br>
> -; IR-NEXT: %29 = phi <4 x i32> [ %tmp9, %bb21 ], [ %19, %Flow2 ]<br>
> -; IR-NEXT: %30 = phi i32 [ %tmp10, %bb21 ], [ %20, %Flow2 ]<br>
> -; IR-NEXT: %31 = phi i1 [ %27, %bb21 ], [ %21, %Flow2 ]<br>
> -; IR-NEXT: call void @<a href="http://llvm.amdgcn.end.cf" rel="noreferrer" target="_blank">llvm.amdgcn.end.cf</a>(i64 %26)<br>
> -; IR-NEXT: br i1 %22, label %bb31.loopexit, label %Flow4<br>
> +; IR: bb31.loopexit:<br>
> +; IR: br label %Flow1<br>
><br>
> ; IR: bb31:<br>
> -; IR-NEXT: call void @<a href="http://llvm.amdgcn.end.cf" rel="noreferrer" target="_blank">llvm.amdgcn.end.cf</a>(i64 %7)<br>
> -; IR-NEXT: store volatile i32 0, i32 addrspace(1)* undef<br>
> -; IR-NEXT: ret void<br>
> +; IR: call void @<a href="http://llvm.amdgcn.end.cf" rel="noreferrer" target="_blank">llvm.amdgcn.end.cf</a>(i64 %7)<br>
> +; IR: store volatile i32 0, i32 addrspace(1)* undef<br>
> +; IR: ret void<br>
><br>
><br>
> ; GCN-LABEL: {{^}}nested_loop_conditions:<br>
><br>
> Added: llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/<wbr>backedge-id-bug.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll?rev=321751&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/StructurizeCFG/<wbr>AMDGPU/backedge-id-bug.ll?rev=<wbr>321751&view=auto</a><br>
> ==============================<wbr>==============================<wbr>==================<br>
> --- llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/<wbr>backedge-id-bug.ll (added)<br>
> +++ llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/<wbr>backedge-id-bug.ll Wed Jan 3 10:45:37 2018<br>
> @@ -0,0 +1,301 @@<br>
> +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py<br>
> +; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -structurizecfg %s | FileCheck %s<br>
> +<br>
> +; StructurizeCFG::orderNodes used an arbitrary and nonsensical sorting<br>
> +; function which broke the basic backedge identification algorithm. It<br>
> +; would use RPO order, but then do a weird partial sort by the loop<br>
> +; depth assuming blocks are sorted by loop. However a block can appear<br>
> +; in between blocks of a loop that is not part of a loop, breaking the<br>
> +; assumption of the sort.<br>
> +;<br>
> +; The collectInfos must be done in RPO order. The actual<br>
> +; structurization order I think is less important, but unless the loop<br>
> +; headers are identified in RPO order, it finds the wrong set of back<br>
> +; edges.<br>
> +<br>
> +define amdgpu_kernel void @loop_backedge_misidentified(<wbr>i32 addrspace(1)* %arg0) #0 {<br>
> +; CHECK-LABEL: @loop_backedge_misidentified(<br>
> +; CHECK-NEXT: entry:<br>
> +; CHECK-NEXT: [[TMP:%.*]] = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16<br>
> +; CHECK-NEXT: [[LOAD1:%.*]] = load volatile <2 x float>, <2 x float> addrspace(1)* undef<br>
> +; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()<br>
> +; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG0:%.*]], i32 [[TID]]<br>
> +; CHECK-NEXT: [[I_INITIAL:%.*]] = load volatile i32, i32 addrspace(1)* [[GEP]], align 4<br>
> +; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]<br>
> +; CHECK: LOOP.HEADER:<br>
> +; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_INITIAL]], [[ENTRY:%.*]] ], [ [[TMP10:%.*]], [[FLOW4:%.*]] ]<br>
> +; CHECK-NEXT: call void asm sideeffect "s_nop 0x100b<br>
> +; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[I]] to i64<br>
> +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 [[TMP12]]<br>
> +; CHECK-NEXT: [[TMP14:%.*]] = load <4 x i32>, <4 x i32> addrspace(1)* [[TMP13]], align 16<br>
> +; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP14]], i64 0<br>
> +; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 65535<br>
> +; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[TMP16]], 1<br>
> +; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[TMP17]], true<br>
> +; CHECK-NEXT: br i1 [[TMP0]], label [[BB62:%.*]], label [[FLOW:%.*]]<br>
> +; CHECK: Flow2:<br>
> +; CHECK-NEXT: br label [[FLOW]]<br>
> +; CHECK: bb18:<br>
> +; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i32> [[TMP]], i64 0<br>
> +; CHECK-NEXT: [[TMP22:%.*]] = lshr i32 [[TMP19]], 16<br>
> +; CHECK-NEXT: [[TMP24:%.*]] = urem i32 [[TMP22]], 52<br>
> +; CHECK-NEXT: [[TMP25:%.*]] = mul nuw nsw i32 [[TMP24]], 52<br>
> +; CHECK-NEXT: br label [[INNER_LOOP:%.*]]<br>
> +; CHECK: Flow3:<br>
> +; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[TMP59:%.*]], [[INNER_LOOP_BREAK:%.*]] ], [ [[TMP7:%.*]], [[FLOW]] ]<br>
> +; CHECK-NEXT: [[TMP2:%.*]] = phi i1 [ true, [[INNER_LOOP_BREAK]] ], [ [[TMP8:%.*]], [[FLOW]] ]<br>
> +; CHECK-NEXT: br i1 [[TMP2]], label [[END_ELSE_BLOCK:%.*]], label [[FLOW4]]<br>
> +; CHECK: INNER_LOOP:<br>
> +; CHECK-NEXT: [[INNER_LOOP_J:%.*]] = phi i32 [ [[INNER_LOOP_J_INC:%.*]], [[INNER_LOOP]] ], [ [[TMP25]], [[BB18:%.*]] ]<br>
> +; CHECK-NEXT: call void asm sideeffect "<br>
> +; CHECK-NEXT: [[INNER_LOOP_J_INC]] = add nsw i32 [[INNER_LOOP_J]], 1<br>
> +; CHECK-NEXT: [[INNER_LOOP_CMP:%.*]] = icmp eq i32 [[INNER_LOOP_J]], 0<br>
> +; CHECK-NEXT: br i1 [[INNER_LOOP_CMP]], label [[INNER_LOOP_BREAK]], label [[INNER_LOOP]]<br>
> +; CHECK: INNER_LOOP_BREAK:<br>
> +; CHECK-NEXT: [[TMP59]] = extractelement <4 x i32> [[TMP14]], i64 2<br>
> +; CHECK-NEXT: call void asm sideeffect "s_nop 23 ", "~{memory}"() #0<br>
> +; CHECK-NEXT: br label [[FLOW3:%.*]]<br>
> +; CHECK: bb62:<br>
> +; CHECK-NEXT: [[LOAD13:%.*]] = icmp ult i32 [[TMP16]], 271<br>
> +; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[LOAD13]], true<br>
> +; CHECK-NEXT: br i1 [[TMP3]], label [[INCREMENT_I:%.*]], label [[FLOW1:%.*]]<br>
> +; CHECK: Flow1:<br>
> +; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ [[INC_I:%.*]], [[INCREMENT_I]] ], [ undef, [[BB62]] ]<br>
> +; CHECK-NEXT: [[TMP5:%.*]] = phi i1 [ true, [[INCREMENT_I]] ], [ false, [[BB62]] ]<br>
> +; CHECK-NEXT: [[TMP6:%.*]] = phi i1 [ false, [[INCREMENT_I]] ], [ true, [[BB62]] ]<br>
> +; CHECK-NEXT: br i1 [[TMP6]], label [[BB64:%.*]], label [[FLOW2:%.*]]<br>
> +; CHECK: bb64:<br>
> +; CHECK-NEXT: call void asm sideeffect "s_nop 42", "~{memory}"() #0<br>
> +; CHECK-NEXT: br label [[FLOW2]]<br>
> +; CHECK: Flow:<br>
> +; CHECK-NEXT: [[TMP7]] = phi i32 [ [[TMP4]], [[FLOW2]] ], [ undef, [[LOOP_HEADER]] ]<br>
> +; CHECK-NEXT: [[TMP8]] = phi i1 [ [[TMP5]], [[FLOW2]] ], [ false, [[LOOP_HEADER]] ]<br>
> +; CHECK-NEXT: [[TMP9:%.*]] = phi i1 [ false, [[FLOW2]] ], [ true, [[LOOP_HEADER]] ]<br>
> +; CHECK-NEXT: br i1 [[TMP9]], label [[BB18]], label [[FLOW3]]<br>
> +; CHECK: INCREMENT_I:<br>
> +; CHECK-NEXT: [[INC_I]] = add i32 [[I]], 1<br>
> +; CHECK-NEXT: call void asm sideeffect "s_nop 0x1336<br>
> +; CHECK-NEXT: br label [[FLOW1]]<br>
> +; CHECK: END_ELSE_BLOCK:<br>
> +; CHECK-NEXT: [[I_FINAL:%.*]] = phi i32 [ [[TMP1]], [[FLOW3]] ]<br>
> +; CHECK-NEXT: call void asm sideeffect "s_nop 0x1337<br>
> +; CHECK-NEXT: [[CMP_END_ELSE_BLOCK:%.*]] = icmp eq i32 [[I_FINAL]], -1<br>
> +; CHECK-NEXT: br label [[FLOW4]]<br>
> +; CHECK: Flow4:<br>
> +; CHECK-NEXT: [[TMP10]] = phi i32 [ [[I_FINAL]], [[END_ELSE_BLOCK]] ], [ undef, [[FLOW3]] ]<br>
> +; CHECK-NEXT: [[TMP11:%.*]] = phi i1 [ [[CMP_END_ELSE_BLOCK]], [[END_ELSE_BLOCK]] ], [ true, [[FLOW3]] ]<br>
> +; CHECK-NEXT: br i1 [[TMP11]], label [[RETURN:%.*]], label [[LOOP_HEADER]]<br>
> +; CHECK: RETURN:<br>
> +; CHECK-NEXT: call void asm sideeffect "s_nop 0x99<br>
> +; CHECK-NEXT: store volatile <2 x float> [[LOAD1]], <2 x float> addrspace(1)* undef, align 8<br>
> +; CHECK-NEXT: ret void<br>
> +;<br>
> +entry:<br>
> + %tmp = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16<br>
> + %load1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef<br>
> + %tid = call i32 @llvm.amdgcn.workitem.id.x()<br>
> + %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i32 %tid<br>
> + %i.initial = load volatile i32, i32 addrspace(1)* %gep, align 4<br>
> + br label %LOOP.HEADER<br>
> +<br>
> +LOOP.HEADER:<br>
> + %i = phi i32 [ %i.final, %END_ELSE_BLOCK ], [ %i.initial, %entry ]<br>
> + call void asm sideeffect "s_nop 0x100b ; loop $0 ", "r,~{memory}"(i32 %i) #0<br>
> + %tmp12 = zext i32 %i to i64<br>
> + %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 %tmp12<br>
> + %tmp14 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp13, align 16<br>
> + %tmp15 = extractelement <4 x i32> %tmp14, i64 0<br>
> + %tmp16 = and i32 %tmp15, 65535<br>
> + %tmp17 = icmp eq i32 %tmp16, 1<br>
> + br i1 %tmp17, label %bb18, label %bb62<br>
> +<br>
> +bb18:<br>
> + %tmp19 = extractelement <2 x i32> %tmp, i64 0<br>
> + %tmp22 = lshr i32 %tmp19, 16<br>
> + %tmp24 = urem i32 %tmp22, 52<br>
> + %tmp25 = mul nuw nsw i32 %tmp24, 52<br>
> + br label %INNER_LOOP<br>
> +<br>
> +INNER_LOOP:<br>
> + %inner.loop.j = phi i32 [ %tmp25, %bb18 ], [ %inner.loop.j.inc, %INNER_LOOP ]<br>
> + call void asm sideeffect "; inner loop body", ""() #0<br>
> + %inner.loop.j.inc = add nsw i32 %inner.loop.j, 1<br>
> + %inner.loop.cmp = icmp eq i32 %inner.loop.j, 0<br>
> + br i1 %inner.loop.cmp, label %INNER_LOOP_BREAK, label %INNER_LOOP<br>
> +<br>
> +INNER_LOOP_BREAK:<br>
> + %tmp59 = extractelement <4 x i32> %tmp14, i64 2<br>
> + call void asm sideeffect "s_nop 23 ", "~{memory}"() #0<br>
> + br label %END_ELSE_BLOCK<br>
> +<br>
> +bb62:<br>
> + %load13 = icmp ult i32 %tmp16, 271<br>
> + br i1 %load13, label %bb64, label %INCREMENT_I<br>
> +<br>
> +bb64:<br>
> + call void asm sideeffect "s_nop 42", "~{memory}"() #0<br>
> + br label %RETURN<br>
> +<br>
> +INCREMENT_I:<br>
> + %inc.i = add i32 %i, 1<br>
> + call void asm sideeffect "s_nop 0x1336 ; increment $0", "v,~{memory}"(i32 %inc.i) #0<br>
> + br label %END_ELSE_BLOCK<br>
> +<br>
> +END_ELSE_BLOCK:<br>
> + %i.final = phi i32 [ %tmp59, %INNER_LOOP_BREAK ], [ %inc.i, %INCREMENT_I ]<br>
> + call void asm sideeffect "s_nop 0x1337 ; end else block $0", "v,~{memory}"(i32 %i.final) #0<br>
> + %cmp.end.else.block = icmp eq i32 %i.final, -1<br>
> + br i1 %cmp.end.else.block, label %RETURN, label %LOOP.HEADER<br>
> +<br>
> +RETURN:<br>
> + call void asm sideeffect "s_nop 0x99 ; ClosureEval return", "~{memory}"() #0<br>
> + store volatile <2 x float> %load1, <2 x float> addrspace(1)* undef, align 8<br>
> + ret void<br>
> +}<br>
> +<br>
> +; The same function, except break to return block goes directly to the<br>
> +; return, which managed to hide the bug.<br>
> +define amdgpu_kernel void @loop_backedge_misidentified_<wbr>alt(i32 addrspace(1)* %arg0) #0 {<br>
> +; CHECK-LABEL: @loop_backedge_misidentified_<wbr>alt(<br>
> +; CHECK-NEXT: entry:<br>
> +; CHECK-NEXT: [[TMP:%.*]] = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16<br>
> +; CHECK-NEXT: [[LOAD1:%.*]] = load volatile <2 x float>, <2 x float> addrspace(1)* undef<br>
> +; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()<br>
> +; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG0:%.*]], i32 [[TID]]<br>
> +; CHECK-NEXT: [[I_INITIAL:%.*]] = load volatile i32, i32 addrspace(1)* [[GEP]], align 4<br>
> +; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]<br>
> +; CHECK: LOOP.HEADER:<br>
> +; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_INITIAL]], [[ENTRY:%.*]] ], [ [[TMP9:%.*]], [[FLOW3:%.*]] ]<br>
> +; CHECK-NEXT: call void asm sideeffect "s_nop 0x100b<br>
> +; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[I]] to i64<br>
> +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 [[TMP12]]<br>
> +; CHECK-NEXT: [[TMP14:%.*]] = load <4 x i32>, <4 x i32> addrspace(1)* [[TMP13]], align 16<br>
> +; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP14]], i64 0<br>
> +; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 65535<br>
> +; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[TMP16]], 1<br>
> +; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[TMP17]], true<br>
> +; CHECK-NEXT: br i1 [[TMP0]], label [[BB62:%.*]], label [[FLOW:%.*]]<br>
> +; CHECK: Flow1:<br>
> +; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[INC_I:%.*]], [[INCREMENT_I:%.*]] ], [ undef, [[BB62]] ]<br>
> +; CHECK-NEXT: [[TMP2:%.*]] = phi i1 [ true, [[INCREMENT_I]] ], [ false, [[BB62]] ]<br>
> +; CHECK-NEXT: br label [[FLOW]]<br>
> +; CHECK: bb18:<br>
> +; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i32> [[TMP]], i64 0<br>
> +; CHECK-NEXT: [[TMP22:%.*]] = lshr i32 [[TMP19]], 16<br>
> +; CHECK-NEXT: [[TMP24:%.*]] = urem i32 [[TMP22]], 52<br>
> +; CHECK-NEXT: [[TMP25:%.*]] = mul nuw nsw i32 [[TMP24]], 52<br>
> +; CHECK-NEXT: br label [[INNER_LOOP:%.*]]<br>
> +; CHECK: Flow2:<br>
> +; CHECK-NEXT: [[TMP3:%.*]] = phi i32 [ [[TMP59:%.*]], [[INNER_LOOP_BREAK:%.*]] ], [ [[TMP6:%.*]], [[FLOW]] ]<br>
> +; CHECK-NEXT: [[TMP4:%.*]] = phi i1 [ true, [[INNER_LOOP_BREAK]] ], [ [[TMP7:%.*]], [[FLOW]] ]<br>
> +; CHECK-NEXT: br i1 [[TMP4]], label [[END_ELSE_BLOCK:%.*]], label [[FLOW3]]<br>
> +; CHECK: INNER_LOOP:<br>
> +; CHECK-NEXT: [[INNER_LOOP_J:%.*]] = phi i32 [ [[INNER_LOOP_J_INC:%.*]], [[INNER_LOOP]] ], [ [[TMP25]], [[BB18:%.*]] ]<br>
> +; CHECK-NEXT: call void asm sideeffect "<br>
> +; CHECK-NEXT: [[INNER_LOOP_J_INC]] = add nsw i32 [[INNER_LOOP_J]], 1<br>
> +; CHECK-NEXT: [[INNER_LOOP_CMP:%.*]] = icmp eq i32 [[INNER_LOOP_J]], 0<br>
> +; CHECK-NEXT: br i1 [[INNER_LOOP_CMP]], label [[INNER_LOOP_BREAK]], label [[INNER_LOOP]]<br>
> +; CHECK: INNER_LOOP_BREAK:<br>
> +; CHECK-NEXT: [[TMP59]] = extractelement <4 x i32> [[TMP14]], i64 2<br>
> +; CHECK-NEXT: call void asm sideeffect "s_nop 23 ", "~{memory}"() #0<br>
> +; CHECK-NEXT: br label [[FLOW2:%.*]]<br>
> +; CHECK: bb62:<br>
> +; CHECK-NEXT: [[LOAD13:%.*]] = icmp ult i32 [[TMP16]], 271<br>
> +; CHECK-NEXT: [[TMP5:%.*]] = xor i1 [[LOAD13]], true<br>
> +; CHECK-NEXT: br i1 [[TMP5]], label [[INCREMENT_I]], label [[FLOW1:%.*]]<br>
> +; CHECK: bb64:<br>
> +; CHECK-NEXT: call void asm sideeffect "s_nop 42", "~{memory}"() #0<br>
> +; CHECK-NEXT: br label [[RETURN:%.*]]<br>
> +; CHECK: Flow:<br>
> +; CHECK-NEXT: [[TMP6]] = phi i32 [ [[TMP1]], [[FLOW1]] ], [ undef, [[LOOP_HEADER]] ]<br>
> +; CHECK-NEXT: [[TMP7]] = phi i1 [ [[TMP2]], [[FLOW1]] ], [ false, [[LOOP_HEADER]] ]<br>
> +; CHECK-NEXT: [[TMP8:%.*]] = phi i1 [ false, [[FLOW1]] ], [ true, [[LOOP_HEADER]] ]<br>
> +; CHECK-NEXT: br i1 [[TMP8]], label [[BB18]], label [[FLOW2]]<br>
> +; CHECK: INCREMENT_I:<br>
> +; CHECK-NEXT: [[INC_I]] = add i32 [[I]], 1<br>
> +; CHECK-NEXT: call void asm sideeffect "s_nop 0x1336<br>
> +; CHECK-NEXT: br label [[FLOW1]]<br>
> +; CHECK: END_ELSE_BLOCK:<br>
> +; CHECK-NEXT: [[I_FINAL:%.*]] = phi i32 [ [[TMP3]], [[FLOW2]] ]<br>
> +; CHECK-NEXT: call void asm sideeffect "s_nop 0x1337<br>
> +; CHECK-NEXT: [[CMP_END_ELSE_BLOCK:%.*]] = icmp eq i32 [[I_FINAL]], -1<br>
> +; CHECK-NEXT: br label [[FLOW3]]<br>
> +; CHECK: Flow3:<br>
> +; CHECK-NEXT: [[TMP9]] = phi i32 [ [[I_FINAL]], [[END_ELSE_BLOCK]] ], [ undef, [[FLOW2]] ]<br>
> +; CHECK-NEXT: [[TMP10:%.*]] = phi i1 [ [[CMP_END_ELSE_BLOCK]], [[END_ELSE_BLOCK]] ], [ true, [[FLOW2]] ]<br>
> +; CHECK-NEXT: br i1 [[TMP10]], label [[RETURN]], label [[LOOP_HEADER]]<br>
> +; CHECK: RETURN:<br>
> +; CHECK-NEXT: call void asm sideeffect "s_nop 0x99<br>
> +; CHECK-NEXT: store volatile <2 x float> [[LOAD1]], <2 x float> addrspace(1)* undef, align 8<br>
> +; CHECK-NEXT: ret void<br>
> +;<br>
> +entry:<br>
> + %tmp = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16<br>
> + %load1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef<br>
> + %tid = call i32 @llvm.amdgcn.workitem.id.x()<br>
> + %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i32 %tid<br>
> + %i.initial = load volatile i32, i32 addrspace(1)* %gep, align 4<br>
> + br label %LOOP.HEADER<br>
> +<br>
> +LOOP.HEADER:<br>
> + %i = phi i32 [ %i.final, %END_ELSE_BLOCK ], [ %i.initial, %entry ]<br>
> + call void asm sideeffect "s_nop 0x100b ; loop $0 ", "r,~{memory}"(i32 %i) #0<br>
> + %tmp12 = zext i32 %i to i64<br>
> + %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 %tmp12<br>
> + %tmp14 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp13, align 16<br>
> + %tmp15 = extractelement <4 x i32> %tmp14, i64 0<br>
> + %tmp16 = and i32 %tmp15, 65535<br>
> + %tmp17 = icmp eq i32 %tmp16, 1<br>
> + br i1 %tmp17, label %bb18, label %bb62<br>
> +<br>
> +bb18:<br>
> + %tmp19 = extractelement <2 x i32> %tmp, i64 0<br>
> + %tmp22 = lshr i32 %tmp19, 16<br>
> + %tmp24 = urem i32 %tmp22, 52<br>
> + %tmp25 = mul nuw nsw i32 %tmp24, 52<br>
> + br label %INNER_LOOP<br>
> +<br>
> +INNER_LOOP:<br>
> + %inner.loop.j = phi i32 [ %tmp25, %bb18 ], [ %inner.loop.j.inc, %INNER_LOOP ]<br>
> + call void asm sideeffect "; inner loop body", ""() #0<br>
> + %inner.loop.j.inc = add nsw i32 %inner.loop.j, 1<br>
> + %inner.loop.cmp = icmp eq i32 %inner.loop.j, 0<br>
> + br i1 %inner.loop.cmp, label %INNER_LOOP_BREAK, label %INNER_LOOP<br>
> +<br>
> +INNER_LOOP_BREAK:<br>
> + %tmp59 = extractelement <4 x i32> %tmp14, i64 2<br>
> + call void asm sideeffect "s_nop 23 ", "~{memory}"() #0<br>
> + br label %END_ELSE_BLOCK<br>
> +<br>
> +bb62:<br>
> + %load13 = icmp ult i32 %tmp16, 271<br>
> + ;br i1 %load13, label %bb64, label %INCREMENT_I<br>
> + ; branching directly to the return avoids the bug<br>
> + br i1 %load13, label %RETURN, label %INCREMENT_I<br>
> +<br>
> +<br>
> +bb64:<br>
> + call void asm sideeffect "s_nop 42", "~{memory}"() #0<br>
> + br label %RETURN<br>
> +<br>
> +INCREMENT_I:<br>
> + %inc.i = add i32 %i, 1<br>
> + call void asm sideeffect "s_nop 0x1336 ; increment $0", "v,~{memory}"(i32 %inc.i) #0<br>
> + br label %END_ELSE_BLOCK<br>
> +<br>
> +END_ELSE_BLOCK:<br>
> + %i.final = phi i32 [ %tmp59, %INNER_LOOP_BREAK ], [ %inc.i, %INCREMENT_I ]<br>
> + call void asm sideeffect "s_nop 0x1337 ; end else block $0", "v,~{memory}"(i32 %i.final) #0<br>
> + %cmp.end.else.block = icmp eq i32 %i.final, -1<br>
> + br i1 %cmp.end.else.block, label %RETURN, label %LOOP.HEADER<br>
> +<br>
> +RETURN:<br>
> + call void asm sideeffect "s_nop 0x99 ; ClosureEval return", "~{memory}"() #0<br>
> + store volatile <2 x float> %load1, <2 x float> addrspace(1)* undef, align 8<br>
> + ret void<br>
> +}<br>
> +<br>
> +declare i32 @llvm.amdgcn.workitem.id.x() #1<br>
> +<br>
> +attributes #0 = { convergent nounwind }<br>
> +attributes #1 = { convergent nounwind readnone }<br>
><br>
> Added: llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/lit.<wbr>local.cfg<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/StructurizeCFG/AMDGPU/lit.local.cfg?rev=321751&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/StructurizeCFG/<wbr>AMDGPU/lit.local.cfg?rev=<wbr>321751&view=auto</a><br>
> ==============================<wbr>==============================<wbr>==================<br>
> --- llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/lit.<wbr>local.cfg (added)<br>
> +++ llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/lit.<wbr>local.cfg Wed Jan 3 10:45:37 2018<br>
> @@ -0,0 +1,2 @@<br>
> +if not 'AMDGPU' in config.root.targets:<br>
> + config.unsupported = True<br>
><br>
> Modified: llvm/trunk/test/Transforms/<wbr>StructurizeCFG/nested-loop-<wbr>order.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/StructurizeCFG/nested-loop-order.ll?rev=321751&r1=321750&r2=321751&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/StructurizeCFG/<wbr>nested-loop-order.ll?rev=<wbr>321751&r1=321750&r2=321751&<wbr>view=diff</a><br>
> ==============================<wbr>==============================<wbr>==================<br>
> --- llvm/trunk/test/Transforms/<wbr>StructurizeCFG/nested-loop-<wbr>order.ll (original)<br>
> +++ llvm/trunk/test/Transforms/<wbr>StructurizeCFG/nested-loop-<wbr>order.ll Wed Jan 3 10:45:37 2018<br>
> @@ -1,32 +1,76 @@<br>
> +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py<br>
> ; RUN: opt -S -structurizecfg %s -o - | FileCheck %s<br>
><br>
> define void @main(float addrspace(1)* %out) {<br>
> -<br>
> -; CHECK: main_body:<br>
> -; CHECK: br label %LOOP.outer<br>
> +; CHECK-LABEL: @main(<br>
> +; CHECK-NEXT: main_body:<br>
> +; CHECK-NEXT: br label [[LOOP_OUTER:%.*]]<br>
> +; CHECK: LOOP.outer:<br>
> +; CHECK-NEXT: [[TEMP8_0_PH:%.*]] = phi float [ 0.000000e+00, [[MAIN_BODY:%.*]] ], [ [[TMP13:%.*]], [[FLOW3:%.*]] ]<br>
> +; CHECK-NEXT: [[TEMP4_0_PH:%.*]] = phi i32 [ 0, [[MAIN_BODY]] ], [ [[TMP12:%.*]], [[FLOW3]] ]<br>
> +; CHECK-NEXT: br label [[LOOP:%.*]]<br>
> +; CHECK: LOOP:<br>
> +; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ undef, [[LOOP_OUTER]] ], [ [[TMP12]], [[FLOW:%.*]] ]<br>
> +; CHECK-NEXT: [[TMP1:%.*]] = phi float [ undef, [[LOOP_OUTER]] ], [ [[TMP13]], [[FLOW]] ]<br>
> +; CHECK-NEXT: [[TEMP4_0:%.*]] = phi i32 [ [[TEMP4_0_PH]], [[LOOP_OUTER]] ], [ [[TMP15:%.*]], [[FLOW]] ]<br>
> +; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TEMP4_0]], 1<br>
> +; CHECK-NEXT: [[TMP22:%.*]] = icmp sgt i32 [[TMP20]], 3<br>
> +; CHECK-NEXT: [[TMP2:%.*]] = xor i1 [[TMP22]], true<br>
> +; CHECK-NEXT: br i1 [[TMP2]], label [[ENDIF:%.*]], label [[FLOW]]<br>
> +; CHECK: Flow2:<br>
> +; CHECK-NEXT: [[TMP3:%.*]] = phi float [ [[TEMP8_0_PH]], [[IF29:%.*]] ], [ [[TMP9:%.*]], [[FLOW1:%.*]] ]<br>
> +; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ [[TMP20]], [[IF29]] ], [ undef, [[FLOW1]] ]<br>
> +; CHECK-NEXT: [[TMP5:%.*]] = phi i1 [ [[TMP32:%.*]], [[IF29]] ], [ true, [[FLOW1]] ]<br>
> +; CHECK-NEXT: br label [[FLOW]]<br>
> +; CHECK: Flow3:<br>
> +; CHECK-NEXT: br i1 [[TMP16:%.*]], label [[ENDLOOP:%.*]], label [[LOOP_OUTER]]<br>
> +; CHECK: ENDLOOP:<br>
> +; CHECK-NEXT: [[TEMP8_1:%.*]] = phi float [ [[TMP14:%.*]], [[FLOW3]] ]<br>
> +; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i32 [[TMP20]], 3<br>
> +; CHECK-NEXT: [[DOT45:%.*]] = select i1 [[TMP23]], float 0.000000e+00, float 1.000000e+00<br>
> +; CHECK-NEXT: store float [[DOT45]], float addrspace(1)* [[OUT:%.*]]<br>
> +; CHECK-NEXT: ret void<br>
> +; CHECK: ENDIF:<br>
> +; CHECK-NEXT: [[TMP31:%.*]] = icmp sgt i32 [[TMP20]], 1<br>
> +; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[TMP31]], true<br>
> +; CHECK-NEXT: br i1 [[TMP6]], label [[ENDIF28:%.*]], label [[FLOW1]]<br>
> +; CHECK: Flow1:<br>
> +; CHECK-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP20]], [[ENDIF28]] ], [ [[TMP0]], [[ENDIF]] ]<br>
> +; CHECK-NEXT: [[TMP8:%.*]] = phi float [ [[TMP35:%.*]], [[ENDIF28]] ], [ [[TMP1]], [[ENDIF]] ]<br>
> +; CHECK-NEXT: [[TMP9]] = phi float [ [[TMP35]], [[ENDIF28]] ], [ [[TEMP8_0_PH]], [[ENDIF]] ]<br>
> +; CHECK-NEXT: [[TMP10:%.*]] = phi i1 [ [[TMP36:%.*]], [[ENDIF28]] ], [ true, [[ENDIF]] ]<br>
> +; CHECK-NEXT: [[TMP11:%.*]] = phi i1 [ false, [[ENDIF28]] ], [ true, [[ENDIF]] ]<br>
> +; CHECK-NEXT: br i1 [[TMP11]], label [[IF29]], label [[FLOW2:%.*]]<br>
> +; CHECK: IF29:<br>
> +; CHECK-NEXT: [[TMP32]] = icmp sgt i32 [[TMP20]], 2<br>
> +; CHECK-NEXT: br label [[FLOW2]]<br>
> +; CHECK: Flow:<br>
> +; CHECK-NEXT: [[TMP12]] = phi i32 [ [[TMP7]], [[FLOW2]] ], [ [[TMP0]], [[LOOP]] ]<br>
> +; CHECK-NEXT: [[TMP13]] = phi float [ [[TMP8]], [[FLOW2]] ], [ [[TMP1]], [[LOOP]] ]<br>
> +; CHECK-NEXT: [[TMP14]] = phi float [ [[TMP3]], [[FLOW2]] ], [ [[TEMP8_0_PH]], [[LOOP]] ]<br>
> +; CHECK-NEXT: [[TMP15]] = phi i32 [ [[TMP4]], [[FLOW2]] ], [ undef, [[LOOP]] ]<br>
> +; CHECK-NEXT: [[TMP16]] = phi i1 [ [[TMP10]], [[FLOW2]] ], [ true, [[LOOP]] ]<br>
> +; CHECK-NEXT: [[TMP17:%.*]] = phi i1 [ [[TMP5]], [[FLOW2]] ], [ true, [[LOOP]] ]<br>
> +; CHECK-NEXT: br i1 [[TMP17]], label [[FLOW3]], label [[LOOP]]<br>
> +; CHECK: ENDIF28:<br>
> +; CHECK-NEXT: [[TMP35]] = fadd float [[TEMP8_0_PH]], 1.000000e+00<br>
> +; CHECK-NEXT: [[TMP36]] = icmp sgt i32 [[TMP20]], 2<br>
> +; CHECK-NEXT: br label [[FLOW1]]<br>
> +;<br>
> main_body:<br>
> br label %LOOP.outer<br>
><br>
> -; CHECK: LOOP.outer:<br>
> -; CHECK: br label %LOOP<br>
> LOOP.outer: ; preds = %ENDIF28, %main_body<br>
> %<a href="http://temp8.0.ph" rel="noreferrer" target="_blank">temp8.0.ph</a> = phi float [ 0.000000e+00, %main_body ], [ %tmp35, %ENDIF28 ]<br>
> %<a href="http://temp4.0.ph" rel="noreferrer" target="_blank">temp4.0.ph</a> = phi i32 [ 0, %main_body ], [ %tmp20, %ENDIF28 ]<br>
> br label %LOOP<br>
><br>
> -; CHECK: LOOP:<br>
> -; br i1 %{{[0-9]+}}, label %ENDIF, label %Flow<br>
> LOOP: ; preds = %IF29, %LOOP.outer<br>
> %temp4.0 = phi i32 [ %<a href="http://temp4.0.ph" rel="noreferrer" target="_blank">temp4.0.ph</a>, %LOOP.outer ], [ %tmp20, %IF29 ]<br>
> %tmp20 = add i32 %temp4.0, 1<br>
> %tmp22 = icmp sgt i32 %tmp20, 3<br>
> br i1 %tmp22, label %ENDLOOP, label %ENDIF<br>
><br>
> -; CHECK: Flow3<br>
> -; CHECK: br i1 %{{[0-9]+}}, label %ENDLOOP, label %LOOP.outer<br>
> -<br>
> -; CHECK: ENDLOOP:<br>
> -; CHECK: ret void<br>
> ENDLOOP: ; preds = %ENDIF28, %IF29, %LOOP<br>
> %temp8.1 = phi float [ %<a href="http://temp8.0.ph" rel="noreferrer" target="_blank">temp8.0.ph</a>, %LOOP ], [ %<a href="http://temp8.0.ph" rel="noreferrer" target="_blank">temp8.0.ph</a>, %IF29 ], [ %tmp35, %ENDIF28 ]<br>
> %tmp23 = icmp eq i32 %tmp20, 3<br>
> @@ -34,29 +78,14 @@ ENDLOOP:<br>
> store float %.45, float addrspace(1)* %out<br>
> ret void<br>
><br>
> -; CHECK: ENDIF:<br>
> -; CHECK: br i1 %tmp31, label %IF29, label %Flow1<br>
> ENDIF: ; preds = %LOOP<br>
> %tmp31 = icmp sgt i32 %tmp20, 1<br>
> br i1 %tmp31, label %IF29, label %ENDIF28<br>
><br>
> -; CHECK: Flow:<br>
> -; CHECK: br i1 %{{[0-9]+}}, label %Flow2, label %LOOP<br>
> -<br>
> -; CHECK: IF29:<br>
> -; CHECK: br label %Flow1<br>
> IF29: ; preds = %ENDIF<br>
> %tmp32 = icmp sgt i32 %tmp20, 2<br>
> br i1 %tmp32, label %ENDLOOP, label %LOOP<br>
><br>
> -; CHECK: Flow1:<br>
> -; CHECK: br label %Flow<br>
> -<br>
> -; CHECK: Flow2:<br>
> -; CHECK: br i1 %{{[0-9]+}}, label %ENDIF28, label %Flow3<br>
> -<br>
> -; CHECK: ENDIF28:<br>
> -; CHECK: br label %Flow3<br>
> ENDIF28: ; preds = %ENDIF<br>
> %tmp35 = fadd float %<a href="http://temp8.0.ph" rel="noreferrer" target="_blank">temp8.0.ph</a>, 1.0<br>
> %tmp36 = icmp sgt i32 %tmp20, 2<br>
><br>
><br>
> ______________________________<wbr>_________________<br>
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</div></div></blockquote></div><br></div>