<html><head><meta http-equiv="Content-Type" content="text/html; charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">Thanks!<br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Jan 30, 2018, at 2:55 AM, Hans Wennborg <<a href="mailto:hans@chromium.org" class="">hans@chromium.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Merged in r323746.</div><div class="gmail_extra"><br class=""><div class="gmail_quote">On Tue, Jan 30, 2018 at 12:47 AM, Quentin Colombet <span dir="ltr" class=""><<a href="mailto:qcolombet@apple.com" target="_blank" class="">qcolombet@apple.com</a>></span> wrote:<br class=""><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Hans,<br class="">
<br class="">
Could we pull that commit in the release please?<br class="">
<br class="">
With GISel, this is a pattern that can come up more often.<br class="">
<br class="">
Cheers,<br class="">
-Quentin<br class="">
<div class="HOEnZb"><div class="h5"><br class="">
> On Jan 29, 2018, at 3:42 PM, Quentin Colombet via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class="">
><br class="">
> Author: qcolombet<br class="">
> Date: Mon Jan 29 15:42:37 2018<br class="">
> New Revision: 323710<br class="">
><br class="">
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=323710&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project?rev=323710&view=rev</a><br class="">
> Log:<br class="">
> [RAFast] Don't dereference MBB::end<br class="">
><br class="">
> When RAFast sees liveins in on a basic block, it uses that information<br class="">
> to initialize the availability of the registers. The called<br class="">
> method uses an instruction as one of its argument and in the liveins<br class="">
> case, RAFast was dereferencing MBB::begin which can be MBB::end for<br class="">
> empty basic block.<br class="">
><br class="">
> Change the API of definePhysReg to use MachineBasicBlock::iterator<br class="">
> instead of MachineInstr so that we don't dereference an<br class="">
> invalid iterator while making the call.<br class="">
><br class="">
> <a href="rdar://problem/36952401" class="">rdar://problem/36952401</a><br class="">
><br class="">
> Added:<br class="">
> llvm/trunk/test/CodeGen/<wbr class="">AArch64/fast-regalloc-empty-<wbr class="">bb-with-liveins.mir<br class="">
> Modified:<br class="">
> llvm/trunk/lib/CodeGen/<wbr class="">RegAllocFast.cpp<br class="">
><br class="">
> Modified: llvm/trunk/lib/CodeGen/<wbr class="">RegAllocFast.cpp<br class="">
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=323710&r1=323709&r2=323710&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/<wbr class="">CodeGen/RegAllocFast.cpp?rev=<wbr class="">323710&r1=323709&r2=323710&<wbr class="">view=diff</a><br class="">
> ==============================<wbr class="">==============================<wbr class="">==================<br class="">
> --- llvm/trunk/lib/CodeGen/<wbr class="">RegAllocFast.cpp (original)<br class="">
> +++ llvm/trunk/lib/CodeGen/<wbr class="">RegAllocFast.cpp Mon Jan 29 15:42:37 2018<br class="">
> @@ -193,9 +193,10 @@ namespace {<br class="">
> void spillVirtReg(<wbr class="">MachineBasicBlock::iterator MI, unsigned VirtReg);<br class="">
><br class="">
> void usePhysReg(MachineOperand &MO);<br class="">
> - void definePhysReg(MachineInstr &MI, MCPhysReg PhysReg, RegState NewState);<br class="">
> + void definePhysReg(<wbr class="">MachineBasicBlock::iterator MI, MCPhysReg PhysReg,<br class="">
> + RegState NewState);<br class="">
> unsigned calcSpillCost(MCPhysReg PhysReg) const;<br class="">
> - void assignVirtToPhysReg(LiveReg&, MCPhysReg PhysReg);<br class="">
> + void assignVirtToPhysReg(LiveReg &, MCPhysReg PhysReg);<br class="">
><br class="">
> LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {<br class="">
> return LiveVirtRegs.find(<wbr class="">TargetRegisterInfo::<wbr class="">virtReg2Index(VirtReg));<br class="">
> @@ -434,8 +435,8 @@ void RegAllocFast::usePhysReg(<wbr class="">MachineOpe<br class="">
> /// Mark PhysReg as reserved or free after spilling any virtregs. This is very<br class="">
> /// similar to defineVirtReg except the physreg is reserved instead of<br class="">
> /// allocated.<br class="">
> -void RegAllocFast::definePhysReg(<wbr class="">MachineInstr &MI, MCPhysReg PhysReg,<br class="">
> - RegState NewState) {<br class="">
> +void RegAllocFast::definePhysReg(<wbr class="">MachineBasicBlock::iterator MI,<br class="">
> + MCPhysReg PhysReg, RegState NewState) {<br class="">
> markRegUsedInInstr(PhysReg);<br class="">
> switch (unsigned VirtReg = PhysRegState[PhysReg]) {<br class="">
> case regDisabled:<br class="">
> @@ -857,7 +858,7 @@ void RegAllocFast::<wbr class="">allocateBasicBlock(Ma<br class="">
> // Add live-in registers as live.<br class="">
> for (const MachineBasicBlock::<wbr class="">RegisterMaskPair LI : MBB.liveins())<br class="">
> if (MRI->isAllocatable(LI.<wbr class="">PhysReg))<br class="">
> - definePhysReg(*MII, LI.PhysReg, regReserved);<br class="">
> + definePhysReg(MII, LI.PhysReg, regReserved);<br class="">
><br class="">
> VirtDead.clear();<br class="">
> Coalesced.clear();<br class="">
><br class="">
> Added: llvm/trunk/test/CodeGen/<wbr class="">AArch64/fast-regalloc-empty-<wbr class="">bb-with-liveins.mir<br class="">
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir?rev=323710&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/AArch64/fast-regalloc-<wbr class="">empty-bb-with-liveins.mir?rev=<wbr class="">323710&view=auto</a><br class="">
> ==============================<wbr class="">==============================<wbr class="">==================<br class="">
> --- llvm/trunk/test/CodeGen/<wbr class="">AArch64/fast-regalloc-empty-<wbr class="">bb-with-liveins.mir (added)<br class="">
> +++ llvm/trunk/test/CodeGen/<wbr class="">AArch64/fast-regalloc-empty-<wbr class="">bb-with-liveins.mir Mon Jan 29 15:42:37 2018<br class="">
> @@ -0,0 +1,26 @@<br class="">
> +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.<wbr class="">py<br class="">
> +# RUN: llc -mtriple aarch64-apple-ios -run-pass regallocfast -o - %s | FileCheck %s<br class="">
> +# This test used to crash the fast register alloc.<br class="">
> +# Basically, when a basic block has liveins, the fast regalloc<br class="">
> +# was deferencing the begin iterator of this block. However,<br class="">
> +# when this block is empty and it will just crashed!<br class="">
> +---<br class="">
> +name: crashing<br class="">
> +tracksRegLiveness: true<br class="">
> +body: |<br class="">
> + ; CHECK-LABEL: name: crashing<br class="">
> + ; CHECK: bb.0:<br class="">
> + ; CHECK: successors: %bb.1(0x80000000)<br class="">
> + ; CHECK: liveins: %x0, %x1<br class="">
> + ; CHECK: bb.1:<br class="">
> + ; CHECK: renamable %w0 = MOVi32imm -1<br class="">
> + ; CHECK: RET_ReallyLR implicit killed %w0<br class="">
> + bb.1:<br class="">
> + liveins: %x0, %x1<br class="">
> +<br class="">
> + bb.2:<br class="">
> + %0:gpr32 = MOVi32imm -1<br class="">
> + %w0 = COPY %0<br class="">
> + RET_ReallyLR implicit %w0<br class="">
> +<br class="">
> +...<br class="">
><br class="">
><br class="">
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