<font size=2 face="sans-serif">Hi Eric, </font><br><br><font size=2 face="sans-serif">I've reverted the change. Sorry
about breaking tests! </font><br><br><font size=2 face="sans-serif">Stefan </font><br><br><br><br><font size=1 color=#5f5f5f face="sans-serif">From:
</font><font size=1 face="sans-serif">Eric Christopher <echristo@gmail.com></font><br><font size=1 color=#5f5f5f face="sans-serif">To:
</font><font size=1 face="sans-serif">Stefan Pintilie <stefanp@ca.ibm.com></font><br><font size=1 color=#5f5f5f face="sans-serif">Cc:
</font><font size=1 face="sans-serif">llvm-commits@lists.llvm.org</font><br><font size=1 color=#5f5f5f face="sans-serif">Date:
</font><font size=1 face="sans-serif">2018/01/11 07:23 PM</font><br><font size=1 color=#5f5f5f face="sans-serif">Subject:
</font><font size=1 face="sans-serif">Re: [llvm] r322124
- [PowerPC] Manually schedule the prologue and epilogue</font><br><hr noshade><br><br><br><font size=3>Hi Stefan,</font><br><br><font size=3>I'm seeing some internal tests breaking with this, while
I'm working on a testcase would you mind terribly reverting? I'm also seeing
if I can duplicate using public code.</font><br><br><font size=3>Thanks!</font><br><br><font size=3>-eric</font><br><br><font size=3>On Tue, Jan 9, 2018 at 1:58 PM Stefan Pintilie via llvm-commits
<</font><a href="mailto:llvm-commits@lists.llvm.org"><font size=3 color=blue><u>llvm-commits@lists.llvm.org</u></font></a><font size=3>>
wrote:</font><br><font size=3>Author: stefanp<br>Date: Tue Jan 9 13:57:49 2018<br>New Revision: 322124<br><br>URL: </font><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject-3Frev-3D322124-26view-3Drev&d=DwMFaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=49spR2UR1xU856U9bA0eIMAhPpF3lrnwBpgJHMQL-Ic&m=_8JN5Cnrd_mRFtlqfSoqsqA1_Dl7ogxz-xyFzv-E7x4&s=UtKuHRm4WvwVAZLfd6C5BfXfBIyJw8f_j8FosNZT1GU&e=" target=_blank><font size=3 color=blue><u>http://llvm.org/viewvc/llvm-project?rev=322124&view=rev</u></font></a><font size=3><br>Log:<br>[PowerPC] Manually schedule the prologue and epilogue<br><br>This patch makes the following changes to the schedule of instructions
in the<br>prologue and epilogue.<br><br>The stack pointer update is moved down in the prologue so that the callee
saves<br>do not have to wait for the update to happen.<br>Saving the lr is moved down in the prologue to hide the latency of the
mflr.<br>The stack pointer is moved up in the epilogue so that restoring of the
lr can<br>happen sooner.<br>The mtlr is moved up in the epilogue so that it is away form the blr at
the end<br>of the epilogue. The latency of the mtlr can now be hidden by the loads
of the<br>callee saved registers.<br><br>This commit is almost identical to this one: r322036 except that two warnings<br>that broke build bots have been fixed.<br><br>The revision number is D41737 as before.<br><br>Modified:<br> llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp<br> llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll<br> llvm/trunk/test/CodeGen/PowerPC/ppc-redzone-alignment-bug.ll<br> llvm/trunk/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll<br> llvm/trunk/test/CodeGen/PowerPC/tls_get_addr_clobbers.ll<br> llvm/trunk/test/CodeGen/PowerPC/vsxD-Form-spills.ll<br><br>Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp<br>URL: </font><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_PowerPC_PPCFrameLowering.cpp-3Frev-3D322124-26r1-3D322123-26r2-3D322124-26view-3Ddiff&d=DwMFaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=49spR2UR1xU856U9bA0eIMAhPpF3lrnwBpgJHMQL-Ic&m=_8JN5Cnrd_mRFtlqfSoqsqA1_Dl7ogxz-xyFzv-E7x4&s=0CHhxJMEbAvGJXZxBI68OvXoBbm6A1ZXSzue0Q2vTp8&e=" target=_blank><font size=3 color=blue><u>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=322124&r1=322123&r2=322124&view=diff</u></font></a><font size=3><br>==============================================================================<br>--- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original)<br>+++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Tue Jan 9
13:57:49 2018<br>@@ -823,6 +823,39 @@ void PPCFrameLowering::emitPrologue(Mach<br> assert((isPPC64 || !MustSaveCR) &&<br> "Prologue CR saving supported only
in 64-bit mode");<br><br>+ // Check if we can move the stack update instruction (stdu) down
the prologue<br>+ // past the callee saves. Hopefully this will avoid the situation
where the<br>+ // saves are waiting for the update on the store with update
to complete.<br>+ MachineBasicBlock::iterator StackUpdateLoc = MBBI;<br>+ bool MovingStackUpdateDown = false;<br>+ // This optimization has a number of guards. At this point we are
being very<br>+ // cautious and we do not try to do this when we have a fast
call or<br>+ // we are using PIC base or we are using a frame pointer
or a base pointer.<br>+ // It would be possible to turn on this optimization under
these conditions<br>+ // as well but it would require further modifications to
the prologue and<br>+ // epilogue. For example, if we want to turn on this optimization
for<br>+ // functions that use frame pointers we would have to take
into consideration<br>+ // the fact that spills to the stack may be using r30 instead
of r1.<br>+ // Aside form that we need to have a non-zero frame and we need
to have a<br>+ // non-large frame size. Notice that we did not use !isLargeFrame
but we used<br>+ // isInt<16>(FrameSize) instead. This is important
because this guard has to<br>+ // be identical to the one in the epilogue and in the epilogue
the variable<br>+ // is defined as bool isLargeFrame = !isInt<16>(FrameSize);<br>+ if (FrameSize && !FI->hasFastCall() && !FI->usesPICBase()
&& !HasFP &&<br>+ !HasBP && isInt<16>(FrameSize)) {<br>+ const std::vector<CalleeSavedInfo> &Info = MFI.getCalleeSavedInfo();<br>+ for (unsigned i=0; i<Info.size(); i++) {<br>+ int FrIdx = Info[i].getFrameIdx();<br>+ if (FrIdx < 0) {<br>+ if (MFI.isFixedObjectIndex(FrIdx) &&
MFI.getObjectOffset(FrIdx) < 0) {<br>+ MFI.setObjectOffset(FrIdx, MFI.getObjectOffset(FrIdx)
+ NegFrameSize);<br>+ StackUpdateLoc++;<br>+ MovingStackUpdateDown = true;<br>+ }<br>+ }<br>+ }<br>+ }<br>+<br> // If we need to spill the CR and the LR but we don't have
two separate<br> // registers available, we must spill them one at a time<br> if (MustSaveCR && SingleScratchReg && MustSaveLR)
{<br>@@ -886,7 +919,7 @@ void PPCFrameLowering::emitPrologue(Mach<br> }<br><br> if (MustSaveLR)<br>- BuildMI(MBB, MBBI, dl, StoreInst)<br>+ BuildMI(MBB, StackUpdateLoc, dl, StoreInst)<br> .addReg(ScratchReg, getKillRegState(true))<br> .addImm(LROffset)<br> .addReg(SPReg);<br>@@ -954,7 +987,7 @@ void PPCFrameLowering::emitPrologue(Mach<br> HasSTUX = true;<br><br> } else if (!isLargeFrame) {<br>- BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)<br>+ BuildMI(MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg)<br> .addReg(SPReg)<br> .addImm(NegFrameSize)<br> .addReg(SPReg);<br>@@ -1194,6 +1227,12 @@ void PPCFrameLowering::emitPrologue(Mach<br> }<br><br> int Offset = MFI.getObjectOffset(CSI[I].getFrameIdx());<br>+ // We have changed the object offset above but we
do not want to change<br>+ // the actual offsets in the CFI instruction
so we have to undo the<br>+ // offset change here.<br>+ if (MovingStackUpdateDown)<br>+ Offset -= NegFrameSize;<br>+<br> unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(<br> nullptr, MRI->getDwarfRegNum(Reg,
true), Offset));<br> BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))<br>@@ -1339,6 +1378,23 @@ void PPCFrameLowering::emitEpilogue(Mach<br> unsigned RBReg = SPReg;<br> unsigned SPAdd = 0;<br><br>+ // Check if we can move the stack update instruction up the epilogue<br>+ // past the callee saves. This will allow the move to LR
instruction<br>+ // to be executed before the restores of the callee saves
which means<br>+ // that the callee saves can hide the latency from the MTLR
instrcution.<br>+ MachineBasicBlock::iterator StackUpdateLoc = MBBI;<br>+ if (FrameSize && !FI->hasFastCall() && !FI->usesPICBase()
&& !HasFP &&<br>+ !HasBP && !isLargeFrame) {<br>+ const std::vector< CalleeSavedInfo > & Info =
MFI.getCalleeSavedInfo();<br>+ for (unsigned i=0; i<Info.size(); i++) {<br>+ int FrIdx = Info[i].getFrameIdx();<br>+ if (FrIdx < 0) {<br>+ if (MFI.isFixedObjectIndex(FrIdx) &&
MFI.getObjectOffset(FrIdx) < 0)<br>+ StackUpdateLoc--;<br>+ }<br>+ }<br>+ }<br>+<br> if (FrameSize) {<br> // In the prologue, the loaded (or persistent) stack
pointer value is<br> // offset by the STDU/STDUX/STWU/STWUX instruction.
For targets with red<br>@@ -1368,7 +1424,7 @@ void PPCFrameLowering::emitEpilogue(Mach<br> }<br> } else if (!isLargeFrame && !HasBP &&
!MFI.hasVarSizedObjects()) {<br> if (HasRedZone) {<br>- BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)<br>+ BuildMI(MBB, StackUpdateLoc, dl, AddImmInst,
SPReg)<br> .addReg(SPReg)<br> .addImm(FrameSize);<br> } else {<br>@@ -1392,7 +1448,7 @@ void PPCFrameLowering::emitEpilogue(Mach<br> .addReg(FPReg);<br> RBReg = FPReg;<br> }<br>- BuildMI(MBB, MBBI, dl, LoadInst, RBReg)<br>+ BuildMI(MBB, StackUpdateLoc, dl, LoadInst, RBReg)<br> .addImm(0)<br> .addReg(SPReg);<br> }<br>@@ -1425,7 +1481,7 @@ void PPCFrameLowering::emitEpilogue(Mach<br> // a base register anyway, because it may happen to be R0.<br> bool LoadedLR = false;<br> if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd))
{<br>- BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)<br>+ BuildMI(MBB, StackUpdateLoc, dl, LoadInst, ScratchReg)<br> .addImm(LROffset+SPAdd)<br> .addReg(RBReg);<br> LoadedLR = true;<br>@@ -1497,7 +1553,7 @@ void PPCFrameLowering::emitEpilogue(Mach<br> .addReg(TempReg, getKillRegState(i ==
e-1));<br><br> if (MustSaveLR)<br>- BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);<br>+ BuildMI(MBB, StackUpdateLoc, dl, MTLRInst).addReg(ScratchReg);<br><br> // Callee pop calling convention. Pop parameter/linkage area.
Used for tail<br> // call optimization<br><br>Modified: llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll<br>URL: </font><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_PowerPC_MCSE-2Dcaller-2Dpreserved-2Dreg.ll-3Frev-3D322124-26r1-3D322123-26r2-3D322124-26view-3Ddiff&d=DwMFaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=49spR2UR1xU856U9bA0eIMAhPpF3lrnwBpgJHMQL-Ic&m=_8JN5Cnrd_mRFtlqfSoqsqA1_Dl7ogxz-xyFzv-E7x4&s=drt_rver31lXXIFYLNnHwAcCES6Z-UnqcMnfZNc6eDY&e=" target=_blank><font size=3 color=blue><u>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll?rev=322124&r1=322123&r2=322124&view=diff</u></font></a><font size=3><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll (original)<br>+++ llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll Tue Jan
9 13:57:49 2018<br>@@ -15,12 +15,12 @@<br> define noalias i8* @_ZN2CC3funEv(%class.CC* %this) {<br> ; CHECK-LABEL: _ZN2CC3funEv:<br> ; CHECK: mflr 0<br>-; CHECK-NEXT: std 0, 16(1)<br>-; CHECK-NEXT: stdu 1, -48(1)<br> ; CHECK-NEXT: .cfi_def_cfa_offset 48<br> ; CHECK-NEXT: .cfi_offset lr, 16<br> ; CHECK-NEXT: .cfi_offset r30, -16<br>-; CHECK-NEXT: std 30, 32(1)<br>+; CHECK-NEXT: std 30, -16(1)<br>+; CHECK-NEXT: std 0, 16(1)<br>+; CHECK-NEXT: stdu 1, -48(1)<br> ; CHECK-NEXT: mr 30, 3<br> ; CHECK-NEXT: ld 12, 0(30)<br> ; CHECK-NEXT: std 2, 24(1)<br>@@ -38,11 +38,11 @@ define noalias i8* @_ZN2CC3funEv(%class.<br> ; CHECK-NEXT: mr 3, 30<br> ; CHECK-NEXT: bl _ZN2CC3barEPi<br> ; CHECK-NEXT: nop<br>-; CHECK: ld 30, 32(1)<br>-; CHECK-NEXT: li 3, 0<br>+; CHECK: li 3, 0<br> ; CHECK-NEXT: addi 1, 1, 48<br> ; CHECK-NEXT: ld 0, 16(1)<br> ; CHECK-NEXT: mtlr 0<br>+; CHECK: ld 30, -16(1)<br> ; CHECK-NEXT: blr<br> entry:<br> %foo = getelementptr inbounds %class.CC, %class.CC* %this,
i64 0, i32 0, i32 0<br><br>Modified: llvm/trunk/test/CodeGen/PowerPC/ppc-redzone-alignment-bug.ll<br>URL: </font><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_PowerPC_ppc-2Dredzone-2Dalignment-2Dbug.ll-3Frev-3D322124-26r1-3D322123-26r2-3D322124-26view-3Ddiff&d=DwMFaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=49spR2UR1xU856U9bA0eIMAhPpF3lrnwBpgJHMQL-Ic&m=_8JN5Cnrd_mRFtlqfSoqsqA1_Dl7ogxz-xyFzv-E7x4&s=476jjE_IvsqLNiAK-w6a4N-8dbJHRDZZwtWhaidVFXQ&e=" target=_blank><font size=3 color=blue><u>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc-redzone-alignment-bug.ll?rev=322124&r1=322123&r2=322124&view=diff</u></font></a><font size=3><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/PowerPC/ppc-redzone-alignment-bug.ll (original)<br>+++ llvm/trunk/test/CodeGen/PowerPC/ppc-redzone-alignment-bug.ll Tue Jan
9 13:57:49 2018<br>@@ -16,12 +16,12 @@ entry:<br> ; stfd 14, 416(1)<br><br> ; After the fix by patch D34337:<br>+; CHECK-LE:std 15, -280(1)<br>+; CHECK-LE:stfd 14, -144(1)<br> ; CHECK-LE: stdu 1, -528(1)<br>-; CHECK-LE:std 15, 248(1)<br>-; CHECK-LE:stfd 14, 384(1)<br>+; CHECK-BE:std 15, -280(1)<br>+; CHECK-BE:stfd 14, -144(1)<br> ; CHECK-BE: stdu 1, -544(1)<br>-; CHECK-BE:std 15, 264(1)<br>-; CHECK-BE:stfd 14, 400(1)<br> }<br><br> define signext i32 @foo() {<br><br>Modified: llvm/trunk/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll<br>URL: </font><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_PowerPC_ppc-2Dshrink-2Dwrapping.ll-3Frev-3D322124-26r1-3D322123-26r2-3D322124-26view-3Ddiff&d=DwMFaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=49spR2UR1xU856U9bA0eIMAhPpF3lrnwBpgJHMQL-Ic&m=_8JN5Cnrd_mRFtlqfSoqsqA1_Dl7ogxz-xyFzv-E7x4&s=CCXQap-T2xo19ePobaICt6u1lxFhlqr5RT6SZDYWirU&e=" target=_blank><font size=3 color=blue><u>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll?rev=322124&r1=322123&r2=322124&view=diff</u></font></a><font size=3><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll (original)<br>+++ llvm/trunk/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll Tue Jan
9 13:57:49 2018<br>@@ -110,7 +110,7 @@ declare i32 @doSomething(i32, i32*)<br> ;<br> ; Epilogue code.<br> ; CHECK: mtlr {{[0-9]+}}<br>-; CHECK-NEXT: blr<br>+; CHECK: blr<br> ;<br> ; ENABLE: .[[ELSE_LABEL]]: # %if.else<br> ; Shift second argument by one and store into returned register.<br>@@ -171,7 +171,7 @@ declare i32 @something(...)<br> ; Next BB<br> ; CHECK: %for.end<br> ; CHECK: mtlr {{[0-9]+}}<br>-; CHECK-NEXT: blr<br>+; CHECK: blr<br> define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {<br> entry:<br> br label %for.preheader<br>@@ -209,9 +209,9 @@ for.end:<br> ; Make sure we save the link register<br> ; CHECK: mflr {{[0-9]+}}<br> ;<br>-; DISABLE: cmplwi 0, 3, 0<br>-; DISABLE-NEXT: std<br>+; DISABLE: std<br> ; DISABLE-NEXT: std<br>+; DISABLE: cmplwi 0, 3, 0<br> ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]<br> ;<br> ; Loop preheader<br>@@ -240,7 +240,7 @@ for.end:<br> ; DISABLE: .[[EPILOG_BB]]: # %if.end<br> ; Epilog code<br> ; CHECK: mtlr {{[0-9]+}}<br>-; CHECK-NEXT: blr<br>+; CHECK: blr<br> ;<br> ; ENABLE: .[[ELSE_LABEL]]: # %if.else<br> ; Shift second argument by one and store into returned register.<br>@@ -291,9 +291,9 @@ declare void @somethingElse(...)<br> ; Make sure we save the link register<br> ; CHECK: mflr {{[0-9]+}}<br> ;<br>-; DISABLE: cmplwi 0, 3, 0<br>-; DISABLE-NEXT: std<br>+; DISABLE: std<br> ; DISABLE-NEXT: std<br>+; DISABLE: cmplwi 0, 3, 0<br> ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]<br> ;<br> ; CHECK: bl somethingElse<br>@@ -322,7 +322,7 @@ declare void @somethingElse(...)<br> ;<br> ; Epilogue code.<br> ; CHECK: mtlr {{[0-9]+}}<br>-; CHECK-NEXT: blr<br>+; CHECK: blr<br> ;<br> ; ENABLE: .[[ELSE_LABEL]]: # %if.else<br> ; Shift second argument by one and store into returned register.<br><br>Modified: llvm/trunk/test/CodeGen/PowerPC/tls_get_addr_clobbers.ll<br>URL: </font><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_PowerPC_tls-5Fget-5Faddr-5Fclobbers.ll-3Frev-3D322124-26r1-3D322123-26r2-3D322124-26view-3Ddiff&d=DwMFaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=49spR2UR1xU856U9bA0eIMAhPpF3lrnwBpgJHMQL-Ic&m=_8JN5Cnrd_mRFtlqfSoqsqA1_Dl7ogxz-xyFzv-E7x4&s=wj5YcGValR1qg6W_Qg0Ccsqf1vOWmR9PcZH3omTec_4&e=" target=_blank><font size=3 color=blue><u>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls_get_addr_clobbers.ll?rev=322124&r1=322123&r2=322124&view=diff</u></font></a><font size=3><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/PowerPC/tls_get_addr_clobbers.ll (original)<br>+++ llvm/trunk/test/CodeGen/PowerPC/tls_get_addr_clobbers.ll Tue Jan
9 13:57:49 2018<br>@@ -6,7 +6,7 @@ define void @test_foo(i32* nocapture %x0<br> entry:<br><br> ; CHECK-LABEL: test_foo:<br>-; CHECK: stdu 1, {{-?[0-9]+}}(1)<br>+; CHECK-DAG: stdu 1, {{-?[0-9]+}}(1)<br> ; CHECK-DAG: mr [[BACKUP_3:[0-9]+]], 3<br> ; CHECK-DAG: mr [[BACKUP_4:[0-9]+]], 4<br> ; CHECK-DAG: mr [[BACKUP_5:[0-9]+]], 5<br>@@ -15,14 +15,14 @@ entry:<br> ; CHECK-DAG: mr [[BACKUP_8:[0-9]+]], 8<br> ; CHECK-DAG: mr [[BACKUP_9:[0-9]+]], 9<br> ; CHECK-DAG: mr [[BACKUP_10:[0-9]+]], 10<br>-; CHECK-DAG: std [[BACKUP_3]], {{[0-9]+}}(1)<br>-; CHECK-DAG: std [[BACKUP_4]], {{[0-9]+}}(1)<br>-; CHECK-DAG: std [[BACKUP_5]], {{[0-9]+}}(1)<br>-; CHECK-DAG: std [[BACKUP_6]], {{[0-9]+}}(1)<br>-; CHECK-DAG: std [[BACKUP_7]], {{[0-9]+}}(1)<br>-; CHECK-DAG: std [[BACKUP_8]], {{[0-9]+}}(1)<br>-; CHECK-DAG: std [[BACKUP_9]], {{[0-9]+}}(1)<br>-; CHECK-DAG: std [[BACKUP_10]], {{[0-9]+}}(1)<br>+; CHECK-DAG: std [[BACKUP_3]], {{-?[0-9]+}}(1)<br>+; CHECK-DAG: std [[BACKUP_4]], {{-?[0-9]+}}(1)<br>+; CHECK-DAG: std [[BACKUP_5]], {{-?[0-9]+}}(1)<br>+; CHECK-DAG: std [[BACKUP_6]], {{-?[0-9]+}}(1)<br>+; CHECK-DAG: std [[BACKUP_7]], {{-?[0-9]+}}(1)<br>+; CHECK-DAG: std [[BACKUP_8]], {{-?[0-9]+}}(1)<br>+; CHECK-DAG: std [[BACKUP_9]], {{-?[0-9]+}}(1)<br>+; CHECK-DAG: std [[BACKUP_10]], {{-?[0-9]+}}(1)<br> ; CHECK: bl __tls_get_addr<br> ; CHECK-DAG: stw 3, 0([[BACKUP_3]])<br> ; CHECK-DAG: stw 3, 0([[BACKUP_4]])<br><br>Modified: llvm/trunk/test/CodeGen/PowerPC/vsxD-Form-spills.ll<br>URL: </font><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_PowerPC_vsxD-2DForm-2Dspills.ll-3Frev-3D322124-26r1-3D322123-26r2-3D322124-26view-3Ddiff&d=DwMFaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=49spR2UR1xU856U9bA0eIMAhPpF3lrnwBpgJHMQL-Ic&m=_8JN5Cnrd_mRFtlqfSoqsqA1_Dl7ogxz-xyFzv-E7x4&s=69WKHp0rovtOanTJcMCycWqK5btIPuyPaiKRrzOlADY&e=" target=_blank><font size=3 color=blue><u>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vsxD-Form-spills.ll?rev=322124&r1=322123&r2=322124&view=diff</u></font></a><font size=3><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/PowerPC/vsxD-Form-spills.ll (original)<br>+++ llvm/trunk/test/CodeGen/PowerPC/vsxD-Form-spills.ll Tue Jan 9
13:57:49 2018<br>@@ -4,35 +4,37 @@<br> define <4 x i32> @testSpill(<4 x i32> %a, <4 x i32>
%b) {<br><br> ; CHECK-LABEL: testSpill:<br>-; CHECK: li 11, 80<br>-; CHECK: li 12, 96<br>-; CHECK: li 3, 48<br>-; CHECK: li 10, 64<br>-; CHECK: stxvd2x 62, 1, 11 # 16-byte Folded Spill<br>-; CHECK: stxvd2x 63, 1, 12 # 16-byte Folded Spill<br>-; CHECK: stxvd2x 60, 1, 3 # 16-byte Folded Spill<br>-; CHECK: stxvd2x 61, 1, 10 # 16-byte Folded Spill<br>-; CHECK: li 9, 96<br>-; CHECK: li 10, 80<br>-; CHECK: li 11, 64<br>-; CHECK: li 12, 48<br>-; CHECK: lxvd2x 63, 1, 9 # 16-byte Folded Reload<br>-; CHECK: lxvd2x 62, 1, 10 # 16-byte Folded Reload<br>-; CHECK: lxvd2x 61, 1, 11 # 16-byte Folded Reload<br>-; CHECK: lxvd2x 60, 1, 12 # 16-byte Folded Reload<br>+; CHECK-DAG: li [[REG64:[0-9]+]], -64<br>+; CHECK-DAG: li [[REG48:[0-9]+]], -48<br>+; CHECK-DAG: li [[REG32:[0-9]+]], -32<br>+; CHECK-DAG: li [[REG16:[0-9]+]], -16<br>+; CHECK-NOT: li<br>+; CHECK-DAG: stxvd2x 60, 1, [[REG64]] # 16-byte Folded Spill<br>+; CHECK-DAG: stxvd2x 61, 1, [[REG48]] # 16-byte Folded Spill<br>+; CHECK-DAG: stxvd2x 62, 1, [[REG32]] # 16-byte Folded Spill<br>+; CHECK-DAG: stxvd2x 63, 1, [[REG16]] # 16-byte Folded Spill<br>+; CHECK: std 0, 16(1)<br>+; CHECK-DAG: li [[REG16:[0-9]+]], -16<br>+; CHECK-DAG: li [[REG32:[0-9]+]], -32<br>+; CHECK-DAG: li [[REG48:[0-9]+]], -48<br>+; CHECK-DAG: li [[REG64:[0-9]+]], -64<br> ; CHECK: mtlr 0<br>+; CHECK-DAG: lxvd2x 63, 1, [[REG16]] # 16-byte Folded Reload<br>+; CHECK-DAG: lxvd2x 62, 1, [[REG32]] # 16-byte Folded Reload<br>+; CHECK-DAG: lxvd2x 61, 1, [[REG48]] # 16-byte Folded Reload<br>+; CHECK-DAG: lxvd2x 60, 1, [[REG64]] # 16-byte Folded Reload<br> ; CHECK-NEXT: blr<br> ;<br> ; CHECK-PWR9-LABEL: testSpill:<br>-; CHECK-PWR9: stxv 62, 80(1) # 16-byte Folded Spill<br>-; CHECK-PWR9: stxv 63, 96(1) # 16-byte Folded Spill<br>-; CHECK-PWR9: stxv 60, 48(1) # 16-byte Folded Spill<br>-; CHECK-PWR9: stxv 61, 64(1) # 16-byte Folded Spill<br>-; CHECK-PWR9: lxv 63, 96(1) # 16-byte Folded Reload<br>-; CHECK-PWR9: lxv 62, 80(1) # 16-byte Folded Reload<br>-; CHECK-PWR9: lxv 61, 64(1) # 16-byte Folded Reload<br>-; CHECK-PWR9: lxv 60, 48(1) # 16-byte Folded Reload<br>+; CHECK-PWR9-DAG: stxv 60, -64(1) # 16-byte Folded Spill<br>+; CHECK-PWR9-DAG: stxv 61, -48(1) # 16-byte Folded Spill<br>+; CHECK-PWR9-DAG: stxv 62, -32(1) # 16-byte Folded Spill<br>+; CHECK-PWR9-DAG: stxv 63, -16(1) # 16-byte Folded Spill<br> ; CHECK-PWR9: mtlr 0<br>+; CHECK-PWR9-DAG: lxv 63, -16(1) # 16-byte Folded Reload<br>+; CHECK-PWR9-DAG: lxv 62, -32(1) # 16-byte Folded Reload<br>+; CHECK-PWR9-DAG: lxv 61, -48(1) # 16-byte Folded Reload<br>+; CHECK-PWR9-DAG: lxv 60, -64(1) # 16-byte Folded Reload<br> ; CHECK-PWR9-NEXT: blr<br><br> entry:<br><br><br>_______________________________________________<br>llvm-commits mailing list</font><font size=3 color=blue><u><br></u></font><a href="mailto:llvm-commits@lists.llvm.org" target=_blank><font size=3 color=blue><u>llvm-commits@lists.llvm.org</u></font></a><font size=3 color=blue><u><br></u></font><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.llvm.org_cgi-2Dbin_mailman_listinfo_llvm-2Dcommits&d=DwMFaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=49spR2UR1xU856U9bA0eIMAhPpF3lrnwBpgJHMQL-Ic&m=_8JN5Cnrd_mRFtlqfSoqsqA1_Dl7ogxz-xyFzv-E7x4&s=u3OlVZobW4kR321fiH8mB-3au8GeTD94nsAwHH7SmI0&e=" target=_blank><font size=3 color=blue><u>http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</u></font></a><br><BR>