<div dir="ltr">Hello Matt,<br><br>This commit broke tests on the next builders:<br><br><a href="http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/6668">http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/6668</a><br><a href="http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu">http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu</a><br><br>. . .<br>Unexpected Passing Tests (1):<br> LLVM :: Transforms/StructurizeCFG/AMDGPU/backedge-id-bug-xfail.ll<br><br>Please have a look?<br>BTW do you get email notifications from the master on build failures?<br><br>Thanks<br><br>Galina<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Jan 4, 2018 at 9:23 AM, Matt Arsenault via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: arsenm<br>
Date: Thu Jan 4 09:23:24 2018<br>
New Revision: 321806<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=321806&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=321806&view=rev</a><br>
Log:<br>
StructurizeCFG: xfail one of the testcases from r321751<br>
<br>
It fails with -verify-region-info. This seems to be a issue<br>
with RegionInfo itself which existed before.<br>
<br>
Added:<br>
llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/<wbr>backedge-id-bug-xfail.ll<br>
Modified:<br>
llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/<wbr>backedge-id-bug.ll<br>
<br>
Added: llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/<wbr>backedge-id-bug-xfail.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug-xfail.ll?rev=321806&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/StructurizeCFG/<wbr>AMDGPU/backedge-id-bug-xfail.<wbr>ll?rev=321806&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/<wbr>backedge-id-bug-xfail.ll (added)<br>
+++ llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/<wbr>backedge-id-bug-xfail.ll Thu Jan 4 09:23:24 2018<br>
@@ -0,0 +1,77 @@<br>
+; XFAIL: *<br>
+; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -structurizecfg -verify-region-info %s<br>
+<br>
+; FIXME: Merge into backedge-id-bug<br>
+; Variant which has an issue with region construction<br>
+<br>
+define amdgpu_kernel void @loop_backedge_misidentified_<wbr>alt(i32 addrspace(1)* %arg0) #0 {<br>
+entry:<br>
+ %tmp = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16<br>
+ %load1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef<br>
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()<br>
+ %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i32 %tid<br>
+ %i.initial = load volatile i32, i32 addrspace(1)* %gep, align 4<br>
+ br label %LOOP.HEADER<br>
+<br>
+LOOP.HEADER:<br>
+ %i = phi i32 [ %i.final, %END_ELSE_BLOCK ], [ %i.initial, %entry ]<br>
+ call void asm sideeffect "s_nop 0x100b ; loop $0 ", "r,~{memory}"(i32 %i) #0<br>
+ %tmp12 = zext i32 %i to i64<br>
+ %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 %tmp12<br>
+ %tmp14 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp13, align 16<br>
+ %tmp15 = extractelement <4 x i32> %tmp14, i64 0<br>
+ %tmp16 = and i32 %tmp15, 65535<br>
+ %tmp17 = icmp eq i32 %tmp16, 1<br>
+ br i1 %tmp17, label %bb18, label %bb62<br>
+<br>
+bb18:<br>
+ %tmp19 = extractelement <2 x i32> %tmp, i64 0<br>
+ %tmp22 = lshr i32 %tmp19, 16<br>
+ %tmp24 = urem i32 %tmp22, 52<br>
+ %tmp25 = mul nuw nsw i32 %tmp24, 52<br>
+ br label %INNER_LOOP<br>
+<br>
+INNER_LOOP:<br>
+ %inner.loop.j = phi i32 [ %tmp25, %bb18 ], [ %inner.loop.j.inc, %INNER_LOOP ]<br>
+ call void asm sideeffect "; inner loop body", ""() #0<br>
+ %inner.loop.j.inc = add nsw i32 %inner.loop.j, 1<br>
+ %inner.loop.cmp = icmp eq i32 %inner.loop.j, 0<br>
+ br i1 %inner.loop.cmp, label %INNER_LOOP_BREAK, label %INNER_LOOP<br>
+<br>
+INNER_LOOP_BREAK:<br>
+ %tmp59 = extractelement <4 x i32> %tmp14, i64 2<br>
+ call void asm sideeffect "s_nop 23 ", "~{memory}"() #0<br>
+ br label %END_ELSE_BLOCK<br>
+<br>
+bb62:<br>
+ %load13 = icmp ult i32 %tmp16, 271<br>
+ ;br i1 %load13, label %bb64, label %INCREMENT_I<br>
+ ; branching directly to the return avoids the bug<br>
+ br i1 %load13, label %RETURN, label %INCREMENT_I<br>
+<br>
+<br>
+bb64:<br>
+ call void asm sideeffect "s_nop 42", "~{memory}"() #0<br>
+ br label %RETURN<br>
+<br>
+INCREMENT_I:<br>
+ %inc.i = add i32 %i, 1<br>
+ call void asm sideeffect "s_nop 0x1336 ; increment $0", "v,~{memory}"(i32 %inc.i) #0<br>
+ br label %END_ELSE_BLOCK<br>
+<br>
+END_ELSE_BLOCK:<br>
+ %i.final = phi i32 [ %tmp59, %INNER_LOOP_BREAK ], [ %inc.i, %INCREMENT_I ]<br>
+ call void asm sideeffect "s_nop 0x1337 ; end else block $0", "v,~{memory}"(i32 %i.final) #0<br>
+ %cmp.end.else.block = icmp eq i32 %i.final, -1<br>
+ br i1 %cmp.end.else.block, label %RETURN, label %LOOP.HEADER<br>
+<br>
+RETURN:<br>
+ call void asm sideeffect "s_nop 0x99 ; ClosureEval return", "~{memory}"() #0<br>
+ store volatile <2 x float> %load1, <2 x float> addrspace(1)* undef, align 8<br>
+ ret void<br>
+}<br>
+<br>
+declare i32 @llvm.amdgcn.workitem.id.x() #1<br>
+<br>
+attributes #0 = { convergent nounwind }<br>
+attributes #1 = { convergent nounwind readnone }<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/<wbr>backedge-id-bug.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll?rev=321806&r1=321805&r2=321806&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/StructurizeCFG/<wbr>AMDGPU/backedge-id-bug.ll?rev=<wbr>321806&r1=321805&r2=321806&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/<wbr>backedge-id-bug.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>StructurizeCFG/AMDGPU/<wbr>backedge-id-bug.ll Thu Jan 4 09:23:24 2018<br>
@@ -155,145 +155,7 @@ RETURN:<br>
<br>
; The same function, except break to return block goes directly to the<br>
; return, which managed to hide the bug.<br>
-define amdgpu_kernel void @loop_backedge_misidentified_<wbr>alt(i32 addrspace(1)* %arg0) #0 {<br>
-; CHECK-LABEL: @loop_backedge_misidentified_<wbr>alt(<br>
-; CHECK-NEXT: entry:<br>
-; CHECK-NEXT: [[TMP:%.*]] = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16<br>
-; CHECK-NEXT: [[LOAD1:%.*]] = load volatile <2 x float>, <2 x float> addrspace(1)* undef<br>
-; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()<br>
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG0:%.*]], i32 [[TID]]<br>
-; CHECK-NEXT: [[I_INITIAL:%.*]] = load volatile i32, i32 addrspace(1)* [[GEP]], align 4<br>
-; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]<br>
-; CHECK: LOOP.HEADER:<br>
-; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_INITIAL]], [[ENTRY:%.*]] ], [ [[TMP9:%.*]], [[FLOW3:%.*]] ]<br>
-; CHECK-NEXT: call void asm sideeffect "s_nop 0x100b<br>
-; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[I]] to i64<br>
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 [[TMP12]]<br>
-; CHECK-NEXT: [[TMP14:%.*]] = load <4 x i32>, <4 x i32> addrspace(1)* [[TMP13]], align 16<br>
-; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP14]], i64 0<br>
-; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 65535<br>
-; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[TMP16]], 1<br>
-; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[TMP17]], true<br>
-; CHECK-NEXT: br i1 [[TMP0]], label [[BB62:%.*]], label [[FLOW:%.*]]<br>
-; CHECK: Flow1:<br>
-; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[INC_I:%.*]], [[INCREMENT_I:%.*]] ], [ undef, [[BB62]] ]<br>
-; CHECK-NEXT: [[TMP2:%.*]] = phi i1 [ true, [[INCREMENT_I]] ], [ false, [[BB62]] ]<br>
-; CHECK-NEXT: br label [[FLOW]]<br>
-; CHECK: bb18:<br>
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i32> [[TMP]], i64 0<br>
-; CHECK-NEXT: [[TMP22:%.*]] = lshr i32 [[TMP19]], 16<br>
-; CHECK-NEXT: [[TMP24:%.*]] = urem i32 [[TMP22]], 52<br>
-; CHECK-NEXT: [[TMP25:%.*]] = mul nuw nsw i32 [[TMP24]], 52<br>
-; CHECK-NEXT: br label [[INNER_LOOP:%.*]]<br>
-; CHECK: Flow2:<br>
-; CHECK-NEXT: [[TMP3:%.*]] = phi i32 [ [[TMP59:%.*]], [[INNER_LOOP_BREAK:%.*]] ], [ [[TMP6:%.*]], [[FLOW]] ]<br>
-; CHECK-NEXT: [[TMP4:%.*]] = phi i1 [ true, [[INNER_LOOP_BREAK]] ], [ [[TMP7:%.*]], [[FLOW]] ]<br>
-; CHECK-NEXT: br i1 [[TMP4]], label [[END_ELSE_BLOCK:%.*]], label [[FLOW3]]<br>
-; CHECK: INNER_LOOP:<br>
-; CHECK-NEXT: [[INNER_LOOP_J:%.*]] = phi i32 [ [[INNER_LOOP_J_INC:%.*]], [[INNER_LOOP]] ], [ [[TMP25]], [[BB18:%.*]] ]<br>
-; CHECK-NEXT: call void asm sideeffect "<br>
-; CHECK-NEXT: [[INNER_LOOP_J_INC]] = add nsw i32 [[INNER_LOOP_J]], 1<br>
-; CHECK-NEXT: [[INNER_LOOP_CMP:%.*]] = icmp eq i32 [[INNER_LOOP_J]], 0<br>
-; CHECK-NEXT: br i1 [[INNER_LOOP_CMP]], label [[INNER_LOOP_BREAK]], label [[INNER_LOOP]]<br>
-; CHECK: INNER_LOOP_BREAK:<br>
-; CHECK-NEXT: [[TMP59]] = extractelement <4 x i32> [[TMP14]], i64 2<br>
-; CHECK-NEXT: call void asm sideeffect "s_nop 23 ", "~{memory}"() #0<br>
-; CHECK-NEXT: br label [[FLOW2:%.*]]<br>
-; CHECK: bb62:<br>
-; CHECK-NEXT: [[LOAD13:%.*]] = icmp ult i32 [[TMP16]], 271<br>
-; CHECK-NEXT: [[TMP5:%.*]] = xor i1 [[LOAD13]], true<br>
-; CHECK-NEXT: br i1 [[TMP5]], label [[INCREMENT_I]], label [[FLOW1:%.*]]<br>
-; CHECK: bb64:<br>
-; CHECK-NEXT: call void asm sideeffect "s_nop 42", "~{memory}"() #0<br>
-; CHECK-NEXT: br label [[RETURN:%.*]]<br>
-; CHECK: Flow:<br>
-; CHECK-NEXT: [[TMP6]] = phi i32 [ [[TMP1]], [[FLOW1]] ], [ undef, [[LOOP_HEADER]] ]<br>
-; CHECK-NEXT: [[TMP7]] = phi i1 [ [[TMP2]], [[FLOW1]] ], [ false, [[LOOP_HEADER]] ]<br>
-; CHECK-NEXT: [[TMP8:%.*]] = phi i1 [ false, [[FLOW1]] ], [ true, [[LOOP_HEADER]] ]<br>
-; CHECK-NEXT: br i1 [[TMP8]], label [[BB18]], label [[FLOW2]]<br>
-; CHECK: INCREMENT_I:<br>
-; CHECK-NEXT: [[INC_I]] = add i32 [[I]], 1<br>
-; CHECK-NEXT: call void asm sideeffect "s_nop 0x1336<br>
-; CHECK-NEXT: br label [[FLOW1]]<br>
-; CHECK: END_ELSE_BLOCK:<br>
-; CHECK-NEXT: [[I_FINAL:%.*]] = phi i32 [ [[TMP3]], [[FLOW2]] ]<br>
-; CHECK-NEXT: call void asm sideeffect "s_nop 0x1337<br>
-; CHECK-NEXT: [[CMP_END_ELSE_BLOCK:%.*]] = icmp eq i32 [[I_FINAL]], -1<br>
-; CHECK-NEXT: br label [[FLOW3]]<br>
-; CHECK: Flow3:<br>
-; CHECK-NEXT: [[TMP9]] = phi i32 [ [[I_FINAL]], [[END_ELSE_BLOCK]] ], [ undef, [[FLOW2]] ]<br>
-; CHECK-NEXT: [[TMP10:%.*]] = phi i1 [ [[CMP_END_ELSE_BLOCK]], [[END_ELSE_BLOCK]] ], [ true, [[FLOW2]] ]<br>
-; CHECK-NEXT: br i1 [[TMP10]], label [[RETURN]], label [[LOOP_HEADER]]<br>
-; CHECK: RETURN:<br>
-; CHECK-NEXT: call void asm sideeffect "s_nop 0x99<br>
-; CHECK-NEXT: store volatile <2 x float> [[LOAD1]], <2 x float> addrspace(1)* undef, align 8<br>
-; CHECK-NEXT: ret void<br>
-;<br>
-entry:<br>
- %tmp = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16<br>
- %load1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef<br>
- %tid = call i32 @llvm.amdgcn.workitem.id.x()<br>
- %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i32 %tid<br>
- %i.initial = load volatile i32, i32 addrspace(1)* %gep, align 4<br>
- br label %LOOP.HEADER<br>
-<br>
-LOOP.HEADER:<br>
- %i = phi i32 [ %i.final, %END_ELSE_BLOCK ], [ %i.initial, %entry ]<br>
- call void asm sideeffect "s_nop 0x100b ; loop $0 ", "r,~{memory}"(i32 %i) #0<br>
- %tmp12 = zext i32 %i to i64<br>
- %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 %tmp12<br>
- %tmp14 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp13, align 16<br>
- %tmp15 = extractelement <4 x i32> %tmp14, i64 0<br>
- %tmp16 = and i32 %tmp15, 65535<br>
- %tmp17 = icmp eq i32 %tmp16, 1<br>
- br i1 %tmp17, label %bb18, label %bb62<br>
-<br>
-bb18:<br>
- %tmp19 = extractelement <2 x i32> %tmp, i64 0<br>
- %tmp22 = lshr i32 %tmp19, 16<br>
- %tmp24 = urem i32 %tmp22, 52<br>
- %tmp25 = mul nuw nsw i32 %tmp24, 52<br>
- br label %INNER_LOOP<br>
-<br>
-INNER_LOOP:<br>
- %inner.loop.j = phi i32 [ %tmp25, %bb18 ], [ %inner.loop.j.inc, %INNER_LOOP ]<br>
- call void asm sideeffect "; inner loop body", ""() #0<br>
- %inner.loop.j.inc = add nsw i32 %inner.loop.j, 1<br>
- %inner.loop.cmp = icmp eq i32 %inner.loop.j, 0<br>
- br i1 %inner.loop.cmp, label %INNER_LOOP_BREAK, label %INNER_LOOP<br>
-<br>
-INNER_LOOP_BREAK:<br>
- %tmp59 = extractelement <4 x i32> %tmp14, i64 2<br>
- call void asm sideeffect "s_nop 23 ", "~{memory}"() #0<br>
- br label %END_ELSE_BLOCK<br>
-<br>
-bb62:<br>
- %load13 = icmp ult i32 %tmp16, 271<br>
- ;br i1 %load13, label %bb64, label %INCREMENT_I<br>
- ; branching directly to the return avoids the bug<br>
- br i1 %load13, label %RETURN, label %INCREMENT_I<br>
-<br>
-<br>
-bb64:<br>
- call void asm sideeffect "s_nop 42", "~{memory}"() #0<br>
- br label %RETURN<br>
-<br>
-INCREMENT_I:<br>
- %inc.i = add i32 %i, 1<br>
- call void asm sideeffect "s_nop 0x1336 ; increment $0", "v,~{memory}"(i32 %inc.i) #0<br>
- br label %END_ELSE_BLOCK<br>
-<br>
-END_ELSE_BLOCK:<br>
- %i.final = phi i32 [ %tmp59, %INNER_LOOP_BREAK ], [ %inc.i, %INCREMENT_I ]<br>
- call void asm sideeffect "s_nop 0x1337 ; end else block $0", "v,~{memory}"(i32 %i.final) #0<br>
- %cmp.end.else.block = icmp eq i32 %i.final, -1<br>
- br i1 %cmp.end.else.block, label %RETURN, label %LOOP.HEADER<br>
-<br>
-RETURN:<br>
- call void asm sideeffect "s_nop 0x99 ; ClosureEval return", "~{memory}"() #0<br>
- store volatile <2 x float> %load1, <2 x float> addrspace(1)* undef, align 8<br>
- ret void<br>
-}<br>
+; FIXME: Merge variant from backedge-id-bug-xfail<br>
<br>
declare i32 @llvm.amdgcn.workitem.id.x() #1<br>
<br>
<br>
<br>
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</blockquote></div><br></div>