<div dir="ltr">Hello Geoff,<br><br>This commit broke a test on one of our builders:<br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win</a><br><br>. . .<br>Failing Tests (1):<br> LLVM :: CodeGen/ARM/load_store_multiple.ll<br><br>Please have a look?<br>The builder was already red and did not send notifications.<br><br>Thanks<br><br>Galina<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Dec 12, 2017 at 9:53 AM, Geoff Berry via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: gberry<br>
Date: Tue Dec 12 09:53:59 2017<br>
New Revision: 320503<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=320503&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=320503&view=rev</a><br>
Log:<br>
[MachineOperand][MIR] Add isRenamable to MachineOperand.<br>
<br>
Summary:<br>
Add isRenamable() predicate to MachineOperand. This predicate can be<br>
used by machine passes after register allocation to determine whether it<br>
is safe to rename a given register operand. Register operands that<br>
aren't marked as renamable may be required to be assigned their current<br>
register to satisfy constraints that are not captured by the machine<br>
IR (e.g. ABI or ISA constraints).<br>
<br>
Reviewers: qcolombet, MatzeB, hfinkel<br>
<br>
Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D39400" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D39400</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/MIR/<wbr>X86/renamable-register-flag.<wbr>mir<br>
Modified:<br>
llvm/trunk/docs/MIRLangRef.rst<br>
llvm/trunk/include/llvm/<wbr>CodeGen/MachineInstrBuilder.h<br>
llvm/trunk/include/llvm/<wbr>CodeGen/MachineOperand.h<br>
llvm/trunk/lib/CodeGen/<wbr>MIRParser/MILexer.cpp<br>
llvm/trunk/lib/CodeGen/<wbr>MIRParser/MILexer.h<br>
llvm/trunk/lib/CodeGen/<wbr>MIRParser/MIParser.cpp<br>
llvm/trunk/lib/CodeGen/<wbr>MachineOperand.cpp<br>
llvm/trunk/lib/CodeGen/<wbr>MachineVerifier.cpp<br>
llvm/trunk/lib/CodeGen/<wbr>RegAllocFast.cpp<br>
llvm/trunk/lib/CodeGen/<wbr>VirtRegMap.cpp<br>
llvm/trunk/lib/Target/ARM/<wbr>ARMBaseInstrInfo.cpp<br>
llvm/trunk/lib/Target/ARM/<wbr>ARMExpandPseudoInsts.cpp<br>
llvm/trunk/lib/Target/ARM/<wbr>ARMISelLowering.cpp<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-misched-<wbr>multimmo.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/shrink-carry.mir<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/splitkit.mir<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/stack-slot-color-sgpr-<wbr>vgpr-spills.mir<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/subreg_interference.mir<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/syncscopes.ll<br>
llvm/trunk/test/CodeGen/<wbr>Hexagon/regalloc-bad-undef.mir<br>
llvm/trunk/test/CodeGen/<wbr>PowerPC/byval-agg-info.ll<br>
llvm/trunk/test/CodeGen/<wbr>SystemZ/regalloc-fast-invalid-<wbr>kill-flag.mir<br>
llvm/trunk/test/CodeGen/X86/<wbr>tail-merge-debugloc.ll<br>
llvm/trunk/test/DebugInfo/X86/<wbr>pr34545.ll<br>
llvm/trunk/test/DebugInfo/X86/<wbr>sdag-salvage-add.ll<br>
<br>
Modified: llvm/trunk/docs/MIRLangRef.rst<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/MIRLangRef.rst?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/docs/<wbr>MIRLangRef.rst?rev=320503&r1=<wbr>320502&r2=320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/docs/MIRLangRef.rst (original)<br>
+++ llvm/trunk/docs/MIRLangRef.rst Tue Dec 12 09:53:59 2017<br>
@@ -529,6 +529,9 @@ corresponding internal ``llvm::RegState`<br>
* - ``debug-use``<br>
- ``RegState::Debug``<br>
<br>
+ * - ``renamable``<br>
+ - ``RegState::Renamable``<br>
+<br>
.. _subregister-indices:<br>
<br>
Subregister Indices<br>
<br>
Modified: llvm/trunk/include/llvm/<wbr>CodeGen/MachineInstrBuilder.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/include/<wbr>llvm/CodeGen/<wbr>MachineInstrBuilder.h?rev=<wbr>320503&r1=320502&r2=320503&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/<wbr>CodeGen/MachineInstrBuilder.h (original)<br>
+++ llvm/trunk/include/llvm/<wbr>CodeGen/MachineInstrBuilder.h Tue Dec 12 09:53:59 2017<br>
@@ -25,6 +25,7 @@<br>
#include "llvm/CodeGen/MachineInstr.h"<br>
#include "llvm/CodeGen/<wbr>MachineInstrBundle.h"<br>
#include "llvm/CodeGen/MachineOperand.<wbr>h"<br>
+#include "llvm/CodeGen/<wbr>TargetRegisterInfo.h"<br>
#include "llvm/IR/InstrTypes.h"<br>
#include "llvm/IR/Intrinsics.h"<br>
#include "llvm/Support/ErrorHandling.h"<br>
@@ -48,6 +49,7 @@ namespace RegState {<br>
EarlyClobber = 0x40,<br>
Debug = 0x80,<br>
InternalRead = 0x100,<br>
+ Renamable = 0x200,<br>
DefineNoRead = Define | Undef,<br>
ImplicitDefine = Implicit | Define,<br>
ImplicitKill = Implicit | Kill<br>
@@ -91,7 +93,8 @@ public:<br>
flags & RegState::EarlyClobber,<br>
SubReg,<br>
flags & RegState::Debug,<br>
- flags & RegState::InternalRead));<br>
+ flags & RegState::InternalRead,<br>
+ flags & RegState::Renamable));<br>
return *this;<br>
}<br>
<br>
@@ -443,6 +446,9 @@ inline unsigned getInternalReadRegState(<br>
inline unsigned getDebugRegState(bool B) {<br>
return B ? RegState::Debug : 0;<br>
}<br>
+inline unsigned getRenamableRegState(bool B) {<br>
+ return B ? RegState::Renamable : 0;<br>
+}<br>
<br>
/// Get all register state flags from machine operand \p RegOp.<br>
inline unsigned getRegState(const MachineOperand &RegOp) {<br>
@@ -453,7 +459,10 @@ inline unsigned getRegState(const Machin<br>
getDeadRegState(RegOp.isDead()<wbr>) |<br>
getUndefRegState(RegOp.<wbr>isUndef()) |<br>
getInternalReadRegState(RegOp.<wbr>isInternalRead()) |<br>
- getDebugRegState(RegOp.<wbr>isDebug());<br>
+ getDebugRegState(RegOp.<wbr>isDebug()) |<br>
+ getRenamableRegState(<br>
+ TargetRegisterInfo::<wbr>isPhysicalRegister(RegOp.<wbr>getReg()) &&<br>
+ RegOp.isRenamable());<br>
}<br>
<br>
/// Helper class for constructing bundles of MachineInstrs.<br>
<br>
Modified: llvm/trunk/include/llvm/<wbr>CodeGen/MachineOperand.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/include/<wbr>llvm/CodeGen/MachineOperand.h?<wbr>rev=320503&r1=320502&r2=<wbr>320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/<wbr>CodeGen/MachineOperand.h (original)<br>
+++ llvm/trunk/include/llvm/<wbr>CodeGen/MachineOperand.h Tue Dec 12 09:53:59 2017<br>
@@ -86,24 +86,30 @@ private:<br>
/// before MachineInstr::tieOperands().<br>
unsigned char TiedTo : 4;<br>
<br>
- /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register<br>
- /// operands.<br>
-<br>
/// IsDef - True if this is a def, false if this is a use of the register.<br>
+ /// This is only valid on register operands.<br>
///<br>
bool IsDef : 1;<br>
<br>
/// IsImp - True if this is an implicit def or use, false if it is explicit.<br>
+ /// This is only valid on register opderands.<br>
///<br>
bool IsImp : 1;<br>
<br>
- /// IsKill - True if this instruction is the last use of the register on this<br>
- /// path through the function. This is only valid on uses of registers.<br>
- bool IsKill : 1;<br>
-<br>
- /// IsDead - True if this register is never used by a subsequent instruction.<br>
- /// This is only valid on definitions of registers.<br>
- bool IsDead : 1;<br>
+ /// IsDeadOrKill<br>
+ /// For uses: IsKill - True if this instruction is the last use of the<br>
+ /// register on this path through the function.<br>
+ /// For defs: IsDead - True if this register is never used by a subsequent<br>
+ /// instruction.<br>
+ /// This is only valid on register operands.<br>
+ bool IsDeadOrKill : 1;<br>
+<br>
+ /// IsRenamable - True if this register may be renamed, i.e. it does not<br>
+ /// generate a value that is somehow read in a way that is not represented by<br>
+ /// the Machine IR (e.g. to meet an ABI or ISA requirement). This is only<br>
+ /// valid on physical register operands. Virtual registers are assumed to<br>
+ /// always be renamable regardless of the value of this field.<br>
+ bool IsRenamable : 1;<br>
<br>
/// IsUndef - True if this register operand reads an "undef" value, i.e. the<br>
/// read value doesn't matter. This flag can be set on both use and def<br>
@@ -333,12 +339,12 @@ public:<br>
<br>
bool isDead() const {<br>
assert(isReg() && "Wrong MachineOperand accessor");<br>
- return IsDead;<br>
+ return IsDeadOrKill & IsDef;<br>
}<br>
<br>
bool isKill() const {<br>
assert(isReg() && "Wrong MachineOperand accessor");<br>
- return IsKill;<br>
+ return IsDeadOrKill & !IsDef;<br>
}<br>
<br>
bool isUndef() const {<br>
@@ -346,6 +352,8 @@ public:<br>
return IsUndef;<br>
}<br>
<br>
+ bool isRenamable() const;<br>
+<br>
bool isInternalRead() const {<br>
assert(isReg() && "Wrong MachineOperand accessor");<br>
return IsInternalRead;<br>
@@ -418,12 +426,12 @@ public:<br>
void setIsKill(bool Val = true) {<br>
assert(isReg() && !IsDef && "Wrong MachineOperand mutator");<br>
assert((!Val || !isDebug()) && "Marking a debug operation as kill");<br>
- IsKill = Val;<br>
+ IsDeadOrKill = Val;<br>
}<br>
<br>
void setIsDead(bool Val = true) {<br>
assert(isReg() && IsDef && "Wrong MachineOperand mutator");<br>
- IsDead = Val;<br>
+ IsDeadOrKill = Val;<br>
}<br>
<br>
void setIsUndef(bool Val = true) {<br>
@@ -431,6 +439,12 @@ public:<br>
IsUndef = Val;<br>
}<br>
<br>
+ void setIsRenamable(bool Val = true);<br>
+<br>
+ /// Set IsRenamable to true if there are no extra register allocation<br>
+ /// requirements placed on this operand by the parent instruction's opcode.<br>
+ void setIsRenamableIfNoExtraRegAllo<wbr>cReq();<br>
+<br>
void setIsInternalRead(bool Val = true) {<br>
assert(isReg() && "Wrong MachineOperand mutator");<br>
IsInternalRead = Val;<br>
@@ -675,14 +689,15 @@ public:<br>
bool isUndef = false,<br>
bool isEarlyClobber = false,<br>
unsigned SubReg = 0, bool isDebug = false,<br>
- bool isInternalRead = false) {<br>
+ bool isInternalRead = false,<br>
+ bool isRenamable = false) {<br>
assert(!(isDead && !isDef) && "Dead flag on non-def");<br>
assert(!(isKill && isDef) && "Kill flag on def");<br>
MachineOperand Op(MachineOperand::MO_<wbr>Register);<br>
Op.IsDef = isDef;<br>
Op.IsImp = isImp;<br>
- Op.IsKill = isKill;<br>
- Op.IsDead = isDead;<br>
+ Op.IsDeadOrKill = isKill | isDead;<br>
+ Op.IsRenamable = isRenamable;<br>
Op.IsUndef = isUndef;<br>
Op.IsInternalRead = isInternalRead;<br>
Op.IsEarlyClobber = isEarlyClobber;<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>MIRParser/MILexer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/MIRParser/MILexer.cpp?<wbr>rev=320503&r1=320502&r2=<wbr>320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>MIRParser/MILexer.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>MIRParser/MILexer.cpp Tue Dec 12 09:53:59 2017<br>
@@ -208,6 +208,7 @@ static MIToken::TokenKind getIdentifierK<br>
.Case("internal", MIToken::kw_internal)<br>
.Case("early-clobber", MIToken::kw_early_clobber)<br>
.Case("debug-use", MIToken::kw_debug_use)<br>
+ .Case("renamable", MIToken::kw_renamable)<br>
.Case("tied-def", MIToken::kw_tied_def)<br>
.Case("frame-setup", MIToken::kw_frame_setup)<br>
.Case("debug-location", MIToken::kw_debug_location)<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>MIRParser/MILexer.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.h?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/MIRParser/MILexer.h?<wbr>rev=320503&r1=320502&r2=<wbr>320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>MIRParser/MILexer.h (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>MIRParser/MILexer.h Tue Dec 12 09:53:59 2017<br>
@@ -60,6 +60,7 @@ struct MIToken {<br>
kw_internal,<br>
kw_early_clobber,<br>
kw_debug_use,<br>
+ kw_renamable,<br>
kw_tied_def,<br>
kw_frame_setup,<br>
kw_debug_location,<br>
@@ -166,7 +167,8 @@ public:<br>
return Kind == kw_implicit || Kind == kw_implicit_define ||<br>
Kind == kw_def || Kind == kw_dead || Kind == kw_killed ||<br>
Kind == kw_undef || Kind == kw_internal ||<br>
- Kind == kw_early_clobber || Kind == kw_debug_use;<br>
+ Kind == kw_early_clobber || Kind == kw_debug_use ||<br>
+ Kind == kw_renamable;<br>
}<br>
<br>
bool isMemoryOperandFlag() const {<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>MIRParser/MIParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/MIRParser/MIParser.<wbr>cpp?rev=320503&r1=320502&r2=<wbr>320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>MIRParser/MIParser.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>MIRParser/MIParser.cpp Tue Dec 12 09:53:59 2017<br>
@@ -1060,6 +1060,9 @@ bool MIParser::parseRegisterFlag(<wbr>unsigne<br>
case MIToken::kw_debug_use:<br>
Flags |= RegState::Debug;<br>
break;<br>
+ case MIToken::kw_renamable:<br>
+ Flags |= RegState::Renamable;<br>
+ break;<br>
default:<br>
llvm_unreachable("The current token should be a register flag");<br>
}<br>
@@ -1212,7 +1215,8 @@ bool MIParser::<wbr>parseRegisterOperand(Mach<br>
Reg, Flags & RegState::Define, Flags & RegState::Implicit,<br>
Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef,<br>
Flags & RegState::EarlyClobber, SubReg, Flags & RegState::Debug,<br>
- Flags & RegState::InternalRead);<br>
+ Flags & RegState::InternalRead, Flags & RegState::Renamable);<br>
+<br>
return false;<br>
}<br>
<br>
@@ -1880,6 +1884,7 @@ bool MIParser::parseMachineOperand(<wbr>Machi<br>
case MIToken::kw_internal:<br>
case MIToken::kw_early_clobber:<br>
case MIToken::kw_debug_use:<br>
+ case MIToken::kw_renamable:<br>
case MIToken::underscore:<br>
case MIToken::NamedRegister:<br>
case MIToken::VirtualRegister:<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>MachineOperand.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineOperand.cpp?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/MachineOperand.cpp?<wbr>rev=320503&r1=320502&r2=<wbr>320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>MachineOperand.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>MachineOperand.cpp Tue Dec 12 09:53:59 2017<br>
@@ -90,6 +90,7 @@ void MachineOperand::setIsDef(bool Val)<br>
assert((!Val || !isDebug()) && "Marking a debug operation as def");<br>
if (IsDef == Val)<br>
return;<br>
+ assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");<br>
// MRI may keep uses and defs in different list positions.<br>
if (MachineFunction *MF = getMFIfAvailable(*this)) {<br>
MachineRegisterInfo &MRI = MF->getRegInfo();<br>
@@ -101,6 +102,34 @@ void MachineOperand::setIsDef(bool Val)<br>
IsDef = Val;<br>
}<br>
<br>
+bool MachineOperand::isRenamable() const {<br>
+ assert(isReg() && "Wrong MachineOperand accessor");<br>
+ assert(TargetRegisterInfo::<wbr>isPhysicalRegister(getReg()) &&<br>
+ "isRenamable should only be checked on physical registers");<br>
+ return IsRenamable;<br>
+}<br>
+<br>
+void MachineOperand::<wbr>setIsRenamable(bool Val) {<br>
+ assert(isReg() && "Wrong MachineOperand accessor");<br>
+ assert(TargetRegisterInfo::<wbr>isPhysicalRegister(getReg()) &&<br>
+ "setIsRenamable should only be called on physical registers");<br>
+ if (const MachineInstr *MI = getParent())<br>
+ if ((isDef() && MI->hasExtraDefRegAllocReq()) ||<br>
+ (isUse() && MI->hasExtraSrcRegAllocReq()))<br>
+ assert(!Val && "isRenamable should be false for "<br>
+ "hasExtraDefRegAllocReq/<wbr>hasExtraSrcRegAllocReq opcodes");<br>
+ IsRenamable = Val;<br>
+}<br>
+<br>
+void MachineOperand::<wbr>setIsRenamableIfNoExtraRegAllo<wbr>cReq() {<br>
+ if (const MachineInstr *MI = getParent())<br>
+ if ((isDef() && MI->hasExtraDefRegAllocReq()) ||<br>
+ (isUse() && MI->hasExtraSrcRegAllocReq()))<br>
+ return;<br>
+<br>
+ setIsRenamable(true);<br>
+}<br>
+<br>
// If this operand is currently a register operand, and if this is in a<br>
// function, deregister the operand from the register's use/def list.<br>
void MachineOperand::<wbr>removeRegFromUses() {<br>
@@ -194,13 +223,15 @@ void MachineOperand::<wbr>ChangeToRegister(un<br>
RegInfo-><wbr>removeRegOperandFromUseList(<wbr>this);<br>
<br>
// Change this to a register and set the reg#.<br>
+ assert(!(isDead && !isDef) && "Dead flag on non-def");<br>
+ assert(!(isKill && isDef) && "Kill flag on def");<br>
OpKind = MO_Register;<br>
SmallContents.RegNo = Reg;<br>
SubReg_TargetFlags = 0;<br>
IsDef = isDef;<br>
IsImp = isImp;<br>
- IsKill = isKill;<br>
- IsDead = isDead;<br>
+ IsDeadOrKill = isKill | isDead;<br>
+ IsRenamable = false;<br>
IsUndef = isUndef;<br>
IsInternalRead = false;<br>
IsEarlyClobber = false;<br>
@@ -389,6 +420,8 @@ void MachineOperand::print(raw_<wbr>ostream &<br>
OS << "early-clobber ";<br>
if (isDebug())<br>
OS << "debug-use ";<br>
+ if (TargetRegisterInfo::<wbr>isPhysicalRegister(getReg()) && isRenamable())<br>
+ OS << "renamable ";<br>
OS << printReg(Reg, TRI);<br>
// Print the sub register.<br>
if (unsigned SubReg = getSubReg()) {<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>MachineVerifier.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/MachineVerifier.cpp?<wbr>rev=320503&r1=320502&r2=<wbr>320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>MachineVerifier.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>MachineVerifier.cpp Tue Dec 12 09:53:59 2017<br>
@@ -1101,6 +1101,14 @@ MachineVerifier::<wbr>visitMachineOperand(con<br>
}<br>
}<br>
}<br>
+ if (MO->isRenamable() &&<br>
+ ((MO->isDef() && MI->hasExtraDefRegAllocReq()) ||<br>
+ (MO->isUse() && MI->hasExtraSrcRegAllocReq()))<wbr>) {<br>
+ report("Illegal isRenamable setting for opcode with extra regalloc "<br>
+ "requirements",<br>
+ MO, MONum);<br>
+ return;<br>
+ }<br>
} else {<br>
// Virtual register.<br>
const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>RegAllocFast.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/RegAllocFast.cpp?rev=<wbr>320503&r1=320502&r2=320503&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>RegAllocFast.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>RegAllocFast.cpp Tue Dec 12 09:53:59 2017<br>
@@ -699,11 +699,13 @@ bool RegAllocFast::setPhysReg(<wbr>MachineIns<br>
bool Dead = MO.isDead();<br>
if (!MO.getSubReg()) {<br>
MO.setReg(PhysReg);<br>
+ MO.<wbr>setIsRenamableIfNoExtraRegAllo<wbr>cReq();<br>
return MO.isKill() || Dead;<br>
}<br>
<br>
// Handle subregister index.<br>
MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);<br>
+ MO.<wbr>setIsRenamableIfNoExtraRegAllo<wbr>cReq();<br>
MO.setSubReg(0);<br>
<br>
// A kill flag implies killing the full register. Add corresponding super<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>VirtRegMap.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/VirtRegMap.cpp?rev=<wbr>320503&r1=320502&r2=320503&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>VirtRegMap.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>VirtRegMap.cpp Tue Dec 12 09:53:59 2017<br>
@@ -530,6 +530,7 @@ void VirtRegRewriter::rewrite() {<br>
// Rewrite. Note we could have used MachineOperand::substPhysReg()<wbr>, but<br>
// we need the inlining here.<br>
MO.setReg(PhysReg);<br>
+ MO.<wbr>setIsRenamableIfNoExtraRegAllo<wbr>cReq();<br>
}<br>
<br>
// Add any missing super-register kills after rewriting the whole<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/<wbr>ARMBaseInstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>ARM/ARMBaseInstrInfo.cpp?rev=<wbr>320503&r1=320502&r2=320503&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/ARM/<wbr>ARMBaseInstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/<wbr>ARMBaseInstrInfo.cpp Tue Dec 12 09:53:59 2017<br>
@@ -1357,25 +1357,34 @@ void ARMBaseInstrInfo::<wbr>expandMEMCPY(Mach<br>
<br>
MachineInstrBuilder LDM, STM;<br>
if (isThumb1 || !MI->getOperand(1).isDead()) {<br>
+ MachineOperand LDWb(MI->getOperand(1));<br>
+ LDWb.setIsRenamable(false);<br>
LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD<br>
: isThumb1 ? ARM::tLDMIA_UPD<br>
: ARM::LDMIA_UPD))<br>
- .add(MI->getOperand(1));<br>
+ .add(LDWb);<br>
} else {<br>
LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));<br>
}<br>
<br>
if (isThumb1 || !MI->getOperand(0).isDead()) {<br>
+ MachineOperand STWb(MI->getOperand(0));<br>
+ STWb.setIsRenamable(false);<br>
STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD<br>
: isThumb1 ? ARM::tSTMIA_UPD<br>
: ARM::STMIA_UPD))<br>
- .add(MI->getOperand(0));<br>
+ .add(STWb);<br>
} else {<br>
STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));<br>
}<br>
<br>
- LDM.add(MI->getOperand(3)).<wbr>add(predOps(ARMCC::AL));<br>
- STM.add(MI->getOperand(2)).<wbr>add(predOps(ARMCC::AL));<br>
+ MachineOperand LDBase(MI->getOperand(3));<br>
+ LDBase.setIsRenamable(false);<br>
+ LDM.add(LDBase).add(predOps(<wbr>ARMCC::AL));<br>
+<br>
+ MachineOperand STBase(MI->getOperand(2));<br>
+ STBase.setIsRenamable(false);<br>
+ STM.add(STBase).add(predOps(<wbr>ARMCC::AL));<br>
<br>
// Sort the scratch registers into ascending order.<br>
const TargetRegisterInfo &TRI = getRegisterInfo();<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/<wbr>ARMExpandPseudoInsts.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>ARM/ARMExpandPseudoInsts.cpp?<wbr>rev=320503&r1=320502&r2=<wbr>320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/ARM/<wbr>ARMExpandPseudoInsts.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/<wbr>ARMExpandPseudoInsts.cpp Tue Dec 12 09:53:59 2017<br>
@@ -606,8 +606,11 @@ void ARMExpandPseudo::ExpandVTBL(<wbr>Machine<br>
<br>
// Transfer the destination register operand.<br>
MIB.add(MI.getOperand(OpIdx++)<wbr>);<br>
- if (IsExt)<br>
- MIB.add(MI.getOperand(OpIdx++)<wbr>);<br>
+ if (IsExt) {<br>
+ MachineOperand VdSrc(MI.getOperand(OpIdx++));<br>
+ VdSrc.setIsRenamable(false);<br>
+ MIB.add(VdSrc);<br>
+ }<br>
<br>
bool SrcIsKill = MI.getOperand(OpIdx).isKill();<br>
unsigned SrcReg = MI.getOperand(OpIdx++).getReg(<wbr>);<br>
@@ -616,7 +619,9 @@ void ARMExpandPseudo::ExpandVTBL(<wbr>Machine<br>
MIB.addReg(D0);<br>
<br>
// Copy the other source register operand.<br>
- MIB.add(MI.getOperand(OpIdx++)<wbr>);<br>
+ MachineOperand VmSrc(MI.getOperand(OpIdx++));<br>
+ VmSrc.setIsRenamable(false);<br>
+ MIB.add(VmSrc);<br>
<br>
// Copy the predicate operands.<br>
MIB.add(MI.getOperand(OpIdx++)<wbr>);<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/<wbr>ARMISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>ARM/ARMISelLowering.cpp?rev=<wbr>320503&r1=320502&r2=320503&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/ARM/<wbr>ARMISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/<wbr>ARMISelLowering.cpp Tue Dec 12 09:53:59 2017<br>
@@ -8974,8 +8974,11 @@ ARMTargetLowering::<wbr>EmitInstrWithCustomIn<br>
<br>
// Thumb1 post-indexed loads are really just single-register LDMs.<br>
case ARM::tLDR_postidx: {<br>
+ MachineOperand Def(MI.getOperand(1));<br>
+ if (TargetRegisterInfo::<wbr>isPhysicalRegister(Def.getReg(<wbr>)))<br>
+ Def.setIsRenamable(false);<br>
BuildMI(*BB, MI, dl, TII->get(ARM::tLDMIA_UPD))<br>
- .add(MI.getOperand(1)) // Rn_wb<br>
+ .add(Def) // Rn_wb<br>
.add(MI.getOperand(2)) // Rn<br>
.add(MI.getOperand(3)) // PredImm<br>
.add(MI.getOperand(4)) // PredReg<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-misched-<wbr>multimmo.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-misched-multimmo.ll?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-misched-<wbr>multimmo.ll?rev=320503&r1=<wbr>320502&r2=320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-misched-<wbr>multimmo.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-misched-<wbr>multimmo.ll Tue Dec 12 09:53:59 2017<br>
@@ -8,11 +8,11 @@<br>
; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.<br>
;<br>
; CHECK-LABEL: # Machine code for function foo:<br>
-; CHECK: SU(2): %w{{[0-9]+}}, %w{{[0-9]+}} = LDPWi<br>
+; CHECK: SU(2): renamable %w{{[0-9]+}}, renamable %w{{[0-9]+}} = LDPWi<br>
; CHECK: Successors:<br>
; CHECK-NOT: ch SU(4)<br>
; CHECK: SU(3)<br>
-; CHECK: SU(4): STRWui %wzr, %x{{[0-9]+}}<br>
+; CHECK: SU(4): STRWui %wzr, renamable %x{{[0-9]+}}<br>
define i32 @foo() {<br>
entry:<br>
%0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/shrink-carry.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/shrink-carry.mir?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/shrink-carry.<wbr>mir?rev=320503&r1=320502&r2=<wbr>320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/shrink-carry.mir (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/shrink-carry.mir Tue Dec 12 09:53:59 2017<br>
@@ -1,7 +1,7 @@<br>
# RUN: llc -march=amdgcn -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-insert-skips -o - %s | FileCheck -check-prefix=GCN %s<br>
<br>
# GCN-LABEL: name: subbrev{{$}}<br>
-# GCN: V_SUBBREV_U32_e64 0, undef %vgpr0, killed %vcc, implicit %exec<br>
+# GCN: V_SUBBREV_U32_e64 0, undef %vgpr0, killed renamable %vcc, implicit %exec<br>
<br>
---<br>
name: subbrev<br>
@@ -25,7 +25,7 @@ body: |<br>
...<br>
<br>
# GCN-LABEL: name: subb{{$}}<br>
-# GCN: V_SUBB_U32_e64 undef %vgpr0, 0, killed %vcc, implicit %exec<br>
+# GCN: V_SUBB_U32_e64 undef %vgpr0, 0, killed renamable %vcc, implicit %exec<br>
<br>
---<br>
name: subb<br>
@@ -49,7 +49,7 @@ body: |<br>
...<br>
<br>
# GCN-LABEL: name: addc{{$}}<br>
-# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec<br>
+# GCN: V_ADDC_U32_e32 0, undef renamable %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec<br>
<br>
---<br>
name: addc<br>
@@ -73,7 +73,7 @@ body: |<br>
...<br>
<br>
# GCN-LABEL: name: addc2{{$}}<br>
-# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec<br>
+# GCN: V_ADDC_U32_e32 0, undef renamable %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec<br>
<br>
---<br>
name: addc2<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/splitkit.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/splitkit.mir?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/splitkit.mir?<wbr>rev=320503&r1=320502&r2=<wbr>320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/splitkit.mir (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/splitkit.mir Tue Dec 12 09:53:59 2017<br>
@@ -37,13 +37,13 @@ body: |<br>
# CHECK: [[REG0:%sgpr[0-9]+]] = COPY %sgpr0<br>
# CHECK: [[REG1:%sgpr[0-9]+]] = COPY %sgpr2<br>
# CHECK: S_NOP 0<br>
-# CHECK: S_NOP 0, implicit [[REG0]]<br>
-# CHECK: S_NOP 0, implicit [[REG1]]<br>
-# CHECK: %sgpr0 = COPY [[REG0]]<br>
-# CHECK: %sgpr2 = COPY [[REG1]]<br>
+# CHECK: S_NOP 0, implicit renamable [[REG0]]<br>
+# CHECK: S_NOP 0, implicit renamable [[REG1]]<br>
+# CHECK: %sgpr0 = COPY renamable [[REG0]]<br>
+# CHECK: %sgpr2 = COPY renamable [[REG1]]<br>
# CHECK: S_NOP<br>
-# CHECK: S_NOP 0, implicit %sgpr0<br>
-# CHECK: S_NOP 0, implicit %sgpr2<br>
+# CHECK: S_NOP 0, implicit renamable %sgpr0<br>
+# CHECK: S_NOP 0, implicit renamable %sgpr2<br>
name: func1<br>
tracksRegLiveness: true<br>
body: |<br>
@@ -67,8 +67,8 @@ body: |<br>
# Check that copy hoisting out of loops works. This mainly should not crash the<br>
# compiler when it hoists a subreg copy sequence.<br>
# CHECK-LABEL: name: splitHoist<br>
-# CHECK: S_NOP 0, implicit-def %sgpr0<br>
-# CHECK: S_NOP 0, implicit-def %sgpr3<br>
+# CHECK: S_NOP 0, implicit-def renamable %sgpr0<br>
+# CHECK: S_NOP 0, implicit-def renamable %sgpr3<br>
# CHECK-NEXT: SI_SPILL_S128_SAVE<br>
name: splitHoist<br>
tracksRegLiveness: true<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/stack-slot-color-sgpr-<wbr>vgpr-spills.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/stack-slot-<wbr>color-sgpr-vgpr-spills.mir?<wbr>rev=320503&r1=320502&r2=<wbr>320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/stack-slot-color-sgpr-<wbr>vgpr-spills.mir (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/stack-slot-color-sgpr-<wbr>vgpr-spills.mir Tue Dec 12 09:53:59 2017<br>
@@ -9,10 +9,10 @@<br>
# CHECK: - { id: 1, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,<br>
# CHECK-NEXT: stack-id: 1,<br>
<br>
-# CHECK: SI_SPILL_V32_SAVE killed %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0)<br>
+# CHECK: SI_SPILL_V32_SAVE killed renamable %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0)<br>
# CHECK: %vgpr0 = SI_SPILL_V32_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 4 from %stack.0)<br>
<br>
-# CHECK: SI_SPILL_S32_SAVE killed %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1)<br>
+# CHECK: SI_SPILL_S32_SAVE killed renamable %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1)<br>
# CHECK: %sgpr6 = SI_SPILL_S32_RESTORE %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (load 4 from %stack.1)<br>
<br>
name: no_merge_sgpr_vgpr_spill_slot<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/subreg_interference.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/subreg_interference.mir?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/subreg_<wbr>interference.mir?rev=320503&<wbr>r1=320502&r2=320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/subreg_interference.mir (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/subreg_interference.mir Tue Dec 12 09:53:59 2017<br>
@@ -12,12 +12,12 @@<br>
# sgpr0-sgpr3.<br>
#<br>
# CHECK-LABEL: func0<br>
-# CHECK: S_NOP 0, implicit-def %sgpr0<br>
-# CHECK: S_NOP 0, implicit-def %sgpr3<br>
-# CHECK: S_NOP 0, implicit-def %sgpr1<br>
-# CHECK: S_NOP 0, implicit-def %sgpr2<br>
-# CHECK: S_NOP 0, implicit %sgpr0, implicit %sgpr3<br>
-# CHECK: S_NOP 0, implicit %sgpr1, implicit %sgpr2<br>
+# CHECK: S_NOP 0, implicit-def renamable %sgpr0<br>
+# CHECK: S_NOP 0, implicit-def renamable %sgpr3<br>
+# CHECK: S_NOP 0, implicit-def renamable %sgpr1<br>
+# CHECK: S_NOP 0, implicit-def renamable %sgpr2<br>
+# CHECK: S_NOP 0, implicit renamable %sgpr0, implicit renamable %sgpr3<br>
+# CHECK: S_NOP 0, implicit renamable %sgpr1, implicit renamable %sgpr2<br>
name: func0<br>
body: |<br>
bb.0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/syncscopes.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/syncscopes.ll?<wbr>rev=320503&r1=320502&r2=<wbr>320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/syncscopes.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/syncscopes.ll Tue Dec 12 09:53:59 2017<br>
@@ -1,9 +1,9 @@<br>
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -stop-before=si-debugger-<wbr>insert-nops < %s | FileCheck --check-prefix=GCN %s<br>
<br>
; GCN-LABEL: name: syncscopes<br>
-; GCN: FLAT_STORE_DWORD killed %vgpr1_vgpr2, killed %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out)<br>
-; GCN: FLAT_STORE_DWORD killed %vgpr4_vgpr5, killed %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)<br>
-; GCN: FLAT_STORE_DWORD killed %vgpr7_vgpr8, killed %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)<br>
+; GCN: FLAT_STORE_DWORD killed renamable %vgpr1_vgpr2, killed renamable %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out)<br>
+; GCN: FLAT_STORE_DWORD killed renamable %vgpr4_vgpr5, killed renamable %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)<br>
+; GCN: FLAT_STORE_DWORD killed renamable %vgpr7_vgpr8, killed renamable %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)<br>
define void @syncscopes(<br>
i32 %agent,<br>
i32 addrspace(4)* %agent_out,<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>Hexagon/regalloc-bad-undef.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Hexagon/regalloc-bad-<wbr>undef.mir?rev=320503&r1=<wbr>320502&r2=320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>Hexagon/regalloc-bad-undef.mir (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>Hexagon/regalloc-bad-undef.mir Tue Dec 12 09:53:59 2017<br>
@@ -153,7 +153,7 @@ body: |<br>
%13 = S2_asl_r_p_acc %13, %47, %8.isub_lo<br>
%51 = A2_tfrpi 0<br>
<br>
- ; CHECK: %d2 = S2_extractup undef %d0, 6, 25<br>
+ ; CHECK: %d2 = S2_extractup undef renamable %d0, 6, 25<br>
; CHECK: %d0 = A2_tfrpi 2<br>
; CHECK: %d13 = A2_tfrpi -1<br>
; CHECK-NOT: undef %r4<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/<wbr>X86/renamable-register-flag.<wbr>mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/renamable-register-flag.mir?rev=320503&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/MIR/X86/renamable-<wbr>register-flag.mir?rev=320503&<wbr>view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/MIR/<wbr>X86/renamable-register-flag.<wbr>mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/<wbr>X86/renamable-register-flag.<wbr>mir Tue Dec 12 09:53:59 2017<br>
@@ -0,0 +1,16 @@<br>
+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s<br>
+# This test ensures that the MIR parser parses the 'renamable' register flags<br>
+# correctly.<br>
+<br>
+--- |<br>
+ define void @foo() { ret void }<br>
+...<br>
+---<br>
+name: foo<br>
+body: |<br>
+ ; CHECK: bb.0:<br>
+ bb.0:<br>
+ ; CHECK: renamable %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags<br>
+ renamable %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags<br>
+ RETQ %eax<br>
+...<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>PowerPC/byval-agg-info.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/byval-agg-info.ll?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/PowerPC/byval-agg-<wbr>info.ll?rev=320503&r1=320502&<wbr>r2=320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>PowerPC/byval-agg-info.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>PowerPC/byval-agg-info.ll Tue Dec 12 09:53:59 2017<br>
@@ -13,5 +13,5 @@ entry:<br>
<br>
; Make sure that the MMO on the store has no offset from the byval<br>
; variable itself (we used to have mem:ST8[%v+64]).<br>
-; CHECK: STD killed %x5, 176, %x1; mem:ST8[%v](align=16)<br>
+; CHECK: STD killed renamable %x5, 176, %x1; mem:ST8[%v](align=16)<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>SystemZ/regalloc-fast-invalid-<wbr>kill-flag.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/SystemZ/regalloc-fast-<wbr>invalid-kill-flag.mir?rev=<wbr>320503&r1=320502&r2=320503&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>SystemZ/regalloc-fast-invalid-<wbr>kill-flag.mir (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>SystemZ/regalloc-fast-invalid-<wbr>kill-flag.mir Tue Dec 12 09:53:59 2017<br>
@@ -18,11 +18,11 @@ registers:<br>
- { id: 1, class: gr64bit }<br>
- { id: 2, class: addr64bit }<br>
# CHECK: %r0q = L128<br>
-# CHECK-NEXT: %r0l = COPY %r1l<br>
+# CHECK-NEXT: %r0l = COPY renamable %r1l<br>
# Although R0L partially redefines R0Q, it must not mark R0Q as kill<br>
# because R1D is still live through that instruction.<br>
# CHECK-NOT: implicit killed %r0q<br>
-# CHECK-NEXT: %r2d = COPY %r1d<br>
+# CHECK-NEXT: %r2d = COPY renamable %r1d<br>
# CHECK-NEXT: LARL<br>
body: |<br>
bb.0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>tail-merge-debugloc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-merge-debugloc.ll?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/tail-merge-<wbr>debugloc.ll?rev=320503&r1=<wbr>320502&r2=320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>tail-merge-debugloc.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>tail-merge-debugloc.ll Tue Dec 12 09:53:59 2017<br>
@@ -6,7 +6,7 @@<br>
; location info.<br>
;<br>
; CHECK: [[DLOC:![0-9]+]] = !DILocation(line: 2, column: 2, scope: !{{[0-9]+}})<br>
-; CHECK: TEST64rr{{.*}}%rsi, %rsi, implicit-def %eflags<br>
+; CHECK: TEST64rr{{.*}}%rsi, renamable %rsi, implicit-def %eflags<br>
; CHECK-NEXT: JNE_1{{.*}}, debug-location [[DLOC]]<br>
<br>
target triple = "x86_64-unknown-linux-gnu"<br>
<br>
Modified: llvm/trunk/test/DebugInfo/X86/<wbr>pr34545.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/pr34545.ll?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>DebugInfo/X86/pr34545.ll?rev=<wbr>320503&r1=320502&r2=320503&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/DebugInfo/X86/<wbr>pr34545.ll (original)<br>
+++ llvm/trunk/test/DebugInfo/X86/<wbr>pr34545.ll Tue Dec 12 09:53:59 2017<br>
@@ -2,11 +2,11 @@<br>
<br>
; CHECK: %eax = MOV32rm<br>
; CHECK: DBG_VALUE %eax<br>
-; CHECK: %eax = SHL32rCL killed %eax<br>
+; CHECK: %eax = SHL32rCL killed renamable %eax<br>
; CHECK: DBG_VALUE %eax<br>
; CHECK: DBG_VALUE %rsp, 0, !{{[0-9]+}}, !DIExpression(DW_OP_constu, 4, DW_OP_minus)<br>
; CHECK: DBG_VALUE %eax<br>
-; CHECK: %eax = SHL32rCL killed %eax<br>
+; CHECK: %eax = SHL32rCL killed renamable %eax<br>
; CHECK: DBG_VALUE %eax<br>
; CHECK: RETQ %eax<br>
<br>
<br>
Modified: llvm/trunk/test/DebugInfo/X86/<wbr>sdag-salvage-add.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/sdag-salvage-add.ll?rev=320503&r1=320502&r2=320503&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>DebugInfo/X86/sdag-salvage-<wbr>add.ll?rev=320503&r1=320502&<wbr>r2=320503&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/DebugInfo/X86/<wbr>sdag-salvage-add.ll (original)<br>
+++ llvm/trunk/test/DebugInfo/X86/<wbr>sdag-salvage-add.ll Tue Dec 12 09:53:59 2017<br>
@@ -28,7 +28,7 @@<br>
; CHECK-SAME: !DIExpression(DW_OP_plus_<wbr>uconst, 4096, DW_OP_stack_value)<br>
; CHECK-NEXT: DBG_VALUE debug-use %rax, debug-use %noreg, ![[S4]],<br>
; CHECK-SAME: !DIExpression(DW_OP_plus_<wbr>uconst, 4096, DW_OP_stack_value)<br>
-; CHECK-NEXT: %rdi = MOV64rm killed %rax, 1, %noreg, 4096, %noreg,<br>
+; CHECK-NEXT: %rdi = MOV64rm killed renamable %rax, 1, %noreg, 4096, %noreg,<br>
<br>
source_filename = "test.c"<br>
target datalayout = "e-m:o-i64:64-f80:128-n8:16:<wbr>32:64-S128"<br>
<br>
<br>
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