<div dir="ltr"><div>This commit causes an unused variable error in -Werror builds:</div>lib/Target/X86/X86ISelLowering.cpp:16197:7: error: unused variable 'VT' [-Werror,-Wunused-variable]<br><div><br></div><div>Could you fix it?</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Dec 6, 2017 at 8:37 AM, Craig Topper via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ctopper<br>
Date: Tue Dec 5 23:37:20 2017<br>
New Revision: 319878<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=319878&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=319878&view=rev</a><br>
Log:<br>
[X86] Split 512-bit vector extends from types other than vXi1 out of LowerZERO_EXTEND_AVX512/<wbr>LowerSIGN_EXTEND_AVX512. NFCI<br>
<br>
Most of the code in these routines is for handling extends from vXi1 types. The 512-bit handling for other extends is very much like the AVX2 code. So make the special routines just do vXi1 types and move the other 512-bit handling to the place that handles AVX2.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=319878&r1=319877&r2=319878&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86ISelLowering.cpp?rev=<wbr>319878&r1=319877&r2=319878&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp Tue Dec 5 23:37:20 2017<br>
@@ -16090,6 +16090,19 @@ static SDValue LowerAVXExtend(SDValue Op<br>
MVT InVT = In.getSimpleValueType();<br>
SDLoc dl(Op);<br>
<br>
+ if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&<br>
+ (VT != MVT::v8i32 || InVT != MVT::v8i16) &&<br>
+ (VT != MVT::v16i16 || InVT != MVT::v16i8) &&<br>
+ (VT != MVT::v8i64 || InVT != MVT::v8i32) &&<br>
+ (VT != MVT::v8i64 || InVT != MVT::v8i16) &&<br>
+ (VT != MVT::v16i32 || InVT != MVT::v16i16) &&<br>
+ (VT != MVT::v16i32 || InVT != MVT::v16i8) &&<br>
+ (VT != MVT::v32i16 || InVT != MVT::v32i8))<br>
+ return SDValue();<br>
+<br>
+ if (Subtarget.hasInt256())<br>
+ return DAG.getNode(X86ISD::VZEXT, dl, VT, In);<br>
+<br>
// Optimize vectors in AVX mode:<br>
//<br>
// v8i16 -> v8i32<br>
@@ -16103,14 +16116,6 @@ static SDValue LowerAVXExtend(SDValue Op<br>
// Concat upper and lower parts.<br>
//<br>
<br>
- if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&<br>
- ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&<br>
- ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))<br>
- return SDValue();<br>
-<br>
- if (Subtarget.hasInt256())<br>
- return DAG.getNode(X86ISD::VZEXT, dl, VT, In);<br>
-<br>
SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);<br>
SDValue Undef = DAG.getUNDEF(InVT);<br>
bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;<br>
@@ -16126,21 +16131,16 @@ static SDValue LowerAVXExtend(SDValue Op<br>
return DAG.getNode(ISD::CONCAT_<wbr>VECTORS, dl, VT, OpLo, OpHi);<br>
}<br>
<br>
-static SDValue LowerZERO_EXTEND_AVX512(<wbr>SDValue Op,<br>
- const X86Subtarget &Subtarget, SelectionDAG &DAG) {<br>
+static SDValue LowerZERO_EXTEND_Mask(SDValue Op,<br>
+ const X86Subtarget &Subtarget,<br>
+ SelectionDAG &DAG) {<br>
MVT VT = Op->getSimpleValueType(0);<br>
SDValue In = Op->getOperand(0);<br>
MVT InVT = In.getSimpleValueType();<br>
+ assert(InVT.<wbr>getVectorElementType() == MVT::i1 && "Unexpected input type!");<br>
SDLoc DL(Op);<br>
unsigned NumElts = VT.getVectorNumElements();<br>
<br>
- if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1 &&<br>
- (NumElts == 8 || NumElts == 16 || Subtarget.hasBWI()))<br>
- return DAG.getNode(X86ISD::VZEXT, DL, VT, In);<br>
-<br>
- if (InVT.getVectorElementType() != MVT::i1)<br>
- return SDValue();<br>
-<br>
// Extend VT if the scalar type is v8/v16 and BWI is not supported.<br>
MVT ExtVT = VT;<br>
if (!Subtarget.hasBWI() &&<br>
@@ -16179,12 +16179,11 @@ static SDValue LowerZERO_EXTEND_AVX512(<br>
<br>
static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget &Subtarget,<br>
SelectionDAG &DAG) {<br>
- MVT VT = Op->getSimpleValueType(0);<br>
SDValue In = Op->getOperand(0);<br>
MVT InVT = In.getSimpleValueType();<br>
<br>
- if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)<br>
- return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(Op), VT, In);<br>
+ if (InVT.getVectorElementType() == MVT::i1)<br>
+ return LowerZERO_EXTEND_Mask(Op, Subtarget, DAG);<br>
<br>
if (Subtarget.hasFp256())<br>
if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))<br>
@@ -16199,8 +16198,8 @@ static SDValue LowerZERO_EXTEND(SDValue<br>
SDValue In = Op.getOperand(0);<br>
MVT SVT = In.getSimpleValueType();<br>
<br>
- if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)<br>
- return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);<br>
+ if (SVT.getVectorElementType() == MVT::i1)<br>
+ return LowerZERO_EXTEND_Mask(Op, Subtarget, DAG);<br>
<br>
if (Subtarget.hasFp256())<br>
if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))<br>
@@ -18285,28 +18284,18 @@ SDValue X86TargetLowering::<wbr>LowerSELECT(S<br>
return DAG.getNode(X86ISD::CMOV, DL, Op.getValueType(), Ops);<br>
}<br>
<br>
-static SDValue LowerSIGN_EXTEND_AVX512(<wbr>SDValue Op,<br>
- const X86Subtarget &Subtarget,<br>
- SelectionDAG &DAG) {<br>
+static SDValue LowerSIGN_EXTEND_Mask(SDValue Op,<br>
+ const X86Subtarget &Subtarget,<br>
+ SelectionDAG &DAG) {<br>
MVT VT = Op->getSimpleValueType(0);<br>
SDValue In = Op->getOperand(0);<br>
MVT InVT = In.getSimpleValueType();<br>
+ assert(InVT.<wbr>getVectorElementType() == MVT::i1 && "Unexpected input type!");<br>
MVT VTElt = VT.getVectorElementType();<br>
- MVT InVTElt = InVT.getVectorElementType();<br>
SDLoc dl(Op);<br>
<br>
unsigned NumElts = VT.getVectorNumElements();<br>
<br>
- if (VT.is512BitVector() && InVTElt != MVT::i1 &&<br>
- (NumElts == 8 || NumElts == 16 || Subtarget.hasBWI())) {<br>
- if (In.getOpcode() == X86ISD::VSEXT)<br>
- return getExtendInVec(In.getOpcode(), dl, VT, In.getOperand(0), DAG);<br>
- return getExtendInVec(X86ISD::VSEXT, dl, VT, In, DAG);<br>
- }<br>
-<br>
- if (InVTElt != MVT::i1)<br>
- return SDValue();<br>
-<br>
// Extend VT if the scalar type is v8/v16 and BWI is not supported.<br>
MVT ExtVT = VT;<br>
if (!Subtarget.hasBWI() && VTElt.getSizeInBits() <= 16)<br>
@@ -18441,12 +18430,17 @@ static SDValue LowerSIGN_EXTEND(SDValue<br>
MVT InVT = In.getSimpleValueType();<br>
SDLoc dl(Op);<br>
<br>
- if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)<br>
- return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);<br>
+ if (InVT.getVectorElementType() == MVT::i1)<br>
+ return LowerSIGN_EXTEND_Mask(Op, Subtarget, DAG);<br>
<br>
- if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&<br>
- (VT != MVT::v8i32 || InVT != MVT::v8i16) &&<br>
- (VT != MVT::v16i16 || InVT != MVT::v16i8))<br>
+ if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&<br>
+ (VT != MVT::v8i32 || InVT != MVT::v8i16) &&<br>
+ (VT != MVT::v16i16 || InVT != MVT::v16i8) &&<br>
+ (VT != MVT::v8i64 || InVT != MVT::v8i32) &&<br>
+ (VT != MVT::v8i64 || InVT != MVT::v8i16) &&<br>
+ (VT != MVT::v16i32 || InVT != MVT::v16i16) &&<br>
+ (VT != MVT::v16i32 || InVT != MVT::v16i8) &&<br>
+ (VT != MVT::v32i16 || InVT != MVT::v32i8))<br>
return SDValue();<br>
<br>
if (Subtarget.hasInt256())<br>
<br>
<br>
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</blockquote></div><br></div>