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<p class="MsoNormal"><span style="mso-fareast-language:EN-US">Hi Eli,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US">Thank you for the clue. We will check if this is DAGCombiner::MergeStoresOfConstantsOrVecElts.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US">Thanks,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US">Evgeny<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:12.0pt;color:black">From: </span></b><span style="font-size:12.0pt;color:black">"Friedman, Eli" <efriedma@codeaurora.org><br>
<b>Date: </b>Wednesday, 29 November 2017 at 20:07<br>
<b>To: </b>Nirav Davé <niravd@google.com>, "reviews+D33675+public+bfdf04a775858364@reviews.llvm.org" <reviews+D33675+public+bfdf04a775858364@reviews.llvm.org><br>
<b>Cc: </b>James Y Knight <jyknight@google.com>, "hfinkel@anl.gov" <hfinkel@anl.gov>, "llvm-dev@redking.me.uk" <llvm-dev@redking.me.uk>, Reid Kleckner <rnk@google.com>, James Molloy <James.Molloy@arm.com>, Evgeny Astigeevich <Evgeny.Astigeevich@arm.com>, "simon.dardis@mips.com"
<simon.dardis@mips.com>, Nicolai Hähnle-Montoro <nhaehnle@gmail.com>, Javed Absar <Javed.Absar@arm.com>, llvm-commits <llvm-commits@lists.llvm.org><br>
<b>Subject: </b>Re: [PATCH] D33675: [DAG] Do MergeConsecutiveStores again before Instruction Selection<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><a name="_MailOriginalBody">The example looks like there's a bug in the handling of truncstores: DAGCombiner::MergeStoresOfConstantsOrVecElts does "StoreInt |= C->getAPIntValue().zextOrTrunc(SizeInBits);", which doesn't correctly mask away
the extra bits of a truncstore. Not sure how to write a testcase, though.<br>
<br>
-Eli<br>
<br>
On 11/29/2017 11:01 AM, Nirav Davé wrote:<o:p></o:p></a></p>
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<p class="MsoNormal"><span style="mso-bookmark:_MailOriginalBody">Disabled in ARM in r319331.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="mso-bookmark:_MailOriginalBody"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="mso-bookmark:_MailOriginalBody">On Wed, Nov 29, 2017 at 12:31 PM, Nirav Davé <</span><a href="mailto:niravd@google.com" target="_blank"><span style="mso-bookmark:_MailOriginalBody">niravd@google.com</span><span style="mso-bookmark:_MailOriginalBody"></span></a><span style="mso-bookmark:_MailOriginalBody">>
wrote:<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="mso-bookmark:_MailOriginalBody">Sure If no one objects I'll disable this for just the ARM target. <span class="hoenzb"><span style="color:#888888">
</span></span><span class="hoenzb"><span style="color:#888888"><o:p></o:p></span></span></span></p>
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<p class="MsoNormal"><span style="mso-bookmark:_MailOriginalBody"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="mso-bookmark:_MailOriginalBody"><span style="color:#888888">-Nirav<o:p></o:p></span></span></p>
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<p class="MsoNormal"><span style="mso-bookmark:_MailOriginalBody"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="mso-bookmark:_MailOriginalBody">On Wed, Nov 29, 2017 at 12:23 PM, Evgeny Astigeevich via Phabricator <</span><a href="mailto:reviews@reviews.llvm.org" target="_blank"><span style="mso-bookmark:_MailOriginalBody">reviews@reviews.llvm.org</span><span style="mso-bookmark:_MailOriginalBody"></span></a><span style="mso-bookmark:_MailOriginalBody">>
wrote:<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="mso-bookmark:_MailOriginalBody">eastig added a comment.<br>
<br>
Hi Nirav,<br>
<br>
Could you please revert the changes? They affected Arm targets (Thumb2 code).<br>
The following sequence of stores:<br>
<br>
MOVS r0,#0xe5<br>
STRB r0,[r6,#0x1e5]<br>
MOVS r0,#0xe4<br>
STRB r0,[r6,#0x1e4]<br>
MOVS r0,#0xe6<br>
STRB r0,[r6,#0x1e6]<br>
MOVS r0,#0xe7<br>
STRB r0,[r6,#0x1e7]<br>
<br>
is optimised into<br>
<br>
MVN r0,#0x1b<br>
STR r0,[r6,#0x1e4]<br>
<br>
causing incorrect data to be written.<br>
<br>
We are working on a reproducer.<br>
<br>
Thanks,<br>
Evgeny Astigeevich<br>
The Arm Compiler Optimisation team<o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><span style="mso-bookmark:_MailOriginalBody"><br>
<br>
Repository:<br>
rL LLVM<br>
<br>
</span><a href="https://reviews.llvm.org/D33675" target="_blank"><span style="mso-bookmark:_MailOriginalBody">https://reviews.llvm.org/D33675</span><span style="mso-bookmark:_MailOriginalBody"></span></a><span style="mso-bookmark:_MailOriginalBody"><br>
<br>
<br>
<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="mso-bookmark:_MailOriginalBody"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="mso-bookmark:_MailOriginalBody"><o:p> </o:p></span></p>
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<p><span style="mso-bookmark:_MailOriginalBody"><o:p> </o:p></span></p>
<pre><span style="mso-bookmark:_MailOriginalBody">-- <o:p></o:p></span></pre>
<pre><span style="mso-bookmark:_MailOriginalBody">Employee of Qualcomm Innovation Center, Inc.<o:p></o:p></span></pre>
<pre><span style="mso-bookmark:_MailOriginalBody">Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project<o:p></o:p></span></pre>
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