<div dir="ltr">Can you revert this? This bot has been red since yesterday.<div class="gmail_extra"><br><div class="gmail_quote">On Thu, Nov 16, 2017 at 4:05 PM, Akira Hatanaka <span dir="ltr"><<a href="mailto:ahatanak@gmail.com" target="_blank">ahatanak@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Do you know whether this is causing the following bot to fail?<div><div><br></div><div><a href="http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-expensive/9317/consoleFull#1531177838d489585b-5106-414a-ac11-3ff90657619c" target="_blank">http://lab.llvm.org:8080/<wbr>green/job/clang-stage1-cmake-<wbr>RA-expensive/9317/consoleFull#<wbr>1531177838d489585b-5106-414a-<wbr>ac11-3ff90657619c</a><br><div class="gmail_extra"><br></div><div class="gmail_extra">The assertion in masked_gather_scatter.ll started to fail in build #9307.</div><div><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Nov 15, 2017 at 6:07 PM, Craig Topper via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: ctopper<br>
Date: Wed Nov 15 18:07:45 2017<br>
New Revision: 318368<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=318368&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=318368&view=rev</a><br>
Log:<br>
[X86] Custom type legalize v2f32 masked gathers instead of trying to cleanup after type legalization.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86I<wbr>SelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86I<wbr>SelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=318368&r1=318367&r2=318368&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86ISelLowering.cpp?rev=3183<wbr>68&r1=318367&r2=318368&view=<wbr>diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86I<wbr>SelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86I<wbr>SelLowering.cpp Wed Nov 15 18:07:45 2017<br>
@@ -1370,6 +1370,11 @@ X86TargetLowering::X86TargetLo<wbr>wering(con<br>
setOperationAction(ISD::<wbr>CTPOP, VT, Legal);<br>
}<br>
<br>
+ // Custom legalize 2x32 to get a little better code.<br>
+ if (Subtarget.hasVLX()) {<br>
+ setOperationAction(ISD::MGATHE<wbr>R, MVT::v2f32, Custom);<br>
+ }<br>
+<br>
// Custom lower several nodes.<br>
for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,<br>
MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {<br>
@@ -24378,32 +24383,6 @@ static SDValue LowerMGATHER(SDValue Op,<br>
SDValue RetOps[] = { Sext, NewGather.getValue(1) };<br>
return DAG.getMergeValues(RetOps, dl);<br>
}<br>
- if (N->getMemoryVT() == MVT::v2f32 && Subtarget.hasVLX()) {<br>
- // This transformation is for optimization only.<br>
- // The type legalizer extended mask and index to 4 elements vector<br>
- // in order to match requirements of the common gather node - same<br>
- // vector width of index and value. X86 Gather node allows mismatch<br>
- // of vector width in order to select more optimal instruction at the<br>
- // end.<br>
- assert(VT == MVT::v4f32 && Src0.getValueType() == MVT::v4f32 &&<br>
- "Unexpected type in masked gather");<br>
- if (Mask.getOpcode() == ISD::CONCAT_VECTORS &&<br>
- ISD::isBuildVectorAllZeros(Mas<wbr>k.getOperand(1).getNode()) &&<br>
- Index.getOpcode() == ISD::CONCAT_VECTORS &&<br>
- Index.getOperand(1).isUndef()) {<br>
- Mask = Mask.getOperand(0);<br>
- Index = Index.getOperand(0);<br>
- } else<br>
- return Op;<br>
- SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };<br>
- SDValue NewGather = DAG.getTargetMemSDNode<X86Mask<wbr>edGatherSDNode>(<br>
- DAG.getVTList(MVT::v4f32, MVT::v2i1, MVT::Other), Ops, dl,<br>
- N->getMemoryVT(), N->getMemOperand());<br>
-<br>
- SDValue RetOps[] = { NewGather.getValue(0), NewGather.getValue(2) };<br>
- return DAG.getMergeValues(RetOps, dl);<br>
-<br>
- }<br>
return Op;<br>
}<br>
<br>
@@ -24902,6 +24881,29 @@ void X86TargetLowering::ReplaceNode<wbr>Resul<br>
Results.push_back(DAG.getBuil<wbr>dVector(DstVT, dl, Elts));<br>
return;<br>
}<br>
+ case ISD::MGATHER: {<br>
+ EVT VT = N->getValueType(0);<br>
+ if (VT == MVT::v2f32 && Subtarget.hasVLX()) {<br>
+ auto *Gather = cast<MaskedGatherSDNode>(N);<br>
+ SDValue Index = Gather->getIndex();<br>
+ if (Index.getValueType() != MVT::v2i64)<br>
+ return;<br>
+ SDValue Mask = Gather->getMask();<br>
+ assert(Mask.getValueType() == MVT::v2i1 && "Unexpected mask type");<br>
+ SDValue Src0 = DAG.getNode(ISD::CONCAT_VECTOR<wbr>S, dl, MVT::v4f32,<br>
+ Gather->getValue(),<br>
+ DAG.getUNDEF(MVT::v2f32));<br>
+ SDValue Ops[] = { Gather->getChain(), Src0, Mask, Gather->getBasePtr(),<br>
+ Index };<br>
+ SDValue Res = DAG.getTargetMemSDNode<X86Mask<wbr>edGatherSDNode>(<br>
+ DAG.getVTList(MVT::v4f32, MVT::v2i1, MVT::Other), Ops, dl,<br>
+ Gather->getMemoryVT(), Gather->getMemOperand());<br>
+ Results.push_back(Res);<br>
+ Results.push_back(Res.getValue<wbr>(2));<br>
+ return;<br>
+ }<br>
+ break;<br>
+ }<br>
}<br>
}<br>
<br>
<br>
<br>
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</blockquote></div><br></div></div></div></div></div></div>
</blockquote></div><br></div></div>