<div dir="ltr"><div>Commited a workaround in r318288.</div><div><br></div><div>+<span style="font-size:12.8px">djg, who authored the original </span><span style="font-size:12.8px">cfg-</span><wbr style="font-size:12.8px"><span style="font-size:12.8px">stackify.ll.</span></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Nov 15, 2017 at 11:44 AM, Ilya Biryukov <span dir="ltr"><<a href="mailto:ibiryukov@google.com" target="_blank">ibiryukov@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">It seems this change broke "test/CodeGen/WebAssembly/cfg-<wbr>stackify.ll"<div>The test obviously passes for me if I set -<span style="font-size:12.8px">switch-peel-threshold=101 and disable the optimization. I'm gonna commit this as a quick workaround.</span></div><div><span style="font-size:12.8px">Could you take a look at the test, though? Maybe it's better to update the CHECK: statements accordingly?</span><span style="font-size:12.8px"><br></span></div></div><div class="gmail_extra"><div><div class="gmail-m_-2442190695008164126h5"><br><div class="gmail_quote">On Tue, Nov 14, 2017 at 10:44 PM, Rong Xu via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: xur<br>
Date: Tue Nov 14 13:44:09 2017<br>
New Revision: 318202<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=318202&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=318202&view=rev</a><br>
Log:<br>
[CodeGen] Peel off the dominant case in switch statement in lowering<br>
<br>
This patch peels off the top case in switch statement into a branch if the<br>
probability exceeds a threshold. This will help the branch prediction and<br>
avoids the extra compares when lowering into chain of branches.<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D39262" rel="noreferrer" target="_blank">http://reviews.llvm.org/D39262</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/sw<wbr>itch-lower-peel-top-case.ll<br>
Modified:<br>
llvm/trunk/lib/CodeGen/Selecti<wbr>onDAG/SelectionDAGBuilder.cpp<br>
llvm/trunk/lib/CodeGen/Selecti<wbr>onDAG/SelectionDAGBuilder.h<br>
llvm/trunk/test/CodeGen/Generi<wbr>c/MachineBranchProb.ll<br>
llvm/trunk/test/CodeGen/System<wbr>Z/loop-03.ll<br>
llvm/trunk/test/CodeGen/X86/sw<wbr>itch-bt.ll<br>
llvm/trunk/test/CodeGen/X86/sw<wbr>itch.ll<br>
<br>
Modified: llvm/trunk/lib/CodeGen/Selecti<wbr>onDAG/SelectionDAGBuilder.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=318202&r1=318201&r2=318202&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/CodeGen/S<wbr>electionDAG/SelectionDAGBuilde<wbr>r.cpp?rev=318202&r1=318201&r2=<wbr>318202&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/Selecti<wbr>onDAG/SelectionDAGBuilder.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/Selecti<wbr>onDAG/SelectionDAGBuilder.cpp Tue Nov 14 13:44:09 2017<br>
@@ -134,6 +134,12 @@ LimitFPPrecision("limit-float-<wbr>precision"<br>
cl::location(LimitFloatPrecisi<wbr>on),<br>
cl::init(0));<br>
<br>
+static cl::opt<unsigned> SwitchPeelThreshold(<br>
+ "switch-peel-threshold", cl::Hidden, cl::init(66),<br>
+ cl::desc("Set the case probability threshold for peeling the case from a "<br>
+ "switch statement. A value greater than 100 will void this "<br>
+ "optimization"));<br>
+<br>
// Limit the width of DAG chains. This is important in general to prevent<br>
// DAG-based analysis from blowing up. For example, alias analysis and<br>
// load clustering may not complete in reasonable time. It is difficult to<br>
@@ -9834,6 +9840,74 @@ void SelectionDAGBuilder::splitWork<wbr>Item(<br>
SwitchCases.push_back(CB);<br>
}<br>
<br>
+// Scale CaseProb after peeling a case with the probablity of PeeledCaseProb<br>
+// from the swith statement.<br>
+static BranchProbability scaleCaseProbality(BranchProba<wbr>bility CaseProb,<br>
+ BranchProbability PeeledCaseProb) {<br>
+ if (PeeledCaseProb == BranchProbability::getOne())<br>
+ return BranchProbability::getZero();<br>
+ BranchProbability SwitchProb = PeeledCaseProb.getCompl();<br>
+ return BranchProbability(CaseProb.get<wbr>Numerator(),<br>
+ SwitchProb.scale(CaseProb.get<wbr>Denominator()));<br>
+}<br>
+<br>
+// Try to peel the top probability case if it exceeds the threshold.<br>
+// Return current MachineBasicBlock for the switch statement if the peeling<br>
+// does not occur.<br>
+// If the peeling is performed, return the newly created MachineBasicBlock<br>
+// for the peeled switch statement. Also update Clusters to remove the peeled<br>
+// case. PeeledCaseProb is the BranchProbability for the peeled case.<br>
+MachineBasicBlock *SelectionDAGBuilder::peelDomi<wbr>nantCaseCluster(<br>
+ const SwitchInst &SI, CaseClusterVector &Clusters,<br>
+ BranchProbability &PeeledCaseProb) {<br>
+ MachineBasicBlock *SwitchMBB = FuncInfo.MBB;<br>
+ // Don't perform if there is only one cluster or optimizing for size.<br>
+ if (SwitchPeelThreshold > 100 || !FuncInfo.BPI || Clusters.size() < 2 ||<br>
+ TM.getOptLevel() == CodeGenOpt::None ||<br>
+ SwitchMBB->getParent()->getFun<wbr>ction()->optForMinSize())<br>
+ return SwitchMBB;<br>
+<br>
+ BranchProbability TopCaseProb = BranchProbability(SwitchPeelTh<wbr>reshold, 100);<br>
+ unsigned PeeledCaseIndex = 0;<br>
+ bool SwitchPeeled = false;<br>
+ for (unsigned Index = 0; Index < Clusters.size(); ++Index) {<br>
+ CaseCluster &CC = Clusters[Index];<br>
+ if (CC.Prob < TopCaseProb)<br>
+ continue;<br>
+ TopCaseProb = CC.Prob;<br>
+ PeeledCaseIndex = Index;<br>
+ SwitchPeeled = true;<br>
+ }<br>
+ if (!SwitchPeeled)<br>
+ return SwitchMBB;<br>
+<br>
+ DEBUG(dbgs() << "Peeled one top case in switch stmt, prob: " << TopCaseProb<br>
+ << "\n");<br>
+<br>
+ // Record the MBB for the peeled switch statement.<br>
+ MachineFunction::iterator BBI(SwitchMBB);<br>
+ ++BBI;<br>
+ MachineBasicBlock *PeeledSwitchMBB =<br>
+ FuncInfo.MF->CreateMachineBasi<wbr>cBlock(SwitchMBB->getBasicBloc<wbr>k());<br>
+ FuncInfo.MF->insert(BBI, PeeledSwitchMBB);<br>
+<br>
+ ExportFromCurrentBlock(SI.getC<wbr>ondition());<br>
+ auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex;<br>
+ SwitchWorkListItem W = {SwitchMBB, PeeledCaseIt, PeeledCaseIt,<br>
+ nullptr, nullptr, TopCaseProb.getCompl()};<br>
+ lowerWorkItem(W, SI.getCondition(), SwitchMBB, PeeledSwitchMBB);<br>
+<br>
+ Clusters.erase(PeeledCaseIt);<br>
+ for (CaseCluster &CC : Clusters) {<br>
+ DEBUG(dbgs() << "Scale the probablity for one cluster, before scaling: "<br>
+ << CC.Prob << "\n");<br>
+ CC.Prob = scaleCaseProbality(CC.Prob, TopCaseProb);<br>
+ DEBUG(dbgs() << "After scaling: " << CC.Prob << "\n");<br>
+ }<br>
+ PeeledCaseProb = TopCaseProb;<br>
+ return PeeledSwitchMBB;<br>
+}<br>
+<br>
void SelectionDAGBuilder::visitSwit<wbr>ch(const SwitchInst &SI) {<br>
// Extract cases from the switch.<br>
BranchProbabilityInfo *BPI = FuncInfo.BPI;<br>
@@ -9887,9 +9961,15 @@ void SelectionDAGBuilder::visitSwit<wbr>ch(co<br>
}<br>
}<br>
<br>
+ // The branch probablity of the peeled case.<br>
+ BranchProbability PeeledCaseProb = BranchProbability::getZero();<br>
+ MachineBasicBlock *PeeledSwitchMBB =<br>
+ peelDominantCaseCluster(SI, Clusters, PeeledCaseProb);<br>
+<br>
// If there is only the default destination, jump there directly.<br>
MachineBasicBlock *SwitchMBB = FuncInfo.MBB;<br>
if (Clusters.empty()) {<br>
+ assert(PeeledSwitchMBB == SwitchMBB);<br>
SwitchMBB->addSuccessor(Defau<wbr>ltMBB);<br>
if (DefaultMBB != NextBlock(SwitchMBB)) {<br>
DAG.setRoot(DAG.getNode(ISD::<wbr>BR, getCurSDLoc(), MVT::Other,<br>
@@ -9921,8 +10001,14 @@ void SelectionDAGBuilder::visitSwit<wbr>ch(co<br>
SwitchWorkList WorkList;<br>
CaseClusterIt First = Clusters.begin();<br>
CaseClusterIt Last = Clusters.end() - 1;<br>
- auto DefaultProb = getEdgeProbability(SwitchMBB, DefaultMBB);<br>
- WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultProb});<br>
+ auto DefaultProb = getEdgeProbability(PeeledSwitc<wbr>hMBB, DefaultMBB);<br>
+ // Scale the branchprobability for DefaultMBB if the peel occurs and<br>
+ // DefaultMBB is not replaced.<br>
+ if (PeeledCaseProb != BranchProbability::getZero() &&<br>
+ DefaultMBB == FuncInfo.MBBMap[SI.getDefaultD<wbr>est()])<br>
+ DefaultProb = scaleCaseProbality(DefaultProb<wbr>, PeeledCaseProb);<br>
+ WorkList.push_back(<br>
+ {PeeledSwitchMBB, First, Last, nullptr, nullptr, DefaultProb});<br>
<br>
while (!WorkList.empty()) {<br>
SwitchWorkListItem W = WorkList.back();<br>
<br>
Modified: llvm/trunk/lib/CodeGen/Selecti<wbr>onDAG/SelectionDAGBuilder.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=318202&r1=318201&r2=318202&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/CodeGen/S<wbr>electionDAG/SelectionDAGBuilde<wbr>r.h?rev=318202&r1=318201&r2=31<wbr>8202&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/Selecti<wbr>onDAG/SelectionDAGBuilder.h (original)<br>
+++ llvm/trunk/lib/CodeGen/Selecti<wbr>onDAG/SelectionDAGBuilder.h Tue Nov 14 13:44:09 2017<br>
@@ -369,6 +369,10 @@ private:<br>
MachineBasicBlock *SwitchMBB,<br>
MachineBasicBlock *DefaultMBB);<br>
<br>
+ /// Peel the top probability case if it exceeds the threshold<br>
+ MachineBasicBlock *peelDominantCaseCluster(const SwitchInst &SI,<br>
+ CaseClusterVector &Clusters,<br>
+ BranchProbability &PeeledCaseProb);<br>
<br>
/// A class which encapsulates all of the information needed to generate a<br>
/// stack protector check and signals to isel via its state being initialized<br>
<br>
Modified: llvm/trunk/test/CodeGen/Generi<wbr>c/MachineBranchProb.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/MachineBranchProb.ll?rev=318202&r1=318201&r2=318202&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>Generic/MachineBranchProb.ll?r<wbr>ev=318202&r1=318201&r2=318202&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Generi<wbr>c/MachineBranchProb.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Generi<wbr>c/MachineBranchProb.ll Tue Nov 14 13:44:09 2017<br>
@@ -19,12 +19,15 @@ entry:<br>
i64 1, label %<a href="http://sw.bb" rel="noreferrer" target="_blank">sw.bb</a><br>
i64 4, label %<a href="http://sw.bb" rel="noreferrer" target="_blank">sw.bb</a><br>
i64 5, label %sw.bb1<br>
+ i64 15, label %<a href="http://sw.bb" rel="noreferrer" target="_blank">sw.bb</a><br>
], !prof !0<br>
; CHECK: BB#0: derived from LLVM BB %entry<br>
-; CHECK: Successors according to CFG: BB#2({{[0-9a-fx/= ]+}}75.29%) BB#4({{[0-9a-fx/= ]+}}24.71%)<br>
+; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}92.17%) BB#4({{[0-9a-fx/= ]+}}7.83%)<br>
; CHECK: BB#4: derived from LLVM BB %entry<br>
-; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}47.62%) BB#5({{[0-9a-fx/= ]+}}52.38%)<br>
+; CHECK: Successors according to CFG: BB#2({{[0-9a-fx/= ]+}}75.29%) BB#5({{[0-9a-fx/= ]+}}24.71%)<br>
; CHECK: BB#5: derived from LLVM BB %entry<br>
+; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}47.62%) BB#6({{[0-9a-fx/= ]+}}52.38%)<br>
+; CHECK: BB#6: derived from LLVM BB %entry<br>
; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}36.36%) BB#3({{[0-9a-fx/= ]+}}63.64%)<br>
<br>
<a href="http://sw.bb" rel="noreferrer" target="_blank">sw.bb</a>:<br>
@@ -40,7 +43,7 @@ return:<br>
ret i32 %retval.0<br>
}<br>
<br>
-!0 = !{!"branch_weights", i32 7, i32 6, i32 4, i32 4, i32 64}<br>
+!0 = !{!"branch_weights", i32 7, i32 6, i32 4, i32 4, i32 64, i21 1000}<br>
<br>
<br>
declare void @g(i32)<br>
<br>
Modified: llvm/trunk/test/CodeGen/System<wbr>Z/loop-03.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/loop-03.ll?rev=318202&r1=318201&r2=318202&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>SystemZ/loop-03.ll?rev=318202&<wbr>r1=318201&r2=318202&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/System<wbr>Z/loop-03.ll (original)<br>
+++ llvm/trunk/test/CodeGen/System<wbr>Z/loop-03.ll Tue Nov 14 13:44:09 2017<br>
@@ -3,7 +3,7 @@<br>
; FP128 registers part of the callee saved registers list in order to avoid<br>
; spilling / reloading.<br>
;<br>
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s<br>
+; RUN: llc -switch-peel-threshold=101 < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s<br>
<br>
%0 = type { %0*, %0*, %0*, i32, %1*, i64, i64, i64, i64, i64, i64, %2, %5, %7 }<br>
%1 = type { i32, i32, i32 (%1*, i64, i32)*, i32 (%1*, i64, i64, i32, i8**)*, i32 (%1*, i64, i64, i64, i32)*, i32 (%1*)*, void (i8*)*, i8*, i8* }<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sw<wbr>itch-bt.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/switch-bt.ll?rev=318202&r1=318201&r2=318202&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/switch-bt.ll?rev=318202&r1<wbr>=318201&r2=318202&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/sw<wbr>itch-bt.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sw<wbr>itch-bt.ll Tue Nov 14 13:44:09 2017<br>
@@ -1,4 +1,4 @@<br>
-; RUN: llc -mtriple=x86_64-- -asm-verbose=false < %s -jump-table-density=40 | FileCheck %s<br>
+; RUN: llc -mtriple=x86_64-- -asm-verbose=false < %s -jump-table-density=40 -switch-peel-threshold=101 | FileCheck %s<br>
<br>
; This switch should use bit tests, and the third bit test case is just<br>
; testing for one possible value, so it doesn't need a bt.<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/sw<wbr>itch-lower-peel-top-case.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/switch-lower-peel-top-case.ll?rev=318202&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/switch-lower-peel-top-case<wbr>.ll?rev=318202&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/sw<wbr>itch-lower-peel-top-case.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/sw<wbr>itch-lower-peel-top-case.ll Tue Nov 14 13:44:09 2017<br>
@@ -0,0 +1,135 @@<br>
+; RUN: llc -stop-after=isel < %s | FileCheck %s<br>
+<br>
+define i32 @foo(i32 %n) !prof !1 {<br>
+entry:<br>
+ switch i32 %n, label %bb_default [<br>
+ i32 8, label %bb1<br>
+ i32 -8826, label %bb2<br>
+ i32 18312, label %bb3<br>
+ i32 18568, label %bb4<br>
+ i32 129, label %bb5<br>
+ ], !prof !2<br>
+<br>
+; CHECK: successors: %[[PEELED_CASE_LABEL:.*]](0x59<wbr>99999a), %[[PEELED_SWITCH_LABEL:.*]](0x<wbr>26666666)<br>
+; CHECK: %[[VAL:[0-9]+]]:gr32 = COPY %edi<br>
+; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18568, implicit-def %eflags<br>
+; CHECK: JE_1 %[[PEELED_CASE_LABEL]], implicit %eflags<br>
+; CHECK: JMP_1 %[[PEELED_SWITCH_LABEL]]<br>
+; CHECK: [[PEELED_SWITCH_LABEL]]:<br>
+; CHECK: successors: %[[BB1_LABEL:.*]](0x0206d3a0), %[[BB2_LABEL:.*]](0x7df92c60)<br>
+; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18311, implicit-def %eflags<br>
+; CHECK: JG_1 %[[BB2_LABEL]], implicit %eflags<br>
+; CHECK: JMP_1 %[[BB1_LABEL]]<br>
+; CHECK: [[BB1_LABEL]]:<br>
+; CHECK: successors: %[[CASE2_LABEL:.*]](0x35e50d5b<wbr>), %[[BB3_LABEL:.*]](0x4a1af2a5)<br>
+; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], -8826, implicit-def %eflags<br>
+; CHECK: JE_1 %[[CASE2_LABEL]], implicit %eflags<br>
+; CHECK: JMP_1 %[[BB3_LABEL]]<br>
+; CHECK: [[BB3_LABEL]]<br>
+; CHECK: successors: %[[CASE5_LABEL:.*]](0x45d173c8<wbr>), %[[BB4_LABEL:.*]](0x3a2e8c38)<br>
+; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 129, implicit-def %eflags<br>
+; CHECK: JE_1 %[[CASE5_LABEL]], implicit %eflags<br>
+; CHECK: JMP_1 %[[BB4_LABEL]]<br>
+; CHECK: [[BB4_LABEL:.*]]:<br>
+; CHECK: successors: %[[CASE1_LABEL:.*]](0x66666666<wbr>), %[[DEFAULT_BB_LABEL:.*]](0x199<wbr>9999a)<br>
+; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 8, implicit-def %eflags<br>
+; CHECK: JE_1 %[[CASE1_LABEL]], implicit %eflags<br>
+; CHECK: JMP_1 %[[DEFAULT_BB_LABEL]]<br>
+; CHECK: [[BB2_LABEL]]:<br>
+; CHECK: successors: %[[CASE3_LABEL:.*]](0x7fe44107<wbr>), %[[DEFAULT_BB_LABEL]](0x001bbe<wbr>f9)<br>
+; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18312, implicit-def %eflags<br>
+; CHECK: JE_1 %[[CASE3_LABEL]], implicit %eflags<br>
+; CHECK: JMP_1 %[[DEFAULT_BB_LABEL]]<br>
+<br>
+bb1:<br>
+ br label %return<br>
+bb2:<br>
+ br label %return<br>
+bb3:<br>
+ br label %return<br>
+bb4:<br>
+ br label %return<br>
+bb5:<br>
+ br label %return<br>
+bb_default:<br>
+ br label %return<br>
+<br>
+return:<br>
+ %retval = phi i32 [ 0, %bb_default ], [ 5, %bb5 ], [ 4, %bb4 ], [ 3, %bb3 ], [ 2, %bb2 ], [ 1, %bb1 ]<br>
+ ret i32 %retval<br>
+}<br>
+<br>
+; Test the peeling of the merged cases value 85 and 86.<br>
+define i32 @foo1(i32 %n) !prof !1 {<br>
+entry:<br>
+ switch i32 %n, label %bb_default [<br>
+ i32 -40, label %bb1<br>
+ i32 86, label %bb2<br>
+ i32 85, label %bb2<br>
+ i32 1, label %bb3<br>
+ i32 5, label %bb4<br>
+ i32 7, label %bb5<br>
+ i32 49, label %bb6<br>
+ ], !prof !3<br>
+<br>
+; CHECK: successors: %[[PEELED_CASE_LABEL:.*]](0x59<wbr>999999), %[[PEELED_SWITCH_LABEL:.*]](0x<wbr>26666667)<br>
+; CHECK: %[[VAL:[0-9]+]]:gr32 = COPY %edi<br>
+; CHECK: %{{[0-9]+}}:gr32 = ADD32ri8 %{{[0-9]+}}, -85, implicit-def dead %eflags<br>
+; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %{{[0-9]+}}, 2, implicit-def %eflags<br>
+; CHECK: JB_1 %[[PEELED_CASE_LABEL]], implicit %eflags<br>
+; CHECK: JMP_1 %[[PEELED_SWITCH_LABEL]]<br>
+; CHECK: [[PEELED_SWITCH_LABEL]]:<br>
+; CHECK: successors: %[[BB1_LABEL:.*]](0x0088888a), %[[BB2_LABEL:.*]](0x7f777776)<br>
+; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 4, implicit-def %eflags<br>
+; CHECK: JG_1 %[[BB2_LABEL]], implicit %eflags<br>
+; CHECK: JMP_1 %[[BB1_LABEL]]<br>
+; CHECK: [[BB1_LABEL]]:<br>
+; CHECK: successors: %[[CASE4_LABEL:.*]](0x7f775a4f<wbr>), %[[BB3_LABEL:.*]](0x0088a5b1)<br>
+; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 1, implicit-def %eflags<br>
+; CHECK: JE_1 %[[CASE4_LABEL]], implicit %eflags<br>
+; CHECK: JMP_1 %[[BB3_LABEL]]<br>
+; CHECK: [[BB3_LABEL]]:<br>
+; CHECK: successors: %[[CASE1_LABEL:.*]](0x66666666<wbr>), %[[DEFAULT_BB_LABEL:.*]](0x199<wbr>9999a)<br>
+; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], -40, implicit-def %eflags<br>
+; CHECK: JE_1 %[[CASE1_LABEL]], implicit %eflags<br>
+; CHECK: JMP_1 %[[DEFAULT_BB_LABEL]]<br>
+; CHECK: [[BB2_LABEL]]:<br>
+; CHECK: successors: %[[CASE5_LABEL:.*]](0x00000000<wbr>), %[[BB4_LABEL:.*]](0x80000000)<br>
+; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 5, implicit-def %eflags<br>
+; CHECK: JE_1 %[[CASE5_LABEL]], implicit %eflags<br>
+; CHECK: JMP_1 %[[BB4_LABEL]]<br>
+; CHECK: [[BB4_LABEL]]:<br>
+; CHECK: successors: %[[CASE6_LABEL:.*]](0x00000000<wbr>), %[[BB5_LABEL:.*]](0x80000000)<br>
+; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 7, implicit-def %eflags<br>
+; CHECK: JE_1 %[[CASE6_LABEL]], implicit %eflags<br>
+; CHECK: JMP_1 %[[BB5_LABEL]]<br>
+; CHECK: [[BB5_LABEL]]:<br>
+; CHECK: successors: %[[CASE7_LABEL:.*]](0x00000000<wbr>), %[[DEFAULT_BB_LABEL]](0x800000<wbr>00)<br>
+; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 49, implicit-def %eflags<br>
+; CHECK: JE_1 %[[CASE7_LABEL]], implicit %eflags<br>
+; CHECK: JMP_1 %[[DEFAULT_BB_LABEL]]<br>
+<br>
+<br>
+bb1:<br>
+ br label %return<br>
+bb2:<br>
+ br label %return<br>
+bb3:<br>
+ br label %return<br>
+bb4:<br>
+ br label %return<br>
+bb5:<br>
+ br label %return<br>
+bb6:<br>
+ br label %return<br>
+bb_default:<br>
+ br label %return<br>
+<br>
+return:<br>
+ %retval = phi i32 [ 0, %bb_default ], [ 6, %bb6 ], [ 5, %bb5 ], [ 4, %bb4 ], [ 3, %bb3 ], [ 2, %bb2 ], [ 1, %bb1 ]<br>
+ ret i32 %retval<br>
+}<br>
+!1 = !{!"function_entry_count", i64 100000}<br>
+!2 = !{!"branch_weights", i32 50, i32 100, i32 200, i32 29500, i32 70000, i32 150}<br>
+!3 = !{!"branch_weights", i32 50, i32 100, i32 500, i32 69500, i32 29850, i32 0, i32 0, i32 0}<br>
+<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sw<wbr>itch.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/switch.ll?rev=318202&r1=318201&r2=318202&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/switch.ll?rev=318202&r1=31<wbr>8201&r2=318202&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/sw<wbr>itch.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sw<wbr>itch.ll Tue Nov 14 13:44:09 2017<br>
@@ -1,4 +1,4 @@<br>
-; RUN: llc -mtriple=x86_64-linux-gnu %s -o - -jump-table-density=40 -verify-machineinstrs | FileCheck %s<br>
+; RUN: llc -mtriple=x86_64-linux-gnu %s -o - -jump-table-density=40 -switch-peel-threshold=101 -verify-machineinstrs | FileCheck %s<br>
; RUN: llc -mtriple=x86_64-linux-gnu %s -o - -O0 -jump-table-density=40 -verify-machineinstrs | FileCheck --check-prefix=NOOPT %s<br>
<br>
declare void @g(i32)<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><div><br></div></div></div><span class="gmail-m_-2442190695008164126HOEnZb"><font color="#888888">-- <br><div class="gmail-m_-2442190695008164126m_1198237129547436171gmail_signature"><div dir="ltr"><div><div dir="ltr"><div>Regards,</div><div>Ilya Biryukov</div></div></div></div></div>
</font></span></div>
</blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail-m_-2442190695008164126gmail_signature"><div dir="ltr"><div><div dir="ltr"><div>Regards,</div><div>Ilya Biryukov</div></div></div></div></div>
</div></div>