<div dir="ltr">windows builder is broken<div><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/6092">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/6092</a><br></div><div><span style="color:rgb(0,0,0);font-family:"Courier New",courier,monotype,monospace;font-size:medium">FAILED: lib/Target/Hexagon/CMakeFiles/LLVMHexagonCodeGen.dir/HexagonISelDAGToDAG.cpp.obj </span><br></div><div><pre style="font-family:"Courier New",courier,monotype,monospace;color:rgb(0,0,0);font-size:medium"><span class="gmail-stdout">C:\PROGRA~2\MICROS~1.0\VC\bin\amd64\cl.exe /nologo /TP -DEXPENSIVE_CHECKS -DGTEST_HAS_RTTI=0 -DUNICODE -D_CRT_NONSTDC_NO_DEPRECATE -D_CRT_NONSTDC_NO_WARNINGS -D_CRT_SECURE_NO_DEPRECATE -D_CRT_SECURE_NO_WARNINGS -D_GLIBCXX_DEBUG -D_HAS_EXCEPTIONS=0 -D_SCL_SECURE_NO_DEPRECATE -D_SCL_SECURE_NO_WARNINGS -D_UNICODE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Ilib\Target\Hexagon -IC:\ps4-buildslave2\llvm-clang-x86_64-expensive-checks-win\llvm\lib\Target\Hexagon -Iinclude -IC:\ps4-buildslave2\llvm-clang-x86_64-expensive-checks-win\llvm\include /DWIN32 /D_WINDOWS /Zc:inline /Zc:strictStrings /Oi /Zc:rvalueCast /W4 -wd4141 -wd4146 -wd4180 -wd4244 -wd4258 -wd4267 -wd4291 -wd4345 -wd4351 -wd4355 -wd4456 -wd4457 -wd4458 -wd4459 -wd4503 -wd4624 -wd4722 -wd4800 -wd4100 -wd4127 -wd4512 -wd4505 -wd4610 -wd4510 -wd4702 -wd4245 -wd4706 -wd4310 -wd4701 -wd4703 -wd4389 -wd4611 -wd4805 -wd4204 -wd4577 -wd4091 -wd4592 -wd4319 -wd4324 -w14062 -we4238 /MDd /Zi /Ob0 /Od /RTC1 /EHs-c- /GR- /showIncludes /Folib\Target\Hexagon\CMakeFiles\LLVMHexagonCodeGen.dir\HexagonISelDAGToDAG.cpp.obj /Fdlib\Target\Hexagon\CMakeFiles\LLVMHexagonCodeGen.dir\LLVMHexagonCodeGen.pdb /FS -c C:\ps4-buildslave2\llvm-clang-x86_64-expensive-checks-win\llvm\lib\Target\Hexagon\HexagonISelDAGToDAG.cpp
C:\ps4-buildslave2\llvm-clang-x86_64-expensive-checks-win\build\lib\Target\Hexagon\HexagonGenDAGISel.inc(18): error C2065: 'OPC_SwitchOpcode': undeclared identifier
C:\ps4-buildslave2\llvm-clang-x86_64-expensive-checks-win\build\lib\Target\Hexagon\HexagonGenDAGISel.inc(19): error C2065: 'OPC_RecordMemRef': undeclared identifier
C:\ps4-buildslave2\llvm-clang-x86_64-expensive-checks-win\build\lib\Target\Hexagon\HexagonGenDAGISel.inc(20): error C2065: 'OPC_RecordNode': undeclared identifier
C:\ps4-buildslave2\llvm-clang-x86_64-expensive-checks-win\build\lib\Target\Hexagon\HexagonGenDAGISel.inc(21): error C2065: 'OPC_Scope': undeclared identifier
C:\ps4-buildslave2\llvm-clang-x86_64-expensive-checks-win\build\lib\Target\Hexagon\HexagonGenDAGISel.inc(22): error C2065: 'OPC_MoveChild1': undeclared identifier
C:\ps4-buildslave2\llvm-clang-x86_64-expensive-checks-win\build\lib\Target\Hexagon\HexagonGenDAGISel.inc(23): error C2065: 'OPC_SwitchOpcode': undeclared identifier
C:\ps4-buildslave2\llvm-clang-x86_64-expensive-checks-win\build\lib\Target\Hexagon\HexagonGenDAGISel.inc(24): error C2065: 'OPC_Scope': undeclared identifier</span></pre></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Nov 10, 2017 at 10:39 AM, Krzysztof Parzyszek via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: kparzysz<br>
Date: Fri Nov 10 10:39:45 2017<br>
New Revision: 317904<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=317904&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=317904&view=rev</a><br>
Log:<br>
[Hexagon] Create HexagonISelDAGToDAG.h, NFC<br>
<br>
Added:<br>
llvm/trunk/lib/Target/Hexagon/<wbr>HexagonISelDAGToDAG.h<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/<wbr>HexagonISelDAGToDAG.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/<wbr>HexagonISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=317904&r1=317903&r2=317904&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>Hexagon/HexagonISelDAGToDAG.<wbr>cpp?rev=317904&r1=317903&r2=<wbr>317904&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>HexagonISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>HexagonISelDAGToDAG.cpp Fri Nov 10 10:39:45 2017<br>
@@ -12,6 +12,7 @@<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
<br>
#include "Hexagon.h"<br>
+#include "HexagonISelDAGToDAG.h"<br>
#include "HexagonISelLowering.h"<br>
#include "HexagonMachineFunctionInfo.h"<br>
#include "HexagonTargetMachine.h"<br>
@@ -50,115 +51,8 @@ static cl::opt<bool> CheckSingleUse("hex<br>
// Instruction Selector Implementation<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
<br>
-//===------------------------<wbr>------------------------------<wbr>--------------===//<br>
-/// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine<br>
-/// instructions for SelectionDAG operations.<br>
-///<br>
-namespace {<br>
-class HexagonDAGToDAGISel : public SelectionDAGISel {<br>
- const HexagonSubtarget *HST;<br>
- const HexagonInstrInfo *HII;<br>
- const HexagonRegisterInfo *HRI;<br>
-public:<br>
- explicit HexagonDAGToDAGISel(<wbr>HexagonTargetMachine &tm,<br>
- CodeGenOpt::Level OptLevel)<br>
- : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),<br>
- HRI(nullptr) {}<br>
-<br>
- bool runOnMachineFunction(<wbr>MachineFunction &MF) override {<br>
- // Reset the subtarget each time through.<br>
- HST = &MF.getSubtarget<<wbr>HexagonSubtarget>();<br>
- HII = HST->getInstrInfo();<br>
- HRI = HST->getRegisterInfo();<br>
- SelectionDAGISel::<wbr>runOnMachineFunction(MF);<br>
- return true;<br>
- }<br>
-<br>
- bool ComplexPatternFuncMutatesDAG() const override {<br>
- return true;<br>
- }<br>
- void PreprocessISelDAG() override;<br>
- void EmitFunctionEntryCode() override;<br>
-<br>
- void Select(SDNode *N) override;<br>
-<br>
- // Complex Pattern Selectors.<br>
- inline bool SelectAddrGA(SDValue &N, SDValue &R);<br>
- inline bool SelectAddrGP(SDValue &N, SDValue &R);<br>
- inline bool SelectAnyImm(SDValue &N, SDValue &R);<br>
- inline bool SelectAnyInt(SDValue &N, SDValue &R);<br>
- bool SelectAnyImmediate(SDValue &N, SDValue &R, uint32_t LogAlign);<br>
- bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP,<br>
- uint32_t LogAlign);<br>
- bool SelectAddrFI(SDValue &N, SDValue &R);<br>
- bool DetectUseSxtw(SDValue &N, SDValue &R);<br>
-<br>
- inline bool SelectAnyImm0(SDValue &N, SDValue &R);<br>
- inline bool SelectAnyImm1(SDValue &N, SDValue &R);<br>
- inline bool SelectAnyImm2(SDValue &N, SDValue &R);<br>
- inline bool SelectAnyImm3(SDValue &N, SDValue &R);<br>
-<br>
- StringRef getPassName() const override {<br>
- return "Hexagon DAG->DAG Pattern Instruction Selection";<br>
- }<br>
-<br>
- // Generate a machine instruction node corresponding to the circ/brev<br>
- // load intrinsic.<br>
- MachineSDNode *LoadInstrForLoadIntrinsic(<wbr>SDNode *IntN);<br>
- // Given the circ/brev load intrinsic and the already generated machine<br>
- // instruction, generate the appropriate store (that is a part of the<br>
- // intrinsic's functionality).<br>
- SDNode *StoreInstrForLoadIntrinsic(<wbr>MachineSDNode *LoadN, SDNode *IntN);<br>
-<br>
- void SelectFrameIndex(SDNode *N);<br>
- /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for<br>
- /// inline asm expressions.<br>
- bool SelectInlineAsmMemoryOperand(<wbr>const SDValue &Op,<br>
- unsigned ConstraintID,<br>
- std::vector<SDValue> &OutOps) override;<br>
- bool tryLoadOfLoadIntrinsic(<wbr>LoadSDNode *N);<br>
- void SelectLoad(SDNode *N);<br>
- void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);<br>
- void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);<br>
- void SelectStore(SDNode *N);<br>
- void SelectSHL(SDNode *N);<br>
- void SelectZeroExtend(SDNode *N);<br>
- void SelectIntrinsicWChain(SDNode *N);<br>
- void SelectIntrinsicWOChain(SDNode *N);<br>
- void SelectConstant(SDNode *N);<br>
- void SelectConstantFP(SDNode *N);<br>
- void SelectBitcast(SDNode *N);<br>
-<br>
- // Include the pieces autogenerated from the target description.<br>
- #include "HexagonGenDAGISel.inc"<br>
-<br>
-private:<br>
- bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);<br>
- bool isOrEquivalentToAdd(const SDNode *N) const;<br>
- bool isAlignedMemNode(const MemSDNode *N) const;<br>
- bool isSmallStackStore(const StoreSDNode *N) const;<br>
- bool isPositiveHalfWord(const SDNode *N) const;<br>
- bool hasOneUse(const SDNode *N) const;<br>
-<br>
- // DAG preprocessing functions.<br>
- void ppSimplifyOrSelect0(std::<wbr>vector<SDNode*> &&Nodes);<br>
- void ppAddrReorderAddShl(std::<wbr>vector<SDNode*> &&Nodes);<br>
- void ppAddrRewriteAndSrl(std::<wbr>vector<SDNode*> &&Nodes);<br>
- void ppHoistZextI1(std::vector<<wbr>SDNode*> &&Nodes);<br>
-<br>
- SmallDenseMap<SDNode *,int> RootWeights;<br>
- SmallDenseMap<SDNode *,int> RootHeights;<br>
- SmallDenseMap<const Value *,int> GAUsesInFunction;<br>
- int getWeight(SDNode *N);<br>
- int getHeight(SDNode *N);<br>
- SDValue getMultiplierForSHL(SDNode *N);<br>
- SDValue factorOutPowerOf2(SDValue V, unsigned Power);<br>
- unsigned getUsesInFunction(const Value *V);<br>
- SDValue balanceSubTree(SDNode *N, bool Factorize = false);<br>
- void rebalanceAddressTrees();<br>
-}; // end HexagonDAGToDAGISel<br>
-} // end anonymous namespace<br>
-<br>
+#define GET_DAGISEL_BODY HexagonDAGToDAGISel<br>
+#include "HexagonGenDAGISel.inc"<br>
<br>
/// createHexagonISelDag - This pass converts a legalized DAG into a<br>
/// Hexagon-specific DAG, ready for instruction scheduling.<br>
<br>
Added: llvm/trunk/lib/Target/Hexagon/<wbr>HexagonISelDAGToDAG.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h?rev=317904&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>Hexagon/HexagonISelDAGToDAG.h?<wbr>rev=317904&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>HexagonISelDAGToDAG.h (added)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>HexagonISelDAGToDAG.h Fri Nov 10 10:39:45 2017<br>
@@ -0,0 +1,136 @@<br>
+//===-- HexagonISelDAGToDAG.h ------------------------------<wbr>-----*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+// Hexagon specific code to select Hexagon machine instructions for<br>
+// SelectionDAG operations.<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+<br>
+#ifndef LLVM_LIB_TARGET_HEXAGON_<wbr>HEXAGONISELDAGTODAG_H<br>
+#define LLVM_LIB_TARGET_HEXAGON_<wbr>HEXAGONISELDAGTODAG_H<br>
+<br>
+#include "HexagonSubtarget.h"<br>
+#include "HexagonTargetMachine.h"<br>
+#include "llvm/ADT/StringRef.h"<br>
+#include "llvm/CodeGen/SelectionDAG.h"<br>
+#include "llvm/CodeGen/<wbr>SelectionDAGISel.h"<br>
+#include "llvm/Support/CodeGen.h"<br>
+<br>
+#include <vector><br>
+<br>
+namespace llvm {<br>
+class MachineFunction;<br>
+class HexagonInstrInfo;<br>
+class HexagonRegisterInfo;<br>
+<br>
+class HexagonDAGToDAGISel : public SelectionDAGISel {<br>
+ const HexagonSubtarget *HST;<br>
+ const HexagonInstrInfo *HII;<br>
+ const HexagonRegisterInfo *HRI;<br>
+public:<br>
+ explicit HexagonDAGToDAGISel(<wbr>HexagonTargetMachine &tm,<br>
+ CodeGenOpt::Level OptLevel)<br>
+ : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),<br>
+ HRI(nullptr) {}<br>
+<br>
+ bool runOnMachineFunction(<wbr>MachineFunction &MF) override {<br>
+ // Reset the subtarget each time through.<br>
+ HST = &MF.getSubtarget<<wbr>HexagonSubtarget>();<br>
+ HII = HST->getInstrInfo();<br>
+ HRI = HST->getRegisterInfo();<br>
+ SelectionDAGISel::<wbr>runOnMachineFunction(MF);<br>
+ return true;<br>
+ }<br>
+<br>
+ bool ComplexPatternFuncMutatesDAG() const override {<br>
+ return true;<br>
+ }<br>
+ void PreprocessISelDAG() override;<br>
+ void EmitFunctionEntryCode() override;<br>
+<br>
+ void Select(SDNode *N) override;<br>
+<br>
+ // Complex Pattern Selectors.<br>
+ inline bool SelectAddrGA(SDValue &N, SDValue &R);<br>
+ inline bool SelectAddrGP(SDValue &N, SDValue &R);<br>
+ inline bool SelectAnyImm(SDValue &N, SDValue &R);<br>
+ inline bool SelectAnyInt(SDValue &N, SDValue &R);<br>
+ bool SelectAnyImmediate(SDValue &N, SDValue &R, uint32_t LogAlign);<br>
+ bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP,<br>
+ uint32_t LogAlign);<br>
+ bool SelectAddrFI(SDValue &N, SDValue &R);<br>
+ bool DetectUseSxtw(SDValue &N, SDValue &R);<br>
+<br>
+ inline bool SelectAnyImm0(SDValue &N, SDValue &R);<br>
+ inline bool SelectAnyImm1(SDValue &N, SDValue &R);<br>
+ inline bool SelectAnyImm2(SDValue &N, SDValue &R);<br>
+ inline bool SelectAnyImm3(SDValue &N, SDValue &R);<br>
+<br>
+ StringRef getPassName() const override {<br>
+ return "Hexagon DAG->DAG Pattern Instruction Selection";<br>
+ }<br>
+<br>
+ // Generate a machine instruction node corresponding to the circ/brev<br>
+ // load intrinsic.<br>
+ MachineSDNode *LoadInstrForLoadIntrinsic(<wbr>SDNode *IntN);<br>
+ // Given the circ/brev load intrinsic and the already generated machine<br>
+ // instruction, generate the appropriate store (that is a part of the<br>
+ // intrinsic's functionality).<br>
+ SDNode *StoreInstrForLoadIntrinsic(<wbr>MachineSDNode *LoadN, SDNode *IntN);<br>
+<br>
+ void SelectFrameIndex(SDNode *N);<br>
+ /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for<br>
+ /// inline asm expressions.<br>
+ bool SelectInlineAsmMemoryOperand(<wbr>const SDValue &Op,<br>
+ unsigned ConstraintID,<br>
+ std::vector<SDValue> &OutOps) override;<br>
+ bool tryLoadOfLoadIntrinsic(<wbr>LoadSDNode *N);<br>
+ void SelectLoad(SDNode *N);<br>
+ void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);<br>
+ void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);<br>
+ void SelectStore(SDNode *N);<br>
+ void SelectSHL(SDNode *N);<br>
+ void SelectZeroExtend(SDNode *N);<br>
+ void SelectIntrinsicWChain(SDNode *N);<br>
+ void SelectIntrinsicWOChain(SDNode *N);<br>
+ void SelectConstant(SDNode *N);<br>
+ void SelectConstantFP(SDNode *N);<br>
+ void SelectBitcast(SDNode *N);<br>
+ void SelectVectorShuffle(SDNode *N);<br>
+<br>
+ // Include the pieces autogenerated from the target description.<br>
+ #define GET_DAGISEL_DECL<br>
+ #include "HexagonGenDAGISel.inc"<br>
+<br>
+private:<br>
+ bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);<br>
+ bool isOrEquivalentToAdd(const SDNode *N) const;<br>
+ bool isAlignedMemNode(const MemSDNode *N) const;<br>
+ bool isSmallStackStore(const StoreSDNode *N) const;<br>
+ bool isPositiveHalfWord(const SDNode *N) const;<br>
+ bool hasOneUse(const SDNode *N) const;<br>
+<br>
+ // DAG preprocessing functions.<br>
+ void ppSimplifyOrSelect0(std::<wbr>vector<SDNode*> &&Nodes);<br>
+ void ppAddrReorderAddShl(std::<wbr>vector<SDNode*> &&Nodes);<br>
+ void ppAddrRewriteAndSrl(std::<wbr>vector<SDNode*> &&Nodes);<br>
+ void ppHoistZextI1(std::vector<<wbr>SDNode*> &&Nodes);<br>
+<br>
+ SmallDenseMap<SDNode *,int> RootWeights;<br>
+ SmallDenseMap<SDNode *,int> RootHeights;<br>
+ SmallDenseMap<const Value *,int> GAUsesInFunction;<br>
+ int getWeight(SDNode *N);<br>
+ int getHeight(SDNode *N);<br>
+ SDValue getMultiplierForSHL(SDNode *N);<br>
+ SDValue factorOutPowerOf2(SDValue V, unsigned Power);<br>
+ unsigned getUsesInFunction(const Value *V);<br>
+ SDValue balanceSubTree(SDNode *N, bool Factorize = false);<br>
+ void rebalanceAddressTrees();<br>
+}; // end HexagonDAGToDAGISel<br>
+}<br>
+<br>
+#endif // LLVM_LIB_TARGET_HEXAGON_<wbr>HEXAGONISELDAGTODAG_H<br>
<br>
<br>
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</blockquote></div><br></div>