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FYI, this change causes a regression on our internal performance testing on skyline machines.

<div class=""><br class="">

</div>

<div class="">This patch changes the scheduling of a mov instruction in the hot loop. It results in about 11% performance degradation.<br class="">

<div class="">

<pre class="bz_comment_text" id="comment_text_3" style="font-size: medium; white-space: pre-wrap; width: 50em; font-variant-ligatures: normal; orphans: 2; widows: 2;">Before the change:</pre>

<pre class="bz_comment_text" id="comment_text_3" style="font-size: medium; white-space: pre-wrap; width: 50em; font-variant-ligatures: normal; orphans: 2; widows: 2;"># BB#18:                                #   in Loop: Header=BB0_13 Depth=2

        vmovsd  (%r12,%rbp,8), %xmm0    # xmm0 = mem[0],zero

        vmulsd  (%rax,%rcx,8), %xmm0, %xmm0

        movslq  %r11d, %rdi

        vaddsd  %xmm1, %xmm0, %xmm0

        leaq    1(%rcx), %rbp

        cmpq    %rdi, %rbp

        jge     .LBB0_30

After the change:</pre>

<pre class="bz_comment_text" id="comment_text_3" style="font-size: medium; white-space: pre-wrap; width: 50em; font-variant-ligatures: normal; orphans: 2; widows: 2;"># BB#18:                                #   in Loop: Header=BB0_13 Depth=2

        movslq  %r11d, %rdi

        vmovsd  (%r12,%rbp,8), %xmm0    # xmm0 = mem[0],zero

        vmulsd  (%rax,%rcx,8), %xmm0, %xmm0

        vaddsd  %xmm1, %xmm0, %xmm0

        leaq    1(%rcx), %rbp

        cmpq    %rdi, %rbp

        jge     .LBB0_30

</pre>

<div class="">Let me know if you need more information, e.g. the .ll file.</div>

<div class=""><br class="">

</div>

<div class="">Artur</div>

<div class=""><br class="">

<div>

<blockquote type="cite" class="">

<div class="">On 24 Oct 2017, at 23:19, Gadi Haber via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div>

<br class="Apple-interchange-newline">

<div class="">

<div class="">Author: gadi.haber<br class="">

Date: Tue Oct 24 13:19:47 2017<br class="">

New Revision: 316492<br class="">

<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project?rev=316492&view=rev" class="">http://llvm.org/viewvc/llvm-project?rev=316492&view=rev</a><br class="">

Log:<br class="">

[X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU.<br class="">

<br class="">

Adding the scheduling information for the Browadwell (BDW) CPU target.<br class="">

<br class="">

This patch adds the instruction scheduling information for the Broadwell (BDW) architecture target by adding the file X86SchedBroadwell.td located under the X86 Target.<br class="">

We used the scheduling information retrieved from the Broadwell architects in order to create the file.<br class="">

The scheduling information includes latency, number of micro-Ops and used ports by each BDW instruction.<br class="">

<br class="">

The patch continues the scheduling replacement and insertion effort started with the SandyBridge (SNB) target in r310792, the Haswell (HSW) target in r311879, the SkylakeClient (SKL) target in rL313613 + rL315978 and the SkylakeServer (SKX) in rL315175.<br class="">

<br class="">

Performance fluctuations may be expected due to code alignment effects.<br class="">

<br class="">

Reviewers: zvi, RKSimon, craig.topper<br class="">

Differential Revision: <a href="https://reviews.llvm.org/D39054" class="">https://reviews.llvm.org/D39054</a><br class="">

<br class="">

Change-Id: If6f799e5ff60e1091c8d43b05ea78c53581bae01<br class="">

<br class="">

Added:<br class="">

   llvm/trunk/lib/Target/X86/X86SchedBroadwell.td   (with props)<br class="">

Modified:<br class="">

   llvm/trunk/lib/Target/X86/X86.td<br class="">

   llvm/trunk/lib/Target/X86/X86Schedule.td<br class="">

   llvm/trunk/test/CodeGen/X86/aes-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/avx-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/avx2-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/bmi-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/f16c-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/fma-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/lea32-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/lea64-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/mmx-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/movbe-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/sse-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/sse2-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/sse3-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/sse41-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/sse42-schedule.ll<br class="">

   llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll<br class="">

<br class="">

Modified: llvm/trunk/lib/Target/X86/X86.td<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/lib/Target/X86/X86.td (original)<br class="">

+++ llvm/trunk/lib/Target/X86/X86.td Tue Oct 24 13:19:47 2017<br class="">

@@ -576,7 +576,7 @@ def BDWFeatures : ProcessorFeatures<HSWF<br class="">

  FeatureADX,<br class="">

  FeatureRDSEED<br class="">

]>;<br class="">

-class BroadwellProc<string Name> : ProcModel<Name, HaswellModel,<br class="">

+class BroadwellProc<string Name> : ProcModel<Name, BroadwellModel,<br class="">

                                             BDWFeatures.Value, [<br class="">

  ProcIntelBDW<br class="">

]>;<br class="">

<br class="">

Added: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=316492&view=auto" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=316492&view=auto</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (added)<br class="">

+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Tue Oct 24 13:19:47 2017<br class="">

@@ -0,0 +1,4076 @@<br class="">

+//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//<br class="">

+//<br class="">

+//                     The LLVM Compiler Infrastructure<br class="">

+//<br class="">

+// This file is distributed under the University of Illinois Open Source<br class="">

+// License. See LICENSE.TXT for details.<br class="">

+//<br class="">

+//===----------------------------------------------------------------------===//<br class="">

+//<br class="">

+// This file defines the machine model for Broadwell to support instruction<br class="">

+// scheduling and other instruction cost heuristics.<br class="">

+//<br class="">

+//===----------------------------------------------------------------------===//<br class="">

+def BroadwellModel : SchedMachineModel {<br class="">

+  // All x86 instructions are modeled as a single micro-op, and HW can decode 4<br class="">

+  // instructions per cycle.<br class="">

+  let IssueWidth = 4;<br class="">

+  let MicroOpBufferSize = 192; // Based on the reorder buffer.<br class="">

+  let LoadLatency = 5;<br class="">

+  let MispredictPenalty = 16;<br class="">

+<br class="">

+  // Based on the LSD (loop-stream detector) queue size and benchmarking data.<br class="">

+  let LoopMicroOpBufferSize = 50;<br class="">

+<br class="">

+  // This flag is set to allow the scheduler to assign a default model to <br class="">

+  // unrecognized opcodes.<br class="">

+  let CompleteModel = 0;<br class="">

+}<br class="">

+<br class="">

+let SchedModel = BroadwellModel in {<br class="">

+<br class="">

+// Broadwell can issue micro-ops to 8 different ports in one cycle.<br class="">

+<br class="">

+// Ports 0, 1, 5, and 6 handle all computation.<br class="">

+// Port 4 gets the data half of stores. Store data can be available later than<br class="">

+// the store address, but since we don't model the latency of stores, we can<br class="">

+// ignore that.<br class="">

+// Ports 2 and 3 are identical. They handle loads and the address half of<br class="">

+// stores. Port 7 can handle address calculations.<br class="">

+def BWPort0 : ProcResource<1>;<br class="">

+def BWPort1 : ProcResource<1>;<br class="">

+def BWPort2 : ProcResource<1>;<br class="">

+def BWPort3 : ProcResource<1>;<br class="">

+def BWPort4 : ProcResource<1>;<br class="">

+def BWPort5 : ProcResource<1>;<br class="">

+def BWPort6 : ProcResource<1>;<br class="">

+def BWPort7 : ProcResource<1>;<br class="">

+<br class="">

+// Many micro-ops are capable of issuing on multiple ports.<br class="">

+def BWPort01  : ProcResGroup<[BWPort0, BWPort1]>;<br class="">

+def BWPort23  : ProcResGroup<[BWPort2, BWPort3]>;<br class="">

+def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;<br class="">

+def BWPort04  : ProcResGroup<[BWPort0, BWPort4]>;<br class="">

+def BWPort05  : ProcResGroup<[BWPort0, BWPort5]>;<br class="">

+def BWPort06  : ProcResGroup<[BWPort0, BWPort6]>;<br class="">

+def BWPort15  : ProcResGroup<[BWPort1, BWPort5]>;<br class="">

+def BWPort16  : ProcResGroup<[BWPort1, BWPort6]>;<br class="">

+def BWPort56  : ProcResGroup<[BWPort5, BWPort6]>;<br class="">

+def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;<br class="">

+def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;<br class="">

+def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;<br class="">

+<br class="">

+// 60 Entry Unified Scheduler<br class="">

+def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,<br class="">

+                              BWPort5, BWPort6, BWPort7]> {<br class="">

+  let BufferSize=60;<br class="">

+}<br class="">

+<br class="">

+// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5<br class="">

+// cycles after the memory operand.<br class="">

+def : ReadAdvance<ReadAfterLd, 5>;<br class="">

+<br class="">

+// Many SchedWrites are defined in pairs with and without a folded load.<br class="">

+// Instructions with folded loads are usually micro-fused, so they only appear<br class="">

+// as two micro-ops when queued in the reservation station.<br class="">

+// This multiclass defines the resource usage for variants with and without<br class="">

+// folded loads.<br class="">

+multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,<br class="">

+                          ProcResourceKind ExePort,<br class="">

+                          int Lat> {<br class="">

+  // Register variant is using a single cycle on ExePort.<br class="">

+  def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }<br class="">

+<br class="">

+  // Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the<br class="">

+  // latency.<br class="">

+  def : WriteRes<SchedRW.Folded, [BWPort23, ExePort]> {<br class="">

+     let Latency = !add(Lat, 5);<br class="">

+  }<br class="">

+}<br class="">

+<br class="">

+// A folded store needs a cycle on port 4 for the store data, but it does not<br class="">

+// need an extra port 2/3 cycle to recompute the address.<br class="">

+def : WriteRes<WriteRMW, [BWPort4]>;<br class="">

+<br class="">

+// Arithmetic.<br class="">

+defm : BWWriteResPair<WriteALU,   BWPort0156, 1>; // Simple integer ALU op.<br class="">

+defm : BWWriteResPair<WriteIMul,  BWPort1,   3>; // Integer multiplication.<br class="">

+def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.<br class="">

+def BWDivider : ProcResource<1>; // Integer division issued on port 0.     <br class="">

+def : WriteRes<WriteIDiv, [BWPort0, BWDivider]> { // Integer division.<br class="">

+  let Latency = 25;<br class="">

+  let ResourceCycles = [1, 10];<br class="">

+}<br class="">

+def : WriteRes<WriteIDivLd, [BWPort23, BWPort0, BWDivider]> {<br class="">

+  let Latency = 29;<br class="">

+  let ResourceCycles = [1, 1, 10];<br class="">

+}<br class="">

+<br class="">

+def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.<br class="">

+<br class="">

+// Integer shifts and rotates.<br class="">

+defm : BWWriteResPair<WriteShift, BWPort06,  1>;<br class="">

+<br class="">

+// Loads, stores, and moves, not folded with other operations.<br class="">

+def : WriteRes<WriteLoad,  [BWPort23]> { let Latency = 5; }<br class="">

+def : WriteRes<WriteStore, [BWPort237, BWPort4]>;<br class="">

+def : WriteRes<WriteMove,  [BWPort0156]>;<br class="">

+<br class="">

+// Idioms that clear a register, like xorps %xmm0, %xmm0.<br class="">

+// These can often bypass execution ports completely.<br class="">

+def : WriteRes<WriteZero,  []>;<br class="">

+<br class="">

+// Branches don't produce values, so they have no latency, but they still<br class="">

+// consume resources. Indirect branches can fold loads.<br class="">

+defm : BWWriteResPair<WriteJump,  BWPort06,   1>;<br class="">

+<br class="">

+// Floating point. This covers both scalar and vector operations.<br class="">

+defm : BWWriteResPair<WriteFAdd,   BWPort1, 3>; // Floating point add/sub/compare.<br class="">

+defm : BWWriteResPair<WriteFMul,   BWPort0, 5>; // Floating point multiplication.<br class="">

+defm : BWWriteResPair<WriteFDiv,   BWPort0, 12>; // 10-14 cycles. // Floating point division.<br class="">

+defm : BWWriteResPair<WriteFSqrt,  BWPort0, 15>; // Floating point square root.<br class="">

+defm : BWWriteResPair<WriteFRcp,   BWPort0, 5>; // Floating point reciprocal estimate.<br class="">

+defm : BWWriteResPair<WriteFRsqrt, BWPort0, 5>; // Floating point reciprocal square root estimate.<br class="">

+// defm WriteFMA    : X86SchedWritePair; // Fused Multiply Add.<br class="">

+defm : BWWriteResPair<WriteFShuffle,  BWPort5,  1>; // Floating point vector shuffles.<br class="">

+defm : BWWriteResPair<WriteFBlend,  BWPort015,  1>; // Floating point vector blends.<br class="">

+def : WriteRes<WriteFVarBlend, [BWPort5]> { // Fp vector variable blends.<span class="Apple-tab-span" style="white-space:pre">

</span>      <br class="">

+  let Latency = 2;<br class="">

+  let ResourceCycles = [2];<br class="">

+} <br class="">

+def : WriteRes<WriteFVarBlendLd, [BWPort5, BWPort23]> {<br class="">

+  let Latency = 6;<br class="">

+  let ResourceCycles = [2, 1];<br class="">

+}<br class="">

+<br class="">

+// FMA Scheduling helper class.<br class="">

+// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }<br class="">

+<br class="">

+// Vector integer operations.<br class="">

+defm : BWWriteResPair<WriteVecALU,   BWPort15,  1>; // Vector integer ALU op, no logicals.<br class="">

+defm : BWWriteResPair<WriteVecShift, BWPort0,  1>; // Vector integer shifts.<br class="">

+defm : BWWriteResPair<WriteVecIMul,  BWPort0,   5>; // Vector integer multiply.<br class="">

+defm : BWWriteResPair<WriteShuffle,  BWPort5,  1>; // Vector shuffles.<br class="">

+defm : BWWriteResPair<WriteBlend,  BWPort15,  1>; // Vector blends.<br class="">

+<br class="">

+def : WriteRes<WriteVarBlend, [BWPort5]> { // Vector variable blends.<br class="">

+  let Latency = 2;<br class="">

+  let ResourceCycles = [2];<br class="">

+}<br class="">

+def : WriteRes<WriteVarBlendLd, [BWPort5, BWPort23]> {<br class="">

+  let Latency = 6;<br class="">

+  let ResourceCycles = [2, 1];<br class="">

+}<br class="">

+<br class="">

+def : WriteRes<WriteMPSAD, [BWPort0, BWPort5]> { // Vector MPSAD.     <br class="">

+  let Latency = 6;<br class="">

+  let ResourceCycles = [1, 2];<br class="">

+}<br class="">

+def : WriteRes<WriteMPSADLd, [BWPort23, BWPort0, BWPort5]> {<br class="">

+  let Latency = 6;<br class="">

+  let ResourceCycles = [1, 1, 2];<br class="">

+}<br class="">

+<br class="">

+// Vector bitwise operations.<br class="">

+// These are often used on both floating point and integer vectors.<br class="">

+defm : BWWriteResPair<WriteVecLogic, BWPort015, 1>; // Vector and/or/xor.<br class="">

+<br class="">

+// Conversion between integer and float.<br class="">

+defm : BWWriteResPair<WriteCvtF2I, BWPort1, 3>; // Float -> Integer.<br class="">

+defm : BWWriteResPair<WriteCvtI2F, BWPort1, 4>; // Integer -> Float.<br class="">

+defm : BWWriteResPair<WriteCvtF2F, BWPort1, 3>; // Float -> Float size conversion.<br class="">

+<br class="">

+// Strings instructions.<br class="">

+// Packed Compare Implicit Length Strings, Return Mask<br class="">

+// String instructions.<br class="">

+def : WriteRes<WritePCmpIStrM, [BWPort0]> {<br class="">

+  let Latency = 10;<br class="">

+  let ResourceCycles = [3];<br class="">

+}<br class="">

+def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {<br class="">

+  let Latency = 10;<br class="">

+  let ResourceCycles = [3, 1];<br class="">

+} <br class="">

+// Packed Compare Explicit Length Strings, Return Mask<br class="">

+def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort16, BWPort5]> {<br class="">

+  let Latency = 10;<br class="">

+  let ResourceCycles = [3, 2, 4];<br class="">

+}<br class="">

+def : WriteRes<WritePCmpEStrMLd, [BWPort05, BWPort16, BWPort23]> {<br class="">

+  let Latency = 10;<br class="">

+  let ResourceCycles = [6, 2, 1];<br class="">

+} <br class="">

+  // Packed Compare Implicit Length Strings, Return Index<br class="">

+def : WriteRes<WritePCmpIStrI, [BWPort0]> {<br class="">

+  let Latency = 11;<br class="">

+  let ResourceCycles = [3];<br class="">

+}<br class="">

+def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {<br class="">

+  let Latency = 11;<br class="">

+  let ResourceCycles = [3, 1];<br class="">

+}     <br class="">

+// Packed Compare Explicit Length Strings, Return Index<br class="">

+def : WriteRes<WritePCmpEStrI, [BWPort05, BWPort16]> {<br class="">

+  let Latency = 11;<br class="">

+  let ResourceCycles = [6, 2];<br class="">

+}<br class="">

+def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort16, BWPort5, BWPort23]> {<br class="">

+  let Latency = 11;<br class="">

+  let ResourceCycles = [3, 2, 2, 1];<br class="">

+}<br class="">

+<br class="">

+// AES instructions.<br class="">

+def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.<br class="">

+  let Latency = 7;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {<br class="">

+  let Latency = 7;<br class="">

+  let ResourceCycles = [1, 1];<br class="">

+}<br class="">

+def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.<br class="">

+  let Latency = 14;<br class="">

+  let ResourceCycles = [2];<br class="">

+}<br class="">

+def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {<br class="">

+  let Latency = 14;<br class="">

+  let ResourceCycles = [2, 1];<br class="">

+}<br class="">

+def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5]> { // Key Generation.<br class="">

+  let Latency = 10;<br class="">

+  let ResourceCycles = [2, 8];<br class="">

+}<br class="">

+def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23]> {<br class="">

+  let Latency = 10;<br class="">

+  let ResourceCycles = [2, 7, 1];<br class="">

+}<br class="">

+<br class="">

+// Carry-less multiplication instructions.<br class="">

+def : WriteRes<WriteCLMul, [BWPort0, BWPort5]> {<br class="">

+  let Latency = 7;<br class="">

+  let ResourceCycles = [2, 1];<br class="">

+}<br class="">

+def : WriteRes<WriteCLMulLd, [BWPort0, BWPort5, BWPort23]> {<br class="">

+  let Latency = 7;<br class="">

+  let ResourceCycles = [2, 1, 1];<br class="">

+}<br class="">

+<br class="">

+// Catch-all for expensive system instructions.<br class="">

+def : WriteRes<WriteSystem,     [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;<br class="">

+<br class="">

+// AVX2.<br class="">

+defm : BWWriteResPair<WriteFShuffle256,  BWPort5,  3>; // Fp 256-bit width vector shuffles.<br class="">

+defm : BWWriteResPair<WriteShuffle256,  BWPort5,  3>;  // 256-bit width vector shuffles.<br class="">

+def : WriteRes<WriteVarVecShift, [BWPort0, BWPort5]> { // Variable vector shifts.<br class="">

+  let Latency = 2;<br class="">

+  let ResourceCycles = [2, 1];<br class="">

+}<br class="">

+def : WriteRes<WriteVarVecShiftLd, [BWPort0, BWPort5, BWPort23]> {<br class="">

+  let Latency = 6;<br class="">

+  let ResourceCycles = [2, 1, 1];<br class="">

+}<br class="">

+<br class="">

+// Old microcoded instructions that nobody use.<br class="">

+def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;<br class="">

+<br class="">

+// Fence instructions.<br class="">

+def : WriteRes<WriteFence,  [BWPort23, BWPort4]>;<br class="">

+<br class="">

+// Nop, not very useful expect it provides a model for nops!<br class="">

+def : WriteRes<WriteNop, []>;<br class="">

+<br class="">

+////////////////////////////////////////////////////////////////////////////////<br class="">

+// Horizontal add/sub  instructions.<br class="">

+////////////////////////////////////////////////////////////////////////////////<br class="">

+// HADD, HSUB PS/PD<br class="">

+// x,x / v,v,v.<br class="">

+def : WriteRes<WriteFHAdd, [BWPort1]> {<br class="">

+  let Latency = 3;<br class="">

+}<br class="">

+<br class="">

+// x,m / v,v,m.<br class="">

+def : WriteRes<WriteFHAddLd, [BWPort1, BWPort23]> {<br class="">

+  let Latency = 7;<br class="">

+  let ResourceCycles = [1, 1];<br class="">

+}<br class="">

+<br class="">

+// PHADD|PHSUB (S) W/D.<br class="">

+// v <- v,v.<br class="">

+def : WriteRes<WritePHAdd, [BWPort15]>;<br class="">

+<br class="">

+// v <- v,m.<br class="">

+def : WriteRes<WritePHAddLd, [BWPort15, BWPort23]> {<br class="">

+  let Latency = 5;<br class="">

+  let ResourceCycles = [1, 1];<br class="">

+}<br class="">

+<br class="">

+// Remaining instrs.<br class="">

+<br class="">

+def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {<br class="">

+  let Latency = 1;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64grr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PMOVMSKBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSLLDri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSLLDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSLLQri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSLLQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSLLWri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSLLWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSRADri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSRADrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSRAWri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSRAWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSRLDri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSRLDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSRLQri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSRLQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSRLWri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MMX_PSRLWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MOVPDI2DIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "MOVPQIto64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "PSLLDri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "PSLLQri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "PSLLWri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "PSRADri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "PSRAWri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "PSRLDri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "PSRLQri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "PSRLWri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VMOVPDI2DIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VMOVPQIto64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSLLDYri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSLLDri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSLLQYri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSLLQri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSLLWYri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSLLWri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSRADYri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSRADri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSRAWYri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSRAWri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSRLDYri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSRLDri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSRLQYri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSRLQri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSRLVQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSRLVQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSRLWYri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VPSRLWri")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VTESTPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VTESTPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VTESTPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup1], (instregex "VTESTPSrr")>;<br class="">

+<br class="">

+def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {<br class="">

+  let Latency = 1;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r")>;<br class="">

+def: InstRW<[BWWriteResGroup2], (instregex "COM_FST0r")>;<br class="">

+def: InstRW<[BWWriteResGroup2], (instregex "MMX_MASKMOVQ64")>;<br class="">

+def: InstRW<[BWWriteResGroup2], (instregex "MMX_MASKMOVQ64")>;<br class="">

+def: InstRW<[BWWriteResGroup2], (instregex "UCOM_FPr")>;<br class="">

+def: InstRW<[BWWriteResGroup2], (instregex "UCOM_Fr")>;<br class="">

+def: InstRW<[BWWriteResGroup2], (instregex "VMASKMOVDQU")>;<br class="">

+<br class="">

+def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {<br class="">

+  let Latency = 1;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "ANDNPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "ANDNPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "ANDPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "ANDPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "INSERTPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64to64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVQ2DQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MMX_PALIGNR64irr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MMX_PSHUFBrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MMX_PSHUFWri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MMX_PUNPCKHBWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MMX_PUNPCKHDQirr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MMX_PUNPCKHWDirr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MMX_PUNPCKLBWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MMX_PUNPCKLDQirr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MMX_PUNPCKLWDirr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MOV64toPQIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MOVAPDrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MOVAPSrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MOVDDUPrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MOVDI2PDIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MOVHLPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MOVLHPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MOVSDrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MOVSHDUPrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MOVSLDUPrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MOVSSrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MOVUPDrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "MOVUPSrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "ORPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "ORPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PACKSSDWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PACKSSWBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PACKUSDWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PACKUSWBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PALIGNRrri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PBLENDWrri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PMOVSXBDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PMOVSXBQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PMOVSXBWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PMOVSXDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PMOVSXWDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PMOVSXWQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PMOVZXBDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PMOVZXBQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PMOVZXBWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PMOVZXDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PMOVZXWDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PMOVZXWQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PSHUFBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PSHUFDri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PSHUFHWri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PSHUFLWri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PSLLDQri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PSRLDQri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PUNPCKHBWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PUNPCKHDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PUNPCKHQDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PUNPCKHWDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PUNPCKLBWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PUNPCKLDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PUNPCKLQDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "PUNPCKLWDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "SHUFPDrri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "SHUFPSrri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "UNPCKHPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "UNPCKHPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "UNPCKLPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "UNPCKLPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VANDNPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VANDNPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VANDNPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VANDNPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VANDPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VANDPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VANDPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VANDPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VBROADCASTSSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VINSERTPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOV64toPQIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVAPDYrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVAPDrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVAPSYrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVAPSrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVDDUPYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVDDUPrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVDI2PDIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVHLPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVLHPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVSDrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVSHDUPYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVSHDUPrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVSLDUPYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVSLDUPrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVSSrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVUPDYrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVUPDrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVUPSYrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VMOVUPSrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VORPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VORPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VORPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VORPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPACKSSDWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPACKSSDWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPACKSSWBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPACKSSWBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPACKUSDWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPACKUSDWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPACKUSWBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPACKUSWBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPALIGNRYrri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPALIGNRrri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPBLENDWYrri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPBLENDWrri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPBROADCASTDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPBROADCASTQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPERMILPDYri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPERMILPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPERMILPDri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPERMILPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPERMILPSYri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPERMILPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPERMILPSri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPERMILPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPMOVSXBDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPMOVSXBQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPMOVSXBWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPMOVSXDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPMOVSXWDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPMOVSXWQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPMOVZXBDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPMOVZXBQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPMOVZXBWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPMOVZXDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPMOVZXWDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPMOVZXWQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPSHUFBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPSHUFBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPSHUFDYri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPSHUFDri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPSHUFHWYri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPSHUFHWri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPSHUFLWYri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPSHUFLWri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPSLLDQYri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPSLLDQri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPSRLDQYri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPSRLDQri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKHBWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKHBWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKHDQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKHDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKHQDQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKHQDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKHWDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKHWDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKLBWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKLBWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKLDQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKLDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKLQDQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKLQDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKLWDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VPUNPCKLWDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VSHUFPDYrri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VSHUFPDrri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VSHUFPSYrri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VSHUFPSrri")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VUNPCKHPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VUNPCKHPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VUNPCKHPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VUNPCKHPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VUNPCKLPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VUNPCKLPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VUNPCKLPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VUNPCKLPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VXORPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VXORPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VXORPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "VXORPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "XORPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup3], (instregex "XORPSrr")>;<br class="">

+<br class="">

+def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {<br class="">

+  let Latency = 1;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;<br class="">

+<br class="">

+def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {<br class="">

+  let Latency = 1;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup5], (instregex "FINCSTP")>;<br class="">

+def: InstRW<[BWWriteResGroup5], (instregex "FNOP")>;<br class="">

+<br class="">

+def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {<br class="">

+  let Latency = 1;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri8")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "ADC8rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "ADCX32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "ADCX64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "ADOX32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "ADOX64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "BT(16|32|64)ri8")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "BT(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "BTC(16|32|64)ri8")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "BTC(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "BTR(16|32|64)ri8")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "BTR(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "BTS(16|32|64)ri8")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "BTS(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CDQ")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVAE(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVB(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVE(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVG(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVGE(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVL(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVLE(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVNE(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVNO(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVNP(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVNS(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVO(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVP(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CMOVS(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "CQO")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JAE_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JAE_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JA_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JA_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JBE_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JBE_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JB_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JB_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JE_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JE_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JGE_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JGE_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JG_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JG_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JLE_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JLE_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JL_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JL_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JMP_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JMP_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JNE_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JNE_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JNO_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JNO_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JNP_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JNP_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JNS_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JNS_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JO_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JO_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JP_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JP_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JS_1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "JS_4")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "RORX32ri")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "RORX64ri")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SAR(16|32|64)r1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SAR(16|32|64)ri")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SAR8r1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SAR8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SARX32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SARX64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)ri8")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SBB8rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETAEr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETBr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETEr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETGEr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETGr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETLEr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETLr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETNEr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETNOr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETNPr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETNSr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETOr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETPr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SETSr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SHL(16|32|64)r1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SHL(16|32|64)ri")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SHL8r1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SHL8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SHLX32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SHLX64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SHR(16|32|64)r1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SHR(16|32|64)ri")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SHR8r1")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SHR8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SHRX32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup6], (instregex "SHRX64rr")>;<br class="">

+<br class="">

+def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {<br class="">

+  let Latency = 1;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "ANDN32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "ANDN64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "BLSI32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "BLSI64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "BLSMSK32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "BLSMSK64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "BLSR32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "BLSR64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "BZHI32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "BZHI64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "LEA(16|32|64)r")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSBrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSDrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSWrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PADDBirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PADDDirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PADDQirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PADDSBirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PADDSWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PADDUSBirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PADDUSWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PADDWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PAVGBirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PAVGWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PCMPEQBirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PCMPEQDirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PCMPEQWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PCMPGTBirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PCMPGTDirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PCMPGTWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PMAXSWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PMAXUBirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PMINSWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PMINUBirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSIGNBrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSIGNDrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSIGNWrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSUBBirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSUBDirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSUBQirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSUBSBirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSUBSWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSUBUSBirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSUBUSWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSUBWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PABSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PABSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PABSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PADDBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PADDDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PADDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PADDSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PADDSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PADDUSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PADDUSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PADDWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PAVGBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PAVGWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PCMPEQBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PCMPEQDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PCMPEQQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PCMPEQWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PCMPGTBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PCMPGTDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PCMPGTWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PMAXSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PMAXSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PMAXSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PMAXUBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PMAXUDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PMAXUWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PMINSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PMINSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PMINSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PMINUBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PMINUDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PMINUWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PSIGNBrr128")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PSIGNDrr128")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PSIGNWrr128")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PSUBBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PSUBDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PSUBQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PSUBSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PSUBSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PSUBUSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PSUBUSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "PSUBWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPABSBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPABSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPABSDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPABSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPABSWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPABSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDSBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDSWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDUSBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDUSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDUSWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDUSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPADDWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPAVGBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPAVGBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPAVGWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPAVGWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPEQBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPEQBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPEQDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPEQDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPEQQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPEQQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPEQWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPEQWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPGTBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPGTBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPGTDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPGTDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPGTWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPCMPGTWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMAXSBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMAXSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMAXSDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMAXSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMAXSWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMAXSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMAXUBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMAXUBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMAXUDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMAXUDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMAXUWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMAXUWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMINSBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMINSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMINSDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMINSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMINSWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMINSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMINUBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMINUBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMINUDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMINUDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMINUWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPMINUWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNBYrr256")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNBrr128")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNDYrr256")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNDrr128")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNWYrr256")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNWrr128")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBSBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBSWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBUSBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBUSBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBUSWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBUSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup7], (instregex "VPSUBWrr")>;<br class="">

+<br class="">

+def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {<br class="">

+  let Latency = 1;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "BLENDPDrri")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "BLENDPSrri")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVD64from64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "MMX_PANDNirr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "MMX_PANDirr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "MMX_PORirr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "MMX_PXORirr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "MOVDQArr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "MOVDQUrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "MOVPQI2QIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "PANDNrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "PANDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "PORrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "PXORrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VBLENDPDYrri")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VBLENDPDrri")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VBLENDPSYrri")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VBLENDPSrri")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VMOVDQAYrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VMOVDQArr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VMOVDQUYrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VMOVDQUrr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VMOVPQI2QIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VMOVZPQILo2PQIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VPANDNYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VPANDNrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VPANDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VPANDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDDYrri")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDDrri")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VPORYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VPORrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VPXORYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup8], (instregex "VPXORrr")>;<br class="">

+<br class="">

+def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {<br class="">

+  let Latency = 1;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)ri8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "ADD8i8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "ADD8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "ADD8rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)ri8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "AND8i8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "AND8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "AND8rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "CBW")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "CLC")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "CMC")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)ri8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "CMP8i8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "CMP8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "CMP8rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "CWDE")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "DEC(16|32|64)r")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "DEC8r")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "INC(16|32|64)r")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "INC8r")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "LAHF")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "MOV(16|32|64)rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "MOV8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "MOV8ri_alt")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "MOV8rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr16")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr32")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "MOVZX(16|32|64)rr16")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "MOVZX(16|32|64)rr8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "NEG(16|32|64)r")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "NEG8r")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "NOOP")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "NOT(16|32|64)r")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "NOT8r")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)ri8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "OR8i8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "OR8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "OR8rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "SAHF")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "SGDT64m")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "SIDT64m")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "SLDT64m")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "SMSW16m")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "STC")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "STRm")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)ri8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "SUB8i8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "SUB8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "SUB8rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "SYSCALL")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "TEST(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "TEST8i8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "TEST8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "TEST8rr")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "XCHG(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)ri8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)rr(_REV?)")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "XOR8i8")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "XOR8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup9], (instregex "XOR8rr(_REV?)")>;<br class="">

+<br class="">

+def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {<br class="">

+  let Latency = 1;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MMX_MOVD64from64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MMX_MOVD64mr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MMX_MOVNTQmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MMX_MOVQ64mr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOV(16|32|64)mr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOV8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOV8mr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVAPDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVAPSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVDQAmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVDQUmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVHPDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVHPSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVLPDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVLPSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVNTDQmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVNTI_64mr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVNTImr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVNTPDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVNTPSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVPDI2DImr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVPQI2QImr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVPQIto64mr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVSSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVUPDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "MOVUPSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "ST_FP32m")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "ST_FP64m")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "ST_FP80m")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VEXTRACTF128mr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VEXTRACTI128mr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVAPDYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVAPDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVAPSYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVAPSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVDQAYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVDQAmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVDQUYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVDQUmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVHPDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVHPSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVLPDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVLPSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVNTDQYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVNTDQmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVNTPDYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVNTPDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVNTPSYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVNTPSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVPDI2DImr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVPQI2QImr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVPQIto64mr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVSDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVSSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVUPDYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVUPDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVUPSYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup10], (instregex "VMOVUPSmr")>;<br class="">

+<br class="">

+def BWWriteResGroup11 : SchedWriteRes<[BWPort5]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPDrr0")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPSrr0")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "MMX_PINSRWirri")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "PBLENDVBrr0")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "PINSRBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "PINSRDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "PINSRQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "PINSRWrri")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "VBLENDVPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "VBLENDVPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "VBLENDVPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "VBLENDVPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "VPBLENDVBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "VPBLENDVBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "VPINSRBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "VPINSRDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "VPINSRQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup11], (instregex "VPINSRWrri")>;<br class="">

+<br class="">

+def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup12], (instregex "FDECSTP")>;<br class="">

+<br class="">

+def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup13], (instregex "ROL(16|32|64)r1")>;<br class="">

+def: InstRW<[BWWriteResGroup13], (instregex "ROL(16|32|64)ri")>;<br class="">

+def: InstRW<[BWWriteResGroup13], (instregex "ROL8r1")>;<br class="">

+def: InstRW<[BWWriteResGroup13], (instregex "ROL8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup13], (instregex "ROR(16|32|64)r1")>;<br class="">

+def: InstRW<[BWWriteResGroup13], (instregex "ROR(16|32|64)ri")>;<br class="">

+def: InstRW<[BWWriteResGroup13], (instregex "ROR8r1")>;<br class="">

+def: InstRW<[BWWriteResGroup13], (instregex "ROR8ri")>;<br class="">

+<br class="">

+def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup14], (instregex "LFENCE")>;<br class="">

+def: InstRW<[BWWriteResGroup14], (instregex "MFENCE")>;<br class="">

+def: InstRW<[BWWriteResGroup14], (instregex "WAIT")>;<br class="">

+def: InstRW<[BWWriteResGroup14], (instregex "XGETBV")>;<br class="">

+<br class="">

+def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "CVTPS2PDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "CVTSS2SDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "EXTRACTPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "MMX_PEXTRWirri")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PEXTRBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PEXTRDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PEXTRQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PEXTRWri")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PEXTRWrr_REV")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PSLLDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PSLLQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PSLLWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PSRADrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PSRAWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PSRLDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PSRLQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PSRLWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "PTESTrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VCVTPH2PSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VCVTPH2PSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VCVTPS2PDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VCVTSS2SDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VEXTRACTPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPEXTRBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPEXTRDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPEXTRQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPEXTRWri")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPEXTRWrr_REV")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPSLLDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPSLLQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPSLLWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPSRADrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPSRAWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPSRLDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPSRLQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPSRLWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup15], (instregex "VPTESTrr")>;<br class="">

+<br class="">

+def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;<br class="">

+<br class="">

+def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>;<br class="">

+<br class="">

+def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup18], (instregex "SFENCE")>;<br class="">

+<br class="">

+def BWWriteResGroup19 : SchedWriteRes<[BWPort06,BWPort15]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup19], (instregex "BEXTR32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup19], (instregex "BEXTR64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup19], (instregex "BSWAP(16|32|64)r")>;<br class="">

+<br class="">

+def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8")>;<br class="">

+def: InstRW<[BWWriteResGroup20], (instregex "ADC8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup20], (instregex "CMOVA(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup20], (instregex "CMOVBE(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup20], (instregex "CWD")>;<br class="">

+def: InstRW<[BWWriteResGroup20], (instregex "JRCXZ")>;<br class="">

+def: InstRW<[BWWriteResGroup20], (instregex "SBB8i8")>;<br class="">

+def: InstRW<[BWWriteResGroup20], (instregex "SBB8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup20], (instregex "SETAr")>;<br class="">

+def: InstRW<[BWWriteResGroup20], (instregex "SETBEr")>;<br class="">

+<br class="">

+def BWWriteResGroup21 : SchedWriteRes<[BWPort4,BWPort5,BWPort237]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup21], (instregex "EXTRACTPSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup21], (instregex "PEXTRBmr")>;<br class="">

+def: InstRW<[BWWriteResGroup21], (instregex "PEXTRDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup21], (instregex "PEXTRQmr")>;<br class="">

+def: InstRW<[BWWriteResGroup21], (instregex "PEXTRWmr")>;<br class="">

+def: InstRW<[BWWriteResGroup21], (instregex "STMXCSR")>;<br class="">

+def: InstRW<[BWWriteResGroup21], (instregex "VEXTRACTPSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup21], (instregex "VPEXTRBmr")>;<br class="">

+def: InstRW<[BWWriteResGroup21], (instregex "VPEXTRDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup21], (instregex "VPEXTRQmr")>;<br class="">

+def: InstRW<[BWWriteResGroup21], (instregex "VPEXTRWmr")>;<br class="">

+def: InstRW<[BWWriteResGroup21], (instregex "VSTMXCSR")>;<br class="">

+<br class="">

+def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;<br class="">

+<br class="">

+def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETAEm")>;<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETBm")>;<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETEm")>;<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETGEm")>;<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETGm")>;<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETLEm")>;<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETLm")>;<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETNEm")>;<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETNOm")>;<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETNPm")>;<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETNSm")>;<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETOm")>;<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETPm")>;<br class="">

+def: InstRW<[BWWriteResGroup23], (instregex "SETSm")>;<br class="">

+<br class="">

+def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;<br class="">

+<br class="">

+def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {<br class="">

+  let Latency = 2;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)r")>;<br class="">

+def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>;<br class="">

+def: InstRW<[BWWriteResGroup25], (instregex "PUSH64i8")>;<br class="">

+def: InstRW<[BWWriteResGroup25], (instregex "STOSB")>;<br class="">

+def: InstRW<[BWWriteResGroup25], (instregex "STOSL")>;<br class="">

+def: InstRW<[BWWriteResGroup25], (instregex "STOSQ")>;<br class="">

+def: InstRW<[BWWriteResGroup25], (instregex "STOSW")>;<br class="">

+<br class="">

+def BWWriteResGroup26 : SchedWriteRes<[BWPort0]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup26], (instregex "MOVMSKPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup26], (instregex "MOVMSKPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup26], (instregex "PMOVMSKBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup26], (instregex "VMOVMSKPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup26], (instregex "VMOVMSKPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup26], (instregex "VMOVMSKPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup26], (instregex "VMOVMSKPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup26], (instregex "VPMOVMSKBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup26], (instregex "VPMOVMSKBrr")>;<br class="">

+<br class="">

+def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "ADDPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "ADDPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "ADDSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "ADDSSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "ADDSUBPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "ADDSUBPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "ADD_FST0r")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "ADD_FrST0")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "BSF(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "BSR(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "CMPPDrri")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "CMPPSrri")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "CMPSSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "COMISDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "COMISSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "CVTDQ2PSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "CVTPS2DQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "CVTTPS2DQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "IMUL(32|64)rr(i8?)")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "IMUL8r")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "LZCNT(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "MAXPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "MAXPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "MAXSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "MAXSSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "MINPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "MINPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "MINSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "MINSSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "MMX_CVTPI2PSirr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "MUL8r")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "PDEP32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "PDEP64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "PEXT32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "PEXT64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "POPCNT(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "SHLD(16|32|64)rri8")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "SHRD(16|32|64)rri8")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "SUBPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "SUBPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "SUBR_FPrST0")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "SUBR_FST0r")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "SUBR_FrST0")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "SUBSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "SUBSSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "SUB_FPrST0")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "SUB_FST0r")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "SUB_FrST0")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "TZCNT(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "UCOMISDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "UCOMISSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VADDPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VADDPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VADDPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VADDPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VADDSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VADDSSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VADDSUBPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VADDSUBPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VADDSUBPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VADDSUBPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCMPPDYrri")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCMPPDrri")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCMPPSYrri")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCMPPSrri")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCMPSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCMPSSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCOMISDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCOMISSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCVTDQ2PSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCVTDQ2PSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCVTPS2DQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCVTPS2DQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCVTTPS2DQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VCVTTPS2DQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VMAXPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VMAXPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VMAXPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VMAXPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VMAXSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VMAXSSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VMINPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VMINPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VMINPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VMINPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VMINSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VMINSSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VSUBPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VSUBPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VSUBPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VSUBPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VSUBSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VSUBSSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VUCOMISDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup27], (instregex "VUCOMISSrr")>;<br class="">

+<br class="">

+def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup27_16], (instregex "IMUL16rr(i8?)")>;<br class="">

+<br class="">

+def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VEXTRACTF128rr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VEXTRACTI128rr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VINSERTF128rr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VINSERTI128rr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPBROADCASTBYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPBROADCASTBrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPBROADCASTDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPBROADCASTQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPBROADCASTWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPBROADCASTWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPERM2F128rr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPERM2I128rr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPERMDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPERMPDYri")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPERMPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPERMQYri")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPMOVSXBDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPMOVSXBQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPMOVSXBWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPMOVSXDQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPMOVSXWDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPMOVSXWQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPMOVZXBDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPMOVZXBQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPMOVZXBWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPMOVZXDQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPMOVZXWDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup28], (instregex "VPMOVZXWQYrr")>;<br class="">

+<br class="">

+def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup29], (instregex "MULPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup29], (instregex "MULPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup29], (instregex "MULSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup29], (instregex "MULSSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup29], (instregex "VMULPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup29], (instregex "VMULPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup29], (instregex "VMULPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup29], (instregex "VMULPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup29], (instregex "VMULSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup29], (instregex "VMULSSrr")>;<br class="">

+<br class="">

+def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [3];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup30], (instregex "XADD(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup30], (instregex "XADD8rr")>;<br class="">

+def: InstRW<[BWWriteResGroup30], (instregex "XCHG8rr")>;<br class="">

+<br class="">

+def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup31], (instregex "VPSRAVDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup31], (instregex "VPSRAVDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup31], (instregex "VPSRLVDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup31], (instregex "VPSRLVDrr")>;<br class="">

+<br class="">

+def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDSWrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDWrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBDrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBSWrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBWrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "PHADDDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "PHADDSWrr128")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "PHADDWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "PHSUBDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "PHSUBSWrr128")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "PHSUBWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "VPHADDDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "VPHADDDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "VPHADDSWrr128")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "VPHADDSWrr256")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "VPHADDWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "VPHADDWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBSWrr128")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBSWrr256")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBWrr")>;<br class="">

+<br class="">

+def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSWBirr")>;<br class="">

+def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKUSWBirr")>;<br class="">

+<br class="">

+def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;<br class="">

+<br class="">

+def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup35], (instregex "RCL(16|32|64)r1")>;<br class="">

+def: InstRW<[BWWriteResGroup35], (instregex "RCL(16|32|64)ri")>;<br class="">

+def: InstRW<[BWWriteResGroup35], (instregex "RCL8r1")>;<br class="">

+def: InstRW<[BWWriteResGroup35], (instregex "RCL8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup35], (instregex "RCR(16|32|64)r1")>;<br class="">

+def: InstRW<[BWWriteResGroup35], (instregex "RCR(16|32|64)ri")>;<br class="">

+def: InstRW<[BWWriteResGroup35], (instregex "RCR8r1")>;<br class="">

+def: InstRW<[BWWriteResGroup35], (instregex "RCR8ri")>;<br class="">

+<br class="">

+def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup36], (instregex "ROL(16|32|64)rCL")>;<br class="">

+def: InstRW<[BWWriteResGroup36], (instregex "ROL8rCL")>;<br class="">

+def: InstRW<[BWWriteResGroup36], (instregex "ROR(16|32|64)rCL")>;<br class="">

+def: InstRW<[BWWriteResGroup36], (instregex "ROR8rCL")>;<br class="">

+def: InstRW<[BWWriteResGroup36], (instregex "SAR(16|32|64)rCL")>;<br class="">

+def: InstRW<[BWWriteResGroup36], (instregex "SAR8rCL")>;<br class="">

+def: InstRW<[BWWriteResGroup36], (instregex "SHL(16|32|64)rCL")>;<br class="">

+def: InstRW<[BWWriteResGroup36], (instregex "SHL8rCL")>;<br class="">

+def: InstRW<[BWWriteResGroup36], (instregex "SHR(16|32|64)rCL")>;<br class="">

+def: InstRW<[BWWriteResGroup36], (instregex "SHR8rCL")>;<br class="">

+<br class="">

+def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;<br class="">

+<br class="">

+def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 3;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup38], (instregex "CALL64pcrel32")>;<br class="">

+def: InstRW<[BWWriteResGroup38], (instregex "SETAm")>;<br class="">

+def: InstRW<[BWWriteResGroup38], (instregex "SETBEm")>;<br class="">

+<br class="">

+def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {<br class="">

+  let Latency = 4;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "CVTSD2SI64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "CVTSD2SIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "CVTSS2SI64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "CVTSS2SIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "CVTTSD2SI64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "CVTTSD2SIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "CVTTSS2SI64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "CVTTSS2SIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "VCVTSD2SI64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "VCVTSD2SIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "VCVTSS2SI64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "VCVTSS2SIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "VCVTTSD2SI64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "VCVTTSD2SIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "VCVTTSS2SI64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup39], (instregex "VCVTTSS2SIrr")>;<br class="">

+<br class="">

+def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {<br class="">

+  let Latency = 4;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup40], (instregex "VPSLLDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup40], (instregex "VPSLLQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup40], (instregex "VPSLLWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup40], (instregex "VPSRADYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup40], (instregex "VPSRAWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup40], (instregex "VPSRLDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup40], (instregex "VPSRLQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup40], (instregex "VPSRLWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup40], (instregex "VPTESTYrr")>;<br class="">

+<br class="">

+def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {<br class="">

+  let Latency = 4;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup41], (instregex "FNSTSW16r")>;<br class="">

+<br class="">

+def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {<br class="">

+  let Latency = 4;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "CVTDQ2PDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "CVTPD2DQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "CVTPD2PSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "CVTSD2SSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "CVTSI2SD64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "CVTSI2SDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "CVTSI2SSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "CVTTPD2DQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "IMUL(32|64)r")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPD2PIirr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPI2PDirr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPS2PIirr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTTPD2PIirr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTTPS2PIirr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "MUL(32|64)r")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "MULX64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "VCVTDQ2PDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "VCVTPD2DQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "VCVTPD2PSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "VCVTPS2PHrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "VCVTSD2SSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "VCVTSI2SD64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "VCVTSI2SDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "VCVTSI2SSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup42], (instregex "VCVTTPD2DQrr")>;<br class="">

+<br class="">

+def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 4;<br class="">

+  let NumMicroOps = 4;<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup42_16], (instregex "IMUL16r")>;<br class="">

+def: InstRW<[BWWriteResGroup42_16], (instregex "MUL16r")>;<br class="">

+<br class="">

+def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {<br class="">

+  let Latency = 4;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup43], (instregex "FNSTSWm")>;<br class="">

+<br class="">

+def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {<br class="">

+  let Latency = 4;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m")>;<br class="">

+def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP32m")>;<br class="">

+def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP64m")>;<br class="">

+def: InstRW<[BWWriteResGroup44], (instregex "IST_F16m")>;<br class="">

+def: InstRW<[BWWriteResGroup44], (instregex "IST_F32m")>;<br class="">

+def: InstRW<[BWWriteResGroup44], (instregex "IST_FP16m")>;<br class="">

+def: InstRW<[BWWriteResGroup44], (instregex "IST_FP32m")>;<br class="">

+def: InstRW<[BWWriteResGroup44], (instregex "IST_FP64m")>;<br class="">

+def: InstRW<[BWWriteResGroup44], (instregex "VCVTPS2PHYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup44], (instregex "VCVTPS2PHmr")>;<br class="">

+<br class="">

+def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {<br class="">

+  let Latency = 4;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [4];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup45], (instregex "FNCLEX")>;<br class="">

+<br class="">

+def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {<br class="">

+  let Latency = 4;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,3];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup46], (instregex "VZEROUPPER")>;<br class="">

+<br class="">

+def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {<br class="">

+  let Latency = 5;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDWDirr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMULHRSWrr64")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMULHUWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMULHWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMULLWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMULUDQirr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "MMX_PSADBWirr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "MUL_FPrST0")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "MUL_FST0r")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "MUL_FrST0")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "PCLMULQDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "PCMPGTQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "PHMINPOSUWrr128")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "PMADDUBSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "PMADDWDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "PMULDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "PMULHRSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "PMULHUWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "PMULHWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "PMULLWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "PMULUDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "PSADBWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "RCPPSr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "RCPSSr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "RSQRTPSr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "RSQRTSSr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPCLMULQDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPCMPGTQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPCMPGTQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPHMINPOSUWrr128")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMADDUBSWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMADDUBSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMADDWDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMADDWDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMULDQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMULDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMULHRSWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMULHRSWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMULHUWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMULHUWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMULHWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMULHWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMULLWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMULLWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMULUDQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPMULUDQrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPSADBWYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VPSADBWrr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VRCPPSr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VRCPSSr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VRSQRTPSr")>;<br class="">

+def: InstRW<[BWWriteResGroup47], (instregex "VRSQRTSSr")>;<br class="">

+<br class="">

+def BWWriteResGroup48 : SchedWriteRes<[BWPort01]> {<br class="">

+  let Latency = 5;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD132PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD132PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD132PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD132PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD132SDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD132SSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD213PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD213PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD213PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD213PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD213SDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD213SSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD231PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD231PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD231PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD231PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD231SDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADD231SSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADDSUB132PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADDSUB132PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADDSUB132PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADDSUB132PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADDSUB213PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADDSUB213PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADDSUB213PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADDSUB213PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADDSUB231PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADDSUB231PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADDSUB231PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMADDSUB231PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB132PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB132PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB132PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB132PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB132SDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB132SSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB213PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB213PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB213PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB213PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB213SDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB213SSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB231PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB231PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB231PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB231PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB231SDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUB231SSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUBADD132PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUBADD132PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUBADD132PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUBADD132PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUBADD213PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUBADD213PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUBADD213PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUBADD213PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUBADD231PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUBADD231PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUBADD231PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFMSUBADD231PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD132PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD132PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD132PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD132PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD132SDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD132SSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD213PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD213PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD213PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD213PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD213SDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD213SSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD231PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD231PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD231PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD231PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD231SDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMADD231SSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB132PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB132PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB132PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB132PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB132SDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB132SSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB213PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB213PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB213PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB213PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB213SDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB213SSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB231PDYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB231PDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB231PSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB231PSr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB231SDr")>;<br class="">

+def: InstRW<[BWWriteResGroup48], (instregex "VFNMSUB231SSr")>;<br class="">

+<br class="">

+def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {<br class="">

+  let Latency = 5;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "LDDQUrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVD64from64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVD64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVD64to64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVQ64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOV(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOV64toPQIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOV8rm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVAPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVAPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVDDUPrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVDI2PDIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVDQArm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVDQUrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVNTDQArm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVSHDUPrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVSLDUPrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm16")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm32")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm8")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVUPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVUPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVZX(16|32|64)rm16")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "MOVZX(16|32|64)rm8")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "PREFETCHNTA")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "PREFETCHT0")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "PREFETCHT1")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "PREFETCHT2")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VBROADCASTSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VLDDQUrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOV64toPQIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVAPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVAPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVDDUPrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVDI2PDIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVDQArm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVDQUrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVNTDQArm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVQI2PQIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVSHDUPrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVSLDUPrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVUPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VMOVUPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VPBROADCASTDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup49], (instregex "VPBROADCASTQrm")>;<br class="">

+<br class="">

+def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {<br class="">

+  let Latency = 5;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "CVTSI2SS64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "HADDPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "HADDPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "HSUBPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "HSUBPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "VCVTSI2SS64rr")>;<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "VHADDPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "VHADDPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "VHADDPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "VHADDPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "VHSUBPDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "VHSUBPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "VHSUBPSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup50], (instregex "VHSUBPSrr")>;<br class="">

+<br class="">

+def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {<br class="">

+  let Latency = 5;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;<br class="">

+<br class="">

+def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 5;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup52], (instregex "MULX32rr")>;<br class="">

+<br class="">

+def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> {<br class="">

+  let Latency = 5;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPDYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPSYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPSmr")>;<br class="">

+def: InstRW<[BWWriteResGroup53], (instregex "VPMASKMOVDYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup53], (instregex "VPMASKMOVDmr")>;<br class="">

+def: InstRW<[BWWriteResGroup53], (instregex "VPMASKMOVQYmr")>;<br class="">

+def: InstRW<[BWWriteResGroup53], (instregex "VPMASKMOVQmr")>;<br class="">

+<br class="">

+def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {<br class="">

+  let Latency = 5;<br class="">

+  let NumMicroOps = 5;<br class="">

+  let ResourceCycles = [1,4];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>;<br class="">

+<br class="">

+def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {<br class="">

+  let Latency = 5;<br class="">

+  let NumMicroOps = 5;<br class="">

+  let ResourceCycles = [1,4];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup55], (instregex "XSETBV")>;<br class="">

+<br class="">

+def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {<br class="">

+  let Latency = 5;<br class="">

+  let NumMicroOps = 5;<br class="">

+  let ResourceCycles = [2,3];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(16|32|64)rr")>;<br class="">

+def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG8rr")>;<br class="">

+<br class="">

+def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {<br class="">

+  let Latency = 5;<br class="">

+  let NumMicroOps = 6;<br class="">

+  let ResourceCycles = [1,1,4];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup57], (instregex "PUSHF16")>;<br class="">

+def: InstRW<[BWWriteResGroup57], (instregex "PUSHF64")>;<br class="">

+<br class="">

+def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "LD_F64m")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "LD_F80m")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VBROADCASTF128")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VBROADCASTI128")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VBROADCASTSDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VBROADCASTSSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VLDDQUYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VMOVAPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VMOVAPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VMOVDDUPYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VMOVDQAYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VMOVDQUYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VMOVNTDQAYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VMOVSHDUPYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VMOVSLDUPYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VMOVUPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VMOVUPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VPBROADCASTDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VPBROADCASTQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "ROUNDPDr")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "ROUNDPSr")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "ROUNDSDr")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "ROUNDSSr")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VROUNDPDr")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VROUNDPSr")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VROUNDSDr")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VROUNDSSr")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VROUNDYPDr")>;<br class="">

+def: InstRW<[BWWriteResGroup58], (instregex "VROUNDYPSr")>;<br class="">

+<br class="">

+def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "CVTPS2PDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "CVTSS2SDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSLLDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSLLQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSLLWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSRADrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSRAWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSRLDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSRLQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSRLWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "VCVTPH2PSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "VCVTPH2PSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "VCVTPS2PDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "VCVTSS2SDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "VPSLLVQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "VPSRLVQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "VTESTPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup59], (instregex "VTESTPSrm")>;<br class="">

+<br class="">

+def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup60], (instregex "VCVTPD2DQYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup60], (instregex "VCVTPD2PSYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup60], (instregex "VCVTPS2PHYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup60], (instregex "VCVTTPD2DQYrr")>;<br class="">

+<br class="">

+def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "ANDNPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "ANDNPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "ANDPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "ANDPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "INSERTPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNR64irm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MMX_PINSRWirmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MMX_PSHUFBrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MMX_PSHUFWmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MMX_PUNPCKHBWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MMX_PUNPCKHDQirm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MMX_PUNPCKHWDirm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MMX_PUNPCKLBWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MMX_PUNPCKLDQirm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MMX_PUNPCKLWDirm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MOVHPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MOVHPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MOVLPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "MOVLPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "ORPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "ORPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PACKSSDWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PACKSSWBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PACKUSDWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PACKUSWBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PALIGNRrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PBLENDWrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PINSRBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PINSRDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PINSRQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PINSRWrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PMOVSXBDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PMOVSXBQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PMOVSXBWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PMOVSXDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PMOVSXWDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PMOVSXWQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PMOVZXBDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PMOVZXBQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PMOVZXBWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PMOVZXDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PMOVZXWDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PMOVZXWQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PSHUFBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PSHUFDmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PSHUFHWmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PSHUFLWmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PUNPCKHBWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PUNPCKHDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PUNPCKHQDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PUNPCKHWDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PUNPCKLBWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PUNPCKLDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PUNPCKLQDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "PUNPCKLWDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "SHUFPDrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "SHUFPSrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "UNPCKHPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "UNPCKHPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "UNPCKLPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "UNPCKLPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VANDNPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VANDNPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VANDPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VANDPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VINSERTPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VMOVHPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VMOVHPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VMOVLPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VMOVLPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VORPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VORPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPACKSSDWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPACKSSWBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPACKUSDWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPACKUSWBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPALIGNRrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPBLENDWrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPERMILPDmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPERMILPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPERMILPSmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPERMILPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPINSRBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPINSRDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPINSRQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPINSRWrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPMOVSXBDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPMOVSXBQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPMOVSXBWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPMOVSXDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPMOVSXWDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPMOVSXWQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPMOVZXBDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPMOVZXBQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPMOVZXBWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPMOVZXDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPMOVZXWDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPMOVZXWQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPSHUFBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPSHUFDmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPSHUFHWmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPSHUFLWmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPUNPCKHBWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPUNPCKHDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPUNPCKHQDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPUNPCKHWDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPUNPCKLBWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPUNPCKLDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPUNPCKLQDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VPUNPCKLWDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VSHUFPDrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VSHUFPSrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VUNPCKHPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VUNPCKHPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VUNPCKLPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VUNPCKLPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VXORPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "VXORPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "XORPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup61], (instregex "XORPSrm")>;<br class="">

+<br class="">

+def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64")>;<br class="">

+def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>;<br class="">

+<br class="">

+def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "ADC(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "ADC8rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "ADCX32rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "ADCX64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "ADOX32rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "ADOX64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVAE(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVB(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVE(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVG(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVGE(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVL(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVLE(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVNE(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVNO(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVNP(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVNS(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVO(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVP(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "CMOVS(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "RORX32mi")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "RORX64mi")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "SARX32rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "SARX64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "SBB(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "SBB8rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "SHLX32rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "SHLX64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "SHRX32rm")>;<br class="">

+def: InstRW<[BWWriteResGroup63], (instregex "SHRX64rm")>;<br class="">

+<br class="">

+def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "ANDN32rm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "ANDN64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "BLSI32rm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "BLSI64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "BLSMSK32rm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "BLSMSK64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "BLSR32rm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "BLSR64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "BZHI32rm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "BZHI64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PABSBrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PABSDrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PABSWrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PADDBirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PADDDirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PADDQirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PADDSBirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PADDSWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PADDUSBirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PADDUSWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PADDWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PAVGBirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PAVGWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PCMPEQBirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PCMPEQDirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PCMPEQWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PCMPGTBirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PCMPGTDirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PCMPGTWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PMAXSWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PMAXUBirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PMINSWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PMINUBirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSIGNBrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSIGNDrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSIGNWrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSUBBirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSUBDirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSUBQirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSUBSBirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSUBSWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSUBUSBirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSUBUSWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSUBWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "MOVBE(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PABSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PABSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PABSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PADDBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PADDDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PADDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PADDSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PADDSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PADDUSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PADDUSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PADDWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PAVGBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PAVGWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PCMPEQBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PCMPEQDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PCMPEQQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PCMPEQWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PCMPGTBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PCMPGTDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PCMPGTWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PMAXSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PMAXSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PMAXSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PMAXUBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PMAXUDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PMAXUWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PMINSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PMINSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PMINSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PMINUBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PMINUDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PMINUWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PSIGNBrm128")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PSIGNDrm128")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PSIGNWrm128")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PSUBBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PSUBDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PSUBQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PSUBSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PSUBSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PSUBUSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PSUBUSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "PSUBWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPABSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPABSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPABSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPADDBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPADDDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPADDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPADDSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPADDSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPADDUSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPADDUSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPADDWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPAVGBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPAVGWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPCMPEQBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPCMPEQDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPCMPEQQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPCMPEQWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPCMPGTBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPCMPGTDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPCMPGTWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPMAXSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPMAXSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPMAXSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPMAXUBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPMAXUDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPMAXUWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPMINSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPMINSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPMINSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPMINUBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPMINUDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPMINUWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPSIGNBrm128")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPSIGNDrm128")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPSIGNWrm128")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPSUBBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPSUBDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPSUBQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPSUBSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPSUBSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPSUBUSBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPSUBUSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup64], (instregex "VPSUBWrm")>;<br class="">

+<br class="">

+def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "BLENDPDrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "BLENDPSrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "MMX_PANDNirm")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "MMX_PANDirm")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "MMX_PORirm")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "MMX_PXORirm")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "PANDNrm")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "PANDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "PORrm")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "PXORrm")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "VBLENDPDrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "VBLENDPSrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "VINSERTF128rm")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "VINSERTI128rm")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "VPANDNrm")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "VPANDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "VPBLENDDrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "VPORrm")>;<br class="">

+def: InstRW<[BWWriteResGroup65], (instregex "VPXORrm")>;<br class="">

+<br class="">

+def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "ADD(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "ADD8rm")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "AND(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "AND8rm")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)mi8")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)mr")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "CMP8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "CMP8mr")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "CMP8rm")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "OR(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "OR8rm")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)r")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "SUB(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "SUB8rm")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "TEST(16|32|64)mr")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "TEST8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "TEST8mr")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "XOR(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup66], (instregex "XOR8rm")>;<br class="">

+<br class="">

+def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,1,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup67], (instregex "SHLD(16|32|64)rrCL")>;<br class="">

+def: InstRW<[BWWriteResGroup67], (instregex "SHRD(16|32|64)rrCL")>;<br class="">

+<br class="">

+def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;<br class="">

+<br class="">

+def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "BTR(16|32|64)mi8")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "BTS(16|32|64)mi8")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "SAR(16|32|64)m1")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "SAR(16|32|64)mi")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "SAR8m1")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "SAR8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "SHL(16|32|64)m1")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "SHL(16|32|64)mi")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "SHL8m1")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "SHL8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "SHR(16|32|64)m1")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "SHR(16|32|64)mi")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "SHR8m1")>;<br class="">

+def: InstRW<[BWWriteResGroup69], (instregex "SHR8mi")>;<br class="">

+<br class="">

+def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "ADD(16|32|64)mi8")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "ADD(16|32|64)mr")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "ADD8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "ADD8mr")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "AND(16|32|64)mi8")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "AND(16|32|64)mr")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "AND8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "AND8mr")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "DEC(16|32|64)m")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "DEC8m")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "INC(16|32|64)m")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "INC8m")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "NEG(16|32|64)m")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "NEG8m")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "NOT(16|32|64)m")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "NOT8m")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "OR(16|32|64)mi8")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "OR(16|32|64)mr")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "OR8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "OR8mr")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "PUSH(16|32|64)rmm")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "SUB(16|32|64)mi8")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "SUB(16|32|64)mr")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "SUB8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "SUB8mr")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "XOR(16|32|64)mi8")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "XOR(16|32|64)mr")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "XOR8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup70], (instregex "XOR8mr")>;<br class="">

+<br class="">

+def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {<br class="">

+  let Latency = 6;<br class="">

+  let NumMicroOps = 6;<br class="">

+  let ResourceCycles = [1,5];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup71], (instregex "STD")>;<br class="">

+<br class="">

+def BWWriteResGroup72 : SchedWriteRes<[BWPort5]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup72], (instregex "AESDECLASTrr")>;<br class="">

+def: InstRW<[BWWriteResGroup72], (instregex "AESDECrr")>;<br class="">

+def: InstRW<[BWWriteResGroup72], (instregex "AESENCLASTrr")>;<br class="">

+def: InstRW<[BWWriteResGroup72], (instregex "AESENCrr")>;<br class="">

+def: InstRW<[BWWriteResGroup72], (instregex "VAESDECLASTrr")>;<br class="">

+def: InstRW<[BWWriteResGroup72], (instregex "VAESDECrr")>;<br class="">

+def: InstRW<[BWWriteResGroup72], (instregex "VAESENCLASTrr")>;<br class="">

+def: InstRW<[BWWriteResGroup72], (instregex "VAESENCrr")>;<br class="">

+<br class="">

+def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup73], (instregex "VPSLLDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup73], (instregex "VPSLLQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup73], (instregex "VPSLLVQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup73], (instregex "VPSLLWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup73], (instregex "VPSRADYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup73], (instregex "VPSRAWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup73], (instregex "VPSRLDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup73], (instregex "VPSRLQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup73], (instregex "VPSRLVQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup73], (instregex "VPSRLWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup73], (instregex "VTESTPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup73], (instregex "VTESTPSYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup74], (instregex "FCOM32m")>;<br class="">

+def: InstRW<[BWWriteResGroup74], (instregex "FCOM64m")>;<br class="">

+def: InstRW<[BWWriteResGroup74], (instregex "FCOMP32m")>;<br class="">

+def: InstRW<[BWWriteResGroup74], (instregex "FCOMP64m")>;<br class="">

+<br class="">

+def BWWriteResGroup75 : SchedWriteRes<[BWPort5,BWPort23]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VANDNPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VANDNPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VANDPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VANDPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VORPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VORPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPACKSSDWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPACKSSWBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPACKUSDWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPACKUSWBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPALIGNRYrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPBLENDWYrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPERMILPDYmi")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPERMILPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPERMILPSYmi")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPERMILPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPSHUFBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPSHUFDYmi")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPSHUFHWYmi")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPSHUFLWYmi")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPUNPCKHBWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPUNPCKHDQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPUNPCKHQDQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPUNPCKHWDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPUNPCKLBWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPUNPCKLDQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPUNPCKLQDQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VPUNPCKLWDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VSHUFPDYrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VSHUFPSYrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VUNPCKHPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VUNPCKHPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VUNPCKLPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VUNPCKLPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VXORPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup75], (instregex "VXORPSYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup76 : SchedWriteRes<[BWPort23,BWPort15]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPABSBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPABSDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPABSWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPADDBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPADDDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPADDQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPADDSBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPADDSWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPADDUSBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPADDUSWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPADDWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPAVGBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPAVGWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPCMPEQBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPCMPEQDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPCMPEQQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPCMPEQWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPCMPGTBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPCMPGTDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPCMPGTWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPMAXSBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPMAXSDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPMAXSWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPMAXUBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPMAXUDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPMAXUWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPMINSBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPMINSDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPMINSWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPMINUBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPMINUDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPMINUWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPSIGNBYrm256")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPSIGNDYrm256")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPSIGNWYrm256")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPSUBBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPSUBDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPSUBQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPSUBSBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPSUBSWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPSUBUSBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPSUBUSWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup76], (instregex "VPSUBWYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPDYrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPSYrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup77], (instregex "VPANDNYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup77], (instregex "VPANDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup77], (instregex "VPBLENDDYrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup77], (instregex "VPORYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup77], (instregex "VPXORYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup78 : SchedWriteRes<[BWPort0,BWPort5]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup78], (instregex "MPSADBWrri")>;<br class="">

+def: InstRW<[BWWriteResGroup78], (instregex "VMPSADBWYrri")>;<br class="">

+def: InstRW<[BWWriteResGroup78], (instregex "VMPSADBWrri")>;<br class="">

+<br class="">

+def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup79], (instregex "BLENDVPDrm0")>;<br class="">

+def: InstRW<[BWWriteResGroup79], (instregex "BLENDVPSrm0")>;<br class="">

+def: InstRW<[BWWriteResGroup79], (instregex "MMX_PACKSSDWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup79], (instregex "MMX_PACKSSWBirm")>;<br class="">

+def: InstRW<[BWWriteResGroup79], (instregex "MMX_PACKUSWBirm")>;<br class="">

+def: InstRW<[BWWriteResGroup79], (instregex "PBLENDVBrm0")>;<br class="">

+def: InstRW<[BWWriteResGroup79], (instregex "VBLENDVPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup79], (instregex "VBLENDVPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup79], (instregex "VMASKMOVPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup79], (instregex "VMASKMOVPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup79], (instregex "VPBLENDVBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup79], (instregex "VPMASKMOVDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup79], (instregex "VPMASKMOVQrm")>;<br class="">

+<br class="">

+def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup80], (instregex "LEAVE64")>;<br class="">

+def: InstRW<[BWWriteResGroup80], (instregex "SCASB")>;<br class="">

+def: InstRW<[BWWriteResGroup80], (instregex "SCASL")>;<br class="">

+def: InstRW<[BWWriteResGroup80], (instregex "SCASQ")>;<br class="">

+def: InstRW<[BWWriteResGroup80], (instregex "SCASW")>;<br class="">

+<br class="">

+def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "PSLLQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "PSLLWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "PSRADrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "PSRAWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "PSRLDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "PSRLQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "PSRLWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "PTESTrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "VPSLLDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "VPSLLQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "VPSLLWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "VPSRADrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "VPSRAWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "VPSRLDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "VPSRLQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "VPSRLWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup81], (instregex "VPTESTrm")>;<br class="">

+<br class="">

+def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup82], (instregex "FLDCW16m")>;<br class="">

+<br class="">

+def BWWriteResGroup83 : SchedWriteRes<[BWPort0,BWPort23,BWPort0156]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup83], (instregex "LDMXCSR")>;<br class="">

+def: InstRW<[BWWriteResGroup83], (instregex "VLDMXCSR")>;<br class="">

+<br class="">

+def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup84], (instregex "LRETQ")>;<br class="">

+def: InstRW<[BWWriteResGroup84], (instregex "RETQ")>;<br class="">

+<br class="">

+def BWWriteResGroup85 : SchedWriteRes<[BWPort23,BWPort06,BWPort15]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup85], (instregex "BEXTR32rm")>;<br class="">

+def: InstRW<[BWWriteResGroup85], (instregex "BEXTR64rm")>;<br class="">

+<br class="">

+def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup86], (instregex "CMOVA(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup86], (instregex "CMOVBE(16|32|64)rm")>;<br class="">

+<br class="">

+def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 5;<br class="">

+  let ResourceCycles = [1,1,1,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup87], (instregex "ROL(16|32|64)m1")>;<br class="">

+def: InstRW<[BWWriteResGroup87], (instregex "ROL(16|32|64)mi")>;<br class="">

+def: InstRW<[BWWriteResGroup87], (instregex "ROL8m1")>;<br class="">

+def: InstRW<[BWWriteResGroup87], (instregex "ROL8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup87], (instregex "ROR(16|32|64)m1")>;<br class="">

+def: InstRW<[BWWriteResGroup87], (instregex "ROR(16|32|64)mi")>;<br class="">

+def: InstRW<[BWWriteResGroup87], (instregex "ROR8m1")>;<br class="">

+def: InstRW<[BWWriteResGroup87], (instregex "ROR8mi")>;<br class="">

+<br class="">

+def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 5;<br class="">

+  let ResourceCycles = [1,1,1,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup88], (instregex "XADD(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup88], (instregex "XADD8rm")>;<br class="">

+<br class="">

+def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 5;<br class="">

+  let ResourceCycles = [1,1,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m")>;<br class="">

+def: InstRW<[BWWriteResGroup89], (instregex "FARCALL64")>;<br class="">

+<br class="">

+def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {<br class="">

+  let Latency = 7;<br class="">

+  let NumMicroOps = 7;<br class="">

+  let ResourceCycles = [2,2,1,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup90], (instregex "LOOP")>;<br class="">

+<br class="">

+def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {<br class="">

+  let Latency = 8;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "ADDPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "ADDPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "ADDSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "ADDSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "ADDSUBPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "ADDSUBPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "BSF(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "BSR(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "CMPPDrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "CMPPSrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "CMPSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "COMISDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "COMISSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "CVTDQ2PSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "CVTPS2DQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "CVTTPS2DQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "IMUL64m")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "IMUL(32|64)rm(i8?)")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "IMUL8m")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "LZCNT(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "MAXPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "MAXPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "MAXSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "MAXSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "MINPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "MINPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "MINSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "MINSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPS2PIirm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTTPS2PIirm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "MUL64m")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "MUL8m")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "PDEP32rm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "PDEP64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "PEXT32rm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "PEXT64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "POPCNT(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "SUBPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "SUBPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "SUBSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "SUBSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "TZCNT(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "UCOMISDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "UCOMISSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VADDPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VADDPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VADDSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VADDSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VADDSUBPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VADDSUBPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VCMPPDrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VCMPPSrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VCMPSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VCMPSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VCOMISDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VCOMISSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VCVTDQ2PSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VCVTPS2DQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VCVTTPS2DQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VMAXPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VMAXPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VMAXSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VMAXSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VMINPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VMINPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VMINSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VMINSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VSUBPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VSUBPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VSUBSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VSUBSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VUCOMISDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup91], (instregex "VUCOMISSrm")>;<br class="">

+<br class="">

+def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {<br class="">

+  let Latency = 8;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1]; <br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup91_16], (instregex "IMUL16rm(i8?)")>;<br class="">

+<br class="">

+def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {<br class="">

+  let Latency = 8;<br class="">

+  let NumMicroOps = 5;<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup91_16_2], (instregex "IMUL16m")>;<br class="">

+def: InstRW<[BWWriteResGroup91_16_2], (instregex "MUL16m")>;<br class="">

+<br class="">

+def BWWriteResGroup91_32 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {<br class="">

+  let Latency = 8;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup91_32], (instregex "IMUL32m")>;<br class="">

+def: InstRW<[BWWriteResGroup91_32], (instregex "MUL32m")>;<br class="">

+<br class="">

+def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {<br class="">

+  let Latency = 8;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXDQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXWDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXWQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup92], (instregex "VPMOVZXWDYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> {<br class="">

+  let Latency = 8;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup93], (instregex "MULPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup93], (instregex "MULPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup93], (instregex "MULSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup93], (instregex "MULSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup93], (instregex "VMULPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup93], (instregex "VMULPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup93], (instregex "VMULSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup93], (instregex "VMULSSrm")>;<br class="">

+<br class="">

+def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> {<br class="">

+  let Latency = 8;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup94], (instregex "VBLENDVPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup94], (instregex "VBLENDVPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup94], (instregex "VMASKMOVPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup94], (instregex "VMASKMOVPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup94], (instregex "VPBLENDVBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup94], (instregex "VPMASKMOVDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup94], (instregex "VPMASKMOVQYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup95 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {<br class="">

+  let Latency = 8;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [2,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup95], (instregex "VPSLLVDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup95], (instregex "VPSRAVDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup95], (instregex "VPSRLVDrm")>;<br class="">

+<br class="">

+def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {<br class="">

+  let Latency = 8;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [2,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDSWrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDWrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBDrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBSWrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBWrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "PHADDDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "PHADDSWrm128")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "PHADDWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "PHSUBDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "PHSUBSWrm128")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "PHSUBWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "VPHADDDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "VPHADDSWrm128")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "VPHADDWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "VPHSUBDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "VPHSUBSWrm128")>;<br class="">

+def: InstRW<[BWWriteResGroup96], (instregex "VPHSUBWrm")>;<br class="">

+<br class="">

+def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 8;<br class="">

+  let NumMicroOps = 5;<br class="">

+  let ResourceCycles = [1,1,1,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup97], (instregex "RCL(16|32|64)m1")>;<br class="">

+def: InstRW<[BWWriteResGroup97], (instregex "RCL(16|32|64)mi")>;<br class="">

+def: InstRW<[BWWriteResGroup97], (instregex "RCL8m1")>;<br class="">

+def: InstRW<[BWWriteResGroup97], (instregex "RCL8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup97], (instregex "RCR(16|32|64)m1")>;<br class="">

+def: InstRW<[BWWriteResGroup97], (instregex "RCR(16|32|64)mi")>;<br class="">

+def: InstRW<[BWWriteResGroup97], (instregex "RCR8m1")>;<br class="">

+def: InstRW<[BWWriteResGroup97], (instregex "RCR8mi")>;<br class="">

+<br class="">

+def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 8;<br class="">

+  let NumMicroOps = 5;<br class="">

+  let ResourceCycles = [1,1,2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup98], (instregex "ROR(16|32|64)mCL")>;<br class="">

+def: InstRW<[BWWriteResGroup98], (instregex "ROR8mCL")>;<br class="">

+<br class="">

+def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {<br class="">

+  let Latency = 8;<br class="">

+  let NumMicroOps = 6;<br class="">

+  let ResourceCycles = [1,1,1,3];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup99], (instregex "ADC(16|32|64)mi8")>;<br class="">

+def: InstRW<[BWWriteResGroup99], (instregex "ADC8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup99], (instregex "ADD8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup99], (instregex "AND8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup99], (instregex "OR8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup99], (instregex "SUB8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup99], (instregex "XCHG(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup99], (instregex "XCHG8rm")>;<br class="">

+def: InstRW<[BWWriteResGroup99], (instregex "XOR8mi")>;<br class="">

+<br class="">

+def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 8;<br class="">

+  let NumMicroOps = 6;<br class="">

+  let ResourceCycles = [1,1,1,2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "ADC(16|32|64)mr")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "ADC8mr")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG8rm")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "ROL(16|32|64)mCL")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "ROL8mCL")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "SAR(16|32|64)mCL")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "SAR8mCL")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "SBB(16|32|64)mi8")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "SBB(16|32|64)mr")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "SBB8mi")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "SBB8mr")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "SHL(16|32|64)mCL")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "SHL8mCL")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "SHR(16|32|64)mCL")>;<br class="">

+def: InstRW<[BWWriteResGroup100], (instregex "SHR8mCL")>;<br class="">

+<br class="">

+def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {<br class="">

+  let Latency = 9;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "ADD_F64m")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "ILD_F16m")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "ILD_F32m")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "ILD_F64m")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "SUBR_F32m")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "SUBR_F64m")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "SUB_F32m")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "SUB_F64m")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VADDPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VADDPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VADDSUBPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VADDSUBPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VCMPPDYrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VCMPPSYrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VCVTDQ2PSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VCVTPS2DQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VCVTTPS2DQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VMAXPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VMAXPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VMINPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VMINPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VSUBPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup101], (instregex "VSUBPSYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {<br class="">

+  let Latency = 9;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup102], (instregex "VPERM2F128rm")>;<br class="">

+def: InstRW<[BWWriteResGroup102], (instregex "VPERM2I128rm")>;<br class="">

+def: InstRW<[BWWriteResGroup102], (instregex "VPERMDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup102], (instregex "VPERMPDYmi")>;<br class="">

+def: InstRW<[BWWriteResGroup102], (instregex "VPERMPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup102], (instregex "VPERMQYmi")>;<br class="">

+def: InstRW<[BWWriteResGroup102], (instregex "VPMOVZXBDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup102], (instregex "VPMOVZXBQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup102], (instregex "VPMOVZXBWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup102], (instregex "VPMOVZXDQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup102], (instregex "VPMOVZXWQYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup103 : SchedWriteRes<[BWPort01,BWPort23]> {<br class="">

+  let Latency = 9;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup103], (instregex "VMULPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup103], (instregex "VMULPSYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {<br class="">

+  let Latency = 9;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup104], (instregex "DPPDrri")>;<br class="">

+def: InstRW<[BWWriteResGroup104], (instregex "VDPPDrri")>;<br class="">

+<br class="">

+def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {<br class="">

+  let Latency = 9;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "CVTSD2SI64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "CVTSD2SIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "CVTSS2SI64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "CVTSS2SIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "CVTTSD2SI64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "CVTTSD2SIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "CVTTSS2SIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "VCVTSD2SI64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "VCVTSD2SIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "VCVTSS2SI64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "VCVTSS2SIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "VCVTTSD2SI64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "VCVTTSD2SIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "VCVTTSS2SI64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup105], (instregex "VCVTTSS2SIrm")>;<br class="">

+<br class="">

+def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {<br class="">

+  let Latency = 9;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {<br class="">

+  let Latency = 9;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup107], (instregex "CVTDQ2PDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2DQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2PSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup107], (instregex "CVTSD2SSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup107], (instregex "CVTTPD2DQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVTPD2PIirm")>;<br class="">

+def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVTPI2PDirm")>;<br class="">

+def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVTTPD2PIirm")>;<br class="">

+def: InstRW<[BWWriteResGroup107], (instregex "MULX64rm")>;<br class="">

+def: InstRW<[BWWriteResGroup107], (instregex "VCVTDQ2PDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup107], (instregex "VCVTSD2SSrm")>;<br class="">

+<br class="">

+def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {<br class="">

+  let Latency = 9;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTBYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTBrm")>;<br class="">

+def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTWrm")>;<br class="">

+<br class="">

+def BWWriteResGroup109 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {<br class="">

+  let Latency = 9;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [2,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup109], (instregex "VPSLLVDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup109], (instregex "VPSRAVDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup109], (instregex "VPSRLVDYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup110 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {<br class="">

+  let Latency = 9;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [2,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup110], (instregex "VPHADDDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup110], (instregex "VPHADDSWrm256")>;<br class="">

+def: InstRW<[BWWriteResGroup110], (instregex "VPHADDWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup110], (instregex "VPHSUBDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup110], (instregex "VPHSUBSWrm256")>;<br class="">

+def: InstRW<[BWWriteResGroup110], (instregex "VPHSUBWYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup111 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort0156]> {<br class="">

+  let Latency = 9;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup111], (instregex "SHLD(16|32|64)mri8")>;<br class="">

+def: InstRW<[BWWriteResGroup111], (instregex "SHRD(16|32|64)mri8")>;<br class="">

+<br class="">

+def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 9;<br class="">

+  let NumMicroOps = 5;<br class="">

+  let ResourceCycles = [1,1,3];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;<br class="">

+<br class="">

+def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {<br class="">

+  let Latency = 9;<br class="">

+  let NumMicroOps = 5;<br class="">

+  let ResourceCycles = [1,2,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm")>;<br class="">

+def: InstRW<[BWWriteResGroup113], (instregex "LSL(16|32|64)rm")>;<br class="">

+<br class="">

+def BWWriteResGroup114 : SchedWriteRes<[BWPort0]> {<br class="">

+  let Latency = 10;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup114], (instregex "PMULLDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup114], (instregex "VPMULLDYrr")>;<br class="">

+def: InstRW<[BWWriteResGroup114], (instregex "VPMULLDrr")>;<br class="">

+<br class="">

+def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {<br class="">

+  let Latency = 10;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDWDirm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMULHRSWrm64")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMULHUWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMULHWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMULLWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMULUDQirm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "MMX_PSADBWirm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "PCLMULQDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "PCMPGTQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "PHMINPOSUWrm128")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "PMADDUBSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "PMADDWDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "PMULDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "PMULHRSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "PMULHUWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "PMULHWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "PMULLWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "PMULUDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "PSADBWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "RCPPSm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "RCPSSm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "RSQRTPSm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "RSQRTSSm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VPCLMULQDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VPCMPGTQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VPHMINPOSUWrm128")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VPMADDUBSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VPMADDWDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VPMULDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VPMULHRSWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VPMULHUWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VPMULHWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VPMULLWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VPMULUDQrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VPSADBWrm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VRCPPSm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VRCPSSm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VRSQRTPSm")>;<br class="">

+def: InstRW<[BWWriteResGroup115], (instregex "VRSQRTSSm")>;<br class="">

+<br class="">

+def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> {<br class="">

+  let Latency = 10;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADD132PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADD132PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADD132SDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADD132SSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADD213PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADD213PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADD213SDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADD213SSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADD231PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADD231PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADD231SDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADD231SSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADDSUB132PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADDSUB132PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADDSUB213PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADDSUB213PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADDSUB231PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMADDSUB231PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUB132PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUB132PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUB132SDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUB132SSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUB213PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUB213PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUB213SDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUB213SSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUB231PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUB231PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUB231SDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUB231SSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUBADD132PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUBADD132PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUBADD213PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUBADD213PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUBADD231PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFMSUBADD231PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMADD132PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMADD132PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMADD132SDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMADD132SSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMADD213PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMADD213PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMADD213SDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMADD213SSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMADD231PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMADD231PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMADD231SDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMADD231SSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMSUB132PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMSUB132PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMSUB132SDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMSUB132SSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMSUB213PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMSUB213PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMSUB213SDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMSUB213SSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMSUB231PDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMSUB231PSm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMSUB231SDm")>;<br class="">

+def: InstRW<[BWWriteResGroup116], (instregex "VFNMSUB231SSm")>;<br class="">

+<br class="">

+def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {<br class="">

+  let Latency = 10;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m")>;<br class="">

+def: InstRW<[BWWriteResGroup117], (instregex "FICOM32m")>;<br class="">

+def: InstRW<[BWWriteResGroup117], (instregex "FICOMP16m")>;<br class="">

+def: InstRW<[BWWriteResGroup117], (instregex "FICOMP32m")>;<br class="">

+<br class="">

+def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {<br class="">

+  let Latency = 10;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup119 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {<br class="">

+  let Latency = 10;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup119], (instregex "HADDPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup119], (instregex "HADDPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup119], (instregex "HSUBPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup119], (instregex "HSUBPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup119], (instregex "VHADDPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup119], (instregex "VHADDPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup119], (instregex "VHSUBPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup119], (instregex "VHSUBPSrm")>;<br class="">

+<br class="">

+def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {<br class="">

+  let Latency = 10;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;<br class="">

+<br class="">

+def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 10;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup121], (instregex "MULX32rm")>;<br class="">

+<br class="">

+def BWWriteResGroup122 : SchedWriteRes<[BWPort0]> {<br class="">

+  let Latency = 11;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup122], (instregex "DIVPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup122], (instregex "DIVSSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup122], (instregex "VDIVPSrr")>;<br class="">

+def: InstRW<[BWWriteResGroup122], (instregex "VDIVSSrr")>;<br class="">

+<br class="">

+def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {<br class="">

+  let Latency = 11;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup123], (instregex "MUL_F32m")>;<br class="">

+def: InstRW<[BWWriteResGroup123], (instregex "MUL_F64m")>;<br class="">

+def: InstRW<[BWWriteResGroup123], (instregex "VPCMPGTQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup123], (instregex "VPMADDUBSWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup123], (instregex "VPMADDWDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup123], (instregex "VPMULDQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup123], (instregex "VPMULHRSWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup123], (instregex "VPMULHUWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup123], (instregex "VPMULHWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup123], (instregex "VPMULLWYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup123], (instregex "VPMULUDQYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup123], (instregex "VPSADBWYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup124 : SchedWriteRes<[BWPort01,BWPort23]> {<br class="">

+  let Latency = 11;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMADD132PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMADD132PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMADD213PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMADD213PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMADD231PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMADD231PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMADDSUB132PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMADDSUB132PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMADDSUB213PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMADDSUB213PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMADDSUB231PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMADDSUB231PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMSUB132PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMSUB132PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMSUB213PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMSUB213PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMSUB231PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMSUB231PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMSUBADD132PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMSUBADD132PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMSUBADD213PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMSUBADD213PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMSUBADD231PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFMSUBADD231PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFNMADD132PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFNMADD132PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFNMADD213PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFNMADD213PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFNMADD231PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFNMADD231PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFNMSUB132PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFNMSUB132PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFNMSUB213PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFNMSUB213PSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFNMSUB231PDYm")>;<br class="">

+def: InstRW<[BWWriteResGroup124], (instregex "VFNMSUB231PSYm")>;<br class="">

+<br class="">

+def BWWriteResGroup125 : SchedWriteRes<[BWPort0]> {<br class="">

+  let Latency = 11;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [3];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup125], (instregex "PCMPISTRIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup125], (instregex "PCMPISTRM128rr")>;<br class="">

+def: InstRW<[BWWriteResGroup125], (instregex "VPCMPISTRIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup125], (instregex "VPCMPISTRM128rr")>;<br class="">

+<br class="">

+def BWWriteResGroup126 : SchedWriteRes<[BWPort0,BWPort015]> {<br class="">

+  let Latency = 11;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup126], (instregex "VRCPPSYr")>;<br class="">

+def: InstRW<[BWWriteResGroup126], (instregex "VRSQRTPSYr")>;<br class="">

+<br class="">

+def BWWriteResGroup127 : SchedWriteRes<[BWPort1,BWPort23]> {<br class="">

+  let Latency = 11;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup127], (instregex "ROUNDPDm")>;<br class="">

+def: InstRW<[BWWriteResGroup127], (instregex "ROUNDPSm")>;<br class="">

+def: InstRW<[BWWriteResGroup127], (instregex "ROUNDSDm")>;<br class="">

+def: InstRW<[BWWriteResGroup127], (instregex "ROUNDSSm")>;<br class="">

+def: InstRW<[BWWriteResGroup127], (instregex "VROUNDPDm")>;<br class="">

+def: InstRW<[BWWriteResGroup127], (instregex "VROUNDPSm")>;<br class="">

+def: InstRW<[BWWriteResGroup127], (instregex "VROUNDSDm")>;<br class="">

+def: InstRW<[BWWriteResGroup127], (instregex "VROUNDSSm")>;<br class="">

+<br class="">

+def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {<br class="">

+  let Latency = 11;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup129 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {<br class="">

+  let Latency = 11;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup129], (instregex "VHADDPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup129], (instregex "VHADDPSYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup129], (instregex "VHSUBPDYrm")>;<br class="">

+def: InstRW<[BWWriteResGroup129], (instregex "VHSUBPSYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup130 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 11;<br class="">

+  let NumMicroOps = 6;<br class="">

+  let ResourceCycles = [1,1,1,1,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup130], (instregex "SHLD(16|32|64)mrCL")>;<br class="">

+def: InstRW<[BWWriteResGroup130], (instregex "SHRD(16|32|64)mrCL")>;<br class="">

+<br class="">

+def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 11;<br class="">

+  let NumMicroOps = 7;<br class="">

+  let ResourceCycles = [2,2,3];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL")>;<br class="">

+def: InstRW<[BWWriteResGroup131], (instregex "RCR(16|32|64)rCL")>;<br class="">

+<br class="">

+def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {<br class="">

+  let Latency = 11;<br class="">

+  let NumMicroOps = 9;<br class="">

+  let ResourceCycles = [1,4,1,3];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>;<br class="">

+<br class="">

+def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {<br class="">

+  let Latency = 11;<br class="">

+  let NumMicroOps = 11;<br class="">

+  let ResourceCycles = [2,9];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup133], (instregex "LOOPE")>;<br class="">

+def: InstRW<[BWWriteResGroup133], (instregex "LOOPNE")>;<br class="">

+<br class="">

+def BWWriteResGroup134 : SchedWriteRes<[BWPort5,BWPort23]> {<br class="">

+  let Latency = 12;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup134], (instregex "AESDECLASTrm")>;<br class="">

+def: InstRW<[BWWriteResGroup134], (instregex "AESDECrm")>;<br class="">

+def: InstRW<[BWWriteResGroup134], (instregex "AESENCLASTrm")>;<br class="">

+def: InstRW<[BWWriteResGroup134], (instregex "AESENCrm")>;<br class="">

+def: InstRW<[BWWriteResGroup134], (instregex "VAESDECLASTrm")>;<br class="">

+def: InstRW<[BWWriteResGroup134], (instregex "VAESDECrm")>;<br class="">

+def: InstRW<[BWWriteResGroup134], (instregex "VAESENCLASTrm")>;<br class="">

+def: InstRW<[BWWriteResGroup134], (instregex "VAESENCrm")>;<br class="">

+<br class="">

+def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {<br class="">

+  let Latency = 12;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m")>;<br class="">

+def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI32m")>;<br class="">

+def: InstRW<[BWWriteResGroup135], (instregex "SUBR_FI16m")>;<br class="">

+def: InstRW<[BWWriteResGroup135], (instregex "SUBR_FI32m")>;<br class="">

+def: InstRW<[BWWriteResGroup135], (instregex "SUB_FI16m")>;<br class="">

+def: InstRW<[BWWriteResGroup135], (instregex "SUB_FI32m")>;<br class="">

+def: InstRW<[BWWriteResGroup135], (instregex "VROUNDYPDm")>;<br class="">

+def: InstRW<[BWWriteResGroup135], (instregex "VROUNDYPSm")>;<br class="">

+<br class="">

+def BWWriteResGroup136 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {<br class="">

+  let Latency = 12;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup136], (instregex "MPSADBWrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup136], (instregex "VMPSADBWrmi")>;<br class="">

+<br class="">

+def BWWriteResGroup137 : SchedWriteRes<[BWPort0]> {<br class="">

+  let Latency = 13;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup137], (instregex "SQRTPSr")>;<br class="">

+def: InstRW<[BWWriteResGroup137], (instregex "SQRTSSr")>;<br class="">

+<br class="">

+def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {<br class="">

+  let Latency = 13;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;<br class="">

+<br class="">

+def BWWriteResGroup139 : SchedWriteRes<[BWPort0]> {<br class="">

+  let Latency = 14;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup139], (instregex "DIVPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup139], (instregex "DIVSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup139], (instregex "VDIVPDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup139], (instregex "VDIVSDrr")>;<br class="">

+def: InstRW<[BWWriteResGroup139], (instregex "VSQRTPSr")>;<br class="">

+def: InstRW<[BWWriteResGroup139], (instregex "VSQRTSSr")>;<br class="">

+<br class="">

+def BWWriteResGroup140 : SchedWriteRes<[BWPort5]> {<br class="">

+  let Latency = 14;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup140], (instregex "AESIMCrr")>;<br class="">

+def: InstRW<[BWWriteResGroup140], (instregex "VAESIMCrr")>;<br class="">

+<br class="">

+def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {<br class="">

+  let Latency = 14;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI16m")>;<br class="">

+def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI32m")>;<br class="">

+<br class="">

+def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {<br class="">

+  let Latency = 14;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [2,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup142], (instregex "DPPSrri")>;<br class="">

+def: InstRW<[BWWriteResGroup142], (instregex "VDPPSYrri")>;<br class="">

+def: InstRW<[BWWriteResGroup142], (instregex "VDPPSrri")>;<br class="">

+<br class="">

+def BWWriteResGroup143 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {<br class="">

+  let Latency = 14;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [1,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup143], (instregex "DPPDrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup143], (instregex "VDPPDrmi")>;<br class="">

+<br class="">

+def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {<br class="">

+  let Latency = 14;<br class="">

+  let NumMicroOps = 8;<br class="">

+  let ResourceCycles = [2,2,1,3];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;<br class="">

+<br class="">

+def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {<br class="">

+  let Latency = 14;<br class="">

+  let NumMicroOps = 10;<br class="">

+  let ResourceCycles = [2,3,1,4];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>;<br class="">

+<br class="">

+def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {<br class="">

+  let Latency = 14;<br class="">

+  let NumMicroOps = 12;<br class="">

+  let ResourceCycles = [2,1,4,5];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup146], (instregex "XCH_F")>;<br class="">

+<br class="">

+def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {<br class="">

+  let Latency = 15;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FPrST0")>;<br class="">

+def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FST0r")>;<br class="">

+def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FrST0")>;<br class="">

+<br class="">

+def BWWriteResGroup148 : SchedWriteRes<[BWPort0,BWPort23]> {<br class="">

+  let Latency = 15;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup148], (instregex "PMULLDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup148], (instregex "VPMULLDrm")>;<br class="">

+<br class="">

+def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {<br class="">

+  let Latency = 15;<br class="">

+  let NumMicroOps = 10;<br class="">

+  let ResourceCycles = [1,1,1,4,1,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup149], (instregex "RCL(16|32|64)mCL")>;<br class="">

+def: InstRW<[BWWriteResGroup149], (instregex "RCL8mCL")>;<br class="">

+<br class="">

+def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23]> {<br class="">

+  let Latency = 16;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup150], (instregex "DIVPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup150], (instregex "DIVSSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup150], (instregex "VDIVPSrm")>;<br class="">

+def: InstRW<[BWWriteResGroup150], (instregex "VDIVSSrm")>;<br class="">

+<br class="">

+def BWWriteResGroup151 : SchedWriteRes<[BWPort0,BWPort23]> {<br class="">

+  let Latency = 16;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup151], (instregex "VPMULLDYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup152 : SchedWriteRes<[BWPort0,BWPort23]> {<br class="">

+  let Latency = 16;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [3,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup152], (instregex "PCMPISTRIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup152], (instregex "PCMPISTRM128rm")>;<br class="">

+def: InstRW<[BWWriteResGroup152], (instregex "VPCMPISTRIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup152], (instregex "VPCMPISTRM128rm")>;<br class="">

+<br class="">

+def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {<br class="">

+  let Latency = 16;<br class="">

+  let NumMicroOps = 14;<br class="">

+  let ResourceCycles = [1,1,1,4,2,5];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup153], (instregex "CMPXCHG8B")>;<br class="">

+<br class="">

+def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> {<br class="">

+  let Latency = 16;<br class="">

+  let NumMicroOps = 16;<br class="">

+  let ResourceCycles = [16];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup154], (instregex "VZEROALL")>;<br class="">

+<br class="">

+def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015]> {<br class="">

+  let Latency = 17;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup155], (instregex "VDIVPSYrr")>;<br class="">

+<br class="">

+def BWWriteResGroup156 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {<br class="">

+  let Latency = 17;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [2,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup156], (instregex "VRCPPSYm")>;<br class="">

+def: InstRW<[BWWriteResGroup156], (instregex "VRSQRTPSYm")>;<br class="">

+<br class="">

+def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23]> {<br class="">

+  let Latency = 18;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup157], (instregex "SQRTPSm")>;<br class="">

+def: InstRW<[BWWriteResGroup157], (instregex "SQRTSSm")>;<br class="">

+<br class="">

+def BWWriteResGroup158 : SchedWriteRes<[BWPort0,BWPort5,BWPort0156]> {<br class="">

+  let Latency = 18;<br class="">

+  let NumMicroOps = 8;<br class="">

+  let ResourceCycles = [4,3,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup158], (instregex "PCMPESTRIrr")>;<br class="">

+def: InstRW<[BWWriteResGroup158], (instregex "VPCMPESTRIrr")>;<br class="">

+<br class="">

+def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 18;<br class="">

+  let NumMicroOps = 8;<br class="">

+  let ResourceCycles = [1,1,1,5];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup159], (instregex "CPUID")>;<br class="">

+def: InstRW<[BWWriteResGroup159], (instregex "RDTSC")>;<br class="">

+<br class="">

+def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {<br class="">

+  let Latency = 18;<br class="">

+  let NumMicroOps = 11;<br class="">

+  let ResourceCycles = [2,1,1,3,1,3];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup160], (instregex "RCR(16|32|64)mCL")>;<br class="">

+def: InstRW<[BWWriteResGroup160], (instregex "RCR8mCL")>;<br class="">

+<br class="">

+def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23]> {<br class="">

+  let Latency = 19;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup161], (instregex "DIVPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup161], (instregex "DIVSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup161], (instregex "VDIVPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup161], (instregex "VDIVSDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup161], (instregex "VSQRTPSm")>;<br class="">

+def: InstRW<[BWWriteResGroup161], (instregex "VSQRTSSm")>;<br class="">

+<br class="">

+def BWWriteResGroup162 : SchedWriteRes<[BWPort5,BWPort23]> {<br class="">

+  let Latency = 19;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup162], (instregex "AESIMCrm")>;<br class="">

+def: InstRW<[BWWriteResGroup162], (instregex "VAESIMCrm")>;<br class="">

+<br class="">

+def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {<br class="">

+  let Latency = 19;<br class="">

+  let NumMicroOps = 5;<br class="">

+  let ResourceCycles = [2,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup163], (instregex "DPPSrmi")>;<br class="">

+def: InstRW<[BWWriteResGroup163], (instregex "VDPPSrmi")>;<br class="">

+<br class="">

+def BWWriteResGroup164 : SchedWriteRes<[BWPort0,BWPort5,BWPort015,BWPort0156]> {<br class="">

+  let Latency = 19;<br class="">

+  let NumMicroOps = 9;<br class="">

+  let ResourceCycles = [4,3,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup164], (instregex "PCMPESTRM128rr")>;<br class="">

+def: InstRW<[BWWriteResGroup164], (instregex "VPCMPESTRM128rr")>;<br class="">

+<br class="">

+def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {<br class="">

+  let Latency = 20;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup165], (instregex "DIV_FPrST0")>;<br class="">

+def: InstRW<[BWWriteResGroup165], (instregex "DIV_FST0r")>;<br class="">

+def: InstRW<[BWWriteResGroup165], (instregex "DIV_FrST0")>;<br class="">

+def: InstRW<[BWWriteResGroup165], (instregex "SQRTPDr")>;<br class="">

+def: InstRW<[BWWriteResGroup165], (instregex "SQRTSDr")>;<br class="">

+<br class="">

+def BWWriteResGroup166 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {<br class="">

+  let Latency = 20;<br class="">

+  let NumMicroOps = 5;<br class="">

+  let ResourceCycles = [2,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup166], (instregex "VDPPSYrmi")>;<br class="">

+<br class="">

+def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 20;<br class="">

+  let NumMicroOps = 8;<br class="">

+  let ResourceCycles = [1,1,1,1,1,1,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup167], (instregex "INSB")>;<br class="">

+def: InstRW<[BWWriteResGroup167], (instregex "INSL")>;<br class="">

+def: InstRW<[BWWriteResGroup167], (instregex "INSW")>;<br class="">

+<br class="">

+def BWWriteResGroup168 : SchedWriteRes<[BWPort0]> {<br class="">

+  let Latency = 21;<br class="">

+  let NumMicroOps = 1;<br class="">

+  let ResourceCycles = [1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup168], (instregex "VSQRTPDr")>;<br class="">

+def: InstRW<[BWWriteResGroup168], (instregex "VSQRTSDr")>;<br class="">

+<br class="">

+def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {<br class="">

+  let Latency = 21;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m")>;<br class="">

+def: InstRW<[BWWriteResGroup169], (instregex "DIV_F64m")>;<br class="">

+<br class="">

+def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015]> {<br class="">

+  let Latency = 21;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup170], (instregex "VSQRTPSYr")>;<br class="">

+<br class="">

+def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 21;<br class="">

+  let NumMicroOps = 19;<br class="">

+  let ResourceCycles = [2,1,4,1,1,4,6];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup171], (instregex "CMPXCHG16B")>;<br class="">

+<br class="">

+def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {<br class="">

+  let Latency = 22;<br class="">

+  let NumMicroOps = 18;<br class="">

+  let ResourceCycles = [1,1,16];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;<br class="">

+<br class="">

+def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015]> {<br class="">

+  let Latency = 23;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup173], (instregex "VDIVPDYrr")>;<br class="">

+<br class="">

+def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {<br class="">

+  let Latency = 23;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [2,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup175 : SchedWriteRes<[BWPort0,BWPort5,BWPort23,BWPort0156]> {<br class="">

+  let Latency = 23;<br class="">

+  let NumMicroOps = 9;<br class="">

+  let ResourceCycles = [4,3,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup175], (instregex "PCMPESTRIrm")>;<br class="">

+def: InstRW<[BWWriteResGroup175], (instregex "VPCMPESTRIrm")>;<br class="">

+<br class="">

+def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {<br class="">

+  let Latency = 23;<br class="">

+  let NumMicroOps = 19;<br class="">

+  let ResourceCycles = [3,1,15];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64?)")>;<br class="">

+<br class="">

+def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {<br class="">

+  let Latency = 24;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m")>;<br class="">

+def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI32m")>;<br class="">

+<br class="">

+def BWWriteResGroup178 : SchedWriteRes<[BWPort0,BWPort5,BWPort23,BWPort015,BWPort0156]> {<br class="">

+  let Latency = 24;<br class="">

+  let NumMicroOps = 10;<br class="">

+  let ResourceCycles = [4,3,1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup178], (instregex "PCMPESTRM128rm")>;<br class="">

+def: InstRW<[BWWriteResGroup178], (instregex "VPCMPESTRM128rm")>;<br class="">

+<br class="">

+def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23]> {<br class="">

+  let Latency = 25;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup179], (instregex "SQRTPDm")>;<br class="">

+def: InstRW<[BWWriteResGroup179], (instregex "SQRTSDm")>;<br class="">

+<br class="">

+def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {<br class="">

+  let Latency = 26;<br class="">

+  let NumMicroOps = 2;<br class="">

+  let ResourceCycles = [1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m")>;<br class="">

+def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F64m")>;<br class="">

+def: InstRW<[BWWriteResGroup180], (instregex "VSQRTPDm")>;<br class="">

+def: InstRW<[BWWriteResGroup180], (instregex "VSQRTSDm")>;<br class="">

+<br class="">

+def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {<br class="">

+  let Latency = 27;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [2,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup181], (instregex "VSQRTPSYm")>;<br class="">

+<br class="">

+def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {<br class="">

+  let Latency = 29;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [1,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m")>;<br class="">

+def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI32m")>;<br class="">

+<br class="">

+def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {<br class="">

+  let Latency = 29;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [2,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup183], (instregex "VDIVPDYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {<br class="">

+  let Latency = 22;<br class="">

+  let NumMicroOps = 7;<br class="">

+  let ResourceCycles = [1,3,2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup183_1], (instregex "VGATHERQPDrm")>;<br class="">

+<br class="">

+def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {<br class="">

+  let Latency = 23;<br class="">

+  let NumMicroOps = 9;<br class="">

+  let ResourceCycles = [1,3,4,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup183_2], (instregex "VGATHERQPDYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {<br class="">

+  let Latency = 24;<br class="">

+  let NumMicroOps = 9;<br class="">

+  let ResourceCycles = [1,5,2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup183_3], (instregex "VGATHERQPSYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {<br class="">

+  let Latency = 25;<br class="">

+  let NumMicroOps = 7;<br class="">

+  let ResourceCycles = [1,3,2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup183_4], (instregex "VGATHERDPDrm")>;<br class="">

+def: InstRW<[BWWriteResGroup183_4], (instregex "VGATHERDPSrm")>;<br class="">

+<br class="">

+def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {<br class="">

+  let Latency = 26;<br class="">

+  let NumMicroOps = 9;<br class="">

+  let ResourceCycles = [1,5,2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup183_5], (instregex "VGATHERDPDYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {<br class="">

+  let Latency = 26;<br class="">

+  let NumMicroOps = 14;<br class="">

+  let ResourceCycles = [1,4,8,1];  <br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup183_6], (instregex "VGATHERDPSYrm")>;<br class="">

+<br class="">

+def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {<br class="">

+  let Latency = 27;<br class="">

+  let NumMicroOps = 9;<br class="">

+  let ResourceCycles = [1,5,2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup183_7], (instregex "VGATHERQPSrm")>;<br class="">

+<br class="">

+def BWWriteResGroup184 : SchedWriteRes<[BWPort0,BWPort5,BWPort015]> {<br class="">

+  let Latency = 29;<br class="">

+  let NumMicroOps = 11;<br class="">

+  let ResourceCycles = [2,7,2];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup184], (instregex "AESKEYGENASSIST128rr")>;<br class="">

+def: InstRW<[BWWriteResGroup184], (instregex "VAESKEYGENASSIST128rr")>;<br class="">

+<br class="">

+def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {<br class="">

+  let Latency = 29;<br class="">

+  let NumMicroOps = 27;<br class="">

+  let ResourceCycles = [1,5,1,1,19];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup185], (instregex "XSAVE64")>;<br class="">

+<br class="">

+def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {<br class="">

+  let Latency = 30;<br class="">

+  let NumMicroOps = 28;<br class="">

+  let ResourceCycles = [1,6,1,1,19];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup186], (instregex "XSAVE(OPT?)")>;<br class="">

+<br class="">

+def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> {<br class="">

+  let Latency = 31;<br class="">

+  let NumMicroOps = 31;<br class="">

+  let ResourceCycles = [8,1,21,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;<br class="">

+<br class="">

+def BWWriteResGroup188 : SchedWriteRes<[BWPort0,BWPort5,BWPort23,BWPort015]> {<br class="">

+  let Latency = 33;<br class="">

+  let NumMicroOps = 11;<br class="">

+  let ResourceCycles = [2,7,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup188], (instregex "AESKEYGENASSIST128rm")>;<br class="">

+def: InstRW<[BWWriteResGroup188], (instregex "VAESKEYGENASSIST128rm")>;<br class="">

+<br class="">

+def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015]> {<br class="">

+  let Latency = 34;<br class="">

+  let NumMicroOps = 3;<br class="">

+  let ResourceCycles = [2,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup189], (instregex "VSQRTPDYr")>;<br class="">

+<br class="">

+def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {<br class="">

+  let Latency = 34;<br class="">

+  let NumMicroOps = 8;<br class="">

+  let ResourceCycles = [2,2,2,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup190], (instregex "DIV(16|32|64)m")>;<br class="">

+def: InstRW<[BWWriteResGroup190], (instregex "DIV8m")>;<br class="">

+<br class="">

+def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 34;<br class="">

+  let NumMicroOps = 23;<br class="">

+  let ResourceCycles = [1,5,3,4,10];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup191], (instregex "IN32ri")>;<br class="">

+def: InstRW<[BWWriteResGroup191], (instregex "IN32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup191], (instregex "IN8ri")>;<br class="">

+def: InstRW<[BWWriteResGroup191], (instregex "IN8rr")>;<br class="">

+<br class="">

+def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {<br class="">

+  let Latency = 35;<br class="">

+  let NumMicroOps = 8;<br class="">

+  let ResourceCycles = [2,2,2,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup193], (instregex "IDIV(16|32|64)m")>;<br class="">

+def: InstRW<[BWWriteResGroup193], (instregex "IDIV8m")>;<br class="">

+<br class="">

+def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 35;<br class="">

+  let NumMicroOps = 23;<br class="">

+  let ResourceCycles = [1,5,2,1,4,10];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup194], (instregex "OUT32ir")>;<br class="">

+def: InstRW<[BWWriteResGroup194], (instregex "OUT32rr")>;<br class="">

+def: InstRW<[BWWriteResGroup194], (instregex "OUT8ir")>;<br class="">

+def: InstRW<[BWWriteResGroup194], (instregex "OUT8rr")>;<br class="">

+<br class="">

+def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {<br class="">

+  let Latency = 40;<br class="">

+  let NumMicroOps = 4;<br class="">

+  let ResourceCycles = [2,1,1];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup195], (instregex "VSQRTPDYm")>;<br class="">

+<br class="">

+def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {<br class="">

+  let Latency = 42;<br class="">

+  let NumMicroOps = 22;<br class="">

+  let ResourceCycles = [2,20];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup196], (instregex "RDTSCP")>;<br class="">

+<br class="">

+def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {<br class="">

+  let Latency = 60;<br class="">

+  let NumMicroOps = 64;<br class="">

+  let ResourceCycles = [2,2,8,1,10,2,39];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;<br class="">

+def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;<br class="">

+<br class="">

+def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {<br class="">

+  let Latency = 63;<br class="">

+  let NumMicroOps = 88;<br class="">

+  let ResourceCycles = [4,4,31,1,2,1,45];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup198], (instregex "FXRSTOR64")>;<br class="">

+<br class="">

+def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {<br class="">

+  let Latency = 63;<br class="">

+  let NumMicroOps = 90;<br class="">

+  let ResourceCycles = [4,2,33,1,2,1,47];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup199], (instregex "FXRSTOR")>;<br class="">

+<br class="">

+def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {<br class="">

+  let Latency = 75;<br class="">

+  let NumMicroOps = 15;<br class="">

+  let ResourceCycles = [6,3,6];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup200], (instregex "FNINIT")>;<br class="">

+<br class="">

+def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {<br class="">

+  let Latency = 80;<br class="">

+  let NumMicroOps = 32;<br class="">

+  let ResourceCycles = [7,7,3,3,1,11];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>;<br class="">

+<br class="">

+def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {<br class="">

+  let Latency = 115;<br class="">

+  let NumMicroOps = 100;<br class="">

+  let ResourceCycles = [9,9,11,8,1,11,21,30];<br class="">

+}<br class="">

+def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;<br class="">

+def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;<br class="">

+<br class="">

+} // SchedModel<br class="">

+<br class="">

<br class="">

Propchange: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td<br class="">

------------------------------------------------------------------------------<br class="">

   svn:executable = *<br class="">

<br class="">

Modified: llvm/trunk/lib/Target/X86/X86Schedule.td<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/lib/Target/X86/X86Schedule.td (original)<br class="">

+++ llvm/trunk/lib/Target/X86/X86Schedule.td Tue Oct 24 13:19:47 2017<br class="">

@@ -663,10 +663,10 @@ def GenericPostRAModel : GenericX86Model<br class="">

include "X86ScheduleAtom.td"<br class="">

include "X86SchedSandyBridge.td"<br class="">

include "X86SchedHaswell.td"<br class="">

+include "X86SchedBroadwell.td"<br class="">

include "X86ScheduleSLM.td"<br class="">

include "X86ScheduleZnver1.td"<br class="">

include "X86ScheduleBtVer2.td"<br class="">

include "X86SchedSkylakeClient.td"<br class="">

include "X86SchedSkylakeServer.td"<br class="">

<br class="">

-<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/aes-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/aes-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/aes-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/aes-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/aes-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -38,8 +38,8 @@ define <2 x i64> @test_aesdec(<2 x i64><br class="">

; BROADWELL-LABEL: test_aesdec:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaesdec %xmm1, %xmm0, %xmm0 # sched: [7:1.00]<br class="">

-; BROADWELL-NEXT:    vaesdec (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaesdec (%rdi), %xmm0, %xmm0 # sched: [12:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_aesdec:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -93,8 +93,8 @@ define <2 x i64> @test_aesdeclast(<2 x i<br class="">

; BROADWELL-LABEL: test_aesdeclast:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [7:1.00]<br class="">

-; BROADWELL-NEXT:    vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [12:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_aesdeclast:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -148,8 +148,8 @@ define <2 x i64> @test_aesenc(<2 x i64><br class="">

; BROADWELL-LABEL: test_aesenc:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaesenc %xmm1, %xmm0, %xmm0 # sched: [7:1.00]<br class="">

-; BROADWELL-NEXT:    vaesenc (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaesenc (%rdi), %xmm0, %xmm0 # sched: [12:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_aesenc:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -203,8 +203,8 @@ define <2 x i64> @test_aesenclast(<2 x i<br class="">

; BROADWELL-LABEL: test_aesenclast:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaesenclast %xmm1, %xmm0, %xmm0 # sched: [7:1.00]<br class="">

-; BROADWELL-NEXT:    vaesenclast (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaesenclast (%rdi), %xmm0, %xmm0 # sched: [12:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_aesenclast:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -262,9 +262,9 @@ define <2 x i64> @test_aesimc(<2 x i64><br class="">

; BROADWELL-LABEL: test_aesimc:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaesimc %xmm0, %xmm0 # sched: [14:2.00]<br class="">

-; BROADWELL-NEXT:    vaesimc (%rdi), %xmm1 # sched: [14:2.00]<br class="">

+; BROADWELL-NEXT:    vaesimc (%rdi), %xmm1 # sched: [19:2.00]<br class="">

; BROADWELL-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_aesimc:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -326,9 +326,9 @@ define <2 x i64> @test_aeskeygenassist(<<br class="">

; BROADWELL-LABEL: test_aeskeygenassist:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaeskeygenassist $7, %xmm0, %xmm0 # sched: [29:7.00]<br class="">

-; BROADWELL-NEXT:    vaeskeygenassist $7, (%rdi), %xmm1 # sched: [28:7.00]<br class="">

+; BROADWELL-NEXT:    vaeskeygenassist $7, (%rdi), %xmm1 # sched: [33:7.00]<br class="">

; BROADWELL-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_aeskeygenassist:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/avx-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/avx-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/avx-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -31,8 +31,8 @@ define <4 x double> @test_addpd(<4 x dou<br class="">

; BROADWELL-LABEL: test_addpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vaddpd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaddpd (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_addpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -85,8 +85,8 @@ define <8 x float> @test_addps(<8 x floa<br class="">

; BROADWELL-LABEL: test_addps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vaddps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaddps (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_addps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -139,8 +139,8 @@ define <4 x double> @test_addsubpd(<4 x<br class="">

; BROADWELL-LABEL: test_addsubpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaddsubpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vaddsubpd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaddsubpd (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_addsubpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -194,8 +194,8 @@ define <8 x float> @test_addsubps(<8 x f<br class="">

; BROADWELL-LABEL: test_addsubps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaddsubps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vaddsubps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaddsubps (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_addsubps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -252,9 +252,9 @@ define <4 x double> @test_andnotpd(<4 x<br class="">

; BROADWELL-LABEL: test_andnotpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vandnpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vandnpd (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vandnpd (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_andnotpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -321,9 +321,9 @@ define <8 x float> @test_andnotps(<8 x f<br class="">

; BROADWELL-LABEL: test_andnotps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vandnps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vandnps (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vandnps (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_andnotps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -390,9 +390,9 @@ define <4 x double> @test_andpd(<4 x dou<br class="">

; BROADWELL-LABEL: test_andpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vandpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vandpd (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vandpd (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_andpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -457,9 +457,9 @@ define <8 x float> @test_andps(<8 x floa<br class="">

; BROADWELL-LABEL: test_andps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vandps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vandps (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vandps (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_andps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -525,8 +525,8 @@ define <4 x double> @test_blendpd(<4 x d<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] sched: [1:0.33]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],mem[1,2],ymm0[3] sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],mem[1,2],ymm0[3] sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blendpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -584,8 +584,8 @@ define <8 x float> @test_blendps(<8 x fl<br class="">

; BROADWELL-LABEL: test_blendps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3,4,5,6,7] sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1],mem[2],ymm0[3],mem[4,5,6],ymm0[7] sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1],mem[2],ymm0[3],mem[4,5,6],ymm0[7] sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blendps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -638,8 +638,8 @@ define <4 x double> @test_blendvpd(<4 x<br class="">

; BROADWELL-LABEL: test_blendvpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vblendvpd %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vblendvpd %ymm2, (%rdi), %ymm0, %ymm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vblendvpd %ymm2, (%rdi), %ymm0, %ymm0 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blendvpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -693,8 +693,8 @@ define <8 x float> @test_blendvps(<8 x f<br class="">

; BROADWELL-LABEL: test_blendvps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vblendvps %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vblendvps %ymm2, (%rdi), %ymm0, %ymm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vblendvps %ymm2, (%rdi), %ymm0, %ymm0 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blendvps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -744,8 +744,8 @@ define <8 x float> @test_broadcastf128(<<br class="">

;<br class="">

; BROADWELL-LABEL: test_broadcastf128:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_broadcastf128:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -789,8 +789,8 @@ define <4 x double> @test_broadcastsd_ym<br class="">

;<br class="">

; BROADWELL-LABEL: test_broadcastsd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vbroadcastsd (%rdi), %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vbroadcastsd (%rdi), %ymm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_broadcastsd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -835,8 +835,8 @@ define <4 x float> @test_broadcastss(flo<br class="">

;<br class="">

; BROADWELL-LABEL: test_broadcastss:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vbroadcastss (%rdi), %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vbroadcastss (%rdi), %xmm0 # sched: [5:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_broadcastss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -881,8 +881,8 @@ define <8 x float> @test_broadcastss_ymm<br class="">

;<br class="">

; BROADWELL-LABEL: test_broadcastss_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vbroadcastss (%rdi), %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vbroadcastss (%rdi), %ymm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_broadcastss_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -934,9 +934,9 @@ define <4 x double> @test_cmppd(<4 x dou<br class="">

; BROADWELL-LABEL: test_cmppd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcmpeqpd %ymm1, %ymm0, %ymm1 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vcmpeqpd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vcmpeqpd (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vorpd %ymm0, %ymm1, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cmppd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1002,9 +1002,9 @@ define <8 x float> @test_cmpps(<8 x floa<br class="">

; BROADWELL-LABEL: test_cmpps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcmpeqps %ymm1, %ymm0, %ymm1 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vcmpeqps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vcmpeqps (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vorps %ymm0, %ymm1, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cmpps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1070,9 +1070,9 @@ define <4 x double> @test_cvtdq2pd(<4 x<br class="">

; BROADWELL-LABEL: test_cvtdq2pd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtdq2pd %xmm0, %ymm0 # sched: [6:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtdq2pd (%rdi), %ymm1 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtdq2pd (%rdi), %ymm1 # sched: [11:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtdq2pd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1135,9 +1135,9 @@ define <8 x float> @test_cvtdq2ps(<8 x i<br class="">

; BROADWELL-LABEL: test_cvtdq2ps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtdq2ps %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtdq2ps (%rdi), %ymm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtdq2ps (%rdi), %ymm1 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtdq2ps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1198,9 +1198,9 @@ define <8 x i32> @test_cvtpd2dq(<4 x dou<br class="">

; BROADWELL-LABEL: test_cvtpd2dq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvttpd2dq %ymm0, %xmm0 # sched: [6:1.00]<br class="">

-; BROADWELL-NEXT:    vcvttpd2dqy (%rdi), %xmm1 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    vcvttpd2dqy (%rdi), %xmm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtpd2dq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1261,9 +1261,9 @@ define <8 x float> @test_cvtpd2ps(<4 x d<br class="">

; BROADWELL-LABEL: test_cvtpd2ps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtpd2ps %ymm0, %xmm0 # sched: [6:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtpd2psy (%rdi), %xmm1 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtpd2psy (%rdi), %xmm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtpd2ps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1324,9 +1324,9 @@ define <8 x i32> @test_cvtps2dq(<8 x flo<br class="">

; BROADWELL-LABEL: test_cvtps2dq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvttps2dq %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vcvttps2dq (%rdi), %ymm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vcvttps2dq (%rdi), %ymm1 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vorps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtps2dq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1383,9 +1383,9 @@ define <4 x double> @test_divpd(<4 x dou<br class="">

;<br class="">

; BROADWELL-LABEL: test_divpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vdivpd %ymm1, %ymm0, %ymm0 # sched: [35:2.00]<br class="">

-; BROADWELL-NEXT:    vdivpd (%rdi), %ymm0, %ymm0 # sched: [35:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vdivpd %ymm1, %ymm0, %ymm0 # sched: [23:2.00]<br class="">

+; BROADWELL-NEXT:    vdivpd (%rdi), %ymm0, %ymm0 # sched: [29:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_divpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1437,9 +1437,9 @@ define <8 x float> @test_divps(<8 x floa<br class="">

;<br class="">

; BROADWELL-LABEL: test_divps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vdivps %ymm1, %ymm0, %ymm0 # sched: [21:2.00]<br class="">

-; BROADWELL-NEXT:    vdivps (%rdi), %ymm0, %ymm0 # sched: [21:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vdivps %ymm1, %ymm0, %ymm0 # sched: [17:2.00]<br class="">

+; BROADWELL-NEXT:    vdivps (%rdi), %ymm0, %ymm0 # sched: [23:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_divps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1492,8 +1492,8 @@ define <8 x float> @test_dpps(<8 x float<br class="">

; BROADWELL-LABEL: test_dpps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [14:2.00]<br class="">

-; BROADWELL-NEXT:    vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [14:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [20:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_dpps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1552,7 +1552,7 @@ define <4 x float> @test_extractf128(<8<br class="">

; BROADWELL-NEXT:    vextractf128 $1, %ymm0, %xmm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vextractf128 $1, %ymm1, (%rdi) # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    vzeroupper # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_extractf128:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1608,8 +1608,8 @@ define <4 x double> @test_haddpd(<4 x do<br class="">

; BROADWELL-LABEL: test_haddpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vhaddpd %ymm1, %ymm0, %ymm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    vhaddpd (%rdi), %ymm0, %ymm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vhaddpd (%rdi), %ymm0, %ymm0 # sched: [11:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_haddpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1663,8 +1663,8 @@ define <8 x float> @test_haddps(<8 x flo<br class="">

; BROADWELL-LABEL: test_haddps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vhaddps %ymm1, %ymm0, %ymm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    vhaddps (%rdi), %ymm0, %ymm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vhaddps (%rdi), %ymm0, %ymm0 # sched: [11:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_haddps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1718,8 +1718,8 @@ define <4 x double> @test_hsubpd(<4 x do<br class="">

; BROADWELL-LABEL: test_hsubpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vhsubpd %ymm1, %ymm0, %ymm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    vhsubpd (%rdi), %ymm0, %ymm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vhsubpd (%rdi), %ymm0, %ymm0 # sched: [11:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_hsubpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1773,8 +1773,8 @@ define <8 x float> @test_hsubps(<8 x flo<br class="">

; BROADWELL-LABEL: test_hsubps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vhsubps %ymm1, %ymm0, %ymm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    vhsubps (%rdi), %ymm0, %ymm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vhsubps (%rdi), %ymm0, %ymm0 # sched: [11:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_hsubps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1831,9 +1831,9 @@ define <8 x float> @test_insertf128(<8 x<br class="">

; BROADWELL-LABEL: test_insertf128:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm1 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vinsertf128 $1, (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vinsertf128 $1, (%rdi), %ymm0, %ymm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_insertf128:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1889,8 +1889,8 @@ define <32 x i8> @test_lddqu(i8* %a0) {<br class="">

;<br class="">

; BROADWELL-LABEL: test_lddqu:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vlddqu (%rdi), %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vlddqu (%rdi), %ymm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lddqu:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1940,10 +1940,10 @@ define <2 x double> @test_maskmovpd(i8*<br class="">

;<br class="">

; BROADWELL-LABEL: test_maskmovpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmaskmovpd (%rdi), %xmm0, %xmm2 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vmaskmovpd %xmm1, %xmm0, (%rdi) # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vmaskmovpd (%rdi), %xmm0, %xmm2 # sched: [7:2.00]<br class="">

+; BROADWELL-NEXT:    vmaskmovpd %xmm1, %xmm0, (%rdi) # sched: [5:1.00]<br class="">

; BROADWELL-NEXT:    vmovapd %xmm2, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_maskmovpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2003,10 +2003,10 @@ define <4 x double> @test_maskmovpd_ymm(<br class="">

;<br class="">

; BROADWELL-LABEL: test_maskmovpd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmaskmovpd (%rdi), %ymm0, %ymm2 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vmaskmovpd %ymm1, %ymm0, (%rdi) # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vmaskmovpd (%rdi), %ymm0, %ymm2 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    vmaskmovpd %ymm1, %ymm0, (%rdi) # sched: [5:1.00]<br class="">

; BROADWELL-NEXT:    vmovapd %ymm2, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_maskmovpd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2066,10 +2066,10 @@ define <4 x float> @test_maskmovps(i8* %<br class="">

;<br class="">

; BROADWELL-LABEL: test_maskmovps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmaskmovps (%rdi), %xmm0, %xmm2 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vmaskmovps %xmm1, %xmm0, (%rdi) # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vmaskmovps (%rdi), %xmm0, %xmm2 # sched: [7:2.00]<br class="">

+; BROADWELL-NEXT:    vmaskmovps %xmm1, %xmm0, (%rdi) # sched: [5:1.00]<br class="">

; BROADWELL-NEXT:    vmovaps %xmm2, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_maskmovps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2129,10 +2129,10 @@ define <8 x float> @test_maskmovps_ymm(i<br class="">

;<br class="">

; BROADWELL-LABEL: test_maskmovps_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmaskmovps (%rdi), %ymm0, %ymm2 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vmaskmovps %ymm1, %ymm0, (%rdi) # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vmaskmovps (%rdi), %ymm0, %ymm2 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    vmaskmovps %ymm1, %ymm0, (%rdi) # sched: [5:1.00]<br class="">

; BROADWELL-NEXT:    vmovaps %ymm2, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_maskmovps_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2190,8 +2190,8 @@ define <4 x double> @test_maxpd(<4 x dou<br class="">

; BROADWELL-LABEL: test_maxpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmaxpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vmaxpd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmaxpd (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_maxpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2245,8 +2245,8 @@ define <8 x float> @test_maxps(<8 x floa<br class="">

; BROADWELL-LABEL: test_maxps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmaxps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vmaxps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmaxps (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_maxps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2300,8 +2300,8 @@ define <4 x double> @test_minpd(<4 x dou<br class="">

; BROADWELL-LABEL: test_minpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vminpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vminpd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vminpd (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_minpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2355,8 +2355,8 @@ define <8 x float> @test_minps(<8 x floa<br class="">

; BROADWELL-LABEL: test_minps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vminps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vminps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vminps (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_minps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2412,10 +2412,10 @@ define <4 x double> @test_movapd(<4 x do<br class="">

;<br class="">

; BROADWELL-LABEL: test_movapd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovapd (%rdi), %ymm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovapd (%rdi), %ymm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm0, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovapd %ymm0, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movapd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2474,10 +2474,10 @@ define <8 x float> @test_movaps(<8 x flo<br class="">

;<br class="">

; BROADWELL-LABEL: test_movaps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovaps (%rdi), %ymm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovaps (%rdi), %ymm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vaddps %ymm0, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovaps %ymm0, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movaps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2537,9 +2537,9 @@ define <4 x double> @test_movddup(<4 x d<br class="">

; BROADWELL-LABEL: test_movddup:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vmovddup {{.*#+}} ymm1 = mem[0,0,2,2] sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovddup {{.*#+}} ymm1 = mem[0,0,2,2] sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movddup:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2598,7 +2598,7 @@ define i32 @test_movmskpd(<4 x double> %<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovmskpd %ymm0, %eax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vzeroupper # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movmskpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2650,7 +2650,7 @@ define i32 @test_movmskps(<8 x float> %a<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovmskps %ymm0, %eax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vzeroupper # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movmskps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2702,7 +2702,7 @@ define <4 x double> @test_movntpd(<4 x d<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaddpd %ymm0, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovntpd %ymm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movntpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2755,7 +2755,7 @@ define <8 x float> @test_movntps(<8 x fl<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaddps %ymm0, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovntps %ymm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movntps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2810,9 +2810,9 @@ define <8 x float> @test_movshdup(<8 x f<br class="">

; BROADWELL-LABEL: test_movshdup:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vmovshdup {{.*#+}} ymm1 = mem[1,1,3,3,5,5,7,7] sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovshdup {{.*#+}} ymm1 = mem[1,1,3,3,5,5,7,7] sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movshdup:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2873,9 +2873,9 @@ define <8 x float> @test_movsldup(<8 x f<br class="">

; BROADWELL-LABEL: test_movsldup:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vmovsldup {{.*#+}} ymm1 = mem[0,0,2,2,4,4,6,6] sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovsldup {{.*#+}} ymm1 = mem[0,0,2,2,4,4,6,6] sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movsldup:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2937,10 +2937,10 @@ define <4 x double> @test_movupd(<4 x do<br class="">

;<br class="">

; BROADWELL-LABEL: test_movupd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovupd (%rdi), %ymm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovupd (%rdi), %ymm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm0, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovupd %ymm0, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movupd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3001,10 +3001,10 @@ define <8 x float> @test_movups(<8 x flo<br class="">

;<br class="">

; BROADWELL-LABEL: test_movups:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovups (%rdi), %ymm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovups (%rdi), %ymm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vaddps %ymm0, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovups %ymm0, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movups:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3060,9 +3060,9 @@ define <4 x double> @test_mulpd(<4 x dou<br class="">

;<br class="">

; BROADWELL-LABEL: test_mulpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmulpd %ymm1, %ymm0, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vmulpd (%rdi), %ymm0, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmulpd %ymm1, %ymm0, %ymm0 # sched: [3:0.50]<br class="">

+; BROADWELL-NEXT:    vmulpd (%rdi), %ymm0, %ymm0 # sched: [9:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_mulpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3114,9 +3114,9 @@ define <8 x float> @test_mulps(<8 x floa<br class="">

;<br class="">

; BROADWELL-LABEL: test_mulps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmulps %ymm1, %ymm0, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vmulps (%rdi), %ymm0, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmulps %ymm1, %ymm0, %ymm0 # sched: [3:0.50]<br class="">

+; BROADWELL-NEXT:    vmulps (%rdi), %ymm0, %ymm0 # sched: [9:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_mulps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3172,9 +3172,9 @@ define <4 x double> @orpd(<4 x double> %<br class="">

; BROADWELL-LABEL: orpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vorpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vorpd (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vorpd (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: orpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3239,9 +3239,9 @@ define <8 x float> @test_orps(<8 x float<br class="">

; BROADWELL-LABEL: test_orps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vorps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vorps (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vorps (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_orps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3306,9 +3306,9 @@ define <4 x double> @test_perm2f128(<4 x<br class="">

; BROADWELL-LABEL: test_perm2f128:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[0,1] sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_perm2f128:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3369,9 +3369,9 @@ define <2 x double> @test_permilpd(<2 x<br class="">

; BROADWELL-LABEL: test_permilpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpermilpd {{.*#+}} xmm1 = mem[1,0] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpermilpd {{.*#+}} xmm1 = mem[1,0] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_permilpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3432,9 +3432,9 @@ define <4 x double> @test_permilpd_ymm(<<br class="">

; BROADWELL-LABEL: test_permilpd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,3] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpermilpd {{.*#+}} ymm1 = mem[1,0,2,3] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpermilpd {{.*#+}} ymm1 = mem[1,0,2,3] sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_permilpd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3495,9 +3495,9 @@ define <4 x float> @test_permilps(<4 x f<br class="">

; BROADWELL-LABEL: test_permilps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpermilps {{.*#+}} xmm1 = mem[3,2,1,0] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpermilps {{.*#+}} xmm1 = mem[3,2,1,0] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_permilps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3558,9 +3558,9 @@ define <8 x float> @test_permilps_ymm(<8<br class="">

; BROADWELL-LABEL: test_permilps_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpermilps {{.*#+}} ymm1 = mem[3,2,1,0,7,6,5,4] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpermilps {{.*#+}} ymm1 = mem[3,2,1,0,7,6,5,4] sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_permilps_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3618,8 +3618,8 @@ define <2 x double> @test_permilvarpd(<2<br class="">

; BROADWELL-LABEL: test_permilvarpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpermilpd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpermilpd (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpermilpd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_permilvarpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3673,8 +3673,8 @@ define <4 x double> @test_permilvarpd_ym<br class="">

; BROADWELL-LABEL: test_permilvarpd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpermilpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpermilpd (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpermilpd (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_permilvarpd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3728,8 +3728,8 @@ define <4 x float> @test_permilvarps(<4<br class="">

; BROADWELL-LABEL: test_permilvarps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpermilps %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpermilps (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpermilps (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_permilvarps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3783,8 +3783,8 @@ define <8 x float> @test_permilvarps_ymm<br class="">

; BROADWELL-LABEL: test_permilvarps_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpermilps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpermilps (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpermilps (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_permilvarps_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3840,10 +3840,10 @@ define <8 x float> @test_rcpps(<8 x floa<br class="">

;<br class="">

; BROADWELL-LABEL: test_rcpps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vrcpps (%rdi), %ymm1 # sched: [11:2.00]<br class="">

+; BROADWELL-NEXT:    vrcpps (%rdi), %ymm1 # sched: [17:2.00]<br class="">

; BROADWELL-NEXT:    vrcpps %ymm0, %ymm0 # sched: [11:2.00]<br class="">

; BROADWELL-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_rcpps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3904,10 +3904,10 @@ define <4 x double> @test_roundpd(<4 x d<br class="">

;<br class="">

; BROADWELL-LABEL: test_roundpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vroundpd $7, %ymm0, %ymm0 # sched: [5:1.25]<br class="">

-; BROADWELL-NEXT:    vroundpd $7, (%rdi), %ymm1 # sched: [6:2.00]<br class="">

+; BROADWELL-NEXT:    vroundpd $7, %ymm0, %ymm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    vroundpd $7, (%rdi), %ymm1 # sched: [12:2.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_roundpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3968,10 +3968,10 @@ define <8 x float> @test_roundps(<8 x fl<br class="">

;<br class="">

; BROADWELL-LABEL: test_roundps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vroundps $7, %ymm0, %ymm0 # sched: [5:1.25]<br class="">

-; BROADWELL-NEXT:    vroundps $7, (%rdi), %ymm1 # sched: [6:2.00]<br class="">

+; BROADWELL-NEXT:    vroundps $7, %ymm0, %ymm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    vroundps $7, (%rdi), %ymm1 # sched: [12:2.00]<br class="">

; BROADWELL-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_roundps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4032,10 +4032,10 @@ define <8 x float> @test_rsqrtps(<8 x fl<br class="">

;<br class="">

; BROADWELL-LABEL: test_rsqrtps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vrsqrtps (%rdi), %ymm1 # sched: [11:2.00]<br class="">

+; BROADWELL-NEXT:    vrsqrtps (%rdi), %ymm1 # sched: [17:2.00]<br class="">

; BROADWELL-NEXT:    vrsqrtps %ymm0, %ymm0 # sched: [11:2.00]<br class="">

; BROADWELL-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_rsqrtps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4097,9 +4097,9 @@ define <4 x double> @test_shufpd(<4 x do<br class="">

; BROADWELL-LABEL: test_shufpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vshufpd {{.*#+}} ymm0 = ymm0[1],ymm1[0],ymm0[2],ymm1[3] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vshufpd {{.*#+}} ymm1 = ymm1[1],mem[0],ymm1[2],mem[3] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vshufpd {{.*#+}} ymm1 = ymm1[1],mem[0],ymm1[2],mem[3] sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_shufpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4157,8 +4157,8 @@ define <8 x float> @test_shufps(<8 x flo<br class="">

; BROADWELL-LABEL: test_shufps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[0,0],ymm1[0,0],ymm0[4,4],ymm1[4,4] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[0,3],mem[0,0],ymm0[4,7],mem[4,4] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[0,3],mem[0,0],ymm0[4,7],mem[4,4] sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_shufps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4213,10 +4213,10 @@ define <4 x double> @test_sqrtpd(<4 x do<br class="">

;<br class="">

; BROADWELL-LABEL: test_sqrtpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vsqrtpd (%rdi), %ymm1 # sched: [35:2.00]<br class="">

-; BROADWELL-NEXT:    vsqrtpd %ymm0, %ymm0 # sched: [35:2.00]<br class="">

+; BROADWELL-NEXT:    vsqrtpd (%rdi), %ymm1 # sched: [40:2.00]<br class="">

+; BROADWELL-NEXT:    vsqrtpd %ymm0, %ymm0 # sched: [34:2.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_sqrtpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4277,10 +4277,10 @@ define <8 x float> @test_sqrtps(<8 x flo<br class="">

;<br class="">

; BROADWELL-LABEL: test_sqrtps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vsqrtps (%rdi), %ymm1 # sched: [21:2.00]<br class="">

+; BROADWELL-NEXT:    vsqrtps (%rdi), %ymm1 # sched: [27:2.00]<br class="">

; BROADWELL-NEXT:    vsqrtps %ymm0, %ymm0 # sched: [21:2.00]<br class="">

; BROADWELL-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_sqrtps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4339,8 +4339,8 @@ define <4 x double> @test_subpd(<4 x dou<br class="">

; BROADWELL-LABEL: test_subpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vsubpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vsubpd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vsubpd (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_subpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4393,8 +4393,8 @@ define <8 x float> @test_subps(<8 x floa<br class="">

; BROADWELL-LABEL: test_subps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vsubps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vsubps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vsubps (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_subps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4458,9 +4458,9 @@ define i32 @test_testpd(<2 x double> %a0<br class="">

; BROADWELL-NEXT:    xorl %eax, %eax # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    vtestpd %xmm1, %xmm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    setb %al # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vtestpd (%rdi), %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    adcl $0, %eax # sched: [2:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vtestpd (%rdi), %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    adcl $0, %eax # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_testpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4541,10 +4541,10 @@ define i32 @test_testpd_ymm(<4 x double><br class="">

; BROADWELL-NEXT:    xorl %eax, %eax # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    vtestpd %ymm1, %ymm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    setb %al # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vtestpd (%rdi), %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    adcl $0, %eax # sched: [2:0.50]<br class="">

+; BROADWELL-NEXT:    vtestpd (%rdi), %ymm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    adcl $0, %eax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    vzeroupper # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_testpd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4625,9 +4625,9 @@ define i32 @test_testps(<4 x float> %a0,<br class="">

; BROADWELL-NEXT:    xorl %eax, %eax # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    vtestps %xmm1, %xmm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    setb %al # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vtestps (%rdi), %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    adcl $0, %eax # sched: [2:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vtestps (%rdi), %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    adcl $0, %eax # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_testps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4708,10 +4708,10 @@ define i32 @test_testps_ymm(<8 x float><br class="">

; BROADWELL-NEXT:    xorl %eax, %eax # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    vtestps %ymm1, %ymm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    setb %al # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vtestps (%rdi), %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    adcl $0, %eax # sched: [2:0.50]<br class="">

+; BROADWELL-NEXT:    vtestps (%rdi), %ymm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    adcl $0, %eax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    vzeroupper # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_testps_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4784,9 +4784,9 @@ define <4 x double> @test_unpckhpd(<4 x<br class="">

; BROADWELL-LABEL: test_unpckhpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vunpckhpd {{.*#+}} ymm1 = ymm1[1],mem[1],ymm1[3],mem[3] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vunpckhpd {{.*#+}} ymm1 = ymm1[1],mem[1],ymm1[3],mem[3] sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_unpckhpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4844,8 +4844,8 @@ define <8 x float> @test_unpckhps(<8 x f<br class="">

; BROADWELL-LABEL: test_unpckhps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vunpckhps {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vunpckhps {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7] sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_unpckhps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4901,9 +4901,9 @@ define <4 x double> @test_unpcklpd(<4 x<br class="">

; BROADWELL-LABEL: test_unpcklpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vunpcklpd {{.*#+}} ymm1 = ymm1[0],mem[0],ymm1[2],mem[2] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vunpcklpd {{.*#+}} ymm1 = ymm1[0],mem[0],ymm1[2],mem[2] sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_unpcklpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4961,8 +4961,8 @@ define <8 x float> @test_unpcklps(<8 x f<br class="">

; BROADWELL-LABEL: test_unpcklps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vunpcklps {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vunpcklps {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5] sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_unpcklps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5018,9 +5018,9 @@ define <4 x double> @test_xorpd(<4 x dou<br class="">

; BROADWELL-LABEL: test_xorpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vxorpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vxorpd (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vxorpd (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_xorpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5085,9 +5085,9 @@ define <8 x float> @test_xorps(<8 x floa<br class="">

; BROADWELL-LABEL: test_xorps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vxorps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vxorps (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vxorps (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_xorps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5146,7 +5146,7 @@ define void @test_zeroall() {<br class="">

; BROADWELL-LABEL: test_zeroall:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vzeroall # sched: [16:16.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_zeroall:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5191,7 +5191,7 @@ define void @test_zeroupper() {<br class="">

; BROADWELL-LABEL: test_zeroupper:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vzeroupper # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_zeroupper:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/avx2-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/avx2-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/avx2-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -21,9 +21,9 @@ define <8 x i32> @test_broadcasti128(<8<br class="">

;<br class="">

; BROADWELL-LABEL: test_broadcasti128:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_broadcasti128:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -65,7 +65,7 @@ define <4 x double> @test_broadcastsd_ym<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vbroadcastsd %xmm0, %ymm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm0, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_broadcastsd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -106,7 +106,7 @@ define <4 x float> @test_broadcastss(<4<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vbroadcastss %xmm0, %xmm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm0, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_broadcastss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -147,7 +147,7 @@ define <8 x float> @test_broadcastss_ymm<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vbroadcastss %xmm0, %ymm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %ymm0, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_broadcastss_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -197,7 +197,7 @@ define <4 x i32> @test_extracti128(<8 x<br class="">

; BROADWELL-NEXT:    vextracti128 $1, %ymm0, %xmm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vextracti128 $1, %ymm2, (%rdi) # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    vzeroupper # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_extracti128:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -246,8 +246,8 @@ define <2 x double> @test_gatherdpd(<2 x<br class="">

;<br class="">

; BROADWELL-LABEL: test_gatherdpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [25:3.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_gatherdpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -281,8 +281,8 @@ define <4 x double> @test_gatherdpd_ymm(<br class="">

;<br class="">

; BROADWELL-LABEL: test_gatherdpd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vgatherdpd %ymm2, (%rdi,%xmm1,8), %ymm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vgatherdpd %ymm2, (%rdi,%xmm1,8), %ymm0 # sched: [26:5.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_gatherdpd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -316,8 +316,8 @@ define <4 x float> @test_gatherdps(<4 x<br class="">

;<br class="">

; BROADWELL-LABEL: test_gatherdps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [25:3.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_gatherdps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -351,8 +351,8 @@ define <8 x float> @test_gatherdps_ymm(<<br class="">

;<br class="">

; BROADWELL-LABEL: test_gatherdps_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vgatherdps %ymm2, (%rdi,%ymm1,4), %ymm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vgatherdps %ymm2, (%rdi,%ymm1,4), %ymm0 # sched: [26:4.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_gatherdps_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -386,8 +386,8 @@ define <2 x double> @test_gatherqpd(<2 x<br class="">

;<br class="">

; BROADWELL-LABEL: test_gatherqpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:3.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_gatherqpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -421,8 +421,8 @@ define <4 x double> @test_gatherqpd_ymm(<br class="">

;<br class="">

; BROADWELL-LABEL: test_gatherqpd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vgatherqpd %ymm2, (%rdi,%ymm1,8), %ymm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vgatherqpd %ymm2, (%rdi,%ymm1,8), %ymm0 # sched: [23:3.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_gatherqpd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -456,8 +456,8 @@ define <4 x float> @test_gatherqps(<4 x<br class="">

;<br class="">

; BROADWELL-LABEL: test_gatherqps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [27:5.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_gatherqps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -493,9 +493,9 @@ define <4 x float> @test_gatherqps_ymm(<<br class="">

;<br class="">

; BROADWELL-LABEL: test_gatherqps_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vgatherqps %xmm2, (%rdi,%ymm1,4), %xmm0 # sched: [1:?]<br class="">

+; BROADWELL-NEXT:    vgatherqps %xmm2, (%rdi,%ymm1,4), %xmm0 # sched: [24:5.00]<br class="">

; BROADWELL-NEXT:    vzeroupper # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_gatherqps_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -537,9 +537,9 @@ define <8 x i32> @test_inserti128(<8 x i<br class="">

; BROADWELL-LABEL: test_inserti128:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm1 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vinserti128 $1, (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vinserti128 $1, (%rdi), %ymm0, %ymm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_inserti128:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -583,8 +583,8 @@ define <4 x i64> @test_movntdqa(i8* %a0)<br class="">

;<br class="">

; BROADWELL-LABEL: test_movntdqa:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovntdqa (%rdi), %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmovntdqa (%rdi), %ymm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movntdqa:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -621,8 +621,8 @@ define <16 x i16> @test_mpsadbw(<32 x i8<br class="">

; BROADWELL-LABEL: test_mpsadbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmpsadbw $7, %ymm1, %ymm0, %ymm0 # sched: [7:2.00]<br class="">

-; BROADWELL-NEXT:    vmpsadbw $7, (%rdi), %ymm0, %ymm0 # sched: [7:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmpsadbw $7, (%rdi), %ymm0, %ymm0 # sched: [13:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_mpsadbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -667,9 +667,9 @@ define <32 x i8> @test_pabsb(<32 x i8> %<br class="">

; BROADWELL-LABEL: test_pabsb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpabsb %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpabsb (%rdi), %ymm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpabsb (%rdi), %ymm1 # sched: [7:0.50]<br class="">

; BROADWELL-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pabsb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -717,9 +717,9 @@ define <8 x i32> @test_pabsd(<8 x i32> %<br class="">

; BROADWELL-LABEL: test_pabsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpabsd %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpabsd (%rdi), %ymm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpabsd (%rdi), %ymm1 # sched: [7:0.50]<br class="">

; BROADWELL-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pabsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -767,9 +767,9 @@ define <16 x i16> @test_pabsw(<16 x i16><br class="">

; BROADWELL-LABEL: test_pabsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpabsw %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpabsw (%rdi), %ymm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpabsw (%rdi), %ymm1 # sched: [7:0.50]<br class="">

; BROADWELL-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pabsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -815,8 +815,8 @@ define <16 x i16> @test_packssdw(<8 x i3<br class="">

; BROADWELL-LABEL: test_packssdw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpackssdw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpackssdw (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpackssdw (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_packssdw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -859,8 +859,8 @@ define <32 x i8> @test_packsswb(<16 x i1<br class="">

; BROADWELL-LABEL: test_packsswb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpacksswb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpacksswb (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpacksswb (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_packsswb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -903,8 +903,8 @@ define <16 x i16> @test_packusdw(<8 x i3<br class="">

; BROADWELL-LABEL: test_packusdw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpackusdw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpackusdw (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpackusdw (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_packusdw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -947,8 +947,8 @@ define <32 x i8> @test_packuswb(<16 x i1<br class="">

; BROADWELL-LABEL: test_packuswb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpackuswb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpackuswb (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpackuswb (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_packuswb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -991,8 +991,8 @@ define <32 x i8> @test_paddb(<32 x i8> %<br class="">

; BROADWELL-LABEL: test_paddb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddb (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1033,8 +1033,8 @@ define <8 x i32> @test_paddd(<8 x i32> %<br class="">

; BROADWELL-LABEL: test_paddd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddd (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1075,8 +1075,8 @@ define <4 x i64> @test_paddq(<4 x i64> %<br class="">

; BROADWELL-LABEL: test_paddq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddq (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1117,8 +1117,8 @@ define <32 x i8> @test_paddsb(<32 x i8><br class="">

; BROADWELL-LABEL: test_paddsb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddsb (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddsb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1160,8 +1160,8 @@ define <16 x i16> @test_paddsw(<16 x i16<br class="">

; BROADWELL-LABEL: test_paddsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddsw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1203,8 +1203,8 @@ define <32 x i8> @test_paddusb(<32 x i8><br class="">

; BROADWELL-LABEL: test_paddusb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddusb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddusb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddusb (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddusb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1246,8 +1246,8 @@ define <16 x i16> @test_paddusw(<16 x i1<br class="">

; BROADWELL-LABEL: test_paddusw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddusw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddusw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddusw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddusw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1289,8 +1289,8 @@ define <16 x i16> @test_paddw(<16 x i16><br class="">

; BROADWELL-LABEL: test_paddw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1331,8 +1331,8 @@ define <32 x i8> @test_palignr(<32 x i8><br class="">

; BROADWELL-LABEL: test_palignr:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpalignr {{.*#+}} ymm0 = ymm1[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm0[0],ymm1[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm0[16] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpalignr {{.*#+}} ymm0 = mem[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm0[0],mem[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm0[16] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpalignr {{.*#+}} ymm0 = mem[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm0[0],mem[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm0[16] sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_palignr:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1375,9 +1375,9 @@ define <4 x i64> @test_pand(<4 x i64> %a<br class="">

; BROADWELL-LABEL: test_pand:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpand %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    vpand (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpand (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pand:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1424,9 +1424,9 @@ define <4 x i64> @test_pandn(<4 x i64> %<br class="">

; BROADWELL-LABEL: test_pandn:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpandn %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    vpandn (%rdi), %ymm0, %ymm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpandn (%rdi), %ymm0, %ymm1 # sched: [7:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pandn:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1473,8 +1473,8 @@ define <32 x i8> @test_pavgb(<32 x i8> %<br class="">

; BROADWELL-LABEL: test_pavgb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpavgb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpavgb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpavgb (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pavgb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1525,8 +1525,8 @@ define <16 x i16> @test_pavgw(<16 x i16><br class="">

; BROADWELL-LABEL: test_pavgw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpavgw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpavgw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpavgw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pavgw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1579,9 +1579,9 @@ define <4 x i32> @test_pblendd(<4 x i32><br class="">

; BROADWELL-LABEL: test_pblendd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[3] sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    vpblendd {{.*#+}} xmm1 = mem[0],xmm1[1],mem[2],xmm1[3] sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpblendd {{.*#+}} xmm1 = mem[0],xmm1[1],mem[2],xmm1[3] sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pblendd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1628,9 +1628,9 @@ define <8 x i32> @test_pblendd_ymm(<8 x<br class="">

; BROADWELL-LABEL: test_pblendd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpblendd {{.*#+}} ymm1 = ymm1[0,1,2],ymm0[3,4,5,6],ymm1[7] sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    vpblendd {{.*#+}} ymm1 = ymm1[0],mem[1,2],ymm1[3,4,5,6,7] sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpblendd {{.*#+}} ymm1 = ymm1[0],mem[1,2],ymm1[3,4,5,6,7] sched: [7:0.50]<br class="">

; BROADWELL-NEXT:    vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pblendd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1675,8 +1675,8 @@ define <32 x i8> @test_pblendvb(<32 x i8<br class="">

; BROADWELL-LABEL: test_pblendvb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vpblendvb %ymm3, (%rdi), %ymm0, %ymm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpblendvb %ymm3, (%rdi), %ymm0, %ymm0 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pblendvb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1718,8 +1718,8 @@ define <16 x i16> @test_pblendw(<16 x i1<br class="">

; BROADWELL-LABEL: test_pblendw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4],ymm0[5,6,7,8,9],ymm1[10,11,12],ymm0[13,14,15] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpblendw {{.*#+}} ymm0 = mem[0],ymm0[1],mem[2],ymm0[3],mem[4],ymm0[5],mem[6],ymm0[7],mem[8],ymm0[9],mem[10],ymm0[11],mem[12],ymm0[13],mem[14],ymm0[15] sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpblendw {{.*#+}} ymm0 = mem[0],ymm0[1],mem[2],ymm0[3],mem[4],ymm0[5],mem[6],ymm0[7],mem[8],ymm0[9],mem[10],ymm0[11],mem[12],ymm0[13],mem[14],ymm0[15] sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pblendw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1762,9 +1762,9 @@ define <16 x i8> @test_pbroadcastb(<16 x<br class="">

; BROADWELL-LABEL: test_pbroadcastb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpbroadcastb %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpbroadcastb (%rdi), %xmm1 # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vpbroadcastb (%rdi), %xmm1 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pbroadcastb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1811,9 +1811,9 @@ define <32 x i8> @test_pbroadcastb_ymm(<<br class="">

; BROADWELL-LABEL: test_pbroadcastb_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpbroadcastb %xmm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpbroadcastb (%rdi), %ymm1 # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vpbroadcastb (%rdi), %ymm1 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vpaddb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pbroadcastb_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1860,9 +1860,9 @@ define <4 x i32> @test_pbroadcastd(<4 x<br class="">

; BROADWELL-LABEL: test_pbroadcastd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpbroadcastd %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpbroadcastd (%rdi), %xmm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpbroadcastd (%rdi), %xmm1 # sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pbroadcastd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1908,9 +1908,9 @@ define <8 x i32> @test_pbroadcastd_ymm(<<br class="">

; BROADWELL-LABEL: test_pbroadcastd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpbroadcastd %xmm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpbroadcastd (%rdi), %ymm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpbroadcastd (%rdi), %ymm1 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pbroadcastd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1956,9 +1956,9 @@ define <2 x i64> @test_pbroadcastq(<2 x<br class="">

; BROADWELL-LABEL: test_pbroadcastq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpbroadcastq %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpbroadcastq (%rdi), %xmm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpbroadcastq (%rdi), %xmm1 # sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pbroadcastq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2004,9 +2004,9 @@ define <4 x i64> @test_pbroadcastq_ymm(<<br class="">

; BROADWELL-LABEL: test_pbroadcastq_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpbroadcastq %xmm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpbroadcastq (%rdi), %ymm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpbroadcastq (%rdi), %ymm1 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pbroadcastq_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2052,9 +2052,9 @@ define <8 x i16> @test_pbroadcastw(<8 x<br class="">

; BROADWELL-LABEL: test_pbroadcastw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpbroadcastw %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpbroadcastw (%rdi), %xmm1 # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vpbroadcastw (%rdi), %xmm1 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pbroadcastw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2101,9 +2101,9 @@ define <16 x i16> @test_pbroadcastw_ymm(<br class="">

; BROADWELL-LABEL: test_pbroadcastw_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpbroadcastw %xmm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpbroadcastw (%rdi), %ymm1 # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vpbroadcastw (%rdi), %ymm1 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pbroadcastw_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2148,8 +2148,8 @@ define <32 x i8> @test_pcmpeqb(<32 x i8><br class="">

; BROADWELL-LABEL: test_pcmpeqb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpeqb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpeqb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpcmpeqb (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpeqb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2194,8 +2194,8 @@ define <8 x i32> @test_pcmpeqd(<8 x i32><br class="">

; BROADWELL-LABEL: test_pcmpeqd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpeqd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpeqd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpcmpeqd (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpeqd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2240,8 +2240,8 @@ define <4 x i64> @test_pcmpeqq(<4 x i64><br class="">

; BROADWELL-LABEL: test_pcmpeqq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpeqq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpeqq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpcmpeqq (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpeqq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2286,8 +2286,8 @@ define <16 x i16> @test_pcmpeqw(<16 x i1<br class="">

; BROADWELL-LABEL: test_pcmpeqw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpeqw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpeqw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpcmpeqw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpeqw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2332,8 +2332,8 @@ define <32 x i8> @test_pcmpgtb(<32 x i8><br class="">

; BROADWELL-LABEL: test_pcmpgtb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpgtb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpgtb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpcmpgtb (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpgtb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2378,8 +2378,8 @@ define <8 x i32> @test_pcmpgtd(<8 x i32><br class="">

; BROADWELL-LABEL: test_pcmpgtd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpgtd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpgtd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpcmpgtd (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpgtd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2424,8 +2424,8 @@ define <4 x i64> @test_pcmpgtq(<4 x i64><br class="">

; BROADWELL-LABEL: test_pcmpgtq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpgtq %ymm1, %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpcmpgtq (%rdi), %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpcmpgtq (%rdi), %ymm0, %ymm0 # sched: [11:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpgtq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2470,8 +2470,8 @@ define <16 x i16> @test_pcmpgtw(<16 x i1<br class="">

; BROADWELL-LABEL: test_pcmpgtw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpgtw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpgtw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpcmpgtw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpgtw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2518,9 +2518,9 @@ define <4 x i64> @test_perm2i128(<4 x i6<br class="">

; BROADWELL-LABEL: test_perm2i128:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[0,1] sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_perm2i128:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2567,9 +2567,9 @@ define <8 x i32> @test_permd(<8 x i32> %<br class="">

; BROADWELL-LABEL: test_permd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpermd %ymm1, %ymm0, %ymm1 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpermd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpermd (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_permd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2617,9 +2617,9 @@ define <4 x double> @test_permpd(<4 x do<br class="">

; BROADWELL-LABEL: test_permpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[3,2,2,3] sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpermpd {{.*#+}} ymm1 = mem[0,2,2,3] sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpermpd {{.*#+}} ymm1 = mem[0,2,2,3] sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_permpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2666,9 +2666,9 @@ define <8 x float> @test_permps(<8 x i32<br class="">

; BROADWELL-LABEL: test_permps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpermps %ymm1, %ymm0, %ymm1 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpermps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpermps (%rdi), %ymm0, %ymm0 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_permps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2716,9 +2716,9 @@ define <4 x i64> @test_permq(<4 x i64> %<br class="">

; BROADWELL-LABEL: test_permq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[3,2,2,3] sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpermq {{.*#+}} ymm1 = mem[0,2,2,3] sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpermq {{.*#+}} ymm1 = mem[0,2,2,3] sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_permq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2760,8 +2760,8 @@ define <4 x i32> @test_pgatherdd(<4 x i3<br class="">

;<br class="">

; BROADWELL-LABEL: test_pgatherdd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pgatherdd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2795,8 +2795,8 @@ define <8 x i32> @test_pgatherdd_ymm(<8<br class="">

;<br class="">

; BROADWELL-LABEL: test_pgatherdd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pgatherdd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2830,8 +2830,8 @@ define <2 x i64> @test_pgatherdq(<2 x i6<br class="">

;<br class="">

; BROADWELL-LABEL: test_pgatherdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pgatherdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2865,8 +2865,8 @@ define <4 x i64> @test_pgatherdq_ymm(<4<br class="">

;<br class="">

; BROADWELL-LABEL: test_pgatherdq_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pgatherdq_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2900,8 +2900,8 @@ define <4 x i32> @test_pgatherqd(<4 x i3<br class="">

;<br class="">

; BROADWELL-LABEL: test_pgatherqd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pgatherqd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2937,9 +2937,9 @@ define <4 x i32> @test_pgatherqd_ymm(<4<br class="">

;<br class="">

; BROADWELL-LABEL: test_pgatherqd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0 # sched: [1:?]<br class="">

+; BROADWELL-NEXT:    vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0<br class="">

; BROADWELL-NEXT:    vzeroupper # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pgatherqd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2976,8 +2976,8 @@ define <2 x i64> @test_pgatherqq(<2 x i6<br class="">

;<br class="">

; BROADWELL-LABEL: test_pgatherqq:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pgatherqq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3011,8 +3011,8 @@ define <4 x i64> @test_pgatherqq_ymm(<4<br class="">

;<br class="">

; BROADWELL-LABEL: test_pgatherqq_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [1:?]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pgatherqq_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3049,8 +3049,8 @@ define <8 x i32> @test_phaddd(<8 x i32><br class="">

; BROADWELL-LABEL: test_phaddd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vphaddd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vphaddd (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vphaddd (%rdi), %ymm0, %ymm0 # sched: [9:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phaddd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3092,8 +3092,8 @@ define <16 x i16> @test_phaddsw(<16 x i1<br class="">

; BROADWELL-LABEL: test_phaddsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vphaddsw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vphaddsw (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vphaddsw (%rdi), %ymm0, %ymm0 # sched: [9:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phaddsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3135,8 +3135,8 @@ define <16 x i16> @test_phaddw(<16 x i16<br class="">

; BROADWELL-LABEL: test_phaddw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vphaddw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vphaddw (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vphaddw (%rdi), %ymm0, %ymm0 # sched: [9:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phaddw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3178,8 +3178,8 @@ define <8 x i32> @test_phsubd(<8 x i32><br class="">

; BROADWELL-LABEL: test_phsubd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vphsubd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vphsubd (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vphsubd (%rdi), %ymm0, %ymm0 # sched: [9:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phsubd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3221,8 +3221,8 @@ define <16 x i16> @test_phsubsw(<16 x i1<br class="">

; BROADWELL-LABEL: test_phsubsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vphsubsw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vphsubsw (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vphsubsw (%rdi), %ymm0, %ymm0 # sched: [9:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phsubsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3264,8 +3264,8 @@ define <16 x i16> @test_phsubw(<16 x i16<br class="">

; BROADWELL-LABEL: test_phsubw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vphsubw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vphsubw (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vphsubw (%rdi), %ymm0, %ymm0 # sched: [9:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phsubw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3307,8 +3307,8 @@ define <16 x i16> @test_pmaddubsw(<32 x<br class="">

; BROADWELL-LABEL: test_pmaddubsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaddubsw %ymm1, %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmaddubsw (%rdi), %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaddubsw (%rdi), %ymm0, %ymm0 # sched: [11:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaddubsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3351,8 +3351,8 @@ define <8 x i32> @test_pmaddwd(<16 x i16<br class="">

; BROADWELL-LABEL: test_pmaddwd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaddwd %ymm1, %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmaddwd (%rdi), %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaddwd (%rdi), %ymm0, %ymm0 # sched: [11:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaddwd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3396,10 +3396,10 @@ define <4 x i32> @test_pmaskmovd(i8* %a0<br class="">

;<br class="">

; BROADWELL-LABEL: test_pmaskmovd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [7:2.00]<br class="">

+; BROADWELL-NEXT:    vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [5:1.00]<br class="">

; BROADWELL-NEXT:    vmovdqa %xmm2, %xmm0 # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaskmovd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3445,10 +3445,10 @@ define <8 x i32> @test_pmaskmovd_ymm(i8*<br class="">

;<br class="">

; BROADWELL-LABEL: test_pmaskmovd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [5:1.00]<br class="">

; BROADWELL-NEXT:    vmovdqa %ymm2, %ymm0 # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaskmovd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3494,10 +3494,10 @@ define <2 x i64> @test_pmaskmovq(i8* %a0<br class="">

;<br class="">

; BROADWELL-LABEL: test_pmaskmovq:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [7:2.00]<br class="">

+; BROADWELL-NEXT:    vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [5:1.00]<br class="">

; BROADWELL-NEXT:    vmovdqa %xmm2, %xmm0 # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaskmovq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3543,10 +3543,10 @@ define <4 x i64> @test_pmaskmovq_ymm(i8*<br class="">

;<br class="">

; BROADWELL-LABEL: test_pmaskmovq_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [5:1.00]<br class="">

; BROADWELL-NEXT:    vmovdqa %ymm2, %ymm0 # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaskmovq_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3591,8 +3591,8 @@ define <32 x i8> @test_pmaxsb(<32 x i8><br class="">

; BROADWELL-LABEL: test_pmaxsb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpmaxsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaxsb (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxsb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3634,8 +3634,8 @@ define <8 x i32> @test_pmaxsd(<8 x i32><br class="">

; BROADWELL-LABEL: test_pmaxsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpmaxsd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaxsd (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3677,8 +3677,8 @@ define <16 x i16> @test_pmaxsw(<16 x i16<br class="">

; BROADWELL-LABEL: test_pmaxsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpmaxsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaxsw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3720,8 +3720,8 @@ define <32 x i8> @test_pmaxub(<32 x i8><br class="">

; BROADWELL-LABEL: test_pmaxub:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaxub %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpmaxub (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaxub (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxub:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3763,8 +3763,8 @@ define <8 x i32> @test_pmaxud(<8 x i32><br class="">

; BROADWELL-LABEL: test_pmaxud:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaxud %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpmaxud (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaxud (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxud:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3806,8 +3806,8 @@ define <16 x i16> @test_pmaxuw(<16 x i16<br class="">

; BROADWELL-LABEL: test_pmaxuw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaxuw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpmaxuw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaxuw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxuw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3849,8 +3849,8 @@ define <32 x i8> @test_pminsb(<32 x i8><br class="">

; BROADWELL-LABEL: test_pminsb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpminsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpminsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpminsb (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminsb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3892,8 +3892,8 @@ define <8 x i32> @test_pminsd(<8 x i32><br class="">

; BROADWELL-LABEL: test_pminsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpminsd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpminsd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpminsd (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3935,8 +3935,8 @@ define <16 x i16> @test_pminsw(<16 x i16<br class="">

; BROADWELL-LABEL: test_pminsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpminsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpminsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpminsw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3978,8 +3978,8 @@ define <32 x i8> @test_pminub(<32 x i8><br class="">

; BROADWELL-LABEL: test_pminub:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpminub %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpminub (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpminub (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminub:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4021,8 +4021,8 @@ define <8 x i32> @test_pminud(<8 x i32><br class="">

; BROADWELL-LABEL: test_pminud:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpminud %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpminud (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpminud (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminud:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4064,8 +4064,8 @@ define <16 x i16> @test_pminuw(<16 x i16<br class="">

; BROADWELL-LABEL: test_pminuw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpminuw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpminuw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpminuw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminuw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4108,7 +4108,7 @@ define i32 @test_pmovmskb(<32 x i8> %a0)<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovmskb %ymm0, %eax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vzeroupper # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovmskb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4150,9 +4150,9 @@ define <8 x i32> @test_pmovsxbd(<16 x i8<br class="">

; BROADWELL-LABEL: test_pmovsxbd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovsxbd %xmm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovsxbd (%rdi), %ymm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovsxbd (%rdi), %ymm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovsxbd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4201,9 +4201,9 @@ define <4 x i64> @test_pmovsxbq(<16 x i8<br class="">

; BROADWELL-LABEL: test_pmovsxbq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovsxbq %xmm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovsxbq (%rdi), %ymm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovsxbq (%rdi), %ymm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovsxbq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4252,9 +4252,9 @@ define <16 x i16> @test_pmovsxbw(<16 x i<br class="">

; BROADWELL-LABEL: test_pmovsxbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovsxbw %xmm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovsxbw (%rdi), %ymm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovsxbw (%rdi), %ymm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovsxbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4301,9 +4301,9 @@ define <4 x i64> @test_pmovsxdq(<4 x i32<br class="">

; BROADWELL-LABEL: test_pmovsxdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovsxdq %xmm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovsxdq (%rdi), %ymm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovsxdq (%rdi), %ymm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovsxdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4350,9 +4350,9 @@ define <8 x i32> @test_pmovsxwd(<8 x i16<br class="">

; BROADWELL-LABEL: test_pmovsxwd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovsxwd %xmm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovsxwd (%rdi), %ymm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovsxwd (%rdi), %ymm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovsxwd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4399,9 +4399,9 @@ define <4 x i64> @test_pmovsxwq(<8 x i16<br class="">

; BROADWELL-LABEL: test_pmovsxwq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovsxwq %xmm0, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovsxwq (%rdi), %ymm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovsxwq (%rdi), %ymm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovsxwq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4450,9 +4450,9 @@ define <8 x i32> @test_pmovzxbd(<16 x i8<br class="">

; BROADWELL-LABEL: test_pmovzxbd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovzxbd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4501,9 +4501,9 @@ define <4 x i64> @test_pmovzxbq(<16 x i8<br class="">

; BROADWELL-LABEL: test_pmovzxbq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovzxbq {{.*#+}} ymm1 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero,mem[2],zero,zero,zero,zero,zero,zero,zero,mem[3],zero,zero,zero,zero,zero,zero,zero sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovzxbq {{.*#+}} ymm1 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero,mem[2],zero,zero,zero,zero,zero,zero,zero,mem[3],zero,zero,zero,zero,zero,zero,zero sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovzxbq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4552,9 +4552,9 @@ define <16 x i16> @test_pmovzxbw(<16 x i<br class="">

; BROADWELL-LABEL: test_pmovzxbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero

 sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovzxbw {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovzxbw {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovzxbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4601,9 +4601,9 @@ define <4 x i64> @test_pmovzxdq(<4 x i32<br class="">

; BROADWELL-LABEL: test_pmovzxdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovzxdq {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovzxdq {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovzxdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4650,9 +4650,9 @@ define <8 x i32> @test_pmovzxwd(<8 x i16<br class="">

; BROADWELL-LABEL: test_pmovzxwd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovzxwd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4699,9 +4699,9 @@ define <4 x i64> @test_pmovzxwq(<8 x i16<br class="">

; BROADWELL-LABEL: test_pmovzxwq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovzxwq {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovzxwq {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovzxwq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4748,8 +4748,8 @@ define <4 x i64> @test_pmuldq(<8 x i32><br class="">

; BROADWELL-LABEL: test_pmuldq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmuldq %ymm1, %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmuldq (%rdi), %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmuldq (%rdi), %ymm0, %ymm0 # sched: [11:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmuldq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4792,8 +4792,8 @@ define <16 x i16> @test_pmulhrsw(<16 x i<br class="">

; BROADWELL-LABEL: test_pmulhrsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmulhrsw %ymm1, %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmulhrsw (%rdi), %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmulhrsw (%rdi), %ymm0, %ymm0 # sched: [11:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmulhrsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4835,8 +4835,8 @@ define <16 x i16> @test_pmulhuw(<16 x i1<br class="">

; BROADWELL-LABEL: test_pmulhuw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmulhuw %ymm1, %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmulhuw (%rdi), %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmulhuw (%rdi), %ymm0, %ymm0 # sched: [11:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmulhuw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4878,8 +4878,8 @@ define <16 x i16> @test_pmulhw(<16 x i16<br class="">

; BROADWELL-LABEL: test_pmulhw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmulhw %ymm1, %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmulhw (%rdi), %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmulhw (%rdi), %ymm0, %ymm0 # sched: [11:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmulhw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4921,8 +4921,8 @@ define <8 x i32> @test_pmulld(<8 x i32><br class="">

; BROADWELL-LABEL: test_pmulld:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmulld %ymm1, %ymm0, %ymm0 # sched: [10:2.00]<br class="">

-; BROADWELL-NEXT:    vpmulld (%rdi), %ymm0, %ymm0 # sched: [10:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmulld (%rdi), %ymm0, %ymm0 # sched: [16:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmulld:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4963,8 +4963,8 @@ define <16 x i16> @test_pmullw(<16 x i16<br class="">

; BROADWELL-LABEL: test_pmullw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmullw %ymm1, %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmullw (%rdi), %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmullw (%rdi), %ymm0, %ymm0 # sched: [11:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmullw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5005,8 +5005,8 @@ define <4 x i64> @test_pmuludq(<8 x i32><br class="">

; BROADWELL-LABEL: test_pmuludq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmuludq %ymm1, %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmuludq (%rdi), %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmuludq (%rdi), %ymm0, %ymm0 # sched: [11:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmuludq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5051,9 +5051,9 @@ define <4 x i64> @test_por(<4 x i64> %a0<br class="">

; BROADWELL-LABEL: test_por:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    vpor (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpor (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_por:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5098,8 +5098,8 @@ define <4 x i64> @test_psadbw(<32 x i8><br class="">

; BROADWELL-LABEL: test_psadbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsadbw %ymm1, %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpsadbw (%rdi), %ymm0, %ymm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsadbw (%rdi), %ymm0, %ymm0 # sched: [11:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psadbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5142,8 +5142,8 @@ define <32 x i8> @test_pshufb(<32 x i8><br class="">

; BROADWELL-LABEL: test_pshufb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpshufb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpshufb (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpshufb (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pshufb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5187,9 +5187,9 @@ define <8 x i32> @test_pshufd(<8 x i32><br class="">

; BROADWELL-LABEL: test_pshufd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpshufd {{.*#+}} ymm1 = mem[1,0,3,2,5,4,7,6] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpshufd {{.*#+}} ymm1 = mem[1,0,3,2,5,4,7,6] sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pshufd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5236,9 +5236,9 @@ define <16 x i16> @test_pshufhw(<16 x i1<br class="">

; BROADWELL-LABEL: test_pshufhw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,5,4,8,9,10,11,15,14,13,12] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpshufhw {{.*#+}} ymm1 = mem[0,1,2,3,5,4,7,6,8,9,10,11,13,12,15,14] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpshufhw {{.*#+}} ymm1 = mem[0,1,2,3,5,4,7,6,8,9,10,11,13,12,15,14] sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pshufhw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5285,9 +5285,9 @@ define <16 x i16> @test_pshuflw(<16 x i1<br class="">

; BROADWELL-LABEL: test_pshuflw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[3,2,1,0,4,5,6,7,11,10,9,8,12,13,14,15] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpshuflw {{.*#+}} ymm1 = mem[1,0,3,2,4,5,6,7,9,8,11,10,12,13,14,15] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpshuflw {{.*#+}} ymm1 = mem[1,0,3,2,4,5,6,7,9,8,11,10,12,13,14,15] sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pshuflw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5332,8 +5332,8 @@ define <32 x i8> @test_psignb(<32 x i8><br class="">

; BROADWELL-LABEL: test_psignb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsignb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsignb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsignb (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psignb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5375,8 +5375,8 @@ define <8 x i32> @test_psignd(<8 x i32><br class="">

; BROADWELL-LABEL: test_psignd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsignd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsignd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsignd (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psignd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5418,8 +5418,8 @@ define <16 x i16> @test_psignw(<16 x i16<br class="">

; BROADWELL-LABEL: test_psignw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsignw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsignw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsignw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psignw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5463,9 +5463,9 @@ define <8 x i32> @test_pslld(<8 x i32> %<br class="">

; BROADWELL-LABEL: test_pslld:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpslld %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vpslld (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpslld (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpslld $2, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pslld:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5509,7 +5509,7 @@ define <32 x i8> @test_pslldq(<32 x i8><br class="">

; BROADWELL-LABEL: test_pslldq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pslldq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5547,9 +5547,9 @@ define <4 x i64> @test_psllq(<4 x i64> %<br class="">

; BROADWELL-LABEL: test_psllq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsllq %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vpsllq (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpsllq (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsllq $2, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psllq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5595,8 +5595,8 @@ define <4 x i32> @test_psllvd(<4 x i32><br class="">

; BROADWELL-LABEL: test_psllvd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsllvd %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vpsllvd (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsllvd (%rdi), %xmm0, %xmm0 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psllvd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5638,8 +5638,8 @@ define <8 x i32> @test_psllvd_ymm(<8 x i<br class="">

; BROADWELL-LABEL: test_psllvd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsllvd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vpsllvd (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsllvd (%rdi), %ymm0, %ymm0 # sched: [9:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psllvd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5681,8 +5681,8 @@ define <2 x i64> @test_psllvq(<2 x i64><br class="">

; BROADWELL-LABEL: test_psllvq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsllvq %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpsllvq (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsllvq (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psllvq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5724,8 +5724,8 @@ define <4 x i64> @test_psllvq_ymm(<4 x i<br class="">

; BROADWELL-LABEL: test_psllvq_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsllvq %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpsllvq (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsllvq (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psllvq_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5769,9 +5769,9 @@ define <16 x i16> @test_psllw(<16 x i16><br class="">

; BROADWELL-LABEL: test_psllw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsllw %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vpsllw (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpsllw (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsllw $2, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psllw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5819,9 +5819,9 @@ define <8 x i32> @test_psrad(<8 x i32> %<br class="">

; BROADWELL-LABEL: test_psrad:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrad %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vpsrad (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpsrad (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsrad $2, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrad:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5867,8 +5867,8 @@ define <4 x i32> @test_psravd(<4 x i32><br class="">

; BROADWELL-LABEL: test_psravd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsravd %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vpsravd (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsravd (%rdi), %xmm0, %xmm0 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psravd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5910,8 +5910,8 @@ define <8 x i32> @test_psravd_ymm(<8 x i<br class="">

; BROADWELL-LABEL: test_psravd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsravd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vpsravd (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsravd (%rdi), %ymm0, %ymm0 # sched: [9:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psravd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5955,9 +5955,9 @@ define <16 x i16> @test_psraw(<16 x i16><br class="">

; BROADWELL-LABEL: test_psraw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsraw %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vpsraw (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpsraw (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsraw $2, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psraw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6005,9 +6005,9 @@ define <8 x i32> @test_psrld(<8 x i32> %<br class="">

; BROADWELL-LABEL: test_psrld:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrld %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vpsrld (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpsrld (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsrld $2, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrld:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6051,7 +6051,7 @@ define <32 x i8> @test_psrldq(<32 x i8><br class="">

; BROADWELL-LABEL: test_psrldq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrldq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6089,9 +6089,9 @@ define <4 x i64> @test_psrlq(<4 x i64> %<br class="">

; BROADWELL-LABEL: test_psrlq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrlq %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vpsrlq (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpsrlq (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsrlq $2, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrlq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6137,8 +6137,8 @@ define <4 x i32> @test_psrlvd(<4 x i32><br class="">

; BROADWELL-LABEL: test_psrlvd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrlvd %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vpsrlvd (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsrlvd (%rdi), %xmm0, %xmm0 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrlvd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6180,8 +6180,8 @@ define <8 x i32> @test_psrlvd_ymm(<8 x i<br class="">

; BROADWELL-LABEL: test_psrlvd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrlvd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vpsrlvd (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsrlvd (%rdi), %ymm0, %ymm0 # sched: [9:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrlvd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6223,8 +6223,8 @@ define <2 x i64> @test_psrlvq(<2 x i64><br class="">

; BROADWELL-LABEL: test_psrlvq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrlvq %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpsrlvq (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsrlvq (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrlvq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6266,8 +6266,8 @@ define <4 x i64> @test_psrlvq_ymm(<4 x i<br class="">

; BROADWELL-LABEL: test_psrlvq_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrlvq %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpsrlvq (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsrlvq (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrlvq_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6311,9 +6311,9 @@ define <16 x i16> @test_psrlw(<16 x i16><br class="">

; BROADWELL-LABEL: test_psrlw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrlw %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vpsrlw (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpsrlw (%rdi), %ymm0, %ymm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsrlw $2, %ymm0, %ymm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrlw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6359,8 +6359,8 @@ define <32 x i8> @test_psubb(<32 x i8> %<br class="">

; BROADWELL-LABEL: test_psubb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubb (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6401,8 +6401,8 @@ define <8 x i32> @test_psubd(<8 x i32> %<br class="">

; BROADWELL-LABEL: test_psubd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubd (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6443,8 +6443,8 @@ define <4 x i64> @test_psubq(<4 x i64> %<br class="">

; BROADWELL-LABEL: test_psubq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubq (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6485,8 +6485,8 @@ define <32 x i8> @test_psubsb(<32 x i8><br class="">

; BROADWELL-LABEL: test_psubsb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubsb (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubsb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6528,8 +6528,8 @@ define <16 x i16> @test_psubsw(<16 x i16<br class="">

; BROADWELL-LABEL: test_psubsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubsw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6571,8 +6571,8 @@ define <32 x i8> @test_psubusb(<32 x i8><br class="">

; BROADWELL-LABEL: test_psubusb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubusb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubusb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubusb (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubusb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6614,8 +6614,8 @@ define <16 x i16> @test_psubusw(<16 x i1<br class="">

; BROADWELL-LABEL: test_psubusw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubusw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubusw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubusw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubusw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6657,8 +6657,8 @@ define <16 x i16> @test_psubw(<16 x i16><br class="">

; BROADWELL-LABEL: test_psubw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubw (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6699,8 +6699,8 @@ define <32 x i8> @test_punpckhbw(<32 x i<br class="">

; BROADWELL-LABEL: test_punpckhbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpckhbw {{.*#+}} ymm0 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]

 sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpckhbw {{.*#+}} ymm0 = ymm0[8],mem[8],ymm0[9],mem[9],ymm0[10],mem[10],ymm0[11],mem[11],ymm0[12],mem[12],ymm0[13],mem[13],ymm0[14],mem[14],ymm0[15],mem[15],ymm0[24],mem[24],ymm0[25],mem[25],ymm0[26],mem[26],ymm0[27],mem[27],ymm0[28],mem[28],ymm0[29],mem[29],ymm0[30],mem[30],ymm0[31],mem[31]

 sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpckhbw {{.*#+}} ymm0 = ymm0[8],mem[8],ymm0[9],mem[9],ymm0[10],mem[10],ymm0[11],mem[11],ymm0[12],mem[12],ymm0[13],mem[13],ymm0[14],mem[14],ymm0[15],mem[15],ymm0[24],mem[24],ymm0[25],mem[25],ymm0[26],mem[26],ymm0[27],mem[27],ymm0[28],mem[28],ymm0[29],mem[29],ymm0[30],mem[30],ymm0[31],mem[31]

 sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckhbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6745,10 +6745,10 @@ define <8 x i32> @test_punpckhdq(<8 x i3<br class="">

; BROADWELL-LABEL: test_punpckhdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpckhdq {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpckhdq {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpckhdq {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7] sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckhdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6798,9 +6798,9 @@ define <4 x i64> @test_punpckhqdq(<4 x i<br class="">

; BROADWELL-LABEL: test_punpckhqdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpckhqdq {{.*#+}} ymm1 = ymm0[1],ymm1[1],ymm0[3],ymm1[3] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckhqdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6845,8 +6845,8 @@ define <16 x i16> @test_punpckhwd(<16 x<br class="">

; BROADWELL-LABEL: test_punpckhwd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpckhwd {{.*#+}} ymm0 = ymm0[4],mem[4],ymm0[5],mem[5],ymm0[6],mem[6],ymm0[7],mem[7],ymm0[12],mem[12],ymm0[13],mem[13],ymm0[14],mem[14],ymm0[15],mem[15] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpckhwd {{.*#+}} ymm0 = ymm0[4],mem[4],ymm0[5],mem[5],ymm0[6],mem[6],ymm0[7],mem[7],ymm0[12],mem[12],ymm0[13],mem[13],ymm0[14],mem[14],ymm0[15],mem[15] sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckhwd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6887,8 +6887,8 @@ define <32 x i8> @test_punpcklbw(<32 x i<br class="">

; BROADWELL-LABEL: test_punpcklbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]

 sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpcklbw {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[2],mem[2],ymm0[3],mem[3],ymm0[4],mem[4],ymm0[5],mem[5],ymm0[6],mem[6],ymm0[7],mem[7],ymm0[16],mem[16],ymm0[17],mem[17],ymm0[18],mem[18],ymm0[19],mem[19],ymm0[20],mem[20],ymm0[21],mem[21],ymm0[22],mem[22],ymm0[23],mem[23]

 sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpcklbw {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[2],mem[2],ymm0[3],mem[3],ymm0[4],mem[4],ymm0[5],mem[5],ymm0[6],mem[6],ymm0[7],mem[7],ymm0[16],mem[16],ymm0[17],mem[17],ymm0[18],mem[18],ymm0[19],mem[19],ymm0[20],mem[20],ymm0[21],mem[21],ymm0[22],mem[22],ymm0[23],mem[23]

 sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpcklbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6933,10 +6933,10 @@ define <8 x i32> @test_punpckldq(<8 x i3<br class="">

; BROADWELL-LABEL: test_punpckldq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpckldq {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpckldq {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5] sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckldq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6986,9 +6986,9 @@ define <4 x i64> @test_punpcklqdq(<4 x i<br class="">

; BROADWELL-LABEL: test_punpcklqdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpcklqdq {{.*#+}} ymm1 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[2],mem[2] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[2],mem[2] sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpcklqdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7033,8 +7033,8 @@ define <16 x i16> @test_punpcklwd(<16 x<br class="">

; BROADWELL-LABEL: test_punpcklwd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpcklwd {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[2],mem[2],ymm0[3],mem[3],ymm0[8],mem[8],ymm0[9],mem[9],ymm0[10],mem[10],ymm0[11],mem[11] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpcklwd {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[2],mem[2],ymm0[3],mem[3],ymm0[8],mem[8],ymm0[9],mem[9],ymm0[10],mem[10],ymm0[11],mem[11] sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpcklwd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7077,9 +7077,9 @@ define <4 x i64> @test_pxor(<4 x i64> %a<br class="">

; BROADWELL-LABEL: test_pxor:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpxor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    vpxor (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpxor (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pxor:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/bmi-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/bmi-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/bmi-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -30,10 +30,10 @@ define i16 @test_andn_i16(i16 zeroext %a<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    andnl %esi, %edi, %eax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    notl %edi # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    andw (%rdx), %di # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    andw (%rdx), %di # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    addl %edi, %eax # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill><br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_andn_i16:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -87,9 +87,9 @@ define i32 @test_andn_i32(i32 %a0, i32 %<br class="">

; BROADWELL-LABEL: test_andn_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    andnl %esi, %edi, %ecx # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    andnl (%rdx), %edi, %eax # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    andnl (%rdx), %edi, %eax # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_andn_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -137,9 +137,9 @@ define i64 @test_andn_i64(i64 %a0, i64 %<br class="">

; BROADWELL-LABEL: test_andn_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    andnq %rsi, %rdi, %rcx # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    andnq (%rdx), %rdi, %rax # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    andnq (%rdx), %rdi, %rax # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_andn_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -186,10 +186,10 @@ define i32 @test_bextr_i32(i32 %a0, i32<br class="">

;<br class="">

; BROADWELL-LABEL: test_bextr_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    bextrl %edi, (%rdx), %ecx # sched: [2:0.50]<br class="">

+; BROADWELL-NEXT:    bextrl %edi, (%rdx), %ecx # sched: [7:0.50]<br class="">

; BROADWELL-NEXT:    bextrl %edi, %esi, %eax # sched: [2:0.50]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_bextr_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -236,10 +236,10 @@ define i64 @test_bextr_i64(i64 %a0, i64<br class="">

;<br class="">

; BROADWELL-LABEL: test_bextr_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    bextrq %rdi, (%rdx), %rcx # sched: [2:0.50]<br class="">

+; BROADWELL-NEXT:    bextrq %rdi, (%rdx), %rcx # sched: [7:0.50]<br class="">

; BROADWELL-NEXT:    bextrq %rdi, %rsi, %rax # sched: [2:0.50]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_bextr_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -286,10 +286,10 @@ define i32 @test_blsi_i32(i32 %a0, i32 *<br class="">

;<br class="">

; BROADWELL-LABEL: test_blsi_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    blsil (%rsi), %ecx # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    blsil (%rsi), %ecx # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    blsil %edi, %eax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blsi_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -337,10 +337,10 @@ define i64 @test_blsi_i64(i64 %a0, i64 *<br class="">

;<br class="">

; BROADWELL-LABEL: test_blsi_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    blsiq (%rsi), %rcx # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    blsiq (%rsi), %rcx # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    blsiq %rdi, %rax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blsi_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -388,10 +388,10 @@ define i32 @test_blsmsk_i32(i32 %a0, i32<br class="">

;<br class="">

; BROADWELL-LABEL: test_blsmsk_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    blsmskl (%rsi), %ecx # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    blsmskl (%rsi), %ecx # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    blsmskl %edi, %eax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blsmsk_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -439,10 +439,10 @@ define i64 @test_blsmsk_i64(i64 %a0, i64<br class="">

;<br class="">

; BROADWELL-LABEL: test_blsmsk_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    blsmskq (%rsi), %rcx # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    blsmskq (%rsi), %rcx # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    blsmskq %rdi, %rax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blsmsk_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -490,10 +490,10 @@ define i32 @test_blsr_i32(i32 %a0, i32 *<br class="">

;<br class="">

; BROADWELL-LABEL: test_blsr_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    blsrl (%rsi), %ecx # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    blsrl (%rsi), %ecx # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    blsrl %edi, %eax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blsr_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -541,10 +541,10 @@ define i64 @test_blsr_i64(i64 %a0, i64 *<br class="">

;<br class="">

; BROADWELL-LABEL: test_blsr_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    blsrq (%rsi), %rcx # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    blsrq (%rsi), %rcx # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    blsrq %rdi, %rax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blsr_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -594,11 +594,11 @@ define i16 @test_cttz_i16(i16 zeroext %a<br class="">

;<br class="">

; BROADWELL-LABEL: test_cttz_i16:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    tzcntw (%rsi), %cx # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    tzcntw (%rsi), %cx # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    tzcntw %di, %ax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    orl %ecx, %eax # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill><br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cttz_i16:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -648,10 +648,10 @@ define i32 @test_cttz_i32(i32 %a0, i32 *<br class="">

;<br class="">

; BROADWELL-LABEL: test_cttz_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    tzcntl (%rsi), %ecx # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    tzcntl (%rsi), %ecx # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    tzcntl %edi, %eax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    orl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cttz_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -698,10 +698,10 @@ define i64 @test_cttz_i64(i64 %a0, i64 *<br class="">

;<br class="">

; BROADWELL-LABEL: test_cttz_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    tzcntq (%rsi), %rcx # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    tzcntq (%rsi), %rcx # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    tzcntq %rdi, %rax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    orq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cttz_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -23,10 +23,10 @@ define i32 @test_bzhi_i32(i32 %a0, i32 %<br class="">

;<br class="">

; BROADWELL-LABEL: test_bzhi_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    bzhil %edi, (%rdx), %ecx # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    bzhil %edi, (%rdx), %ecx # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    bzhil %edi, %esi, %eax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_bzhi_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -73,10 +73,10 @@ define i64 @test_bzhi_i64(i64 %a0, i64 %<br class="">

;<br class="">

; BROADWELL-LABEL: test_bzhi_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    bzhiq %rdi, (%rdx), %rcx # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    bzhiq %rdi, (%rdx), %rcx # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    bzhiq %rdi, %rsi, %rax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_bzhi_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -132,9 +132,9 @@ define i64 @test_mulx_i64(i64 %a0, i64 %<br class="">

; BROADWELL-NEXT:    movq %rdx, %rax # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    movq %rdi, %rdx # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    mulxq %rsi, %rsi, %rcx # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    mulxq (%rax), %rdx, %rax # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    mulxq (%rax), %rdx, %rax # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    orq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_mulx_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -193,10 +193,10 @@ define i32 @test_pdep_i32(i32 %a0, i32 %<br class="">

;<br class="">

; BROADWELL-LABEL: test_pdep_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    pdepl (%rdx), %edi, %ecx # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    pdepl (%rdx), %edi, %ecx # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    pdepl %esi, %edi, %eax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pdep_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -243,10 +243,10 @@ define i64 @test_pdep_i64(i64 %a0, i64 %<br class="">

;<br class="">

; BROADWELL-LABEL: test_pdep_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    pdepq (%rdx), %rdi, %rcx # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    pdepq (%rdx), %rdi, %rcx # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    pdepq %rsi, %rdi, %rax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pdep_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -293,10 +293,10 @@ define i32 @test_pext_i32(i32 %a0, i32 %<br class="">

;<br class="">

; BROADWELL-LABEL: test_pext_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    pextl (%rdx), %edi, %ecx # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    pextl (%rdx), %edi, %ecx # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    pextl %esi, %edi, %eax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pext_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -343,10 +343,10 @@ define i64 @test_pext_i64(i64 %a0, i64 %<br class="">

;<br class="">

; BROADWELL-LABEL: test_pext_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    pextq (%rdx), %rdi, %rcx # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    pextq (%rdx), %rdi, %rcx # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    pextq %rsi, %rdi, %rax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pext_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -394,9 +394,9 @@ define i32 @test_rorx_i32(i32 %a0, i32 %<br class="">

; BROADWELL-LABEL: test_rorx_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    rorxl $5, %edi, %ecx # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    rorxl $5, (%rdx), %eax # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    rorxl $5, (%rdx), %eax # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_rorx_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -447,9 +447,9 @@ define i64 @test_rorx_i64(i64 %a0, i64 %<br class="">

; BROADWELL-LABEL: test_rorx_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    rorxq $5, %rdi, %rcx # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    rorxq $5, (%rdx), %rax # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    rorxq $5, (%rdx), %rax # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_rorx_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -500,9 +500,9 @@ define i32 @test_sarx_i32(i32 %a0, i32 %<br class="">

; BROADWELL-LABEL: test_sarx_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    sarxl %esi, %edi, %ecx # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    sarxl %esi, (%rdx), %eax # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    sarxl %esi, (%rdx), %eax # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_sarx_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -549,9 +549,9 @@ define i64 @test_sarx_i64(i64 %a0, i64 %<br class="">

; BROADWELL-LABEL: test_sarx_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    sarxq %rsi, %rdi, %rcx # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    sarxq %rsi, (%rdx), %rax # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    sarxq %rsi, (%rdx), %rax # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_sarx_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -598,9 +598,9 @@ define i32 @test_shlx_i32(i32 %a0, i32 %<br class="">

; BROADWELL-LABEL: test_shlx_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    shlxl %esi, %edi, %ecx # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    shlxl %esi, (%rdx), %eax # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    shlxl %esi, (%rdx), %eax # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_shlx_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -647,9 +647,9 @@ define i64 @test_shlx_i64(i64 %a0, i64 %<br class="">

; BROADWELL-LABEL: test_shlx_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    shlxq %rsi, %rdi, %rcx # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    shlxq %rsi, (%rdx), %rax # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    shlxq %rsi, (%rdx), %rax # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_shlx_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -696,9 +696,9 @@ define i32 @test_shrx_i32(i32 %a0, i32 %<br class="">

; BROADWELL-LABEL: test_shrx_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    shrxl %esi, %edi, %ecx # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    shrxl %esi, (%rdx), %eax # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    shrxl %esi, (%rdx), %eax # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_shrx_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -745,9 +745,9 @@ define i64 @test_shrx_i64(i64 %a0, i64 %<br class="">

; BROADWELL-LABEL: test_shrx_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    shrxq %rsi, %rdi, %rcx # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    shrxq %rsi, (%rdx), %rax # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    shrxq %rsi, (%rdx), %rax # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_shrx_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/f16c-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/f16c-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/f16c-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/f16c-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/f16c-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -31,10 +31,10 @@ define <4 x float> @test_vcvtph2ps_128(<<br class="">

;<br class="">

; BROADWELL-LABEL: test_vcvtph2ps_128:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vcvtph2ps (%rdi), %xmm1 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtph2ps (%rdi), %xmm1 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vcvtph2ps %xmm0, %xmm0 # sched: [2:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vcvtph2ps_128:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -88,10 +88,10 @@ define <8 x float> @test_vcvtph2ps_256(<<br class="">

;<br class="">

; BROADWELL-LABEL: test_vcvtph2ps_256:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vcvtph2ps (%rdi), %ymm1 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtph2ps (%rdi), %ymm1 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vcvtph2ps %xmm0, %ymm0 # sched: [2:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vcvtph2ps_256:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -144,7 +144,7 @@ define <8 x i16> @test_vcvtps2ph_128(<4<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtps2ph $0, %xmm0, %xmm0 # sched: [4:1.00]<br class="">

; BROADWELL-NEXT:    vcvtps2ph $0, %xmm1, (%rdi) # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vcvtps2ph_128:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -196,9 +196,9 @@ define <8 x i16> @test_vcvtps2ph_256(<8<br class="">

; BROADWELL-LABEL: test_vcvtps2ph_256:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtps2ph $0, %ymm0, %xmm0 # sched: [6:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtps2ph $0, %ymm1, (%rdi) # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtps2ph $0, %ymm1, (%rdi) # sched: [4:1.00]<br class="">

; BROADWELL-NEXT:    vzeroupper # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vcvtps2ph_256:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/fma-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fma-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fma-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/fma-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/fma-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -31,8 +31,8 @@ define <2 x double> @test_vfmadd213pd(<2<br class="">

; BROADWELL-LABEL: test_vfmadd213pd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmadd213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmadd213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmadd213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmadd213pd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -79,8 +79,8 @@ define <4 x double> @test_vfmadd213pd_ym<br class="">

; BROADWELL-LABEL: test_vfmadd213pd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmadd213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmadd213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmadd213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmadd213pd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -127,8 +127,8 @@ define <4 x float> @test_vfmadd213ps(<4<br class="">

; BROADWELL-LABEL: test_vfmadd213ps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmadd213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmadd213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmadd213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmadd213ps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -175,8 +175,8 @@ define <8 x float> @test_vfmadd213ps_ymm<br class="">

; BROADWELL-LABEL: test_vfmadd213ps_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmadd213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmadd213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmadd213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmadd213ps_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -223,8 +223,8 @@ define <2 x double> @test_vfmadd213sd(<2<br class="">

; BROADWELL-LABEL: test_vfmadd213sd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmadd213sd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmadd213sd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmadd213sd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmadd213sd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -271,8 +271,8 @@ define <4 x float> @test_vfmadd213ss(<4<br class="">

; BROADWELL-LABEL: test_vfmadd213ss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmadd213ss %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmadd213ss (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmadd213ss (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmadd213ss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -331,8 +331,8 @@ define <2 x double> @test_vfmaddsubpd(<2<br class="">

; BROADWELL-LABEL: test_vfmaddsubpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmaddsub213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmaddsub213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmaddsub213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmaddsubpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -379,8 +379,8 @@ define <4 x double> @test_vfmaddsubpd_ym<br class="">

; BROADWELL-LABEL: test_vfmaddsubpd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmaddsub213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmaddsub213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmaddsub213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmaddsubpd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -427,8 +427,8 @@ define <4 x float> @test_vfmaddsubps(<4<br class="">

; BROADWELL-LABEL: test_vfmaddsubps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmaddsub213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmaddsub213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmaddsub213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmaddsubps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -475,8 +475,8 @@ define <8 x float> @test_vfmaddsubps_ymm<br class="">

; BROADWELL-LABEL: test_vfmaddsubps_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmaddsub213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmaddsub213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmaddsub213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmaddsubps_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -535,8 +535,8 @@ define <2 x double> @test_vfmsubaddpd(<2<br class="">

; BROADWELL-LABEL: test_vfmsubaddpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmsubadd213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmsubadd213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmsubadd213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmsubaddpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -583,8 +583,8 @@ define <4 x double> @test_vfmsubaddpd_ym<br class="">

; BROADWELL-LABEL: test_vfmsubaddpd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmsubadd213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmsubadd213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmsubadd213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmsubaddpd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -631,8 +631,8 @@ define <4 x float> @test_vfmsubaddps(<4<br class="">

; BROADWELL-LABEL: test_vfmsubaddps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmsubadd213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmsubadd213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmsubadd213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmsubaddps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -679,8 +679,8 @@ define <8 x float> @test_vfmsubaddps_ymm<br class="">

; BROADWELL-LABEL: test_vfmsubaddps_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmsubadd213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmsubadd213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmsubadd213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmsubaddps_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -739,8 +739,8 @@ define <2 x double> @test_vfmsub213pd(<2<br class="">

; BROADWELL-LABEL: test_vfmsub213pd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmsub213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmsub213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmsub213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmsub213pd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -787,8 +787,8 @@ define <4 x double> @test_vfmsub213pd_ym<br class="">

; BROADWELL-LABEL: test_vfmsub213pd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmsub213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmsub213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmsub213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmsub213pd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -835,8 +835,8 @@ define <4 x float> @test_vfmsub213ps(<4<br class="">

; BROADWELL-LABEL: test_vfmsub213ps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmsub213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmsub213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmsub213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmsub213ps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -883,8 +883,8 @@ define <8 x float> @test_vfmsub213ps_ymm<br class="">

; BROADWELL-LABEL: test_vfmsub213ps_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmsub213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmsub213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmsub213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmsub213ps_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -931,8 +931,8 @@ define <2 x double> @test_vfmsub213sd(<2<br class="">

; BROADWELL-LABEL: test_vfmsub213sd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmsub213sd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmsub213sd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmsub213sd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmsub213sd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -979,8 +979,8 @@ define <4 x float> @test_vfmsub213ss(<4<br class="">

; BROADWELL-LABEL: test_vfmsub213ss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfmsub213ss %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfmsub213ss (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfmsub213ss (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfmsub213ss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1039,8 +1039,8 @@ define <2 x double> @test_vfnmadd213pd(<<br class="">

; BROADWELL-LABEL: test_vfnmadd213pd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfnmadd213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfnmadd213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfnmadd213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfnmadd213pd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1087,8 +1087,8 @@ define <4 x double> @test_vfnmadd213pd_y<br class="">

; BROADWELL-LABEL: test_vfnmadd213pd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfnmadd213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfnmadd213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfnmadd213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfnmadd213pd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1135,8 +1135,8 @@ define <4 x float> @test_vfnmadd213ps(<4<br class="">

; BROADWELL-LABEL: test_vfnmadd213ps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfnmadd213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfnmadd213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfnmadd213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfnmadd213ps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1183,8 +1183,8 @@ define <8 x float> @test_vfnmadd213ps_ym<br class="">

; BROADWELL-LABEL: test_vfnmadd213ps_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfnmadd213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfnmadd213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfnmadd213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfnmadd213ps_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1231,8 +1231,8 @@ define <2 x double> @test_vfnmadd213sd(<<br class="">

; BROADWELL-LABEL: test_vfnmadd213sd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfnmadd213sd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfnmadd213sd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfnmadd213sd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfnmadd213sd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1279,8 +1279,8 @@ define <4 x float> @test_vfnmadd213ss(<4<br class="">

; BROADWELL-LABEL: test_vfnmadd213ss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfnmadd213ss %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfnmadd213ss (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfnmadd213ss (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfnmadd213ss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1339,8 +1339,8 @@ define <2 x double> @test_vfnmsub213pd(<<br class="">

; BROADWELL-LABEL: test_vfnmsub213pd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfnmsub213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfnmsub213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfnmsub213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfnmsub213pd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1387,8 +1387,8 @@ define <4 x double> @test_vfnmsub213pd_y<br class="">

; BROADWELL-LABEL: test_vfnmsub213pd_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfnmsub213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfnmsub213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfnmsub213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfnmsub213pd_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1435,8 +1435,8 @@ define <4 x float> @test_vfnmsub213ps(<4<br class="">

; BROADWELL-LABEL: test_vfnmsub213ps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfnmsub213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfnmsub213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfnmsub213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfnmsub213ps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1483,8 +1483,8 @@ define <8 x float> @test_vfnmsub213ps_ym<br class="">

; BROADWELL-LABEL: test_vfnmsub213ps_ymm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfnmsub213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfnmsub213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfnmsub213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfnmsub213ps_ymm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1531,8 +1531,8 @@ define <2 x double> @test_vfnmsub213sd(<<br class="">

; BROADWELL-LABEL: test_vfnmsub213sd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfnmsub213sd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfnmsub213sd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfnmsub213sd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfnmsub213sd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1579,8 +1579,8 @@ define <4 x float> @test_vfnmsub213ss(<4<br class="">

; BROADWELL-LABEL: test_vfnmsub213ss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vfnmsub213ss %xmm2, %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vfnmsub213ss (%rdi), %xmm1, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vfnmsub213ss (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_vfnmsub213ss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/lea32-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea32-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea32-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/lea32-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/lea32-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -52,7 +52,7 @@ define i32 @test_lea_offset(i32) {<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    # kill: %EDI<def> %EDI<kill> %RDI<def><br class="">

; BROADWELL-NEXT:    leal -24(%rdi), %eax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_offset:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -116,7 +116,7 @@ define i32 @test_lea_offset_big(i32) {<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    # kill: %EDI<def> %EDI<kill> %RDI<def><br class="">

; BROADWELL-NEXT:    leal 1024(%rdi), %eax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_offset_big:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -187,7 +187,7 @@ define i32 @test_lea_add(i32, i32) {<br class="">

; BROADWELL-NEXT:    # kill: %ESI<def> %ESI<kill> %RSI<def><br class="">

; BROADWELL-NEXT:    # kill: %EDI<def> %EDI<kill> %RDI<def><br class="">

; BROADWELL-NEXT:    leal (%rdi,%rsi), %eax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_add:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -264,7 +264,7 @@ define i32 @test_lea_add_offset(i32, i32<br class="">

; BROADWELL-NEXT:    # kill: %EDI<def> %EDI<kill> %RDI<def><br class="">

; BROADWELL-NEXT:    leal (%rdi,%rsi), %eax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addl $16, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_add_offset:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -347,7 +347,7 @@ define i32 @test_lea_add_offset_big(i32,<br class="">

; BROADWELL-NEXT:    leal (%rdi,%rsi), %eax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addl $-4096, %eax # imm = 0xF000<br class="">

; BROADWELL-NEXT:    # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_add_offset_big:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -417,7 +417,7 @@ define i32 @test_lea_mul(i32) {<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    # kill: %EDI<def> %EDI<kill> %RDI<def><br class="">

; BROADWELL-NEXT:    leal (%rdi,%rdi,2), %eax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_mul:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -485,7 +485,7 @@ define i32 @test_lea_mul_offset(i32) {<br class="">

; BROADWELL-NEXT:    # kill: %EDI<def> %EDI<kill> %RDI<def><br class="">

; BROADWELL-NEXT:    leal (%rdi,%rdi,2), %eax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addl $-32, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_mul_offset:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -559,7 +559,7 @@ define i32 @test_lea_mul_offset_big(i32)<br class="">

; BROADWELL-NEXT:    leal (%rdi,%rdi,8), %eax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addl $10000, %eax # imm = 0x2710<br class="">

; BROADWELL-NEXT:    # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_mul_offset_big:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -632,7 +632,7 @@ define i32 @test_lea_add_scale(i32, i32)<br class="">

; BROADWELL-NEXT:    # kill: %ESI<def> %ESI<kill> %RSI<def><br class="">

; BROADWELL-NEXT:    # kill: %EDI<def> %EDI<kill> %RDI<def><br class="">

; BROADWELL-NEXT:    leal (%rdi,%rsi,2), %eax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_add_scale:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -710,7 +710,7 @@ define i32 @test_lea_add_scale_offset(i3<br class="">

; BROADWELL-NEXT:    # kill: %EDI<def> %EDI<kill> %RDI<def><br class="">

; BROADWELL-NEXT:    leal (%rdi,%rsi,4), %eax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addl $96, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_add_scale_offset:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -794,7 +794,7 @@ define i32 @test_lea_add_scale_offset_bi<br class="">

; BROADWELL-NEXT:    leal (%rdi,%rsi,8), %eax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addl $-1200, %eax # imm = 0xFB50<br class="">

; BROADWELL-NEXT:    # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_add_scale_offset_big:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/lea64-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea64-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea64-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/lea64-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/lea64-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -46,7 +46,7 @@ define i64 @test_lea_offset(i64) {<br class="">

; BROADWELL-LABEL: test_lea_offset:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    leaq -24(%rdi), %rax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_offset:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -101,7 +101,7 @@ define i64 @test_lea_offset_big(i64) {<br class="">

; BROADWELL-LABEL: test_lea_offset_big:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    leaq 1024(%rdi), %rax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_offset_big:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -157,7 +157,7 @@ define i64 @test_lea_add(i64, i64) {<br class="">

; BROADWELL-LABEL: test_lea_add:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    leaq (%rdi,%rsi), %rax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_add:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -216,7 +216,7 @@ define i64 @test_lea_add_offset(i64, i64<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    leaq (%rdi,%rsi), %rax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addq $16, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_add_offset:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -281,7 +281,7 @@ define i64 @test_lea_add_offset_big(i64,<br class="">

; BROADWELL-NEXT:    leaq (%rdi,%rsi), %rax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addq $-4096, %rax # imm = 0xF000<br class="">

; BROADWELL-NEXT:    # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_add_offset_big:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -339,7 +339,7 @@ define i64 @test_lea_mul(i64) {<br class="">

; BROADWELL-LABEL: test_lea_mul:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    leaq (%rdi,%rdi,2), %rax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_mul:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -398,7 +398,7 @@ define i64 @test_lea_mul_offset(i64) {<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    leaq (%rdi,%rdi,2), %rax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addq $-32, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_mul_offset:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -463,7 +463,7 @@ define i64 @test_lea_mul_offset_big(i64)<br class="">

; BROADWELL-NEXT:    leaq (%rdi,%rdi,8), %rax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addq $10000, %rax # imm = 0x2710<br class="">

; BROADWELL-NEXT:    # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_mul_offset_big:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -521,7 +521,7 @@ define i64 @test_lea_add_scale(i64, i64)<br class="">

; BROADWELL-LABEL: test_lea_add_scale:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    leaq (%rdi,%rsi,2), %rax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_add_scale:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -581,7 +581,7 @@ define i64 @test_lea_add_scale_offset(i6<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    leaq (%rdi,%rsi,4), %rax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addq $96, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_add_scale_offset:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -647,7 +647,7 @@ define i64 @test_lea_add_scale_offset_bi<br class="">

; BROADWELL-NEXT:    leaq (%rdi,%rsi,8), %rax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    addq $-1200, %rax # imm = 0xFB50<br class="">

; BROADWELL-NEXT:    # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lea_add_scale_offset_big:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -26,11 +26,11 @@ define i16 @test_ctlz_i16(i16 zeroext %a<br class="">

;<br class="">

; BROADWELL-LABEL: test_ctlz_i16:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    lzcntw (%rsi), %cx # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    lzcntw (%rsi), %cx # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    lzcntw %di, %ax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    orl %ecx, %eax # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill><br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_ctlz_i16:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -80,10 +80,10 @@ define i32 @test_ctlz_i32(i32 %a0, i32 *<br class="">

;<br class="">

; BROADWELL-LABEL: test_ctlz_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    lzcntl (%rsi), %ecx # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    lzcntl (%rsi), %ecx # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    lzcntl %edi, %eax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    orl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_ctlz_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -130,10 +130,10 @@ define i64 @test_ctlz_i64(i64 %a0, i64 *<br class="">

;<br class="">

; BROADWELL-LABEL: test_ctlz_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    lzcntq (%rsi), %rcx # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    lzcntq (%rsi), %rcx # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    lzcntq %rdi, %rax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    orq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_ctlz_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/mmx-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/mmx-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/mmx-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -54,11 +54,11 @@ define i64 @test_cvtpd2pi(<2 x double> %<br class="">

;<br class="">

; BROADWELL-LABEL: test_cvtpd2pi:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    cvtpd2pi (%rdi), %mm0 # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    cvtpd2pi (%rdi), %mm0 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    cvtpd2pi %xmm0, %mm1 # sched: [4:1.00]<br class="">

; BROADWELL-NEXT:    por %mm1, %mm0 # sched: [1:0.33]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtpd2pi:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -139,9 +139,9 @@ define <2 x double> @test_cvtpi2pd(x86_m<br class="">

; BROADWELL-LABEL: test_cvtpi2pd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    cvtpi2pd %mm0, %xmm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    cvtpi2pd (%rdi), %xmm1 # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    cvtpi2pd (%rdi), %xmm1 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtpi2pd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -217,9 +217,9 @@ define <4 x float> @test_cvtpi2ps(x86_mm<br class="">

; BROADWELL-LABEL: test_cvtpi2ps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    cvtpi2ps %mm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    cvtpi2ps (%rdi), %xmm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    cvtpi2ps (%rdi), %xmm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtpi2ps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -300,10 +300,10 @@ define i64 @test_cvtps2pi(<4 x float> %a<br class="">

; BROADWELL-LABEL: test_cvtps2pi:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    cvtps2pi %xmm0, %mm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    cvtps2pi (%rdi), %mm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    cvtps2pi (%rdi), %mm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    por %mm0, %mm1 # sched: [1:0.33]<br class="">

; BROADWELL-NEXT:    movd %mm1, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtps2pi:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -388,11 +388,11 @@ define i64 @test_cvttpd2pi(<2 x double><br class="">

;<br class="">

; BROADWELL-LABEL: test_cvttpd2pi:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    cvttpd2pi (%rdi), %mm0 # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    cvttpd2pi (%rdi), %mm0 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    cvttpd2pi %xmm0, %mm1 # sched: [4:1.00]<br class="">

; BROADWELL-NEXT:    por %mm1, %mm0 # sched: [1:0.33]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvttpd2pi:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -478,10 +478,10 @@ define i64 @test_cvttps2pi(<4 x float> %<br class="">

; BROADWELL-LABEL: test_cvttps2pi:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    cvttps2pi %xmm0, %mm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    cvttps2pi (%rdi), %mm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    cvttps2pi (%rdi), %mm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    por %mm0, %mm1 # sched: [1:0.33]<br class="">

; BROADWELL-NEXT:    movd %mm1, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvttps2pi:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -552,7 +552,7 @@ define void @test_emms() optsize {<br class="">

; BROADWELL-LABEL: test_emms:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    emms # sched: [31:10.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_emms:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -607,7 +607,7 @@ define void @test_maskmovq(x86_mmx %a0,<br class="">

; BROADWELL-LABEL: test_maskmovq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    maskmovq %mm1, %mm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_maskmovq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -708,15 +708,15 @@ define i32 @test_movd(x86_mmx %a0, i32 %<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovd %edi, %xmm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    vmovq %xmm0, -{{[0-9]+}}(%rsp) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    movq -{{[0-9]+}}(%rsp), %mm1 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    movq -{{[0-9]+}}(%rsp), %mm1 # sched: [5:0.50]<br class="">

+; BROADWELL-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vmovlps %xmm0, -{{[0-9]+}}(%rsp) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    paddd -{{[0-9]+}}(%rsp), %mm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    paddd -{{[0-9]+}}(%rsp), %mm1 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    paddd %mm1, %mm0 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm1, %ecx # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %eax # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    movl %ecx, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -829,7 +829,7 @@ define i64 @test_movdq2q(<2 x i64> %a0)<br class="">

; BROADWELL-NEXT:    movdq2q %xmm0, %mm0 # sched: [2:0.67]<br class="">

; BROADWELL-NEXT:    paddd %mm0, %mm0 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movdq2q:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -894,7 +894,7 @@ define void @test_movntq(x86_mmx* %a0, x<br class="">

; BROADWELL-LABEL: test_movntq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    movntq %mm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movntq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -960,10 +960,10 @@ define void @test_movq(i64 *%a0) {<br class="">

;<br class="">

; BROADWELL-LABEL: test_movq:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    movq (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    movq (%rdi), %mm0 # sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    paddd %mm0, %mm0 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    movq %mm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1029,7 +1029,7 @@ define <2 x i64> @test_movq2dq(x86_mmx %<br class="">

; BROADWELL-LABEL: test_movq2dq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    movq2dq %mm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movq2dq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1093,10 +1093,10 @@ define i64 @test_pabsb(x86_mmx *%a0) opt<br class="">

;<br class="">

; BROADWELL-LABEL: test_pabsb:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    pabsb (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pabsb (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    pabsb %mm0, %mm0 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pabsb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1171,10 +1171,10 @@ define i64 @test_pabsd(x86_mmx *%a0) opt<br class="">

;<br class="">

; BROADWELL-LABEL: test_pabsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    pabsd (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pabsd (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    pabsd %mm0, %mm0 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pabsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1249,10 +1249,10 @@ define i64 @test_pabsw(x86_mmx *%a0) opt<br class="">

;<br class="">

; BROADWELL-LABEL: test_pabsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    pabsw (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pabsw (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    pabsw %mm0, %mm0 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pabsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1328,9 +1328,9 @@ define i64 @test_packssdw(x86_mmx %a0, x<br class="">

; BROADWELL-LABEL: test_packssdw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    packssdw %mm1, %mm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    packssdw (%rdi), %mm0 # sched: [2:2.00]<br class="">

+; BROADWELL-NEXT:    packssdw (%rdi), %mm0 # sched: [7:2.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_packssdw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1406,9 +1406,9 @@ define i64 @test_packsswb(x86_mmx %a0, x<br class="">

; BROADWELL-LABEL: test_packsswb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    packsswb %mm1, %mm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    packsswb (%rdi), %mm0 # sched: [2:2.00]<br class="">

+; BROADWELL-NEXT:    packsswb (%rdi), %mm0 # sched: [7:2.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_packsswb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1484,9 +1484,9 @@ define i64 @test_packuswb(x86_mmx %a0, x<br class="">

; BROADWELL-LABEL: test_packuswb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    packuswb %mm1, %mm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    packuswb (%rdi), %mm0 # sched: [2:2.00]<br class="">

+; BROADWELL-NEXT:    packuswb (%rdi), %mm0 # sched: [7:2.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_packuswb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1562,9 +1562,9 @@ define i64 @test_paddb(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_paddb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    paddb %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    paddb (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    paddb (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1640,9 +1640,9 @@ define i64 @test_paddd(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_paddd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    paddd %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    paddd (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    paddd (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1718,9 +1718,9 @@ define i64 @test_paddq(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_paddq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    paddq %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    paddq (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    paddq (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1796,9 +1796,9 @@ define i64 @test_paddsb(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_paddsb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    paddsb %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    paddsb (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    paddsb (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddsb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1874,9 +1874,9 @@ define i64 @test_paddsw(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_paddsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    paddsw %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    paddsw (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    paddsw (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1952,9 +1952,9 @@ define i64 @test_paddusb(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_paddusb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    paddusb %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    paddusb (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    paddusb (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddusb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2030,9 +2030,9 @@ define i64 @test_paddusw(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_paddusw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    paddusw %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    paddusw (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    paddusw (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddusw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2108,9 +2108,9 @@ define i64 @test_paddw(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_paddw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    paddw %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    paddw (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    paddw (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2186,9 +2186,9 @@ define i64 @test_palignr(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_palignr:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    palignr $1, %mm1, %mm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    palignr $1, (%rdi), %mm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    palignr $1, (%rdi), %mm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_palignr:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2264,9 +2264,9 @@ define i64 @test_pand(x86_mmx %a0, x86_m<br class="">

; BROADWELL-LABEL: test_pand:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pand %mm1, %mm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    pand (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pand (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pand:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2342,9 +2342,9 @@ define i64 @test_pandn(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_pandn:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pandn %mm1, %mm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    pandn (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pandn (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pandn:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2420,9 +2420,9 @@ define i64 @test_pavgb(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_pavgb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pavgb %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    pavgb (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pavgb (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pavgb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2498,9 +2498,9 @@ define i64 @test_pavgw(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_pavgw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pavgw %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    pavgw (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pavgw (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pavgw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2576,9 +2576,9 @@ define i64 @test_pcmpeqb(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_pcmpeqb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pcmpeqb %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    pcmpeqb (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pcmpeqb (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpeqb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2654,9 +2654,9 @@ define i64 @test_pcmpeqd(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_pcmpeqd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pcmpeqd %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    pcmpeqd (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pcmpeqd (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpeqd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2732,9 +2732,9 @@ define i64 @test_pcmpeqw(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_pcmpeqw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pcmpeqw %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    pcmpeqw (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pcmpeqw (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpeqw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2810,9 +2810,9 @@ define i64 @test_pcmpgtb(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_pcmpgtb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pcmpgtb %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    pcmpgtb (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pcmpgtb (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpgtb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2888,9 +2888,9 @@ define i64 @test_pcmpgtd(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_pcmpgtd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pcmpgtd %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    pcmpgtd (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pcmpgtd (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpgtd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2966,9 +2966,9 @@ define i64 @test_pcmpgtw(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_pcmpgtw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pcmpgtw %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    pcmpgtw (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pcmpgtw (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpgtw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3034,7 +3034,7 @@ define i32 @test_pextrw(x86_mmx %a0) opt<br class="">

; BROADWELL-LABEL: test_pextrw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pextrw $0, %mm0, %eax # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pextrw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3099,9 +3099,9 @@ define i64 @test_phaddd(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_phaddd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    phaddd %mm1, %mm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    phaddd (%rdi), %mm0 # sched: [3:2.00]<br class="">

+; BROADWELL-NEXT:    phaddd (%rdi), %mm0 # sched: [8:2.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phaddd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3177,9 +3177,9 @@ define i64 @test_phaddsw(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_phaddsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    phaddsw %mm1, %mm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    phaddsw (%rdi), %mm0 # sched: [3:2.00]<br class="">

+; BROADWELL-NEXT:    phaddsw (%rdi), %mm0 # sched: [8:2.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phaddsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3255,9 +3255,9 @@ define i64 @test_phaddw(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_phaddw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    phaddw %mm1, %mm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    phaddw (%rdi), %mm0 # sched: [3:2.00]<br class="">

+; BROADWELL-NEXT:    phaddw (%rdi), %mm0 # sched: [8:2.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phaddw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3333,9 +3333,9 @@ define i64 @test_phsubd(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_phsubd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    phsubd %mm1, %mm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    phsubd (%rdi), %mm0 # sched: [3:2.00]<br class="">

+; BROADWELL-NEXT:    phsubd (%rdi), %mm0 # sched: [8:2.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phsubd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3411,9 +3411,9 @@ define i64 @test_phsubsw(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_phsubsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    phsubsw %mm1, %mm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    phsubsw (%rdi), %mm0 # sched: [3:2.00]<br class="">

+; BROADWELL-NEXT:    phsubsw (%rdi), %mm0 # sched: [8:2.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phsubsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3489,9 +3489,9 @@ define i64 @test_phsubw(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_phsubw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    phsubw %mm1, %mm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    phsubw (%rdi), %mm0 # sched: [3:2.00]<br class="">

+; BROADWELL-NEXT:    phsubw (%rdi), %mm0 # sched: [8:2.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phsubw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3572,10 +3572,10 @@ define i64 @test_pinsrw(x86_mmx %a0, i32<br class="">

; BROADWELL-LABEL: test_pinsrw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pinsrw $0, %edi, %mm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    movswl (%rsi), %eax # sched: [4:0.50]<br class="">

+; BROADWELL-NEXT:    movswl (%rsi), %eax # sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    pinsrw $1, %eax, %mm0 # sched: [2:2.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pinsrw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3656,9 +3656,9 @@ define i64 @test_pmaddwd(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_pmaddwd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pmaddwd %mm1, %mm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    pmaddwd (%rdi), %mm0 # sched: [5:1.00]<br class="">

+; BROADWELL-NEXT:    pmaddwd (%rdi), %mm0 # sched: [10:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaddwd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3734,9 +3734,9 @@ define i64 @test_pmaddubsw(x86_mmx %a0,<br class="">

; BROADWELL-LABEL: test_pmaddubsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pmaddubsw %mm1, %mm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    pmaddubsw (%rdi), %mm0 # sched: [5:1.00]<br class="">

+; BROADWELL-NEXT:    pmaddubsw (%rdi), %mm0 # sched: [10:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaddubsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3812,9 +3812,9 @@ define i64 @test_pmaxsw(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_pmaxsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pmaxsw %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    pmaxsw (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pmaxsw (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3890,9 +3890,9 @@ define i64 @test_pmaxub(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_pmaxub:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pmaxub %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    pmaxub (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pmaxub (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxub:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3968,9 +3968,9 @@ define i64 @test_pminsw(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_pminsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pminsw %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    pminsw (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pminsw (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4046,9 +4046,9 @@ define i64 @test_pminub(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_pminub:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pminub %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    pminub (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pminub (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminub:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4113,8 +4113,8 @@ define i32 @test_pmovmskb(x86_mmx %a0) o<br class="">

;<br class="">

; BROADWELL-LABEL: test_pmovmskb:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    pmovmskb %mm0, %eax # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    pmovmskb %mm0, %eax # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovmskb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4179,9 +4179,9 @@ define i64 @test_pmulhrsw(x86_mmx %a0, x<br class="">

; BROADWELL-LABEL: test_pmulhrsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pmulhrsw %mm1, %mm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    pmulhrsw (%rdi), %mm0 # sched: [5:1.00]<br class="">

+; BROADWELL-NEXT:    pmulhrsw (%rdi), %mm0 # sched: [10:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmulhrsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4257,9 +4257,9 @@ define i64 @test_pmulhw(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_pmulhw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pmulhw %mm1, %mm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    pmulhw (%rdi), %mm0 # sched: [5:1.00]<br class="">

+; BROADWELL-NEXT:    pmulhw (%rdi), %mm0 # sched: [10:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmulhw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4335,9 +4335,9 @@ define i64 @test_pmulhuw(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_pmulhuw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pmulhuw %mm1, %mm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    pmulhuw (%rdi), %mm0 # sched: [5:1.00]<br class="">

+; BROADWELL-NEXT:    pmulhuw (%rdi), %mm0 # sched: [10:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmulhuw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4413,9 +4413,9 @@ define i64 @test_pmullw(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_pmullw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pmullw %mm1, %mm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    pmullw (%rdi), %mm0 # sched: [5:1.00]<br class="">

+; BROADWELL-NEXT:    pmullw (%rdi), %mm0 # sched: [10:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmullw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4491,9 +4491,9 @@ define i64 @test_pmuludq(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_pmuludq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pmuludq %mm1, %mm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    pmuludq (%rdi), %mm0 # sched: [5:1.00]<br class="">

+; BROADWELL-NEXT:    pmuludq (%rdi), %mm0 # sched: [10:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmuludq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4569,9 +4569,9 @@ define i64 @test_por(x86_mmx %a0, x86_mm<br class="">

; BROADWELL-LABEL: test_por:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    por %mm1, %mm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    por (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    por (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_por:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4647,9 +4647,9 @@ define i64 @test_psadbw(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_psadbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psadbw %mm1, %mm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    psadbw (%rdi), %mm0 # sched: [5:1.00]<br class="">

+; BROADWELL-NEXT:    psadbw (%rdi), %mm0 # sched: [10:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psadbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4725,9 +4725,9 @@ define i64 @test_pshufb(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_pshufb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pshufb %mm1, %mm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    pshufb (%rdi), %mm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    pshufb (%rdi), %mm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pshufb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4802,10 +4802,10 @@ define i64 @test_pshufw(x86_mmx *%a0) op<br class="">

;<br class="">

; BROADWELL-LABEL: test_pshufw:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    pshufw $0, (%rdi), %mm0 # mm0 = mem[0,0,0,0] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    pshufw $0, (%rdi), %mm0 # mm0 = mem[0,0,0,0] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    pshufw $0, %mm0, %mm0 # mm0 = mm0[0,0,0,0] sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pshufw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4881,9 +4881,9 @@ define i64 @test_psignb(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_psignb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psignb %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    psignb (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    psignb (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psignb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4959,9 +4959,9 @@ define i64 @test_psignd(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_psignd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psignd %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    psignd (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    psignd (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psignd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5037,9 +5037,9 @@ define i64 @test_psignw(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_psignw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psignw %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    psignw (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    psignw (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psignw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5120,10 +5120,10 @@ define i64 @test_pslld(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_pslld:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pslld %mm1, %mm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    pslld (%rdi), %mm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    pslld (%rdi), %mm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    pslld $7, %mm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pslld:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5210,10 +5210,10 @@ define i64 @test_psllq(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_psllq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psllq %mm1, %mm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    psllq (%rdi), %mm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    psllq (%rdi), %mm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    psllq $7, %mm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psllq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5300,10 +5300,10 @@ define i64 @test_psllw(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_psllw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psllw %mm1, %mm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    psllw (%rdi), %mm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    psllw (%rdi), %mm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    psllw $7, %mm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psllw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5390,10 +5390,10 @@ define i64 @test_psrad(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_psrad:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psrad %mm1, %mm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    psrad (%rdi), %mm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    psrad (%rdi), %mm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    psrad $7, %mm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrad:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5480,10 +5480,10 @@ define i64 @test_psraw(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_psraw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psraw %mm1, %mm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    psraw (%rdi), %mm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    psraw (%rdi), %mm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    psraw $7, %mm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psraw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5570,10 +5570,10 @@ define i64 @test_psrld(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_psrld:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psrld %mm1, %mm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    psrld (%rdi), %mm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    psrld (%rdi), %mm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    psrld $7, %mm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrld:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5660,10 +5660,10 @@ define i64 @test_psrlq(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_psrlq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psrlq %mm1, %mm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    psrlq (%rdi), %mm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    psrlq (%rdi), %mm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    psrlq $7, %mm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrlq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5750,10 +5750,10 @@ define i64 @test_psrlw(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_psrlw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psrlw %mm1, %mm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    psrlw (%rdi), %mm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    psrlw (%rdi), %mm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    psrlw $7, %mm0 # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrlw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5835,9 +5835,9 @@ define i64 @test_psubb(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_psubb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psubb %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    psubb (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    psubb (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5913,9 +5913,9 @@ define i64 @test_psubd(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_psubd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psubd %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    psubd (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    psubd (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5991,9 +5991,9 @@ define i64 @test_psubq(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_psubq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psubq %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    psubq (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    psubq (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6069,9 +6069,9 @@ define i64 @test_psubsb(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_psubsb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psubsb %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    psubsb (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    psubsb (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubsb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6147,9 +6147,9 @@ define i64 @test_psubsw(x86_mmx %a0, x86<br class="">

; BROADWELL-LABEL: test_psubsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psubsw %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    psubsw (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    psubsw (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6225,9 +6225,9 @@ define i64 @test_psubusb(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_psubusb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psubusb %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    psubusb (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    psubusb (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubusb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6303,9 +6303,9 @@ define i64 @test_psubusw(x86_mmx %a0, x8<br class="">

; BROADWELL-LABEL: test_psubusw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psubusw %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    psubusw (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    psubusw (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubusw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6381,9 +6381,9 @@ define i64 @test_psubw(x86_mmx %a0, x86_<br class="">

; BROADWELL-LABEL: test_psubw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    psubw %mm1, %mm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    psubw (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    psubw (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6459,9 +6459,9 @@ define i64 @test_punpckhbw(x86_mmx %a0,<br class="">

; BROADWELL-LABEL: test_punpckhbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    punpckhbw %mm1, %mm0 # mm0 = mm0[4],mm1[4],mm0[5],mm1[5],mm0[6],mm1[6],mm0[7],mm1[7] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    punpckhbw (%rdi), %mm0 # mm0 = mm0[4],mem[4],mm0[5],mem[5],mm0[6],mem[6],mm0[7],mem[7] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    punpckhbw (%rdi), %mm0 # mm0 = mm0[4],mem[4],mm0[5],mem[5],mm0[6],mem[6],mm0[7],mem[7] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckhbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6537,9 +6537,9 @@ define i64 @test_punpckhdq(x86_mmx %a0,<br class="">

; BROADWELL-LABEL: test_punpckhdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    punpckhdq %mm1, %mm0 # mm0 = mm0[1],mm1[1] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    punpckhdq (%rdi), %mm0 # mm0 = mm0[1],mem[1] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    punpckhdq (%rdi), %mm0 # mm0 = mm0[1],mem[1] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckhdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6615,9 +6615,9 @@ define i64 @test_punpckhwd(x86_mmx %a0,<br class="">

; BROADWELL-LABEL: test_punpckhwd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    punpckhwd %mm1, %mm0 # mm0 = mm0[2],mm1[2],mm0[3],mm1[3] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    punpckhwd (%rdi), %mm0 # mm0 = mm0[2],mem[2],mm0[3],mem[3] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    punpckhwd (%rdi), %mm0 # mm0 = mm0[2],mem[2],mm0[3],mem[3] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckhwd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6693,9 +6693,9 @@ define i64 @test_punpcklbw(x86_mmx %a0,<br class="">

; BROADWELL-LABEL: test_punpcklbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    punpcklbw %mm1, %mm0 # mm0 = mm0[0],mm1[0],mm0[1],mm1[1],mm0[2],mm1[2],mm0[3],mm1[3] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    punpcklbw (%rdi), %mm0 # mm0 = mm0[0],mem[0],mm0[1],mem[1],mm0[2],mem[2],mm0[3],mem[3] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    punpcklbw (%rdi), %mm0 # mm0 = mm0[0],mem[0],mm0[1],mem[1],mm0[2],mem[2],mm0[3],mem[3] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpcklbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6771,9 +6771,9 @@ define i64 @test_punpckldq(x86_mmx %a0,<br class="">

; BROADWELL-LABEL: test_punpckldq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    punpckldq %mm1, %mm0 # mm0 = mm0[0],mm1[0] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    punpckldq (%rdi), %mm0 # mm0 = mm0[0],mem[0] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    punpckldq (%rdi), %mm0 # mm0 = mm0[0],mem[0] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckldq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6849,9 +6849,9 @@ define i64 @test_punpcklwd(x86_mmx %a0,<br class="">

; BROADWELL-LABEL: test_punpcklwd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    punpcklwd %mm1, %mm0 # mm0 = mm0[0],mm1[0],mm0[1],mm1[1] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    punpcklwd (%rdi), %mm0 # mm0 = mm0[0],mem[0],mm0[1],mem[1] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    punpcklwd (%rdi), %mm0 # mm0 = mm0[0],mem[0],mm0[1],mem[1] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpcklwd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6927,9 +6927,9 @@ define i64 @test_pxor(x86_mmx %a0, x86_m<br class="">

; BROADWELL-LABEL: test_pxor:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    pxor %mm1, %mm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    pxor (%rdi), %mm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    pxor (%rdi), %mm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    movd %mm0, %rax # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pxor:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/movbe-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movbe-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movbe-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/movbe-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/movbe-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -40,9 +40,9 @@ define i16 @test_movbe_i16(i16 *%a0, i16<br class="">

;<br class="">

; BROADWELL-LABEL: test_movbe_i16:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    movbew (%rdi), %ax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    movbew %si, (%rdx) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    movbew (%rdi), %ax # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    movbew %si, (%rdx) # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movbe_i16:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -100,9 +100,9 @@ define i32 @test_movbe_i32(i32 *%a0, i32<br class="">

;<br class="">

; BROADWELL-LABEL: test_movbe_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    movbel (%rdi), %eax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    movbel %esi, (%rdx) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    movbel (%rdi), %eax # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    movbel %esi, (%rdx) # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movbe_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -160,9 +160,9 @@ define i64 @test_movbe_i64(i64 *%a0, i64<br class="">

;<br class="">

; BROADWELL-LABEL: test_movbe_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    movbeq (%rdi), %rax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    movbeq %rsi, (%rdx) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    movbeq (%rdi), %rax # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    movbeq %rsi, (%rdx) # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movbe_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -46,11 +46,11 @@ define i16 @test_ctpop_i16(i16 zeroext %<br class="">

;<br class="">

; BROADWELL-LABEL: test_ctpop_i16:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    popcntw (%rsi), %cx # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    popcntw (%rsi), %cx # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    popcntw %di, %ax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    orl %ecx, %eax # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill><br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_ctpop_i16:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -114,10 +114,10 @@ define i32 @test_ctpop_i32(i32 %a0, i32<br class="">

;<br class="">

; BROADWELL-LABEL: test_ctpop_i32:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    popcntl (%rsi), %ecx # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    popcntl (%rsi), %ecx # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    popcntl %edi, %eax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    orl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_ctpop_i32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -178,10 +178,10 @@ define i64 @test_ctpop_i64(i64 %a0, i64<br class="">

;<br class="">

; BROADWELL-LABEL: test_ctpop_i64:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    popcntq (%rsi), %rcx # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    popcntq (%rsi), %rcx # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    popcntq %rdi, %rax # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    orq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_ctpop_i64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/sse-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/sse-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/sse-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -45,8 +45,8 @@ define <4 x float> @test_addps(<4 x floa<br class="">

; BROADWELL-LABEL: test_addps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vaddps (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaddps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_addps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -111,8 +111,8 @@ define float @test_addss(float %a0, floa<br class="">

; BROADWELL-LABEL: test_addss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vaddss (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaddss (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_addss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -181,8 +181,8 @@ define <4 x float> @test_andps(<4 x floa<br class="">

; BROADWELL-LABEL: test_andps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vandps %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vandps (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vandps (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_andps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -255,8 +255,8 @@ define <4 x float> @test_andnotps(<4 x f<br class="">

; BROADWELL-LABEL: test_andnotps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vandnps %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vandnps (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vandnps (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_andnotps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -332,9 +332,9 @@ define <4 x float> @test_cmpps(<4 x floa<br class="">

; BROADWELL-LABEL: test_cmpps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcmpeqps %xmm1, %xmm0, %xmm1 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vcmpeqps (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vcmpeqps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vorps %xmm0, %xmm1, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cmpps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -407,8 +407,8 @@ define float @test_cmpss(float %a0, floa<br class="">

; BROADWELL-LABEL: test_cmpss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcmpeqss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vcmpeqss (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vcmpeqss (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cmpss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -521,13 +521,13 @@ define i32 @test_comiss(<4 x float> %a0,<br class="">

; BROADWELL-NEXT:    setnp %al # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    sete %cl # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    andb %al, %cl # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    vcomiss (%rdi), %xmm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    vcomiss (%rdi), %xmm0 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    setnp %al # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    sete %dl # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    andb %al, %dl # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    orb %cl, %dl # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    movzbl %dl, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_comiss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -631,9 +631,9 @@ define float @test_cvtsi2ss(i32 %a0, i32<br class="">

; BROADWELL-LABEL: test_cvtsi2ss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtsi2ss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -708,9 +708,9 @@ define float @test_cvtsi2ssq(i64 %a0, i6<br class="">

; BROADWELL-LABEL: test_cvtsi2ssq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtsi2ssq %rdi, %xmm0, %xmm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtsi2ssq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -785,9 +785,9 @@ define i32 @test_cvtss2si(float %a0, flo<br class="">

; BROADWELL-LABEL: test_cvtss2si:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtss2si %xmm0, %ecx # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtss2si (%rdi), %eax # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtss2si (%rdi), %eax # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtss2si:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -865,9 +865,9 @@ define i64 @test_cvtss2siq(float %a0, fl<br class="">

; BROADWELL-LABEL: test_cvtss2siq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtss2si %xmm0, %rcx # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtss2si (%rdi), %rax # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtss2si (%rdi), %rax # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtss2siq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -945,9 +945,9 @@ define i32 @test_cvttss2si(float %a0, fl<br class="">

; BROADWELL-LABEL: test_cvttss2si:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvttss2si %xmm0, %ecx # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvttss2si (%rdi), %eax # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vcvttss2si (%rdi), %eax # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvttss2si:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1022,9 +1022,9 @@ define i64 @test_cvttss2siq(float %a0, f<br class="">

; BROADWELL-LABEL: test_cvttss2siq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvttss2si %xmm0, %rcx # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvttss2si (%rdi), %rax # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vcvttss2si (%rdi), %rax # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvttss2siq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1093,9 +1093,9 @@ define <4 x float> @test_divps(<4 x floa<br class="">

;<br class="">

; BROADWELL-LABEL: test_divps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vdivps %xmm1, %xmm0, %xmm0 # sched: [13:1.00]<br class="">

-; BROADWELL-NEXT:    vdivps (%rdi), %xmm0, %xmm0 # sched: [13:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vdivps %xmm1, %xmm0, %xmm0 # sched: [11:1.00]<br class="">

+; BROADWELL-NEXT:    vdivps (%rdi), %xmm0, %xmm0 # sched: [16:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_divps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1159,9 +1159,9 @@ define float @test_divss(float %a0, floa<br class="">

;<br class="">

; BROADWELL-LABEL: test_divss:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vdivss %xmm1, %xmm0, %xmm0 # sched: [13:1.00]<br class="">

-; BROADWELL-NEXT:    vdivss (%rdi), %xmm0, %xmm0 # sched: [13:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vdivss %xmm1, %xmm0, %xmm0 # sched: [11:1.00]<br class="">

+; BROADWELL-NEXT:    vdivss (%rdi), %xmm0, %xmm0 # sched: [16:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_divss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1226,8 +1226,8 @@ define void @test_ldmxcsr(i32 %a0) {<br class="">

; BROADWELL-LABEL: test_ldmxcsr:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    movl %edi, -{{[0-9]+}}(%rsp) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vldmxcsr -{{[0-9]+}}(%rsp) # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vldmxcsr -{{[0-9]+}}(%rsp) # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_ldmxcsr:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1294,8 +1294,8 @@ define <4 x float> @test_maxps(<4 x floa<br class="">

; BROADWELL-LABEL: test_maxps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmaxps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vmaxps (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmaxps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_maxps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1361,8 +1361,8 @@ define <4 x float> @test_maxss(<4 x floa<br class="">

; BROADWELL-LABEL: test_maxss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmaxss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vmaxss (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmaxss (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_maxss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1428,8 +1428,8 @@ define <4 x float> @test_minps(<4 x floa<br class="">

; BROADWELL-LABEL: test_minps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vminps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vminps (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vminps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_minps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1495,8 +1495,8 @@ define <4 x float> @test_minss(<4 x floa<br class="">

; BROADWELL-LABEL: test_minss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vminss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vminss (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vminss (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_minss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1566,10 +1566,10 @@ define void @test_movaps(<4 x float> *%a<br class="">

;<br class="">

; BROADWELL-LABEL: test_movaps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovaps (%rdi), %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovaps (%rdi), %xmm0 # sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vaddps %xmm0, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovaps %xmm0, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movaps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1641,7 +1641,7 @@ define <4 x float> @test_movhlps(<4 x fl<br class="">

; BROADWELL-LABEL: test_movhlps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movhlps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1708,10 +1708,10 @@ define void @test_movhps(<4 x float> %a0<br class="">

;<br class="">

; BROADWELL-LABEL: test_movhps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vpextrq $1, %xmm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpextrq $1, %xmm0, (%rdi) # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movhps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1787,7 +1787,7 @@ define <4 x float> @test_movlhps(<4 x fl<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movlhps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1855,10 +1855,10 @@ define void @test_movlps(<4 x float> %a0<br class="">

;<br class="">

; BROADWELL-LABEL: test_movlps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovlps %xmm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movlps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1928,7 +1928,7 @@ define i32 @test_movmskps(<4 x float> %a<br class="">

; BROADWELL-LABEL: test_movmskps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovmskps %xmm0, %eax # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movmskps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1989,7 +1989,7 @@ define void @test_movntps(<4 x float> %a<br class="">

; BROADWELL-LABEL: test_movntps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovntps %xmm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movntps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2052,10 +2052,10 @@ define void @test_movss_mem(float* %a0,<br class="">

;<br class="">

; BROADWELL-LABEL: test_movss_mem:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vaddss %xmm0, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovss %xmm0, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movss_mem:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2125,7 +2125,7 @@ define <4 x float> @test_movss_reg(<4 x<br class="">

; BROADWELL-LABEL: test_movss_reg:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movss_reg:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2188,10 +2188,10 @@ define void @test_movups(<4 x float> *%a<br class="">

;<br class="">

; BROADWELL-LABEL: test_movups:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovups (%rdi), %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovups (%rdi), %xmm0 # sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vaddps %xmm0, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovups %xmm0, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movups:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2259,9 +2259,9 @@ define <4 x float> @test_mulps(<4 x floa<br class="">

;<br class="">

; BROADWELL-LABEL: test_mulps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmulps %xmm1, %xmm0, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vmulps (%rdi), %xmm0, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmulps %xmm1, %xmm0, %xmm0 # sched: [3:0.50]<br class="">

+; BROADWELL-NEXT:    vmulps (%rdi), %xmm0, %xmm0 # sched: [8:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_mulps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2325,9 +2325,9 @@ define float @test_mulss(float %a0, floa<br class="">

;<br class="">

; BROADWELL-LABEL: test_mulss:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmulss %xmm1, %xmm0, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vmulss (%rdi), %xmm0, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmulss %xmm1, %xmm0, %xmm0 # sched: [3:0.50]<br class="">

+; BROADWELL-NEXT:    vmulss (%rdi), %xmm0, %xmm0 # sched: [8:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_mulss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2396,8 +2396,8 @@ define <4 x float> @test_orps(<4 x float<br class="">

; BROADWELL-LABEL: test_orps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vorps %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vorps (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vorps (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_orps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2466,8 +2466,8 @@ define void @test_prefetchnta(i8* %a0) {<br class="">

;<br class="">

; BROADWELL-LABEL: test_prefetchnta:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    prefetchnta (%rdi) # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    prefetchnta (%rdi) # sched: [5:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_prefetchnta:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2534,9 +2534,9 @@ define <4 x float> @test_rcpps(<4 x floa<br class="">

; BROADWELL-LABEL: test_rcpps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vrcpps %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vrcpps (%rdi), %xmm1 # sched: [5:1.00]<br class="">

+; BROADWELL-NEXT:    vrcpps (%rdi), %xmm1 # sched: [10:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_rcpps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2619,10 +2619,10 @@ define <4 x float> @test_rcpss(float %a0<br class="">

; BROADWELL-LABEL: test_rcpss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vrcpss %xmm0, %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vrcpss %xmm1, %xmm1, %xmm1 # sched: [5:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_rcpss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2706,9 +2706,9 @@ define <4 x float> @test_rsqrtps(<4 x fl<br class="">

; BROADWELL-LABEL: test_rsqrtps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vrsqrtps %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vrsqrtps (%rdi), %xmm1 # sched: [5:1.00]<br class="">

+; BROADWELL-NEXT:    vrsqrtps (%rdi), %xmm1 # sched: [10:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_rsqrtps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2791,10 +2791,10 @@ define <4 x float> @test_rsqrtss(float %<br class="">

; BROADWELL-LABEL: test_rsqrtss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vrsqrtss %xmm1, %xmm1, %xmm1 # sched: [5:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_rsqrtss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2871,8 +2871,8 @@ define void @test_sfence() {<br class="">

;<br class="">

; BROADWELL-LABEL: test_sfence:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    sfence # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    sfence # sched: [2:0.33]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_sfence:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2936,8 +2936,8 @@ define <4 x float> @test_shufps(<4 x flo<br class="">

; BROADWELL-LABEL: test_shufps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,3],mem[0,0] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,3],mem[0,0] sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_shufps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3008,9 +3008,9 @@ define <4 x float> @test_sqrtps(<4 x flo<br class="">

; BROADWELL-LABEL: test_sqrtps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vsqrtps %xmm0, %xmm0 # sched: [14:1.00]<br class="">

-; BROADWELL-NEXT:    vsqrtps (%rdi), %xmm1 # sched: [14:1.00]<br class="">

+; BROADWELL-NEXT:    vsqrtps (%rdi), %xmm1 # sched: [19:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_sqrtps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3093,10 +3093,10 @@ define <4 x float> @test_sqrtss(<4 x flo<br class="">

; BROADWELL-LABEL: test_sqrtss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0 # sched: [14:1.00]<br class="">

-; BROADWELL-NEXT:    vmovaps (%rdi), %xmm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovaps (%rdi), %xmm1 # sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vsqrtss %xmm1, %xmm1, %xmm1 # sched: [14:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_sqrtss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3170,9 +3170,9 @@ define i32 @test_stmxcsr() {<br class="">

;<br class="">

; BROADWELL-LABEL: test_stmxcsr:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vstmxcsr -{{[0-9]+}}(%rsp) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    movl -{{[0-9]+}}(%rsp), %eax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vstmxcsr -{{[0-9]+}}(%rsp) # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    movl -{{[0-9]+}}(%rsp), %eax # sched: [5:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_stmxcsr:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3239,8 +3239,8 @@ define <4 x float> @test_subps(<4 x floa<br class="">

; BROADWELL-LABEL: test_subps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vsubps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vsubps (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vsubps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_subps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3305,8 +3305,8 @@ define float @test_subss(float %a0, floa<br class="">

; BROADWELL-LABEL: test_subss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vsubss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vsubss (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vsubss (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_subss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3414,13 +3414,13 @@ define i32 @test_ucomiss(<4 x float> %a0<br class="">

; BROADWELL-NEXT:    setnp %al # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    sete %cl # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    andb %al, %cl # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    vucomiss (%rdi), %xmm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    vucomiss (%rdi), %xmm0 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    setnp %al # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    sete %dl # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    andb %al, %dl # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    orb %cl, %dl # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    movzbl %dl, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_ucomiss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3523,8 +3523,8 @@ define <4 x float> @test_unpckhps(<4 x f<br class="">

; BROADWELL-LABEL: test_unpckhps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vunpckhps {{.*#+}} xmm0 = xmm0[2],mem[2],xmm0[3],mem[3] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vunpckhps {{.*#+}} xmm0 = xmm0[2],mem[2],xmm0[3],mem[3] sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_unpckhps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3593,8 +3593,8 @@ define <4 x float> @test_unpcklps(<4 x f<br class="">

; BROADWELL-LABEL: test_unpcklps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_unpcklps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3663,8 +3663,8 @@ define <4 x float> @test_xorps(<4 x floa<br class="">

; BROADWELL-LABEL: test_xorps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vxorps %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vxorps (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vxorps (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_xorps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/sse2-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/sse2-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/sse2-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -45,8 +45,8 @@ define <2 x double> @test_addpd(<2 x dou<br class="">

; BROADWELL-LABEL: test_addpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vaddpd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaddpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_addpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -111,8 +111,8 @@ define double @test_addsd(double %a0, do<br class="">

; BROADWELL-LABEL: test_addsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vaddsd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaddsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_addsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -182,9 +182,9 @@ define <2 x double> @test_andpd(<2 x dou<br class="">

; BROADWELL-LABEL: test_andpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vandpd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vandpd (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vandpd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_andpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -263,9 +263,9 @@ define <2 x double> @test_andnotpd(<2 x<br class="">

; BROADWELL-LABEL: test_andnotpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vandnpd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vandnpd (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vandnpd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_andnotpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -346,9 +346,9 @@ define <2 x double> @test_cmppd(<2 x dou<br class="">

; BROADWELL-LABEL: test_cmppd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcmpeqpd %xmm1, %xmm0, %xmm1 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vcmpeqpd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vcmpeqpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vorpd %xmm0, %xmm1, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cmppd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -421,8 +421,8 @@ define double @test_cmpsd(double %a0, do<br class="">

; BROADWELL-LABEL: test_cmpsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cmpsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -535,13 +535,13 @@ define i32 @test_comisd(<2 x double> %a0<br class="">

; BROADWELL-NEXT:    setnp %al # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    sete %cl # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    andb %al, %cl # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    vcomisd (%rdi), %xmm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    vcomisd (%rdi), %xmm0 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    setnp %al # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    sete %dl # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    andb %al, %dl # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    orb %cl, %dl # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    movzbl %dl, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_comisd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -645,9 +645,9 @@ define <2 x double> @test_cvtdq2pd(<4 x<br class="">

; BROADWELL-LABEL: test_cvtdq2pd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtdq2pd %xmm0, %xmm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtdq2pd (%rdi), %xmm1 # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtdq2pd (%rdi), %xmm1 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtdq2pd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -725,9 +725,9 @@ define <4 x float> @test_cvtdq2ps(<4 x i<br class="">

; BROADWELL-LABEL: test_cvtdq2ps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtdq2ps %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtdq2ps (%rdi), %xmm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtdq2ps (%rdi), %xmm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtdq2ps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -803,9 +803,9 @@ define <4 x i32> @test_cvtpd2dq(<2 x dou<br class="">

; BROADWELL-LABEL: test_cvtpd2dq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtpd2dq %xmm0, %xmm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtpd2dqx (%rdi), %xmm1 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtpd2dqx (%rdi), %xmm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtpd2dq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -882,9 +882,9 @@ define <4 x float> @test_cvtpd2ps(<2 x d<br class="">

; BROADWELL-LABEL: test_cvtpd2ps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtpd2ps %xmm0, %xmm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtpd2psx (%rdi), %xmm1 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtpd2psx (%rdi), %xmm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtpd2ps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -961,9 +961,9 @@ define <4 x i32> @test_cvtps2dq(<4 x flo<br class="">

; BROADWELL-LABEL: test_cvtps2dq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtps2dq %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtps2dq (%rdi), %xmm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtps2dq (%rdi), %xmm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtps2dq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1040,9 +1040,9 @@ define <2 x double> @test_cvtps2pd(<4 x<br class="">

; BROADWELL-LABEL: test_cvtps2pd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtps2pd %xmm0, %xmm0 # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtps2pd (%rdi), %xmm1 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtps2pd (%rdi), %xmm1 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtps2pd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1119,9 +1119,9 @@ define i32 @test_cvtsd2si(double %a0, do<br class="">

; BROADWELL-LABEL: test_cvtsd2si:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtsd2si %xmm0, %ecx # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtsd2si (%rdi), %eax # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtsd2si (%rdi), %eax # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtsd2si:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1199,9 +1199,9 @@ define i64 @test_cvtsd2siq(double %a0, d<br class="">

; BROADWELL-LABEL: test_cvtsd2siq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtsd2si %xmm0, %rcx # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtsd2si (%rdi), %rax # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtsd2si (%rdi), %rax # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtsd2siq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1285,10 +1285,10 @@ define float @test_cvtsd2ss(double %a0,<br class="">

; BROADWELL-LABEL: test_cvtsd2ss:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtsd2ss %xmm0, %xmm0, %xmm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vcvtsd2ss %xmm1, %xmm1, %xmm1 # sched: [4:1.00]<br class="">

; BROADWELL-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtsd2ss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1367,9 +1367,9 @@ define double @test_cvtsi2sd(i32 %a0, i3<br class="">

; BROADWELL-LABEL: test_cvtsi2sd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtsi2sd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1444,9 +1444,9 @@ define double @test_cvtsi2sdq(i64 %a0, i<br class="">

; BROADWELL-LABEL: test_cvtsi2sdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtsi2sdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1529,10 +1529,10 @@ define double @test_cvtss2sd(float %a0,<br class="">

; BROADWELL-LABEL: test_cvtss2sd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvtss2sd %xmm0, %xmm0, %xmm0 # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vcvtss2sd %xmm1, %xmm1, %xmm1 # sched: [2:1.00]<br class="">

; BROADWELL-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvtss2sd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1612,9 +1612,9 @@ define <4 x i32> @test_cvttpd2dq(<2 x do<br class="">

; BROADWELL-LABEL: test_cvttpd2dq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvttpd2dq %xmm0, %xmm0 # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvttpd2dqx (%rdi), %xmm1 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    vcvttpd2dqx (%rdi), %xmm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvttpd2dq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1692,9 +1692,9 @@ define <4 x i32> @test_cvttps2dq(<4 x fl<br class="">

; BROADWELL-LABEL: test_cvttps2dq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvttps2dq %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vcvttps2dq (%rdi), %xmm1 # sched: [3:1.00]<br class="">

+; BROADWELL-NEXT:    vcvttps2dq (%rdi), %xmm1 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvttps2dq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1769,9 +1769,9 @@ define i32 @test_cvttsd2si(double %a0, d<br class="">

; BROADWELL-LABEL: test_cvttsd2si:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvttsd2si %xmm0, %ecx # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvttsd2si (%rdi), %eax # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vcvttsd2si (%rdi), %eax # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvttsd2si:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1846,9 +1846,9 @@ define i64 @test_cvttsd2siq(double %a0,<br class="">

; BROADWELL-LABEL: test_cvttsd2siq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vcvttsd2si %xmm0, %rcx # sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    vcvttsd2si (%rdi), %rax # sched: [4:1.00]<br class="">

+; BROADWELL-NEXT:    vcvttsd2si (%rdi), %rax # sched: [9:1.00]<br class="">

; BROADWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_cvttsd2siq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1917,9 +1917,9 @@ define <2 x double> @test_divpd(<2 x dou<br class="">

;<br class="">

; BROADWELL-LABEL: test_divpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vdivpd %xmm1, %xmm0, %xmm0 # sched: [20:1.00]<br class="">

-; BROADWELL-NEXT:    vdivpd (%rdi), %xmm0, %xmm0 # sched: [20:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vdivpd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]<br class="">

+; BROADWELL-NEXT:    vdivpd (%rdi), %xmm0, %xmm0 # sched: [19:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_divpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1983,9 +1983,9 @@ define double @test_divsd(double %a0, do<br class="">

;<br class="">

; BROADWELL-LABEL: test_divsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vdivsd %xmm1, %xmm0, %xmm0 # sched: [20:1.00]<br class="">

-; BROADWELL-NEXT:    vdivsd (%rdi), %xmm0, %xmm0 # sched: [20:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vdivsd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]<br class="">

+; BROADWELL-NEXT:    vdivsd (%rdi), %xmm0, %xmm0 # sched: [19:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_divsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2051,7 +2051,7 @@ define void @test_lfence() {<br class="">

; BROADWELL-LABEL: test_lfence:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    lfence # sched: [2:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lfence:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2112,7 +2112,7 @@ define void @test_mfence() {<br class="">

; BROADWELL-LABEL: test_mfence:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    mfence # sched: [2:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_mfence:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2171,7 +2171,7 @@ define void @test_maskmovdqu(<16 x i8> %<br class="">

; BROADWELL-LABEL: test_maskmovdqu:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmaskmovdqu %xmm1, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_maskmovdqu:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2231,8 +2231,8 @@ define <2 x double> @test_maxpd(<2 x dou<br class="">

; BROADWELL-LABEL: test_maxpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmaxpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vmaxpd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmaxpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_maxpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2298,8 +2298,8 @@ define <2 x double> @test_maxsd(<2 x dou<br class="">

; BROADWELL-LABEL: test_maxsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmaxsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vmaxsd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmaxsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_maxsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2365,8 +2365,8 @@ define <2 x double> @test_minpd(<2 x dou<br class="">

; BROADWELL-LABEL: test_minpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vminpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vminpd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vminpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_minpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2432,8 +2432,8 @@ define <2 x double> @test_minsd(<2 x dou<br class="">

; BROADWELL-LABEL: test_minsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vminsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vminsd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vminsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_minsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2503,10 +2503,10 @@ define void @test_movapd(<2 x double> *%<br class="">

;<br class="">

; BROADWELL-LABEL: test_movapd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovapd (%rdi), %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovapd (%rdi), %xmm0 # sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovapd %xmm0, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movapd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2579,10 +2579,10 @@ define void @test_movdqa(<2 x i64> *%a0,<br class="">

;<br class="">

; BROADWELL-LABEL: test_movdqa:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovdqa (%rdi), %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovdqa (%rdi), %xmm0 # sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    vmovdqa %xmm0, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movdqa:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2655,10 +2655,10 @@ define void @test_movdqu(<2 x i64> *%a0,<br class="">

;<br class="">

; BROADWELL-LABEL: test_movdqu:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovdqu (%rdi), %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovdqu (%rdi), %xmm0 # sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    vmovdqu %xmm0, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movdqu:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2747,12 +2747,12 @@ define i32 @test_movd(<4 x i32> %a0, i32<br class="">

; BROADWELL-LABEL: test_movd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovd %edi, %xmm1 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm2, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    vmovd %xmm0, %eax # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    vmovd %xmm1, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2858,12 +2858,12 @@ define i64 @test_movd_64(<2 x i64> %a0,<br class="">

; BROADWELL-LABEL: test_movd_64:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovq %rdi, %xmm1 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vmovq {{.*#+}} xmm2 = mem[0],zero sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovq {{.*#+}} xmm2 = mem[0],zero sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm2, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    vmovq %xmm0, %rax # sched: [1:1.00]<br class="">

; BROADWELL-NEXT:    vmovq %xmm1, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movd_64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2953,10 +2953,10 @@ define void @test_movhpd(<2 x double> %a<br class="">

;<br class="">

; BROADWELL-LABEL: test_movhpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovhpd %xmm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movhpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3032,10 +3032,10 @@ define void @test_movlpd(<2 x double> %a<br class="">

;<br class="">

; BROADWELL-LABEL: test_movlpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovlpd %xmm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movlpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3104,7 +3104,7 @@ define i32 @test_movmskpd(<2 x double> %<br class="">

; BROADWELL-LABEL: test_movmskpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovmskpd %xmm0, %eax # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movmskpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3167,7 +3167,7 @@ define void @test_movntdqa(<2 x i64> %a0<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    vmovntdq %xmm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movntdqa:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3232,7 +3232,7 @@ define void @test_movntpd(<2 x double> %<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovntpd %xmm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movntpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3300,10 +3300,10 @@ define <2 x i64> @test_movq_mem(<2 x i64<br class="">

;<br class="">

; BROADWELL-LABEL: test_movq_mem:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    vmovq %xmm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movq_mem:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3377,7 +3377,7 @@ define <2 x i64> @test_movq_reg(<2 x i64<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero sched: [1:0.33]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm0, %xmm1, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movq_reg:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3445,10 +3445,10 @@ define void @test_movsd_mem(double* %a0,<br class="">

;<br class="">

; BROADWELL-LABEL: test_movsd_mem:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vaddsd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovsd %xmm0, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movsd_mem:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3519,7 +3519,7 @@ define <2 x double> @test_movsd_reg(<2 x<br class="">

; BROADWELL-LABEL: test_movsd_reg:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movsd_reg:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3582,10 +3582,10 @@ define void @test_movupd(<2 x double> *%<br class="">

;<br class="">

; BROADWELL-LABEL: test_movupd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovupd (%rdi), %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovupd (%rdi), %xmm0 # sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

; BROADWELL-NEXT:    vmovupd %xmm0, (%rsi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movupd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3653,9 +3653,9 @@ define <2 x double> @test_mulpd(<2 x dou<br class="">

;<br class="">

; BROADWELL-LABEL: test_mulpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmulpd %xmm1, %xmm0, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vmulpd (%rdi), %xmm0, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmulpd %xmm1, %xmm0, %xmm0 # sched: [3:0.50]<br class="">

+; BROADWELL-NEXT:    vmulpd (%rdi), %xmm0, %xmm0 # sched: [8:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_mulpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3719,9 +3719,9 @@ define double @test_mulsd(double %a0, do<br class="">

;<br class="">

; BROADWELL-LABEL: test_mulsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmulsd %xmm1, %xmm0, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    vmulsd (%rdi), %xmm0, %xmm0 # sched: [5:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmulsd %xmm1, %xmm0, %xmm0 # sched: [3:0.50]<br class="">

+; BROADWELL-NEXT:    vmulsd (%rdi), %xmm0, %xmm0 # sched: [8:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_mulsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3791,9 +3791,9 @@ define <2 x double> @test_orpd(<2 x doub<br class="">

; BROADWELL-LABEL: test_orpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vorpd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vorpd (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vorpd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_orpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3871,8 +3871,8 @@ define <8 x i16> @test_packssdw(<4 x i32<br class="">

; BROADWELL-LABEL: test_packssdw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpackssdw (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpackssdw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_packssdw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3943,8 +3943,8 @@ define <16 x i8> @test_packsswb(<8 x i16<br class="">

; BROADWELL-LABEL: test_packsswb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpacksswb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpacksswb (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpacksswb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_packsswb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4015,8 +4015,8 @@ define <16 x i8> @test_packuswb(<8 x i16<br class="">

; BROADWELL-LABEL: test_packuswb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpackuswb (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpackuswb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_packuswb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4087,8 +4087,8 @@ define <16 x i8> @test_paddb(<16 x i8> %<br class="">

; BROADWELL-LABEL: test_paddb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddb (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4157,8 +4157,8 @@ define <4 x i32> @test_paddd(<4 x i32> %<br class="">

; BROADWELL-LABEL: test_paddd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddd (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4223,8 +4223,8 @@ define <2 x i64> @test_paddq(<2 x i64> %<br class="">

; BROADWELL-LABEL: test_paddq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddq (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4293,8 +4293,8 @@ define <16 x i8> @test_paddsb(<16 x i8><br class="">

; BROADWELL-LABEL: test_paddsb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddsb (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddsb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4364,8 +4364,8 @@ define <8 x i16> @test_paddsw(<8 x i16><br class="">

; BROADWELL-LABEL: test_paddsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddsw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4435,8 +4435,8 @@ define <16 x i8> @test_paddusb(<16 x i8><br class="">

; BROADWELL-LABEL: test_paddusb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddusb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddusb (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddusb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4506,8 +4506,8 @@ define <8 x i16> @test_paddusw(<8 x i16><br class="">

; BROADWELL-LABEL: test_paddusw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddusw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddusw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddusw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4577,8 +4577,8 @@ define <8 x i16> @test_paddw(<8 x i16> %<br class="">

; BROADWELL-LABEL: test_paddw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpaddw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpaddw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_paddw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4648,9 +4648,9 @@ define <2 x i64> @test_pand(<2 x i64> %a<br class="">

; BROADWELL-LABEL: test_pand:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpand %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    vpand (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpand (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pand:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4731,9 +4731,9 @@ define <2 x i64> @test_pandn(<2 x i64> %<br class="">

; BROADWELL-LABEL: test_pandn:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpandn %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    vpandn (%rdi), %xmm0, %xmm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpandn (%rdi), %xmm0, %xmm1 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pandn:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4809,8 +4809,8 @@ define <16 x i8> @test_pavgb(<16 x i8> %<br class="">

; BROADWELL-LABEL: test_pavgb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpavgb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpavgb (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pavgb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4889,8 +4889,8 @@ define <8 x i16> @test_pavgw(<8 x i16> %<br class="">

; BROADWELL-LABEL: test_pavgw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpavgw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpavgw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpavgw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pavgw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -4972,9 +4972,9 @@ define <16 x i8> @test_pcmpeqb(<16 x i8><br class="">

; BROADWELL-LABEL: test_pcmpeqb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpeqb %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpeqb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpcmpeqb (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpeqb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5053,9 +5053,9 @@ define <4 x i32> @test_pcmpeqd(<4 x i32><br class="">

; BROADWELL-LABEL: test_pcmpeqd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpeqd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpeqd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5134,9 +5134,9 @@ define <8 x i16> @test_pcmpeqw(<8 x i16><br class="">

; BROADWELL-LABEL: test_pcmpeqw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpeqw %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpeqw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpcmpeqw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpeqw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5216,9 +5216,9 @@ define <16 x i8> @test_pcmpgtb(<16 x i8><br class="">

; BROADWELL-LABEL: test_pcmpgtb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpgtb %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpgtb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpcmpgtb (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpgtb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5298,9 +5298,9 @@ define <4 x i32> @test_pcmpgtd(<4 x i32><br class="">

; BROADWELL-LABEL: test_pcmpgtd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpgtd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpgtd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5380,9 +5380,9 @@ define <8 x i16> @test_pcmpgtw(<8 x i16><br class="">

; BROADWELL-LABEL: test_pcmpgtw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpgtw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5455,7 +5455,7 @@ define i16 @test_pextrw(<8 x i16> %a0) {<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpextrw $6, %xmm0, %eax # sched: [2:1.00]<br class="">

; BROADWELL-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill><br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pextrw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5522,8 +5522,8 @@ define <8 x i16> @test_pinsrw(<8 x i16><br class="">

; BROADWELL-LABEL: test_pinsrw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pinsrw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5596,8 +5596,8 @@ define <4 x i32> @test_pmaddwd(<8 x i16><br class="">

; BROADWELL-LABEL: test_pmaddwd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaddwd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5668,8 +5668,8 @@ define <8 x i16> @test_pmaxsw(<8 x i16><br class="">

; BROADWELL-LABEL: test_pmaxsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5739,8 +5739,8 @@ define <16 x i8> @test_pmaxub(<16 x i8><br class="">

; BROADWELL-LABEL: test_pmaxub:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpmaxub (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaxub (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxub:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5810,8 +5810,8 @@ define <8 x i16> @test_pminsw(<8 x i16><br class="">

; BROADWELL-LABEL: test_pminsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpminsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpminsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpminsw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5881,8 +5881,8 @@ define <16 x i8> @test_pminub(<16 x i8><br class="">

; BROADWELL-LABEL: test_pminub:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpminub %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpminub (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpminub (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminub:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -5945,7 +5945,7 @@ define i32 @test_pmovmskb(<16 x i8> %a0)<br class="">

; BROADWELL-LABEL: test_pmovmskb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovmskb %xmm0, %eax # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovmskb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6005,8 +6005,8 @@ define <8 x i16> @test_pmulhuw(<8 x i16><br class="">

; BROADWELL-LABEL: test_pmulhuw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmulhuw %xmm1, %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmulhuw (%rdi), %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmulhuw (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmulhuw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6072,8 +6072,8 @@ define <8 x i16> @test_pmulhw(<8 x i16><br class="">

; BROADWELL-LABEL: test_pmulhw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmulhw %xmm1, %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmulhw (%rdi), %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmulhw (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmulhw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6139,8 +6139,8 @@ define <8 x i16> @test_pmullw(<8 x i16><br class="">

; BROADWELL-LABEL: test_pmullw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmullw %xmm1, %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmullw (%rdi), %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmullw (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmullw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6213,8 +6213,8 @@ define <2 x i64> @test_pmuludq(<4 x i32><br class="">

; BROADWELL-LABEL: test_pmuludq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmuludq %xmm1, %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmuludq (%rdi), %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmuludq (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmuludq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6286,9 +6286,9 @@ define <2 x i64> @test_por(<2 x i64> %a0<br class="">

; BROADWELL-LABEL: test_por:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    vpor (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpor (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_por:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6366,8 +6366,8 @@ define <2 x i64> @test_psadbw(<16 x i8><br class="">

; BROADWELL-LABEL: test_psadbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsadbw %xmm1, %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpsadbw (%rdi), %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsadbw (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psadbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6441,9 +6441,9 @@ define <4 x i32> @test_pshufd(<4 x i32><br class="">

; BROADWELL-LABEL: test_pshufd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpshufd {{.*#+}} xmm1 = mem[3,2,1,0] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpshufd {{.*#+}} xmm1 = mem[3,2,1,0] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pshufd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6520,9 +6520,9 @@ define <8 x i16> @test_pshufhw(<8 x i16><br class="">

; BROADWELL-LABEL: test_pshufhw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpshufhw {{.*#+}} xmm1 = mem[0,1,2,3,7,6,5,4] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpshufhw {{.*#+}} xmm1 = mem[0,1,2,3,7,6,5,4] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pshufhw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6599,9 +6599,9 @@ define <8 x i16> @test_pshuflw(<8 x i16><br class="">

; BROADWELL-LABEL: test_pshuflw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpshuflw {{.*#+}} xmm1 = mem[3,2,1,0,4,5,6,7] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpshuflw {{.*#+}} xmm1 = mem[3,2,1,0,4,5,6,7] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pshuflw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6676,9 +6676,9 @@ define <4 x i32> @test_pslld(<4 x i32> %<br class="">

; BROADWELL-LABEL: test_pslld:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpslld %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vpslld (%rdi), %xmm0, %xmm0 # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpslld (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpslld $2, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pslld:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6751,7 +6751,7 @@ define <4 x i32> @test_pslldq(<4 x i32><br class="">

; BROADWELL-LABEL: test_pslldq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pslldq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6815,9 +6815,9 @@ define <2 x i64> @test_psllq(<2 x i64> %<br class="">

; BROADWELL-LABEL: test_psllq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsllq %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vpsllq (%rdi), %xmm0, %xmm0 # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsllq (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsllq $2, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psllq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6894,9 +6894,9 @@ define <8 x i16> @test_psllw(<8 x i16> %<br class="">

; BROADWELL-LABEL: test_psllw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsllw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vpsllw (%rdi), %xmm0, %xmm0 # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsllw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsllw $2, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psllw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -6973,9 +6973,9 @@ define <4 x i32> @test_psrad(<4 x i32> %<br class="">

; BROADWELL-LABEL: test_psrad:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrad %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vpsrad (%rdi), %xmm0, %xmm0 # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsrad (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsrad $2, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrad:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7052,9 +7052,9 @@ define <8 x i16> @test_psraw(<8 x i16> %<br class="">

; BROADWELL-LABEL: test_psraw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsraw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vpsraw (%rdi), %xmm0, %xmm0 # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsraw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsraw $2, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psraw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7131,9 +7131,9 @@ define <4 x i32> @test_psrld(<4 x i32> %<br class="">

; BROADWELL-LABEL: test_psrld:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrld %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vpsrld (%rdi), %xmm0, %xmm0 # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsrld (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsrld $2, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrld:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7206,7 +7206,7 @@ define <4 x i32> @test_psrldq(<4 x i32><br class="">

; BROADWELL-LABEL: test_psrldq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrldq {{.*#+}} xmm0 = xmm0[4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrldq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7270,9 +7270,9 @@ define <2 x i64> @test_psrlq(<2 x i64> %<br class="">

; BROADWELL-LABEL: test_psrlq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrlq %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vpsrlq (%rdi), %xmm0, %xmm0 # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsrlq (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsrlq $2, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrlq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7349,9 +7349,9 @@ define <8 x i16> @test_psrlw(<8 x i16> %<br class="">

; BROADWELL-LABEL: test_psrlw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsrlw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vpsrlw (%rdi), %xmm0, %xmm0 # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsrlw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    vpsrlw $2, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psrlw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7427,8 +7427,8 @@ define <16 x i8> @test_psubb(<16 x i8> %<br class="">

; BROADWELL-LABEL: test_psubb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubb (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7497,8 +7497,8 @@ define <4 x i32> @test_psubd(<4 x i32> %<br class="">

; BROADWELL-LABEL: test_psubd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubd (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7563,8 +7563,8 @@ define <2 x i64> @test_psubq(<2 x i64> %<br class="">

; BROADWELL-LABEL: test_psubq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubq (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7633,8 +7633,8 @@ define <16 x i8> @test_psubsb(<16 x i8><br class="">

; BROADWELL-LABEL: test_psubsb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubsb (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubsb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7704,8 +7704,8 @@ define <8 x i16> @test_psubsw(<8 x i16><br class="">

; BROADWELL-LABEL: test_psubsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubsw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7775,8 +7775,8 @@ define <16 x i8> @test_psubusb(<16 x i8><br class="">

; BROADWELL-LABEL: test_psubusb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubusb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubusb (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubusb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7846,8 +7846,8 @@ define <8 x i16> @test_psubusw(<8 x i16><br class="">

; BROADWELL-LABEL: test_psubusw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubusw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubusw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubusw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7917,8 +7917,8 @@ define <8 x i16> @test_psubw(<8 x i16> %<br class="">

; BROADWELL-LABEL: test_psubw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsubw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsubw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsubw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psubw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -7987,8 +7987,8 @@ define <16 x i8> @test_punpckhbw(<16 x i<br class="">

; BROADWELL-LABEL: test_punpckhbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpckhbw {{.*#+}} xmm0 = xmm0[8],mem[8],xmm0[9],mem[9],xmm0[10],mem[10],xmm0[11],mem[11],xmm0[12],mem[12],xmm0[13],mem[13],xmm0[14],mem[14],xmm0[15],mem[15] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpckhbw {{.*#+}} xmm0 = xmm0[8],mem[8],xmm0[9],mem[9],xmm0[10],mem[10],xmm0[11],mem[11],xmm0[12],mem[12],xmm0[13],mem[13],xmm0[14],mem[14],xmm0[15],mem[15] sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckhbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -8060,9 +8060,9 @@ define <4 x i32> @test_punpckhdq(<4 x i3<br class="">

; BROADWELL-LABEL: test_punpckhdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpckhdq {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpckhdq {{.*#+}} xmm1 = xmm1[2],mem[2],xmm1[3],mem[3] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpckhdq {{.*#+}} xmm1 = xmm1[2],mem[2],xmm1[3],mem[3] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckhdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -8137,9 +8137,9 @@ define <2 x i64> @test_punpckhqdq(<2 x i<br class="">

; BROADWELL-LABEL: test_punpckhqdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpckhqdq {{.*#+}} xmm1 = xmm1[1],mem[1] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpckhqdq {{.*#+}} xmm1 = xmm1[1],mem[1] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckhqdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -8213,8 +8213,8 @@ define <8 x i16> @test_punpckhwd(<8 x i1<br class="">

; BROADWELL-LABEL: test_punpckhwd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm0[4],mem[4],xmm0[5],mem[5],xmm0[6],mem[6],xmm0[7],mem[7] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm0[4],mem[4],xmm0[5],mem[5],xmm0[6],mem[6],xmm0[7],mem[7] sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckhwd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -8283,8 +8283,8 @@ define <16 x i8> @test_punpcklbw(<16 x i<br class="">

; BROADWELL-LABEL: test_punpcklbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3],xmm0[4],mem[4],xmm0[5],mem[5],xmm0[6],mem[6],xmm0[7],mem[7] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3],xmm0[4],mem[4],xmm0[5],mem[5],xmm0[6],mem[6],xmm0[7],mem[7] sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpcklbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -8356,9 +8356,9 @@ define <4 x i32> @test_punpckldq(<4 x i3<br class="">

; BROADWELL-LABEL: test_punpckldq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpckldq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -8433,9 +8433,9 @@ define <2 x i64> @test_punpcklqdq(<2 x i<br class="">

; BROADWELL-LABEL: test_punpcklqdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpcklqdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -8509,8 +8509,8 @@ define <8 x i16> @test_punpcklwd(<8 x i1<br class="">

; BROADWELL-LABEL: test_punpcklwd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3] sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_punpcklwd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -8580,9 +8580,9 @@ define <2 x i64> @test_pxor(<2 x i64> %a<br class="">

; BROADWELL-LABEL: test_pxor:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpxor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    vpxor (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpxor (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pxor:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -8657,9 +8657,9 @@ define <2 x double> @test_shufpd(<2 x do<br class="">

; BROADWELL-LABEL: test_shufpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vshufpd {{.*#+}} xmm0 = xmm0[1],xmm1[0] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vshufpd {{.*#+}} xmm1 = xmm1[1],mem[0] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vshufpd {{.*#+}} xmm1 = xmm1[1],mem[0] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_shufpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -8735,9 +8735,9 @@ define <2 x double> @test_sqrtpd(<2 x do<br class="">

; BROADWELL-LABEL: test_sqrtpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vsqrtpd %xmm0, %xmm0 # sched: [21:1.00]<br class="">

-; BROADWELL-NEXT:    vsqrtpd (%rdi), %xmm1 # sched: [21:1.00]<br class="">

+; BROADWELL-NEXT:    vsqrtpd (%rdi), %xmm1 # sched: [26:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_sqrtpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -8820,10 +8820,10 @@ define <2 x double> @test_sqrtsd(<2 x do<br class="">

; BROADWELL-LABEL: test_sqrtsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [21:1.00]<br class="">

-; BROADWELL-NEXT:    vmovapd (%rdi), %xmm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovapd (%rdi), %xmm1 # sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [21:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_sqrtsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -8898,8 +8898,8 @@ define <2 x double> @test_subpd(<2 x dou<br class="">

; BROADWELL-LABEL: test_subpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vsubpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vsubpd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vsubpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_subpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -8964,8 +8964,8 @@ define double @test_subsd(double %a0, do<br class="">

; BROADWELL-LABEL: test_subsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vsubsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vsubsd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vsubsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_subsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -9073,13 +9073,13 @@ define i32 @test_ucomisd(<2 x double> %a<br class="">

; BROADWELL-NEXT:    setnp %al # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    sete %cl # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    andb %al, %cl # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    vucomisd (%rdi), %xmm0 # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    vucomisd (%rdi), %xmm0 # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    setnp %al # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    sete %dl # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    andb %al, %dl # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    orb %cl, %dl # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    movzbl %dl, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_ucomisd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -9183,9 +9183,9 @@ define <2 x double> @test_unpckhpd(<2 x<br class="">

; BROADWELL-LABEL: test_unpckhpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vunpckhpd {{.*#+}} xmm1 = xmm1[1],mem[1] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vunpckhpd {{.*#+}} xmm1 = xmm1[1],mem[1] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_unpckhpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -9266,9 +9266,9 @@ define <2 x double> @test_unpcklpd(<2 x<br class="">

; BROADWELL-LABEL: test_unpcklpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm0[0],mem[0] sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm0[0],mem[0] sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_unpcklpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -9343,9 +9343,9 @@ define <2 x double> @test_xorpd(<2 x dou<br class="">

; BROADWELL-LABEL: test_xorpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vxorpd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vxorpd (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vxorpd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_xorpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/sse3-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/sse3-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/sse3-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -45,8 +45,8 @@ define <2 x double> @test_addsubpd(<2 x<br class="">

; BROADWELL-LABEL: test_addsubpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaddsubpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_addsubpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -112,8 +112,8 @@ define <4 x float> @test_addsubps(<4 x f<br class="">

; BROADWELL-LABEL: test_addsubps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vaddsubps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vaddsubps (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vaddsubps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_addsubps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -179,8 +179,8 @@ define <2 x double> @test_haddpd(<2 x do<br class="">

; BROADWELL-LABEL: test_haddpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vhaddpd %xmm1, %xmm0, %xmm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    vhaddpd (%rdi), %xmm0, %xmm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vhaddpd (%rdi), %xmm0, %xmm0 # sched: [10:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_haddpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -246,8 +246,8 @@ define <4 x float> @test_haddps(<4 x flo<br class="">

; BROADWELL-LABEL: test_haddps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vhaddps %xmm1, %xmm0, %xmm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    vhaddps (%rdi), %xmm0, %xmm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vhaddps (%rdi), %xmm0, %xmm0 # sched: [10:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_haddps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -313,8 +313,8 @@ define <2 x double> @test_hsubpd(<2 x do<br class="">

; BROADWELL-LABEL: test_hsubpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vhsubpd %xmm1, %xmm0, %xmm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    vhsubpd (%rdi), %xmm0, %xmm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vhsubpd (%rdi), %xmm0, %xmm0 # sched: [10:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_hsubpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -380,8 +380,8 @@ define <4 x float> @test_hsubps(<4 x flo<br class="">

; BROADWELL-LABEL: test_hsubps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vhsubps %xmm1, %xmm0, %xmm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    vhsubps (%rdi), %xmm0, %xmm0 # sched: [5:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vhsubps (%rdi), %xmm0, %xmm0 # sched: [10:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_hsubps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -443,8 +443,8 @@ define <16 x i8> @test_lddqu(i8* %a0) {<br class="">

;<br class="">

; BROADWELL-LABEL: test_lddqu:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vlddqu (%rdi), %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vlddqu (%rdi), %xmm0 # sched: [5:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_lddqu:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -511,7 +511,7 @@ define void @test_monitor(i8* %a0, i32 %<br class="">

; BROADWELL-NEXT:    leaq (%rdi), %rax # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    movl %esi, %ecx # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    monitor # sched: [100:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_monitor:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -585,9 +585,9 @@ define <2 x double> @test_movddup(<2 x d<br class="">

; BROADWELL-LABEL: test_movddup:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vsubpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movddup:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -663,9 +663,9 @@ define <4 x float> @test_movshdup(<4 x f<br class="">

; BROADWELL-LABEL: test_movshdup:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movshdup:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -741,9 +741,9 @@ define <4 x float> @test_movsldup(<4 x f<br class="">

; BROADWELL-LABEL: test_movsldup:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [5:0.50]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movsldup:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -819,8 +819,8 @@ define void @test_mwait(i32 %a0, i32 %a1<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    movl %edi, %ecx # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    movl %esi, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    mwait # sched: [20:2.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    mwait # sched: [100:0.25]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_mwait:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/sse41-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/sse41-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/sse41-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -43,8 +43,8 @@ define <2 x double> @test_blendpd(<2 x d<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1] sched: [1:0.33]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],mem[1] sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],mem[1] sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blendpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -109,8 +109,8 @@ define <4 x float> @test_blendps(<4 x fl<br class="">

; BROADWELL-LABEL: test_blendps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3] sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2,3] sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2,3] sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blendps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -175,8 +175,8 @@ define <2 x double> @test_blendvpd(<2 x<br class="">

; BROADWELL-LABEL: test_blendvpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vblendvpd %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vblendvpd %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vblendvpd %xmm2, (%rdi), %xmm0, %xmm0 # sched: [7:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blendvpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -242,8 +242,8 @@ define <4 x float> @test_blendvps(<4 x f<br class="">

; BROADWELL-LABEL: test_blendvps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vblendvps %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vblendvps %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vblendvps %xmm2, (%rdi), %xmm0, %xmm0 # sched: [7:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_blendvps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -303,8 +303,8 @@ define <2 x double> @test_dppd(<2 x doub<br class="">

; BROADWELL-LABEL: test_dppd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vdppd $7, %xmm1, %xmm0, %xmm0 # sched: [9:1.00]<br class="">

-; BROADWELL-NEXT:    vdppd $7, (%rdi), %xmm0, %xmm0 # sched: [9:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vdppd $7, (%rdi), %xmm0, %xmm0 # sched: [14:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_dppd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -364,8 +364,8 @@ define <4 x float> @test_dpps(<4 x float<br class="">

; BROADWELL-LABEL: test_dpps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vdpps $7, %xmm1, %xmm0, %xmm0 # sched: [14:2.00]<br class="">

-; BROADWELL-NEXT:    vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [14:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [19:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_dpps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -425,8 +425,8 @@ define i32 @test_extractps(<4 x float> %<br class="">

; BROADWELL-LABEL: test_extractps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vextractps $3, %xmm0, %eax # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vextractps $1, %xmm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vextractps $1, %xmm0, (%rdi) # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_extractps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -487,8 +487,8 @@ define <4 x float> @test_insertps(<4 x f<br class="">

; BROADWELL-LABEL: test_insertps:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vinsertps {{.*#+}} xmm0 = zero,xmm1[0],xmm0[2,3] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_insertps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -543,8 +543,8 @@ define <2 x i64> @test_movntdqa(i8* %a0)<br class="">

;<br class="">

; BROADWELL-LABEL: test_movntdqa:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vmovntdqa (%rdi), %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmovntdqa (%rdi), %xmm0 # sched: [5:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_movntdqa:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -598,8 +598,8 @@ define <8 x i16> @test_mpsadbw(<16 x i8><br class="">

; BROADWELL-LABEL: test_mpsadbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vmpsadbw $7, %xmm1, %xmm0, %xmm0 # sched: [7:2.00]<br class="">

-; BROADWELL-NEXT:    vmpsadbw $7, (%rdi), %xmm0, %xmm0 # sched: [7:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vmpsadbw $7, (%rdi), %xmm0, %xmm0 # sched: [12:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_mpsadbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -660,8 +660,8 @@ define <8 x i16> @test_packusdw(<4 x i32<br class="">

; BROADWELL-LABEL: test_packusdw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpackusdw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpackusdw (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpackusdw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_packusdw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -728,8 +728,8 @@ define <16 x i8> @test_pblendvb(<16 x i8<br class="">

; BROADWELL-LABEL: test_pblendvb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vpblendvb %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpblendvb %xmm2, (%rdi), %xmm0, %xmm0 # sched: [7:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pblendvb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -789,8 +789,8 @@ define <8 x i16> @test_pblendw(<8 x i16><br class="">

; BROADWELL-LABEL: test_pblendw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3],xmm0[4,5,6],mem[7] sched: [4:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3],xmm0[4,5,6],mem[7] sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pblendw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -849,8 +849,8 @@ define <2 x i64> @test_pcmpeqq(<2 x i64><br class="">

; BROADWELL-LABEL: test_pcmpeqq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpeqq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpcmpeqq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpcmpeqq (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpeqq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -913,8 +913,8 @@ define i32 @test_pextrb(<16 x i8> %a0, i<br class="">

; BROADWELL-LABEL: test_pextrb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpextrb $3, %xmm0, %eax # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vpextrb $1, %xmm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpextrb $1, %xmm0, (%rdi) # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pextrb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -979,8 +979,8 @@ define i32 @test_pextrd(<4 x i32> %a0, i<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpaddd %xmm0, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    vpextrd $3, %xmm0, %eax # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vpextrd $1, %xmm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpextrd $1, %xmm0, (%rdi) # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pextrd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1044,8 +1044,8 @@ define i64 @test_pextrq(<2 x i64> %a0, <<br class="">

; BROADWELL-LABEL: test_pextrq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpextrq $1, %xmm0, %rax # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vpextrq $1, %xmm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpextrq $1, %xmm0, (%rdi) # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pextrq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1104,8 +1104,8 @@ define i32 @test_pextrw(<8 x i16> %a0, i<br class="">

; BROADWELL-LABEL: test_pextrw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpextrw $3, %xmm0, %eax # sched: [2:1.00]<br class="">

-; BROADWELL-NEXT:    vpextrw $1, %xmm0, (%rdi) # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpextrw $1, %xmm0, (%rdi) # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pextrw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1164,9 +1164,9 @@ define <8 x i16> @test_phminposuw(<8 x i<br class="">

;<br class="">

; BROADWELL-LABEL: test_phminposuw:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vphminposuw (%rdi), %xmm0 # sched: [5:1.00]<br class="">

+; BROADWELL-NEXT:    vphminposuw (%rdi), %xmm0 # sched: [10:1.00]<br class="">

; BROADWELL-NEXT:    vphminposuw %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phminposuw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1226,8 +1226,8 @@ define <16 x i8> @test_pinsrb(<16 x i8><br class="">

; BROADWELL-LABEL: test_pinsrb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpinsrb $1, %edi, %xmm0, %xmm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vpinsrb $3, (%rsi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpinsrb $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pinsrb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1286,8 +1286,8 @@ define <4 x i32> @test_pinsrd(<4 x i32><br class="">

; BROADWELL-LABEL: test_pinsrd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpinsrd $1, %edi, %xmm0, %xmm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vpinsrd $3, (%rsi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpinsrd $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pinsrd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1350,9 +1350,9 @@ define <2 x i64> @test_pinsrq(<2 x i64><br class="">

; BROADWELL-LABEL: test_pinsrq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpinsrq $1, %rdi, %xmm0, %xmm0 # sched: [2:2.00]<br class="">

-; BROADWELL-NEXT:    vpinsrq $1, (%rsi), %xmm1, %xmm1 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpinsrq $1, (%rsi), %xmm1, %xmm1 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pinsrq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1416,8 +1416,8 @@ define <16 x i8> @test_pmaxsb(<16 x i8><br class="">

; BROADWELL-LABEL: test_pmaxsb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpmaxsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaxsb (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxsb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1477,8 +1477,8 @@ define <4 x i32> @test_pmaxsd(<4 x i32><br class="">

; BROADWELL-LABEL: test_pmaxsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpmaxsd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaxsd (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1538,8 +1538,8 @@ define <4 x i32> @test_pmaxud(<4 x i32><br class="">

; BROADWELL-LABEL: test_pmaxud:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaxud %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpmaxud (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaxud (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxud:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1599,8 +1599,8 @@ define <8 x i16> @test_pmaxuw(<8 x i16><br class="">

; BROADWELL-LABEL: test_pmaxuw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaxuw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpmaxuw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaxuw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaxuw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1660,8 +1660,8 @@ define <16 x i8> @test_pminsb(<16 x i8><br class="">

; BROADWELL-LABEL: test_pminsb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpminsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpminsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpminsb (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminsb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1721,8 +1721,8 @@ define <4 x i32> @test_pminsd(<4 x i32><br class="">

; BROADWELL-LABEL: test_pminsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpminsd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpminsd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpminsd (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1782,8 +1782,8 @@ define <4 x i32> @test_pminud(<4 x i32><br class="">

; BROADWELL-LABEL: test_pminud:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpminud %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpminud (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpminud (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminud:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1843,8 +1843,8 @@ define <8 x i16> @test_pminuw(<8 x i16><br class="">

; BROADWELL-LABEL: test_pminuw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpminuw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpminuw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpminuw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pminuw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1909,9 +1909,9 @@ define <8 x i16> @test_pmovsxbw(<16 x i8<br class="">

; BROADWELL-LABEL: test_pmovsxbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovsxbw %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovsxbw (%rdi), %xmm1 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovsxbw (%rdi), %xmm1 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovsxbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1981,9 +1981,9 @@ define <4 x i32> @test_pmovsxbd(<16 x i8<br class="">

; BROADWELL-LABEL: test_pmovsxbd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovsxbd %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovsxbd (%rdi), %xmm1 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovsxbd (%rdi), %xmm1 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovsxbd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2053,9 +2053,9 @@ define <2 x i64> @test_pmovsxbq(<16 x i8<br class="">

; BROADWELL-LABEL: test_pmovsxbq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovsxbq %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovsxbq (%rdi), %xmm1 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovsxbq (%rdi), %xmm1 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovsxbq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2125,9 +2125,9 @@ define <2 x i64> @test_pmovsxdq(<4 x i32<br class="">

; BROADWELL-LABEL: test_pmovsxdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovsxdq %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovsxdq (%rdi), %xmm1 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovsxdq (%rdi), %xmm1 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovsxdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2197,9 +2197,9 @@ define <4 x i32> @test_pmovsxwd(<8 x i16<br class="">

; BROADWELL-LABEL: test_pmovsxwd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovsxwd %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovsxwd (%rdi), %xmm1 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovsxwd (%rdi), %xmm1 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovsxwd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2269,9 +2269,9 @@ define <2 x i64> @test_pmovsxwq(<8 x i16<br class="">

; BROADWELL-LABEL: test_pmovsxwq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovsxwq %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovsxwq (%rdi), %xmm1 # sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovsxwq (%rdi), %xmm1 # sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovsxwq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2341,9 +2341,9 @@ define <8 x i16> @test_pmovzxbw(<16 x i8<br class="">

; BROADWELL-LABEL: test_pmovzxbw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovzxbw {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovzxbw {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovzxbw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2413,9 +2413,9 @@ define <4 x i32> @test_pmovzxbd(<16 x i8<br class="">

; BROADWELL-LABEL: test_pmovzxbd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovzxbd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2485,9 +2485,9 @@ define <2 x i64> @test_pmovzxbq(<16 x i8<br class="">

; BROADWELL-LABEL: test_pmovzxbq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovzxbq {{.*#+}} xmm1 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovzxbq {{.*#+}} xmm1 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovzxbq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2557,9 +2557,9 @@ define <2 x i64> @test_pmovzxdq(<4 x i32<br class="">

; BROADWELL-LABEL: test_pmovzxdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovzxdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2629,9 +2629,9 @@ define <4 x i32> @test_pmovzxwd(<8 x i16<br class="">

; BROADWELL-LABEL: test_pmovzxwd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovzxwd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2701,9 +2701,9 @@ define <2 x i64> @test_pmovzxwq(<8 x i16<br class="">

; BROADWELL-LABEL: test_pmovzxwq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpmovzxwq {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero sched: [1:1.00]<br class="">

+; BROADWELL-NEXT:    vpmovzxwq {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero sched: [6:1.00]<br class="">

; BROADWELL-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmovzxwq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2768,8 +2768,8 @@ define <2 x i64> @test_pmuldq(<4 x i32><br class="">

; BROADWELL-LABEL: test_pmuldq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmuldq %xmm1, %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmuldq (%rdi), %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmuldq (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmuldq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2830,8 +2830,8 @@ define <4 x i32> @test_pmulld(<4 x i32><br class="">

; BROADWELL-LABEL: test_pmulld:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmulld %xmm1, %xmm0, %xmm0 # sched: [10:2.00]<br class="">

-; BROADWELL-NEXT:    vpmulld (%rdi), %xmm0, %xmm0 # sched: [10:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmulld (%rdi), %xmm0, %xmm0 # sched: [15:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmulld:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2907,11 +2907,11 @@ define i32 @test_ptest(<2 x i64> %a0, <2<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vptest %xmm1, %xmm0 # sched: [2:1.00]<br class="">

; BROADWELL-NEXT:    setb %al # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vptest (%rdi), %xmm0 # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vptest (%rdi), %xmm0 # sched: [7:1.00]<br class="">

; BROADWELL-NEXT:    setb %cl # sched: [1:0.50]<br class="">

; BROADWELL-NEXT:    andb %al, %cl # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    movzbl %cl, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_ptest:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -2992,10 +2992,10 @@ define <2 x double> @test_roundpd(<2 x d<br class="">

;<br class="">

; BROADWELL-LABEL: test_roundpd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vroundpd $7, %xmm0, %xmm0 # sched: [5:1.25]<br class="">

-; BROADWELL-NEXT:    vroundpd $7, (%rdi), %xmm1 # sched: [6:2.00]<br class="">

+; BROADWELL-NEXT:    vroundpd $7, %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    vroundpd $7, (%rdi), %xmm1 # sched: [11:2.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_roundpd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3064,10 +3064,10 @@ define <4 x float> @test_roundps(<4 x fl<br class="">

;<br class="">

; BROADWELL-LABEL: test_roundps:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vroundps $7, %xmm0, %xmm0 # sched: [5:1.25]<br class="">

-; BROADWELL-NEXT:    vroundps $7, (%rdi), %xmm1 # sched: [6:2.00]<br class="">

+; BROADWELL-NEXT:    vroundps $7, %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    vroundps $7, (%rdi), %xmm1 # sched: [11:2.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_roundps:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3137,10 +3137,10 @@ define <2 x double> @test_roundsd(<2 x d<br class="">

;<br class="">

; BROADWELL-LABEL: test_roundsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vroundsd $7, %xmm1, %xmm0, %xmm1 # sched: [5:1.25]<br class="">

-; BROADWELL-NEXT:    vroundsd $7, (%rdi), %xmm0, %xmm0 # sched: [6:2.00]<br class="">

+; BROADWELL-NEXT:    vroundsd $7, %xmm1, %xmm0, %xmm1 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    vroundsd $7, (%rdi), %xmm0, %xmm0 # sched: [11:2.00]<br class="">

; BROADWELL-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_roundsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -3210,10 +3210,10 @@ define <4 x float> @test_roundss(<4 x fl<br class="">

;<br class="">

; BROADWELL-LABEL: test_roundss:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vroundss $7, %xmm1, %xmm0, %xmm1 # sched: [5:1.25]<br class="">

-; BROADWELL-NEXT:    vroundss $7, (%rdi), %xmm0, %xmm0 # sched: [6:2.00]<br class="">

+; BROADWELL-NEXT:    vroundss $7, %xmm1, %xmm0, %xmm1 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    vroundss $7, (%rdi), %xmm0, %xmm0 # sched: [11:2.00]<br class="">

; BROADWELL-NEXT:    vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_roundss:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/sse42-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/sse42-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/sse42-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -42,9 +42,9 @@ define i32 @crc32_32_8(i32 %a0, i8 %a1,<br class="">

; BROADWELL-LABEL: crc32_32_8:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    crc32b %sil, %edi # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    crc32b (%rdx), %edi # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    crc32b (%rdx), %edi # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    movl %edi, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: crc32_32_8:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -112,9 +112,9 @@ define i32 @crc32_32_16(i32 %a0, i16 %a1<br class="">

; BROADWELL-LABEL: crc32_32_16:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    crc32w %si, %edi # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    crc32w (%rdx), %edi # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    crc32w (%rdx), %edi # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    movl %edi, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: crc32_32_16:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -182,9 +182,9 @@ define i32 @crc32_32_32(i32 %a0, i32 %a1<br class="">

; BROADWELL-LABEL: crc32_32_32:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    crc32l %esi, %edi # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    crc32l (%rdx), %edi # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    crc32l (%rdx), %edi # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    movl %edi, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: crc32_32_32:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -252,9 +252,9 @@ define i64 @crc32_64_8(i64 %a0, i8 %a1,<br class="">

; BROADWELL-LABEL: crc32_64_8:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    crc32b %sil, %edi # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    crc32b (%rdx), %edi # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    crc32b (%rdx), %edi # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    movq %rdi, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: crc32_64_8:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -322,9 +322,9 @@ define i64 @crc32_64_64(i64 %a0, i64 %a1<br class="">

; BROADWELL-LABEL: crc32_64_64:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    crc32q %rsi, %rdi # sched: [3:1.00]<br class="">

-; BROADWELL-NEXT:    crc32q (%rdx), %rdi # sched: [7:1.00]<br class="">

+; BROADWELL-NEXT:    crc32q (%rdx), %rdi # sched: [8:1.00]<br class="">

; BROADWELL-NEXT:    movq %rdi, %rax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: crc32_64_64:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -421,10 +421,10 @@ define i32 @test_pcmpestri(<16 x i8> %a0<br class="">

; BROADWELL-NEXT:    movl %ecx, %esi # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    movl $7, %eax # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    movl $7, %edx # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    vpcmpestri $7, (%rdi), %xmm0 # sched: [18:4.00]<br class="">

+; BROADWELL-NEXT:    vpcmpestri $7, (%rdi), %xmm0 # sched: [23:4.00]<br class="">

; BROADWELL-NEXT:    # kill: %ECX<def> %ECX<kill> %RCX<def><br class="">

; BROADWELL-NEXT:    leal (%rcx,%rsi), %eax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpestri:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -533,8 +533,8 @@ define <16 x i8> @test_pcmpestrm(<16 x i<br class="">

; BROADWELL-NEXT:    vpcmpestrm $7, %xmm1, %xmm0 # sched: [19:4.00]<br class="">

; BROADWELL-NEXT:    movl $7, %eax # sched: [1:0.25]<br class="">

; BROADWELL-NEXT:    movl $7, %edx # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    vpcmpestrm $7, (%rdi), %xmm0 # sched: [19:4.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpcmpestrm $7, (%rdi), %xmm0 # sched: [24:4.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpestrm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -623,10 +623,10 @@ define i32 @test_pcmpistri(<16 x i8> %a0<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpistri $7, %xmm1, %xmm0 # sched: [11:3.00]<br class="">

; BROADWELL-NEXT:    movl %ecx, %eax # sched: [1:0.25]<br class="">

-; BROADWELL-NEXT:    vpcmpistri $7, (%rdi), %xmm0 # sched: [11:3.00]<br class="">

+; BROADWELL-NEXT:    vpcmpistri $7, (%rdi), %xmm0 # sched: [16:3.00]<br class="">

; BROADWELL-NEXT:    # kill: %ECX<def> %ECX<kill> %RCX<def><br class="">

; BROADWELL-NEXT:    leal (%rcx,%rax), %eax # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpistri:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -699,8 +699,8 @@ define <16 x i8> @test_pcmpistrm(<16 x i<br class="">

; BROADWELL-LABEL: test_pcmpistrm:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpistrm $7, %xmm1, %xmm0 # sched: [11:3.00]<br class="">

-; BROADWELL-NEXT:    vpcmpistrm $7, (%rdi), %xmm0 # sched: [11:3.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpcmpistrm $7, (%rdi), %xmm0 # sched: [16:3.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpistrm:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -760,8 +760,8 @@ define <2 x i64> @test_pcmpgtq(<2 x i64><br class="">

; BROADWELL-LABEL: test_pcmpgtq:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpcmpgtq (%rdi), %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpcmpgtq (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pcmpgtq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -823,9 +823,9 @@ define <2 x i64> @test_pclmulqdq(<2 x i6<br class="">

;<br class="">

; BROADWELL-LABEL: test_pclmulqdq:<br class="">

; BROADWELL:       # BB#0:<br class="">

-; BROADWELL-NEXT:    vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # sched: [11:2.00]<br class="">

-; BROADWELL-NEXT:    vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [11:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # sched: [5:1.00]<br class="">

+; BROADWELL-NEXT:    vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pclmulqdq:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

Modified: llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll<br class="">

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff" class="">

http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll?rev=316492&r1=316491&r2=316492&view=diff</a><br class="">

==============================================================================<br class="">

--- llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll (original)<br class="">

+++ llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll Tue Oct 24 13:19:47 2017<br class="">

@@ -51,9 +51,9 @@ define <16 x i8> @test_pabsb(<16 x i8> %<br class="">

; BROADWELL-LABEL: test_pabsb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpabsb %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpabsb (%rdi), %xmm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpabsb (%rdi), %xmm1 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pabsb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -130,9 +130,9 @@ define <4 x i32> @test_pabsd(<4 x i32> %<br class="">

; BROADWELL-LABEL: test_pabsd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpabsd %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpabsd (%rdi), %xmm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpabsd (%rdi), %xmm1 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pabsd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -209,9 +209,9 @@ define <8 x i16> @test_pabsw(<8 x i16> %<br class="">

; BROADWELL-LABEL: test_pabsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpabsw %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpabsw (%rdi), %xmm1 # sched: [1:0.50]<br class="">

+; BROADWELL-NEXT:    vpabsw (%rdi), %xmm1 # sched: [6:0.50]<br class="">

; BROADWELL-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pabsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -287,8 +287,8 @@ define <8 x i16> @test_palignr(<8 x i16><br class="">

; BROADWELL-LABEL: test_palignr:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpalignr {{.*#+}} xmm0 = mem[14,15],xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13] sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpalignr {{.*#+}} xmm0 = mem[14,15],xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13] sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_palignr:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -353,8 +353,8 @@ define <4 x i32> @test_phaddd(<4 x i32><br class="">

; BROADWELL-LABEL: test_phaddd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vphaddd %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vphaddd (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vphaddd (%rdi), %xmm0, %xmm0 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phaddd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -420,8 +420,8 @@ define <8 x i16> @test_phaddsw(<8 x i16><br class="">

; BROADWELL-LABEL: test_phaddsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vphaddsw %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vphaddsw (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vphaddsw (%rdi), %xmm0, %xmm0 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phaddsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -487,8 +487,8 @@ define <8 x i16> @test_phaddw(<8 x i16><br class="">

; BROADWELL-LABEL: test_phaddw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vphaddw %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vphaddw (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vphaddw (%rdi), %xmm0, %xmm0 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phaddw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -554,8 +554,8 @@ define <4 x i32> @test_phsubd(<4 x i32><br class="">

; BROADWELL-LABEL: test_phsubd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vphsubd %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vphsubd (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vphsubd (%rdi), %xmm0, %xmm0 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phsubd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -621,8 +621,8 @@ define <8 x i16> @test_phsubsw(<8 x i16><br class="">

; BROADWELL-LABEL: test_phsubsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vphsubsw %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vphsubsw (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vphsubsw (%rdi), %xmm0, %xmm0 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phsubsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -688,8 +688,8 @@ define <8 x i16> @test_phsubw(<8 x i16><br class="">

; BROADWELL-LABEL: test_phsubw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vphsubw %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    vphsubw (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vphsubw (%rdi), %xmm0, %xmm0 # sched: [8:2.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_phsubw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -755,8 +755,8 @@ define <8 x i16> @test_pmaddubsw(<16 x i<br class="">

; BROADWELL-LABEL: test_pmaddubsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmaddubsw %xmm1, %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmaddubsw (%rdi), %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmaddubsw (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmaddubsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -823,8 +823,8 @@ define <8 x i16> @test_pmulhrsw(<8 x i16<br class="">

; BROADWELL-LABEL: test_pmulhrsw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpmulhrsw %xmm1, %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    vpmulhrsw (%rdi), %xmm0, %xmm0 # sched: [5:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpmulhrsw (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pmulhrsw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -890,8 +890,8 @@ define <16 x i8> @test_pshufb(<16 x i8><br class="">

; BROADWELL-LABEL: test_pshufb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpshufb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    vpshufb (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpshufb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_pshufb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -961,8 +961,8 @@ define <16 x i8> @test_psignb(<16 x i8><br class="">

; BROADWELL-LABEL: test_psignb:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsignb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsignb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsignb (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psignb:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1032,8 +1032,8 @@ define <4 x i32> @test_psignd(<4 x i32><br class="">

; BROADWELL-LABEL: test_psignd:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsignd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsignd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsignd (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psignd:<br class="">

; SKYLAKE:       # BB#0:<br class="">

@@ -1103,8 +1103,8 @@ define <8 x i16> @test_psignw(<8 x i16><br class="">

; BROADWELL-LABEL: test_psignw:<br class="">

; BROADWELL:       # BB#0:<br class="">

; BROADWELL-NEXT:    vpsignw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    vpsignw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br class="">

-; BROADWELL-NEXT:    retq # sched: [2:1.00]<br class="">

+; BROADWELL-NEXT:    vpsignw (%rdi), %xmm0, %xmm0 # sched: [6:0.50]<br class="">

+; BROADWELL-NEXT:    retq # sched: [7:1.00]<br class="">

;<br class="">

; SKYLAKE-LABEL: test_psignw:<br class="">

; SKYLAKE:       # BB#0:<br class="">

<br class="">

<br class="">

_______________________________________________<br class="">

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http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits<br class="">

</div>

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</blockquote>

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<br class="">

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