<div dir="ltr"><pre><span class="gmail-stdout"><font color="#000000" face="Courier New, courier, monotype, monospace" size="3"><a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/8811/steps/check-llvm%20ubsan/logs/stdio">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/8811/steps/check-llvm%20ubsan/logs/stdio</a><br></font></span></pre><pre><span class="gmail-stdout"><font color="#000000" face="Courier New, courier, monotype, monospace" size="3"><br></font></span></pre><pre style="font-family:"Courier New",courier,monotype,monospace;color:rgb(0,0,0);font-size:medium"><span class="gmail-stdout">Testing: 0 .. 10.. 20.. 30.. 40.. 50..
FAIL: LLVM :: CodeGen/X86/mmx-schedule.ll (13526 of 22418)
******************** TEST 'LLVM :: CodeGen/X86/mmx-schedule.ll' FAILED ********************
Script:
--
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+ssse3 | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=GENERIC
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=atom | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=ATOM
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=slm | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=SLM
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=sandybridge | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=SANDY
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=ivybridge | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=SANDY
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=HASWELL
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=SKYLAKE
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skx | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=SKX
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=BTVER2
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=ZNVER1
--
Exit Code: 1
Command Output (stderr):
--
/b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll:57:17: error: expected string not found in input
; SKYLAKE-NEXT: cvtpd2pi (%rdi), %mm1 # sched: [5:1.00]
^
<stdin>:9:2: note: scanning from here
cvtpd2pi (%rdi), %mm1 # sched: [11:1.00]
^
/b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll:133:17: error: expected string not found in input
; SKYLAKE-NEXT: cvtpi2pd (%rdi), %xmm1 # sched: [5:1.00]
^
<stdin>:23:2: note: scanning from here
cvtpi2pd (%rdi), %xmm1 # sched: [10:1.00]
^
/b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll:204:17: error: expected string not found in input
; SKYLAKE-NEXT: cvtpi2ps (%rdi), %xmm1 # sched: [4:1.00]
^
<stdin>:36:2: note: scanning from here
cvtpi2ps (%rdi), %xmm1 # sched: [9:1.00]</span></pre></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Oct 16, 2017 at 11:47 PM, Gadi Haber via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: gadi.haber<br>
Date: Mon Oct 16 23:47:04 2017<br>
New Revision: 315978<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=315978&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=315978&view=rev</a><br>
Log:<br>
[X86][SKL] Updated scheduling information for the SkylakeClient target<br>
<br>
Updated the scheduling information for the SkylakeClient target with the following changes:<br>
<br>
1. regrouped the instructions after adding load and store latencies.<br>
2. regrouped the instructions after adding identified missing ports in several groups.<br>
The changes were made after revisiting the latencies impact of all the load and store uOps.<br>
<br>
Reviewers: zvi, RKSimon, craig.topper<br>
Differential Revision: <a href="https://reviews.llvm.org/D38727" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D38727</a><br>
<br>
Change-Id: I778a308cc11e490e8fa5e27e20474<wbr>12a1dca029f<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/<wbr>X86SchedSkylakeClient.td<br>
llvm/trunk/test/CodeGen/X86/<wbr>aes-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>avx-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>avx2-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>bmi-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>bmi2-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>f16c-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>fma-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>lea32-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>lea64-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>lzcnt-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>movbe-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>popcnt-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>sse-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>sse2-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>sse3-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>sse41-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>sse42-schedule.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>ssse3-schedule.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86SchedSkylakeClient.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86SchedSkylakeClient.td?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86SchedSkylakeClient.td (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86SchedSkylakeClient.td Mon Oct 16 23:47:04 2017<br>
@@ -307,3705 +307,3904 @@ def : WriteRes<WritePHAddLd, [SKLPort15,<br>
<br>
// Remaining instrs.<br>
<br>
-def SKLWriteResGroup0 : SchedWriteRes<[SKLPort23]> {<br>
+def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {<br>
let Latency = 1;<br>
let NumMicroOps = 1;<br>
let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "LDDQUrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "LD_F32m")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "LD_F64m")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "LD_F80m")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MMX_MOVD64from64rm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MMX_MOVD64rm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MMX_MOVD64to64rm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MMX_MOVQ64rm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOV(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOV64toPQIrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOV8rm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVAPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVAPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVDDUPrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVDI2PDIrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVDQArm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVDQUrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVNTDQArm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVSHDUPrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVSLDUPrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVSX(16|32|64)rm16")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVSX(16|32|64)rm32")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVSX(16|32|64)rm8")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVUPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVUPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVZX(16|32|64)rm16")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVZX(16|32|64)rm8")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "PREFETCHNTA")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "PREFETCHT0")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "PREFETCHT1")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "PREFETCHT2")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTF128")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTI128")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTSDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTSSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VLDDQUYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VLDDQUrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOV64toPQIrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVAPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVAPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVAPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVAPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDDUPYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDDUPrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDI2PDIrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDQAYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDQArm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDQUYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDQUrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVNTDQAYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVNTDQArm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVQI2PQIrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSHDUPYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSHDUPrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSLDUPYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSLDUPrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVUPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVUPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVUPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVUPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VPBROADCASTDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VPBROADCASTDrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VPBROADCASTQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup0], (instregex "VPBROADCASTQrm")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDSBirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDSWirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDUSBirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDUSWirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PAVGBirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PAVGWirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PCMPEQBirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PCMPEQDirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PCMPEQWirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PCMPGTBirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PCMPGTDirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PCMPGTWirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PMAXSWirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PMAXUBirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PMINSWirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PMINUBirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSLLDri")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSLLDrr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSLLQri")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSLLQrr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSLLWri")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSLLWrr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRADri")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRADrr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRAWri")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRAWrr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRLDri")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRLDrr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRLQri")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRLQrr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRLWri")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRLWrr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSUBSBirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSUBSWirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSUBUSBirr")>;<br>
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSUBUSWirr")>;<br>
+<br>
+def SKLWriteResGroup2 : SchedWriteRes<[SKLPort1]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_MASKMOVQ64")>;<br>
+<br>
+def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "COM_FST0r")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "INSERTPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_MOVD64rr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_MOVD64to64rr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PALIGNR64irr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PSHUFBrr64")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PSHUFWri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKHBWirr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKHDQirr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKHWDirr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKLBWirr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKLDQirr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKLWDirr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MOV64toPQIrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVDDUPrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVDI2PDIrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVHLPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVLHPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVSDrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVSHDUPrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVSLDUPrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVUPDrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVUPSrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PACKSSDWrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PACKSSWBrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PACKUSDWrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PACKUSWBrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PALIGNRrri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PBLENDWrri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVSXBDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVSXBQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVSXBWrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVSXDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVSXWDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVSXWQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVZXBDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVZXBQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVZXBWrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVZXDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVZXWDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVZXWQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PSHUFBrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PSHUFDri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PSHUFHWri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PSHUFLWri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PSLLDQri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PSRLDQri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKHBWrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKHDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKHQDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKHWDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKLBWrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKLDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKLQDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKLWDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "SHUFPDrri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "SHUFPSrri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "UCOM_FPr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "UCOM_Fr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "UNPCKHPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "UNPCKHPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "UNPCKLPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "UNPCKLPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VBROADCASTSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VINSERTPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOV64toPQIrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVDDUPYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVDDUPrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVDI2PDIrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVHLPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVLHPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSDrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSHDUPYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSHDUPrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSLDUPYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSLDUPrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPDYrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPDrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPSYrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPSrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKSSDWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKSSDWrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKSSWBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKSSWBrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKUSDWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKUSDWrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKUSWBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKUSWBrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPALIGNRYrri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPALIGNRrri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPBLENDWYrri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPBLENDWrri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPBROADCASTDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPBROADCASTQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPDYri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPDri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPSYri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPSri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVSXBDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVSXBQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVSXBWrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVSXDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVSXWDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVSXWQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVZXBDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVZXBQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVZXBWrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVZXDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVZXWDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVZXWQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFBrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFDYri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFDri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFHWYri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFHWri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFLWYri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFLWri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLDQYri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLDQri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLDQYri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLDQri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHBWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHBWrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHDQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHQDQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHQDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHWDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHWDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLBWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLBWrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLDQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLQDQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLQDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLWDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLWDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VSHUFPDYrri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VSHUFPDrri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VSHUFPSYrri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VSHUFPSrri")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKHPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKHPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKHPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKHPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKLPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKLPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKLPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKLPSrr")>;<br>
+<br>
+def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;<br>
+<br>
+def SKLWriteResGroup5 : SchedWriteRes<[SKLPort01]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PABSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PABSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PABSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PADDSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PADDSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PADDUSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PADDUSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PAVGBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PAVGWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPEQBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPEQDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPEQQrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPEQWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPGTBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPGTDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPGTWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PMAXSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PMAXSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PMAXSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PMAXUBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PMAXUDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PMAXUWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PMINSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PMINSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PMINSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PMINUBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PMINUDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PMINUWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSIGNBrr128")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSIGNDrr128")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSIGNWrr128")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSLLDri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSLLQri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSLLWri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSRADri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSRAWri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSRLDri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSRLQri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSRLWri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSUBSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSUBSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSUBUSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "PSUBUSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPABSBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPABSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPABSDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPABSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPABSWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPABSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDSBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDSWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDUSBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDUSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDUSWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDUSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPAVGBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPAVGBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPAVGWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPAVGWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQQrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPGTBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPGTBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPGTDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPGTDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPGTWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPGTWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXSBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXSDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXSWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXUBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXUBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXUDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXUDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXUWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXUWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINSBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINSDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINSWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNBYrr256")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNBrr128")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNDYrr256")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNDrr128")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNWYrr256")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNWrr128")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLDYri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLDri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLQYri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLQri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLVDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLVDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLVQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLVQrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLWYri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLWri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRADYri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRADri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRAVDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRAVDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRAWYri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRAWri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLDYri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLDri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLQYri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLQri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLVDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLVDrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLVQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLVQrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLWYri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLWri")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBSBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBSWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBUSBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBUSBrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBUSWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBUSWrr")>;<br>
+<br>
+def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "FINCSTP")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "FNOP")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_MOVQ64rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSBrr64")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSDrr64")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSWrr64")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PADDBirr")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PADDDirr")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PADDQirr")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PADDWirr")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PANDNirr")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PANDirr")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PORirr")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSIGNBrr64")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSIGNDrr64")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSIGNWrr64")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSUBBirr")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSUBDirr")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSUBQirr")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSUBWirr")>;<br>
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PXORirr")>;<br>
+<br>
+def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri8")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "ADC8rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "ADCX32rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "ADCX64rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "ADOX32rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "ADOX64rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "BT(16|32|64)ri8")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "BT(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "BTC(16|32|64)ri8")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "BTC(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "BTR(16|32|64)ri8")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "BTR(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "BTS(16|32|64)ri8")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "BTS(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CDQ")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CLAC")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVAE(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVB(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVE(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVG(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVGE(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVL(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVLE(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVNE(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVNO(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVNP(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVNS(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVO(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVP(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVS(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "CQO")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JAE_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JAE_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JA_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JA_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JBE_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JBE_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JB_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JB_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JE_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JE_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JGE_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JGE_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JG_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JG_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JLE_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JLE_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JL_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JL_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JMP_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JMP_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JNE_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JNE_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JNO_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JNO_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JNP_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JNP_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JNS_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JNS_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JO_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JO_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JP_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JP_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JS_1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "JS_4")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "RORX32ri")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "RORX64ri")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SAR(16|32|64)r1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SAR(16|32|64)ri")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SAR8r1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SAR8ri")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SARX32rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SARX64rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)ri8")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SBB8rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETAEr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETBr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETEr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETGEr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETGr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETLEr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETLr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETNEr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETNOr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETNPr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETNSr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETOr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETPr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SETSr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SHL(16|32|64)r1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SHL(16|32|64)ri")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SHL8r1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SHL8ri")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SHLX32rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SHLX64rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SHR(16|32|64)r1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SHR(16|32|64)ri")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SHR8r1")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SHR8ri")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SHRX32rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "SHRX64rr")>;<br>
+def: InstRW<[SKLWriteResGroup7], (instregex "STAC")>;<br>
+<br>
+def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup8], (instregex "ANDN32rr")>;<br>
+def: InstRW<[SKLWriteResGroup8], (instregex "ANDN64rr")>;<br>
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSI32rr")>;<br>
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSI64rr")>;<br>
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSMSK32rr")>;<br>
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSMSK64rr")>;<br>
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSR32rr")>;<br>
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSR64rr")>;<br>
+def: InstRW<[SKLWriteResGroup8], (instregex "BZHI32rr")>;<br>
+def: InstRW<[SKLWriteResGroup8], (instregex "BZHI64rr")>;<br>
+def: InstRW<[SKLWriteResGroup8], (instregex "LEA(16|32|64)r")>;<br>
+<br>
+def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "ANDNPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "ANDNPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "ANDPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "ANDPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "BLENDPDrri")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "BLENDPSrri")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "MMX_MOVD64from64rr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "MOVAPDrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "MOVAPSrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "MOVDQArr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "MOVDQUrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "MOVPQI2QIrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "MOVSSrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "ORPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "ORPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "PADDBrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "PADDDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "PADDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "PADDWrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "PANDNrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "PANDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "PORrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "PSUBBrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "PSUBDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "PSUBQrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "PSUBWrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "PXORrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDNPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDNPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDNPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDNPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VBLENDPDYrri")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VBLENDPDrri")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VBLENDPSYrri")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VBLENDPSrri")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPDYrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPDrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPSYrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPSrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQAYrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQArr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQUYrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQUrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVPQI2QIrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVSSrr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVZPQILo2PQIrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VORPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VORPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VORPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VORPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDBrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDWrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPANDNYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPANDNrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPANDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPANDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPBLENDDYrri")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPBLENDDrri")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPORYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPORrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBBrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBQrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBWrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPXORYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VPXORrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VXORPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VXORPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VXORPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "VXORPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "XORPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup9], (instregex "XORPSrr")>;<br>
+<br>
+def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "ADD8i8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "ADD8ri")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "ADD8rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)ri8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "AND8i8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "AND8ri")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "AND8rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "CBW")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "CLC")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "CMC")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "CMP8i8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "CMP8ri")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "CMP8rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "CWDE")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "DEC(16|32|64)r")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "DEC8r")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "INC(16|32|64)r")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "INC8r")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "LAHF")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "MOV(16|32|64)rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "MOV8ri(_alt?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "MOV8rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "MOVZX(16|32|64)rr16")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "MOVZX(16|32|64)rr8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "NEG(16|32|64)r")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "NEG8r")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "NOOP")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "NOT(16|32|64)r")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "NOT8r")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)ri8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "OR8i8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "OR8ri")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "OR8rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "SAHF")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "SGDT64m")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "SIDT64m")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "SLDT64m")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "SMSW16m")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "STC")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "STRm")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "SUB8i8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "SUB8ri")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "SUB8rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "SYSCALL")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "TEST(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "TEST8i8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "TEST8ri")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "TEST8rr")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)ri8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)rr(_REV?)")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "XOR8i8")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "XOR8ri")>;<br>
+def: InstRW<[SKLWriteResGroup10], (instregex "XOR8rr(_REV?)")>;<br>
+<br>
+def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MMX_MOVD64from64rm")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MMX_MOVD64mr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MMX_MOVNTQmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MMX_MOVQ64mr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOV(16|32|64)mr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOV8mi")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOV8mr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVAPDmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVAPSmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVDQAmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVDQUmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVHPDmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVHPSmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVLPDmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVLPSmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVNTDQmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVNTI_64mr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVNTImr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVNTPDmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVNTPSmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVPDI2DImr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVPQI2QImr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVPQIto64mr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVSSmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVUPDmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVUPSmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP32m")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP64m")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP80m")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VEXTRACTF128mr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VEXTRACTI128mr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVAPDYmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVAPDmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVAPSYmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVAPSmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVDQAYmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVDQAmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVDQUYmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVDQUmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVHPDmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVHPSmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVLPDmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVLPSmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVNTDQYmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVNTDQmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVNTPDYmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVNTPDmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVNTPSYmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVNTPSmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVPDI2DImr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVPQI2QImr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVPQIto64mr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVSDmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVSSmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVUPDYmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVUPDmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVUPSYmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVUPSmr")>;<br>
+def: InstRW<[SKLWriteResGroup11], (instregex "VMPTRSTm")>;<br>
+<br>
+def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0]> {<br>
+ let Latency = 2;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "COMISDrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "COMISSrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_MOVD64from64rr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_MOVD64grr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMOVMSKBrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "MOVMSKPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "MOVMSKPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "MOVPDI2DIrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "MOVPQIto64rr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "PMOVMSKBrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "UCOMISDrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "UCOMISSrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VCOMISDrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VCOMISSrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VMOVMSKPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VMOVMSKPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VMOVMSKPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VMOVMSKPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VMOVPDI2DIrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VMOVPQIto64rr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VPMOVMSKBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VPMOVMSKBrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VTESTPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VTESTPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VTESTPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VTESTPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VUCOMISDrr")>;<br>
+def: InstRW<[SKLWriteResGroup12], (instregex "VUCOMISSrr")>;<br>
<br>
-def SKLWriteResGroup1 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "FBSTPm")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MMX_MOVD64from64rm")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MMX_MOVD64mr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MMX_MOVNTQmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MMX_MOVQ64mr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOV(16|32|64)mr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOV8mi")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOV8mr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVAPDmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVAPSmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVDQAmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVDQUmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVHPDmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVHPSmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVLPDmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVLPSmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTDQmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTI_64mr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTImr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTPDmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTPSmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVPDI2DImr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVPQI2QImr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVPQIto64mr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVSSmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVUPDmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVUPSmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "ST_FP32m")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "ST_FP64m")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "ST_FP80m")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VEXTRACTF128mr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VEXTRACTI128mr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVAPDYmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVAPDmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVAPSYmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVAPSmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVDQAYmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVDQAmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVDQUYmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVDQUmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVHPDmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVHPSmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVLPDmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVLPSmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTDQYmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTDQmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTPDYmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTPDmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTPSYmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTPSmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVPDI2DImr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVPQI2QImr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVPQIto64mr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVSDmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVSSmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVUPDYmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVUPDmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVUPSYmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVUPSmr")>;<br>
-def: InstRW<[SKLWriteResGroup1], (instregex "VMPTRSTm")>;<br>
-<br>
-def SKLWriteResGroup2 : SchedWriteRes<[SKLPort0]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 1;<br>
- let ResourceCycles = [1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PADDSBirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PADDSWirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PADDUSBirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PADDUSWirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PAVGBirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PAVGWirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPEQBirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPEQDirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPEQWirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPGTBirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPGTDirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPGTWirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PMAXSWirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PMAXUBirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PMINSWirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PMINUBirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLDri")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLDrr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLQri")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLQrr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLWri")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLWrr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRADri")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRADrr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRAWri")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRAWrr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLDri")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLDrr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLQri")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLQrr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLWri")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLWrr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSUBSBirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSUBSWirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSUBUSBirr")>;<br>
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSUBUSWirr")>;<br>
-<br>
-def SKLWriteResGroup3 : SchedWriteRes<[SKLPort1]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 1;<br>
- let ResourceCycles = [1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "MMX_MASKMOVQ64")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PABSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PABSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PABSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PADDSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PADDSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PADDUSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PADDUSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PAVGBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PAVGWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPEQBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPEQDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPEQQrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPEQWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPGTBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPGTDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPGTWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PMAXSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PMAXSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PMAXSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PMAXUBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PMAXUDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PMAXUWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PMINSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PMINSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PMINSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PMINUBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PMINUDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PMINUWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSIGNBrr128")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSIGNDrr128")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSIGNWrr128")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSLLDri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSLLQri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSLLWri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSRADri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSRAWri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSRLDri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSRLQri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSRLWri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSUBSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSUBSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSUBUSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "PSUBUSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPABSBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPABSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPABSDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPABSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPABSWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPABSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDSBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDSWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDUSBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDUSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDUSWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDUSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPAVGBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPAVGBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPAVGWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPAVGWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQQrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNBYrr256")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNBrr128")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNDYrr256")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNDrr128")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNWYrr256")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNWrr128")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLDYri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLDri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLQYri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLQri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLVDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLVDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLVQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLVQrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLWYri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLWri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRADYri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRADri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRAVDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRAVDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRAWYri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRAWri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLDYri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLDri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLQYri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLQri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLVDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLVDrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLVQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLVQrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLWYri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLWri")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBSBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBSWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBUSBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBUSBrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBUSWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBUSWrr")>;<br>
-<br>
-def SKLWriteResGroup4 : SchedWriteRes<[SKLPort5]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 1;<br>
- let ResourceCycles = [1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "COMP_FST0r")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "COM_FST0r")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "FINCSTP")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "FNOP")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "INSERTPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_MOVD64rr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_MOVD64to64rr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_MOVQ64rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PABSBrr64")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PABSDrr64")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PABSWrr64")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PADDBirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PADDDirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PADDQirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PADDWirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PALIGNR64irr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PANDNirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PANDirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PORirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSHUFBrr64")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSHUFWri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSIGNBrr64")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSIGNDrr64")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSIGNWrr64")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSUBBirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSUBDirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSUBQirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSUBWirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKHBWirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKHDQirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKHWDirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKLBWirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKLDQirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKLWDirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PXORirr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MOV64toPQIrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVDDUPrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVDI2PDIrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVHLPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVLHPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVSDrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVSHDUPrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVSLDUPrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVUPDrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVUPSrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PACKSSDWrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PACKSSWBrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PACKUSDWrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PACKUSWBrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PALIGNRrri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PBLENDWrri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXBDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXBQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXBWrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXWDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXWQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXBDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXBQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXBWrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXWDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXWQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PSHUFBrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PSHUFDri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PSHUFHWri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PSHUFLWri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PSLLDQri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PSRLDQri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKHBWrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKHDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKHQDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKHWDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKLBWrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKLDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKLQDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKLWDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "SHUFPDrri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "SHUFPSrri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "UCOM_FPr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "UCOM_Fr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "UNPCKHPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "UNPCKHPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "UNPCKLPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "UNPCKLPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VBROADCASTSSrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VINSERTPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOV64toPQIrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVDDUPYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVDDUPrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVDI2PDIrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVHLPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVLHPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSDrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSHDUPYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSHDUPrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSLDUPYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSLDUPrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVUPDYrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVUPDrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVUPSYrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVUPSrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKSSDWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKSSDWrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKSSWBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKSSWBrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKUSDWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKUSDWrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKUSWBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKUSWBrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPALIGNRYrri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPALIGNRrri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPBLENDWYrri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPBLENDWrri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPBROADCASTDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPBROADCASTQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPDYri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPDri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPSYri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPSri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXBDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXBQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXBWrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXWDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXWQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXBDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXBQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXBWrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXWDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXWQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFBrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFDYri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFDri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFHWYri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFHWri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFLWYri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFLWri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSLLDQYri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSLLDQri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSRLDQYri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSRLDQri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHBWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHBWrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHDQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHQDQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHQDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHWDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHWDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLBWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLBWrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLDQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLQDQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLQDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLWDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLWDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VSHUFPDYrri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VSHUFPDrri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VSHUFPSYrri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VSHUFPSrri")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKHPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKHPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKHPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKHPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKLPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKLPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKLPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKLPSrr")>;<br>
-<br>
-def SKLWriteResGroup5 : SchedWriteRes<[SKLPort6]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 1;<br>
- let ResourceCycles = [1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "ADC(16|32|64)ri8")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "ADC(16|32|64)rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "ADC8rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "ADCX32rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "ADCX64rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "ADOX32rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "ADOX64rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "BT(16|32|64)ri8")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "BT(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "BTC(16|32|64)ri8")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "BTC(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "BTR(16|32|64)ri8")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "BTR(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "BTS(16|32|64)ri8")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "BTS(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CDQ")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CLAC")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVAE(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVB(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVE(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVG(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVGE(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVL(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVLE(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVNE(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVNO(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVNP(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVNS(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVO(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVP(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVS(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "CQO")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JAE_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JAE_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JA_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JA_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JBE_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JBE_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JB_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JB_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JE_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JE_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JGE_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JGE_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JG_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JG_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JLE_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JLE_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JL_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JL_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JMP(16|32|64)r")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JMP_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JMP_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JNE_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JNE_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JNO_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JNO_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JNP_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JNP_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JNS_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JNS_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JO_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JO_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JP_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JP_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JS_1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "JS_4")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "RORX32ri")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "RORX64ri")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SAR(16|32|64)r1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SAR(16|32|64)ri")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SAR8r1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SAR8ri")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SARX32rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SARX64rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SBB(16|32|64)ri8")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SBB(16|32|64)rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SBB8rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETAEr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETBr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETEr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETGEr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETGr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETLEr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETLr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETNEr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETNOr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETNPr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETNSr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETOr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETPr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SETSr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SHL(16|32|64)r1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SHL(16|32|64)ri")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SHL8r1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SHL8ri")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SHLX32rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SHLX64rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SHR(16|32|64)r1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SHR(16|32|64)ri")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SHR8r1")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SHR8ri")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SHRX32rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "SHRX64rr")>;<br>
-def: InstRW<[SKLWriteResGroup5], (instregex "STAC")>;<br>
-<br>
-def SKLWriteResGroup6 : SchedWriteRes<[SKLPort15]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 1;<br>
- let ResourceCycles = [1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "ANDN32rr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "ANDN64rr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "ANDNPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "ANDNPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "ANDPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "ANDPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "BLENDPDrri")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "BLENDPSrri")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "BLSI32rr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "BLSI64rr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "BLSMSK32rr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "BLSMSK64rr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "BLSR32rr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "BLSR64rr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "BZHI32rr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "BZHI64rr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "LEA(16|32|64)r")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "MMX_MOVD64from64rr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "MOVAPDrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "MOVAPSrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "MOVDQArr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "MOVDQUrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "MOVPQI2QIrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "MOVSSrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "ORPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "ORPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "PADDBrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "PADDDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "PADDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "PADDWrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "PANDNrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "PANDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "PORrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "PSUBBrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "PSUBDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "PSUBQrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "PSUBWrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "PXORrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDNPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDNPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDNPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDNPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VBLENDPDYrri")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VBLENDPDrri")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VBLENDPSYrri")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VBLENDPSrri")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVAPDYrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVAPDrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVAPSYrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVAPSrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVDQAYrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVDQArr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVDQUYrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVDQUrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVPQI2QIrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVSSrr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVZPQILo2PQIrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VORPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VORPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VORPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VORPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDBrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDWrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPANDNYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPANDNrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPANDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPANDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPBLENDDYrri")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPBLENDDrri")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPORYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPORrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBBrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBQrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBWrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPXORYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VPXORrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VXORPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VXORPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VXORPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "VXORPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "XORPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup6], (instregex "XORPSrr")>;<br>
-<br>
-def SKLWriteResGroup7 : SchedWriteRes<[SKLPort0156]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 1;<br>
- let ResourceCycles = [1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "ADD(16|32|64)ri8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "ADD(16|32|64)rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "ADD8i8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "ADD8ri")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "ADD8rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "AND(16|32|64)ri8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "AND(16|32|64)rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "AND8i8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "AND8ri")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "AND8rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "CBW")>;<br>
-//def: InstRW<[SKLWriteResGroup7], (instregex "CDQE")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "CLC")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "CMC")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "CMP(16|32|64)ri8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "CMP(16|32|64)rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "CMP8i8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "CMP8ri")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "CMP8rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "CWDE")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "DEC(16|32|64)r")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "DEC8r")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "INC(16|32|64)r")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "INC8r")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "LAHF")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "MOV(16|32|64)rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "MOV8ri(_alt?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "MOV8rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "MOVSX(16|32|64)rr16")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "MOVSX(16|32|64)rr32")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "MOVSX(16|32|64)rr8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "MOVZX(16|32|64)rr16")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "MOVZX(16|32|64)rr8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "NEG(16|32|64)r")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "NEG8r")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "NOOP")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "NOT(16|32|64)r")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "NOT8r")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "OR(16|32|64)ri8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "OR(16|32|64)rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "OR8i8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "OR8ri")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "OR8rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "SAHF")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "SGDT64m")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "SIDT64m")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "SLDT64m")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "SMSW16m")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "STC")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "STRm")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "SUB(16|32|64)ri8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "SUB(16|32|64)rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "SUB8i8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "SUB8ri")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "SUB8rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "SYSCALL")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "TEST(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "TEST8i8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "TEST8ri")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "TEST8rr")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "XCHG(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "XOR(16|32|64)ri8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "XOR(16|32|64)rr(_REV?)")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "XOR8i8")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "XOR8ri")>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "XOR8rr(_REV?)")>;<br>
-<br>
-def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PADDSBirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PADDSWirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PADDUSBirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PADDUSWirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PAVGBirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PAVGWirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPEQBirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPEQDirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPEQWirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPGTBirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPGTDirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPGTWirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMAXSWirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMAXUBirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMINSWirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMINUBirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSLLDrm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSLLQrm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSLLWrm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRADrm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRAWrm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRLDrm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRLQrm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRLWrm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSUBSBirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSUBSWirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSUBUSBirm")>;<br>
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSUBUSWirm")>;<br>
-<br>
-def SKLWriteResGroup13 : SchedWriteRes<[SKLPort0,<wbr>SKLPort237]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MASKMOVQ64")>;<br>
-def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVDQU")>;<br>
-def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVPDYmr")>;<br>
-def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVPDmr")>;<br>
-def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVPSYmr")>;<br>
-def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVPSmr")>;<br>
-def: InstRW<[SKLWriteResGroup13], (instregex "VPMASKMOVDYmr")>;<br>
-def: InstRW<[SKLWriteResGroup13], (instregex "VPMASKMOVDmr")>;<br>
-def: InstRW<[SKLWriteResGroup13], (instregex "VPMASKMOVQYmr")>;<br>
-def: InstRW<[SKLWriteResGroup13], (instregex "VPMASKMOVQmr")>;<br>
-<br>
-def SKLWriteResGroup14 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "FCOM32m")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "FCOM64m")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "FCOMP32m")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "FCOMP64m")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "INSERTPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PALIGNR64irm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PINSRWirmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PSHUFBrm64")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PSHUFWmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKHBWirm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKHDQirm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKHWDirm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKLBWirm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKLDQirm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKLWDirm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MOVHPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MOVHPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MOVLPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "MOVLPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PACKSSDWrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PACKSSWBrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PACKUSDWrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PACKUSWBrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PALIGNRrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PBLENDWrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PINSRBrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PINSRDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PINSRQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PINSRWrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXBDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXBQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXBWrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXWDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXWQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXBDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXBQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXBWrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXWDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXWQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PSHUFBrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PSHUFDmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PSHUFHWmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PSHUFLWmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKHBWrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKHDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKHQDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKHWDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKLBWrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKLDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKLQDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKLWDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "SHUFPDrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "SHUFPSrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "UNPCKHPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "UNPCKHPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "UNPCKLPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "UNPCKLPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VINSERTPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VMOVHPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VMOVHPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VMOVLPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VMOVLPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKSSDWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKSSDWrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKSSWBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKSSWBrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKUSDWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKUSDWrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKUSWBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKUSWBrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPALIGNRYrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPALIGNRrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPBLENDWYrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPBLENDWrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPBROADCASTBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPBROADCASTBrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPBROADCASTWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPBROADCASTWrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPDYmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPDmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPSYmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPSmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPINSRBrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPINSRDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPINSRQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPINSRWrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXBDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXBQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXBWrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXWDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXWQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXBDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXBQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXBWrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXWDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXWQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFBrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFDYmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFDmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFHWYmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFHWmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFLWYmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFLWmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHBWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHBWrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHDQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHQDQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHQDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHWDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHWDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLBWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLBWrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLDQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLQDQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLQDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLWDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLWDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VSHUFPDYrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VSHUFPDrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VSHUFPSYrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VSHUFPSrmi")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKHPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKHPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKHPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKHPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKLPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKLPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKLPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKLPSrm")>;<br>
-<br>
-def SKLWriteResGroup15 : SchedWriteRes<[SKLPort6,<wbr>SKLPort23]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup15], (instregex "FARJMP64")>;<br>
-def: InstRW<[SKLWriteResGroup15], (instregex "JMP(16|32|64)m")>;<br>
-<br>
-def SKLWriteResGroup16 : SchedWriteRes<[SKLPort01,<wbr>SKLPort23]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PABSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PABSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PABSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PADDSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PADDSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PADDUSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PADDUSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PAVGBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PAVGWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPEQBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPEQDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPEQQrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPEQWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPGTBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPGTDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPGTWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PMAXSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PMAXSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PMAXSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PMAXUBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PMAXUDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PMAXUWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PMINSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PMINSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PMINSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PMINUBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PMINUDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PMINUWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSIGNBrm128")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSIGNDrm128")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSIGNWrm128")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSLLDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSLLQrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSLLWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSRADrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSRAWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSRLDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSRLQrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSRLWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSUBSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSUBSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSUBUSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "PSUBUSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPABSBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPABSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPABSDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPABSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPABSWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPABSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDSBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDSWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDUSBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDUSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDUSWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDUSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPAVGBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPAVGBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPAVGWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPAVGWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQQrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNBYrm256")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNBrm128")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNDYrm256")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNDrm128")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNWYrm256")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNWrm128")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLQrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLVDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLVDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLVQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLVQrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRADYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRADrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRAVDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRAVDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRAWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRAWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLQrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLVDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLVDrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLVQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLVQrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBSBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBSWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBUSBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBUSBrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBUSWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBUSWrm")>;<br>
-<br>
-def SKLWriteResGroup17 : SchedWriteRes<[SKLPort23,<wbr>SKLPort05]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PABSBrm64")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PABSDrm64")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PABSWrm64")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PADDBirm")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PADDDirm")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PADDQirm")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PADDWirm")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PANDNirm")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PANDirm")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PORirm")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSIGNBrm64")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSIGNDrm64")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSIGNWrm64")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSUBBirm")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSUBDirm")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSUBQirm")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSUBWirm")>;<br>
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PXORirm")>;<br>
-<br>
-def SKLWriteResGroup18 : SchedWriteRes<[SKLPort23,<wbr>SKLPort06]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "ADC(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "ADC8rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "ADCX32rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "ADCX64rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "ADOX32rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "ADOX64rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "BT(16|32|64)mi8")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVAE(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVB(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVE(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVG(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVGE(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVL(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVLE(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVNE(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVNO(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVNP(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVNS(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVO(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVP(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVS(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "RORX32mi")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "RORX64mi")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "SARX32rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "SARX64rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "SBB(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "SBB8rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "SHLX32rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "SHLX64rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "SHRX32rm")>;<br>
-def: InstRW<[SKLWriteResGroup18], (instregex "SHRX64rm")>;<br>
-<br>
-def SKLWriteResGroup19 : SchedWriteRes<[SKLPort23,<wbr>SKLPort15]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup19], (instregex "ANDN32rm")>;<br>
-def: InstRW<[SKLWriteResGroup19], (instregex "ANDN64rm")>;<br>
-def: InstRW<[SKLWriteResGroup19], (instregex "BLSI32rm")>;<br>
-def: InstRW<[SKLWriteResGroup19], (instregex "BLSI64rm")>;<br>
-def: InstRW<[SKLWriteResGroup19], (instregex "BLSMSK32rm")>;<br>
-def: InstRW<[SKLWriteResGroup19], (instregex "BLSMSK64rm")>;<br>
-def: InstRW<[SKLWriteResGroup19], (instregex "BLSR32rm")>;<br>
-def: InstRW<[SKLWriteResGroup19], (instregex "BLSR64rm")>;<br>
-def: InstRW<[SKLWriteResGroup19], (instregex "BZHI32rm")>;<br>
-def: InstRW<[SKLWriteResGroup19], (instregex "BZHI64rm")>;<br>
-def: InstRW<[SKLWriteResGroup19], (instregex "MOVBE(16|32|64)rm")>;<br>
-<br>
-def SKLWriteResGroup20 : SchedWriteRes<[SKLPort23,<wbr>SKLPort015]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "ANDNPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "ANDNPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "ANDPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "ANDPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "BLENDPDrmi")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "BLENDPSrmi")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "ORPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "ORPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "PADDBrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "PADDDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "PADDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "PADDWrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "PANDNrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "PANDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "PORrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "PSUBBrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "PSUBDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "PSUBQrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "PSUBWrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "PXORrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDNPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDNPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDNPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDNPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VBLENDPDYrmi")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VBLENDPDrmi")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VBLENDPSYrmi")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VBLENDPSrmi")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VINSERTF128rm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VINSERTI128rm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VMASKMOVPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VMASKMOVPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VMASKMOVPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VMASKMOVPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VORPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VORPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VORPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VORPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDBrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDWrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPANDNYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPANDNrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPANDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPANDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPBLENDDYrmi")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPBLENDDrmi")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPMASKMOVDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPMASKMOVDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPMASKMOVQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPMASKMOVQrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPORYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPORrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBBrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBQrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBWrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPXORYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VPXORrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VXORPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VXORPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VXORPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "VXORPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "XORPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup20], (instregex "XORPSrm")>;<br>
-<br>
-def SKLWriteResGroup21 : SchedWriteRes<[SKLPort23,<wbr>SKLPort0156]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "ADD(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "ADD8rm")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "AND(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "AND8rm")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "CMP(16|32|64)mi8")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "CMP(16|32|64)mr")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "CMP(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "CMP8mi")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "CMP8mr")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "CMP8rm")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "OR(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "OR8rm")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "POP(16|32|64)r(mr?)")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "SUB(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "SUB8rm")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "TEST(16|32|64)mr")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "TEST8mi")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "TEST8mr")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "XOR(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup21], (instregex "XOR8rm")>;<br>
-<br>
-def SKLWriteResGroup22 : SchedWriteRes<[SKLPort237,<wbr>SKLPort0156]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup22], (instregex "SFENCE")>;<br>
-<br>
-def SKLWriteResGroup23 : SchedWriteRes<[SKLPort4,<wbr>SKLPort5,SKLPort237]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup23], (instregex "EXTRACTPSmr")>;<br>
-def: InstRW<[SKLWriteResGroup23], (instregex "PEXTRBmr")>;<br>
-def: InstRW<[SKLWriteResGroup23], (instregex "PEXTRDmr")>;<br>
-def: InstRW<[SKLWriteResGroup23], (instregex "PEXTRQmr")>;<br>
-def: InstRW<[SKLWriteResGroup23], (instregex "PEXTRWmr")>;<br>
-def: InstRW<[SKLWriteResGroup23], (instregex "STMXCSR")>;<br>
-def: InstRW<[SKLWriteResGroup23], (instregex "VEXTRACTPSmr")>;<br>
-def: InstRW<[SKLWriteResGroup23], (instregex "VPEXTRBmr")>;<br>
-def: InstRW<[SKLWriteResGroup23], (instregex "VPEXTRDmr")>;<br>
-def: InstRW<[SKLWriteResGroup23], (instregex "VPEXTRQmr")>;<br>
-def: InstRW<[SKLWriteResGroup23], (instregex "VPEXTRWmr")>;<br>
-def: InstRW<[SKLWriteResGroup23], (instregex "VSTMXCSR")>;<br>
-<br>
-def SKLWriteResGroup24 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort237]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup24], (instregex "FNSTCW16m")>;<br>
-<br>
-def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237,SKLPort06]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETAEm")>;<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETBm")>;<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETEm")>;<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETGEm")>;<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETGm")>;<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETLEm")>;<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETLm")>;<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETNEm")>;<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETNOm")>;<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETNPm")>;<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETNSm")>;<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETOm")>;<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETPm")>;<br>
-def: InstRW<[SKLWriteResGroup25], (instregex "SETSm")>;<br>
-<br>
-def SKLWriteResGroup26 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237,SKLPort15]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup26], (instregex "MOVBE(16|32|64)mr")>;<br>
-<br>
-def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237,SKLPort0156]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup27], (instregex "PUSH(16|32|64)r(mr?)")>;<br>
-def: InstRW<[SKLWriteResGroup27], (instregex "PUSH64i8")>;<br>
-def: InstRW<[SKLWriteResGroup27], (instregex "STOSB")>;<br>
-def: InstRW<[SKLWriteResGroup27], (instregex "STOSL")>;<br>
-def: InstRW<[SKLWriteResGroup27], (instregex "STOSQ")>;<br>
-def: InstRW<[SKLWriteResGroup27], (instregex "STOSW")>;<br>
-<br>
-def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 4;<br>
- let ResourceCycles = [1,1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "BTC(16|32|64)mi8")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "BTR(16|32|64)mi8")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "BTS(16|32|64)mi8")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "SAR(16|32|64)m1")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "SAR(16|32|64)mi")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "SAR8m1")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "SAR8mi")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "SHL(16|32|64)m1")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "SHL(16|32|64)mi")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "SHL8m1")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "SHL8mi")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "SHR(16|32|64)m1")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "SHR(16|32|64)mi")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "SHR8m1")>;<br>
-def: InstRW<[SKLWriteResGroup28], (instregex "SHR8mi")>;<br>
-<br>
-def SKLWriteResGroup29 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 4;<br>
- let ResourceCycles = [1,1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "ADD(16|32|64)mi8")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "ADD(16|32|64)mr")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "ADD8mi")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "ADD8mr")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "AND(16|32|64)mi8")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "AND(16|32|64)mr")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "AND8mi")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "AND8mr")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "DEC(16|32|64)m")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "DEC8m")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "INC(16|32|64)m")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "INC8m")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "NEG(16|32|64)m")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "NEG8m")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "NOT(16|32|64)m")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "NOT8m")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "OR(16|32|64)mi8")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "OR(16|32|64)mr")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "OR8mi")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "OR8mr")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "POP(16|32|64)rmm")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "PUSH(16|32|64)rmm")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "SUB(16|32|64)mi8")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "SUB(16|32|64)mr")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "SUB8mi")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "SUB8mr")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "XOR(16|32|64)mi8")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "XOR(16|32|64)mr")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "XOR8mi")>;<br>
-def: InstRW<[SKLWriteResGroup29], (instregex "XOR8mr")>;<br>
-<br>
-def SKLWriteResGroup31 : SchedWriteRes<[SKLPort0]> {<br>
- let Latency = 2;<br>
- let NumMicroOps = 1;<br>
- let ResourceCycles = [1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "COMISDrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "COMISSrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "MMX_MOVD64from64rr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "MMX_MOVD64grr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "MMX_PMOVMSKBrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "MOVMSKPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "MOVMSKPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "MOVPDI2DIrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "MOVPQIto64rr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "PMOVMSKBrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "UCOMISDrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "UCOMISSrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VCOMISDrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VCOMISSrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VMOVMSKPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VMOVMSKPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VMOVMSKPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VMOVMSKPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VMOVPDI2DIrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VMOVPQIto64rr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VPMOVMSKBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VPMOVMSKBrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VTESTPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VTESTPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VTESTPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VTESTPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VUCOMISDrr")>;<br>
-def: InstRW<[SKLWriteResGroup31], (instregex "VUCOMISSrr")>;<br>
-<br>
-def SKLWriteResGroup32 : SchedWriteRes<[SKLPort5]> {<br>
+def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {<br>
let Latency = 2;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup32], (instregex "MMX_MOVQ2DQrr")>;<br>
-def: InstRW<[SKLWriteResGroup32], (instregex "MMX_PINSRWirri")>;<br>
-def: InstRW<[SKLWriteResGroup32], (instregex "PINSRBrr")>;<br>
-def: InstRW<[SKLWriteResGroup32], (instregex "PINSRDrr")>;<br>
-def: InstRW<[SKLWriteResGroup32], (instregex "PINSRQrr")>;<br>
-def: InstRW<[SKLWriteResGroup32], (instregex "PINSRWrri")>;<br>
-def: InstRW<[SKLWriteResGroup32], (instregex "VPINSRBrr")>;<br>
-def: InstRW<[SKLWriteResGroup32], (instregex "VPINSRDrr")>;<br>
-def: InstRW<[SKLWriteResGroup32], (instregex "VPINSRQrr")>;<br>
-def: InstRW<[SKLWriteResGroup32], (instregex "VPINSRWrri")>;<br>
+def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MOVQ2DQrr")>;<br>
+def: InstRW<[SKLWriteResGroup13], (instregex "MMX_PINSRWirri")>;<br>
+def: InstRW<[SKLWriteResGroup13], (instregex "PINSRBrr")>;<br>
+def: InstRW<[SKLWriteResGroup13], (instregex "PINSRDrr")>;<br>
+def: InstRW<[SKLWriteResGroup13], (instregex "PINSRQrr")>;<br>
+def: InstRW<[SKLWriteResGroup13], (instregex "PINSRWrri")>;<br>
+def: InstRW<[SKLWriteResGroup13], (instregex "VPINSRBrr")>;<br>
+def: InstRW<[SKLWriteResGroup13], (instregex "VPINSRDrr")>;<br>
+def: InstRW<[SKLWriteResGroup13], (instregex "VPINSRQrr")>;<br>
+def: InstRW<[SKLWriteResGroup13], (instregex "VPINSRWrri")>;<br>
<br>
-def SKLWriteResGroup33 : SchedWriteRes<[SKLPort05]> {<br>
+def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {<br>
let Latency = 2;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup33], (instregex "FDECSTP")>;<br>
-def: InstRW<[SKLWriteResGroup33], (instregex "MMX_MOVDQ2Qrr")>;<br>
+def: InstRW<[SKLWriteResGroup14], (instregex "FDECSTP")>;<br>
+def: InstRW<[SKLWriteResGroup14], (instregex "MMX_MOVDQ2Qrr")>;<br>
<br>
-def SKLWriteResGroup34 : SchedWriteRes<[SKLPort06]> {<br>
+def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> {<br>
let Latency = 2;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup34], (instregex "CMOVA(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup34], (instregex "CMOVBE(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup34], (instregex "ROL(16|32|64)r1")>;<br>
-def: InstRW<[SKLWriteResGroup34], (instregex "ROL(16|32|64)ri")>;<br>
-def: InstRW<[SKLWriteResGroup34], (instregex "ROL8r1")>;<br>
-def: InstRW<[SKLWriteResGroup34], (instregex "ROL8ri")>;<br>
-def: InstRW<[SKLWriteResGroup34], (instregex "ROR(16|32|64)r1")>;<br>
-def: InstRW<[SKLWriteResGroup34], (instregex "ROR(16|32|64)ri")>;<br>
-def: InstRW<[SKLWriteResGroup34], (instregex "ROR8r1")>;<br>
-def: InstRW<[SKLWriteResGroup34], (instregex "ROR8ri")>;<br>
-def: InstRW<[SKLWriteResGroup34], (instregex "SETAr")>;<br>
-def: InstRW<[SKLWriteResGroup34], (instregex "SETBEr")>;<br>
+def: InstRW<[SKLWriteResGroup15], (instregex "CMOVA(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup15], (instregex "CMOVBE(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup15], (instregex "ROL(16|32|64)r1")>;<br>
+def: InstRW<[SKLWriteResGroup15], (instregex "ROL(16|32|64)ri")>;<br>
+def: InstRW<[SKLWriteResGroup15], (instregex "ROL8r1")>;<br>
+def: InstRW<[SKLWriteResGroup15], (instregex "ROL8ri")>;<br>
+def: InstRW<[SKLWriteResGroup15], (instregex "ROR(16|32|64)r1")>;<br>
+def: InstRW<[SKLWriteResGroup15], (instregex "ROR(16|32|64)ri")>;<br>
+def: InstRW<[SKLWriteResGroup15], (instregex "ROR8r1")>;<br>
+def: InstRW<[SKLWriteResGroup15], (instregex "ROR8ri")>;<br>
+def: InstRW<[SKLWriteResGroup15], (instregex "SETAr")>;<br>
+def: InstRW<[SKLWriteResGroup15], (instregex "SETBEr")>;<br>
<br>
-def SKLWriteResGroup35 : SchedWriteRes<[SKLPort015]> {<br>
+def SKLWriteResGroup16 : SchedWriteRes<[SKLPort015]> {<br>
let Latency = 2;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup35], (instregex "BLENDVPDrr0")>;<br>
-def: InstRW<[SKLWriteResGroup35], (instregex "BLENDVPSrr0")>;<br>
-def: InstRW<[SKLWriteResGroup35], (instregex "PBLENDVBrr0")>;<br>
-def: InstRW<[SKLWriteResGroup35], (instregex "VBLENDVPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup35], (instregex "VBLENDVPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup35], (instregex "VBLENDVPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup35], (instregex "VBLENDVPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup35], (instregex "VPBLENDVBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup35], (instregex "VPBLENDVBrr")>;<br>
+def: InstRW<[SKLWriteResGroup16], (instregex "BLENDVPDrr0")>;<br>
+def: InstRW<[SKLWriteResGroup16], (instregex "BLENDVPSrr0")>;<br>
+def: InstRW<[SKLWriteResGroup16], (instregex "PBLENDVBrr0")>;<br>
+def: InstRW<[SKLWriteResGroup16], (instregex "VBLENDVPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup16], (instregex "VBLENDVPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup16], (instregex "VBLENDVPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup16], (instregex "VBLENDVPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup16], (instregex "VPBLENDVBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup16], (instregex "VPBLENDVBrr")>;<br>
<br>
-def SKLWriteResGroup36 : SchedWriteRes<[SKLPort0156]> {<br>
+def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {<br>
let Latency = 2;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup36], (instregex "LFENCE")>;<br>
-def: InstRW<[SKLWriteResGroup36], (instregex "WAIT")>;<br>
-def: InstRW<[SKLWriteResGroup36], (instregex "XGETBV")>;<br>
+def: InstRW<[SKLWriteResGroup17], (instregex "LFENCE")>;<br>
+def: InstRW<[SKLWriteResGroup17], (instregex "WAIT")>;<br>
+def: InstRW<[SKLWriteResGroup17], (instregex "XGETBV")>;<br>
<br>
-def SKLWriteResGroup37 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup18 : SchedWriteRes<[SKLPort0,<wbr>SKLPort237]> {<br>
let Latency = 2;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup37], (instregex "COMISDrm")>;<br>
-def: InstRW<[SKLWriteResGroup37], (instregex "COMISSrm")>;<br>
-def: InstRW<[SKLWriteResGroup37], (instregex "UCOMISDrm")>;<br>
-def: InstRW<[SKLWriteResGroup37], (instregex "UCOMISSrm")>;<br>
-def: InstRW<[SKLWriteResGroup37], (instregex "VCOMISDrm")>;<br>
-def: InstRW<[SKLWriteResGroup37], (instregex "VCOMISSrm")>;<br>
-def: InstRW<[SKLWriteResGroup37], (instregex "VTESTPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup37], (instregex "VTESTPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup37], (instregex "VTESTPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup37], (instregex "VTESTPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup37], (instregex "VUCOMISDrm")>;<br>
-def: InstRW<[SKLWriteResGroup37], (instregex "VUCOMISSrm")>;<br>
+def: InstRW<[SKLWriteResGroup18], (instregex "MMX_MASKMOVQ64")>;<br>
+def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVDQU")>;<br>
+def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPDYmr")>;<br>
+def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPDmr")>;<br>
+def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPSYmr")>;<br>
+def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPSmr")>;<br>
+def: InstRW<[SKLWriteResGroup18], (instregex "VPMASKMOVDYmr")>;<br>
+def: InstRW<[SKLWriteResGroup18], (instregex "VPMASKMOVDmr")>;<br>
+def: InstRW<[SKLWriteResGroup18], (instregex "VPMASKMOVQYmr")>;<br>
+def: InstRW<[SKLWriteResGroup18], (instregex "VPMASKMOVQmr")>;<br>
<br>
-def SKLWriteResGroup38 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01]> {<br>
+def SKLWriteResGroup19 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01]> {<br>
let Latency = 2;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "PSLLDrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "PSLLQrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "PSLLWrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "PSRADrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "PSRAWrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "PSRLDrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "PSRLQrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "PSRLWrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSLLDrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSLLQrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSLLWrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSRADrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSRAWrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSRLDrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSRLQrr")>;<br>
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSRLWrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "PSLLDrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "PSLLQrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "PSLLWrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "PSRADrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "PSRAWrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "PSRLDrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "PSRLQrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "PSRLWrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSLLDrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSLLQrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSLLWrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSRADrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSRAWrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSRLDrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSRLQrr")>;<br>
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSRLWrr")>;<br>
<br>
-def SKLWriteResGroup39 : SchedWriteRes<[SKLPort6,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,<wbr>SKLPort0156]> {<br>
let Latency = 2;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup39], (instregex "CLFLUSH")>;<br>
+def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;<br>
<br>
-def SKLWriteResGroup40 : SchedWriteRes<[SKLPort06,<wbr>SKLPort15]> {<br>
+def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,<wbr>SKLPort0156]> {<br>
let Latency = 2;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup40], (instregex "BEXTR32rr")>;<br>
-def: InstRW<[SKLWriteResGroup40], (instregex "BEXTR64rr")>;<br>
-def: InstRW<[SKLWriteResGroup40], (instregex "BSWAP(16|32|64)r")>;<br>
+def: InstRW<[SKLWriteResGroup21], (instregex "SFENCE")>;<br>
<br>
-def SKLWriteResGroup41 : SchedWriteRes<[SKLPort06,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup22 : SchedWriteRes<[SKLPort06,<wbr>SKLPort15]> {<br>
let Latency = 2;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup41], (instregex "ADC8i8")>;<br>
-def: InstRW<[SKLWriteResGroup41], (instregex "ADC8ri")>;<br>
-def: InstRW<[SKLWriteResGroup41], (instregex "CWD")>;<br>
-def: InstRW<[SKLWriteResGroup41], (instregex "JRCXZ")>;<br>
-def: InstRW<[SKLWriteResGroup41], (instregex "SBB8i8")>;<br>
-def: InstRW<[SKLWriteResGroup41], (instregex "SBB8ri")>;<br>
-<br>
-def SKLWriteResGroup42 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
- let Latency = 2;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [2,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup42], (instregex "MMX_PACKSSDWirm")>;<br>
-def: InstRW<[SKLWriteResGroup42], (instregex "MMX_PACKSSWBirm")>;<br>
-def: InstRW<[SKLWriteResGroup42], (instregex "MMX_PACKUSWBirm")>;<br>
-<br>
-def SKLWriteResGroup43 : SchedWriteRes<[SKLPort23,<wbr>SKLPort06]> {<br>
- let Latency = 2;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,2];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup43], (instregex "CMOVA(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup43], (instregex "CMOVBE(16|32|64)rm")>;<br>
-<br>
-def SKLWriteResGroup44 : SchedWriteRes<[SKLPort23,<wbr>SKLPort015]> {<br>
- let Latency = 2;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,2];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup44], (instregex "BLENDVPDrm0")>;<br>
-def: InstRW<[SKLWriteResGroup44], (instregex "BLENDVPSrm0")>;<br>
-def: InstRW<[SKLWriteResGroup44], (instregex "PBLENDVBrm0")>;<br>
-def: InstRW<[SKLWriteResGroup44], (instregex "VBLENDVPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup44], (instregex "VBLENDVPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup44], (instregex "VBLENDVPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup44], (instregex "VBLENDVPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup44], (instregex "VPBLENDVBYrm")>;<br>
-def: InstRW<[SKLWriteResGroup44], (instregex "VPBLENDVBrm")>;<br>
-<br>
-def SKLWriteResGroup45 : SchedWriteRes<[SKLPort23,<wbr>SKLPort0156]> {<br>
- let Latency = 2;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,2];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup45], (instregex "LEAVE64")>;<br>
-def: InstRW<[SKLWriteResGroup45], (instregex "SCASB")>;<br>
-def: InstRW<[SKLWriteResGroup45], (instregex "SCASL")>;<br>
-def: InstRW<[SKLWriteResGroup45], (instregex "SCASQ")>;<br>
-def: InstRW<[SKLWriteResGroup45], (instregex "SCASW")>;<br>
+def: InstRW<[SKLWriteResGroup22], (instregex "BEXTR32rr")>;<br>
+def: InstRW<[SKLWriteResGroup22], (instregex "BEXTR64rr")>;<br>
+def: InstRW<[SKLWriteResGroup22], (instregex "BSWAP(16|32|64)r")>;<br>
<br>
-def SKLWriteResGroup46 : SchedWriteRes<[SKLPort237,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,<wbr>SKLPort0156]> {<br>
let Latency = 2;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,2];<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup46], (instregex "MFENCE")>;<br>
+def: InstRW<[SKLWriteResGroup23], (instregex "ADC8i8")>;<br>
+def: InstRW<[SKLWriteResGroup23], (instregex "ADC8ri")>;<br>
+def: InstRW<[SKLWriteResGroup23], (instregex "CWD")>;<br>
+def: InstRW<[SKLWriteResGroup23], (instregex "JRCXZ")>;<br>
+def: InstRW<[SKLWriteResGroup23], (instregex "SBB8i8")>;<br>
+def: InstRW<[SKLWriteResGroup23], (instregex "SBB8ri")>;<br>
<br>
-def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0,<wbr>SKLPort4,SKLPort237]> {<br>
+def SKLWriteResGroup24 : SchedWriteRes<[SKLPort4,<wbr>SKLPort5,SKLPort237]> {<br>
let Latency = 2;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup47], (instregex "FNSTSWm")>;<br>
+def: InstRW<[SKLWriteResGroup24], (instregex "EXTRACTPSmr")>;<br>
+def: InstRW<[SKLWriteResGroup24], (instregex "PEXTRBmr")>;<br>
+def: InstRW<[SKLWriteResGroup24], (instregex "PEXTRDmr")>;<br>
+def: InstRW<[SKLWriteResGroup24], (instregex "PEXTRQmr")>;<br>
+def: InstRW<[SKLWriteResGroup24], (instregex "PEXTRWmr")>;<br>
+def: InstRW<[SKLWriteResGroup24], (instregex "STMXCSR")>;<br>
+def: InstRW<[SKLWriteResGroup24], (instregex "VEXTRACTPSmr")>;<br>
+def: InstRW<[SKLWriteResGroup24], (instregex "VPEXTRBmr")>;<br>
+def: InstRW<[SKLWriteResGroup24], (instregex "VPEXTRDmr")>;<br>
+def: InstRW<[SKLWriteResGroup24], (instregex "VPEXTRQmr")>;<br>
+def: InstRW<[SKLWriteResGroup24], (instregex "VPEXTRWmr")>;<br>
+def: InstRW<[SKLWriteResGroup24], (instregex "VSTMXCSR")>;<br>
<br>
-def SKLWriteResGroup48 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23,SKLPort05]> {<br>
+def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort237]> {<br>
let Latency = 2;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup48], (instregex "FLDCW16m")>;<br>
+def: InstRW<[SKLWriteResGroup25], (instregex "FNSTCW16m")>;<br>
<br>
-def SKLWriteResGroup49 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23,SKLPort0156]> {<br>
+def SKLWriteResGroup26 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237,SKLPort06]> {<br>
let Latency = 2;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup49], (instregex "LDMXCSR")>;<br>
-def: InstRW<[SKLWriteResGroup49], (instregex "VLDMXCSR")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETAEm")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETBm")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETEm")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETGEm")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETGm")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETLEm")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETLm")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETNEm")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETNOm")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETNPm")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETNSm")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETOm")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETPm")>;<br>
+def: InstRW<[SKLWriteResGroup26], (instregex "SETSm")>;<br>
<br>
-def SKLWriteResGroup51 : SchedWriteRes<[SKLPort6,<wbr>SKLPort23,SKLPort0156]> {<br>
+def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237,SKLPort15]> {<br>
let Latency = 2;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup51], (instregex "LRETQ")>;<br>
-def: InstRW<[SKLWriteResGroup51], (instregex "RETQ")>;<br>
+def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;<br>
<br>
-def SKLWriteResGroup52 : SchedWriteRes<[SKLPort23,<wbr>SKLPort06,SKLPort15]> {<br>
+def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237,SKLPort0156]> {<br>
let Latency = 2;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup52], (instregex "BEXTR32rm")>;<br>
-def: InstRW<[SKLWriteResGroup52], (instregex "BEXTR64rm")>;<br>
-<br>
-def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237,SKLPort06]> {<br>
- let Latency = 2;<br>
- let NumMicroOps = 4;<br>
- let ResourceCycles = [1,1,2];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup53], (instregex "SETAm")>;<br>
-def: InstRW<[SKLWriteResGroup53], (instregex "SETBEm")>;<br>
-<br>
-def SKLWriteResGroup54 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort237,<wbr>SKLPort0156]> {<br>
- let Latency = 2;<br>
- let NumMicroOps = 4;<br>
- let ResourceCycles = [1,1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup54], (instregex "CALL(16|32|64)r")>;<br>
-<br>
-def SKLWriteResGroup55 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237,SKLPort06,<wbr>SKLPort0156]> {<br>
- let Latency = 2;<br>
- let NumMicroOps = 4;<br>
- let ResourceCycles = [1,1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup55], (instregex "CALL64pcrel32")>;<br>
-<br>
-def SKLWriteResGroup56 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06]> {<br>
- let Latency = 2;<br>
- let NumMicroOps = 5;<br>
- let ResourceCycles = [1,1,1,2];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup56], (instregex "ROL(16|32|64)m1")>;<br>
-def: InstRW<[SKLWriteResGroup56], (instregex "ROL(16|32|64)mi")>;<br>
-def: InstRW<[SKLWriteResGroup56], (instregex "ROL8m1")>;<br>
-def: InstRW<[SKLWriteResGroup56], (instregex "ROL8mi")>;<br>
-def: InstRW<[SKLWriteResGroup56], (instregex "ROR(16|32|64)m1")>;<br>
-def: InstRW<[SKLWriteResGroup56], (instregex "ROR(16|32|64)mi")>;<br>
-def: InstRW<[SKLWriteResGroup56], (instregex "ROR8m1")>;<br>
-def: InstRW<[SKLWriteResGroup56], (instregex "ROR8mi")>;<br>
-<br>
-def SKLWriteResGroup57 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
- let Latency = 2;<br>
- let NumMicroOps = 5;<br>
- let ResourceCycles = [1,1,1,2];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup57], (instregex "XADD(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup57], (instregex "XADD8rm")>;<br>
-<br>
-def SKLWriteResGroup58 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
- let Latency = 2;<br>
- let NumMicroOps = 5;<br>
- let ResourceCycles = [1,1,1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup58], (instregex "CALL(16|32|64)m")>;<br>
-def: InstRW<[SKLWriteResGroup58], (instregex "FARCALL64")>;<br>
+def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)r")>;<br>
+def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;<br>
+def: InstRW<[SKLWriteResGroup28], (instregex "PUSH64i8")>;<br>
+def: InstRW<[SKLWriteResGroup28], (instregex "STOSB")>;<br>
+def: InstRW<[SKLWriteResGroup28], (instregex "STOSL")>;<br>
+def: InstRW<[SKLWriteResGroup28], (instregex "STOSQ")>;<br>
+def: InstRW<[SKLWriteResGroup28], (instregex "STOSW")>;<br>
<br>
-def SKLWriteResGroup60 : SchedWriteRes<[SKLPort1]> {<br>
+def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {<br>
let Latency = 3;<br>
let NumMicroOps = 1;<br>
let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "BSF(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "BSR(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "IMUL64rr(i8?)")>;<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "IMUL8r")>;<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "LZCNT(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "MUL8r")>;<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "PDEP32rr")>;<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "PDEP64rr")>;<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "PEXT32rr")>;<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "PEXT64rr")>;<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "POPCNT(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "SHLD(16|32|64)rri8")>;<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "SHRD(16|32|64)rri8")>;<br>
-def: InstRW<[SKLWriteResGroup60], (instregex "TZCNT(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "BSF(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "BSR(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "IMUL64rr(i8?)")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "IMUL8r")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "LZCNT(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "MUL8r")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "PDEP32rr")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "PDEP64rr")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "PEXT32rr")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "PEXT64rr")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "POPCNT(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "SHLD(16|32|64)rri8")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "SHRD(16|32|64)rri8")>;<br>
+def: InstRW<[SKLWriteResGroup29], (instregex "TZCNT(16|32|64)rr")>;<br>
<br>
-def SKLWriteResGroup60_16 : SchedWriteRes<[SKLPort1, SKLPort0156]> {<br>
+def SKLWriteResGroup29_16 : SchedWriteRes<[SKLPort1, SKLPort0156]> {<br>
let Latency = 3;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup60_16]<wbr>, (instregex "IMUL16rr(i8?)")>;<br>
+def: InstRW<[SKLWriteResGroup29_16]<wbr>, (instregex "IMUL16rr(i8?)")>;<br>
<br>
-def SKLWriteResGroup60_32 : SchedWriteRes<[SKLPort1]> {<br>
+def SKLWriteResGroup29_32 : SchedWriteRes<[SKLPort1]> {<br>
let Latency = 3;<br>
let NumMicroOps = 1;<br>
}<br>
-def: InstRW<[SKLWriteResGroup60_32]<wbr>, (instregex "IMUL32rr(i8?)")>;<br>
+def: InstRW<[SKLWriteResGroup29_32]<wbr>, (instregex "IMUL32rr(i8?)")>;<br>
<br>
-def SKLWriteResGroup61 : SchedWriteRes<[SKLPort5]> {<br>
+def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {<br>
let Latency = 3;<br>
let NumMicroOps = 1;<br>
let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "ADD_FPrST0")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "ADD_FST0r")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "ADD_FrST0")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "MMX_PSADBWirr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "PCMPGTQrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "PSADBWrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "SUBR_FPrST0")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "SUBR_FST0r")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "SUBR_FrST0")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "SUB_FPrST0")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "SUB_FST0r")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "SUB_FrST0")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VBROADCASTSDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VBROADCASTSSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VEXTRACTF128rr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VEXTRACTI128rr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VINSERTF128rr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VINSERTI128rr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTBYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTBrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTWrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPCMPGTQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPCMPGTQrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPERM2F128rr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPERM2I128rr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPERMDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPERMPDYri")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPERMPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPERMQYri")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXBDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXBQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXBWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXDQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXWDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXWQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXBDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXBQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXBWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXDQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXWDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXWQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPSADBWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup61], (instregex "VPSADBWrr")>;<br>
-<br>
-def SKLWriteResGroup62 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5]> {<br>
- let Latency = 3;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "EXTRACTPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "MMX_PEXTRWirri")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRBrr")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRDrr")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRQrr")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRWri")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRWrr_REV")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "PTESTrr")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "VEXTRACTPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRBrr")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRDrr")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRQrr")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRWri")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRWrr_REV")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "VPTESTYrr")>;<br>
-def: InstRW<[SKLWriteResGroup62], (instregex "VPTESTrr")>;<br>
-<br>
-def SKLWriteResGroup63 : SchedWriteRes<[SKLPort0,<wbr>SKLPort0156]> {<br>
- let Latency = 3;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup63], (instregex "FNSTSW16r")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "ADD_FPrST0")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "ADD_FST0r")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "ADD_FrST0")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "MMX_PSADBWirr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "PCMPGTQrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "PSADBWrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "SUBR_FPrST0")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "SUBR_FST0r")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "SUBR_FrST0")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "SUB_FPrST0")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "SUB_FST0r")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "SUB_FrST0")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VBROADCASTSDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VBROADCASTSSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VEXTRACTF128rr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VEXTRACTI128rr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VINSERTF128rr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VINSERTI128rr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPBROADCASTBYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPBROADCASTBrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPBROADCASTDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPBROADCASTQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPBROADCASTWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPBROADCASTWrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPCMPGTQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPCMPGTQrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPERM2F128rr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPERM2I128rr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPERMDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPERMPDYri")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPERMPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPERMQYri")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVSXBDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVSXBQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVSXBWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVSXDQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVSXWDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVSXWQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVZXBDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVZXBQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVZXBWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVZXDQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVZXWDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVZXWQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPSADBWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup30], (instregex "VPSADBWrr")>;<br>
<br>
-def SKLWriteResGroup64 : SchedWriteRes<[SKLPort1,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup31 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5]> {<br>
let Latency = 3;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "BSF(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "BSR(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "IMUL64m")>;<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "IMUL(32|64)rm(i8?)")>;<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "IMUL8m")>;<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "LZCNT(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "MUL64m")>;<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "MUL8m")>;<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "PDEP32rm")>;<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "PDEP64rm")>;<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "PEXT32rm")>;<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "PEXT64rm")>;<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "POPCNT(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup64], (instregex "TZCNT(16|32|64)rm")>;<br>
-<br>
-def SKLWriteResGroup64_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {<br>
- let Latency = 3;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup64_16]<wbr>, (instregex "IMUL16rm(i8?)")>;<br>
-<br>
-def SKLWriteResGroup64_16_2 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {<br>
- let Latency = 3;<br>
- let NumMicroOps = 5;<br>
-}<br>
-def: InstRW<[SKLWriteResGroup64_16_<wbr>2], (instregex "IMUL16m")>;<br>
-def: InstRW<[SKLWriteResGroup64_16_<wbr>2], (instregex "MUL16m")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "EXTRACTPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "MMX_PEXTRWirri")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRBrr")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRDrr")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRQrr")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRWri")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRWrr_REV")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "PTESTrr")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "VEXTRACTPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRBrr")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRDrr")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRQrr")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRWri")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRWrr_REV")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "VPTESTYrr")>;<br>
+def: InstRW<[SKLWriteResGroup31], (instregex "VPTESTrr")>;<br>
<br>
-def SKLWriteResGroup64_32 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {<br>
- let Latency = 3;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup64_32]<wbr>, (instregex "IMUL32m")>;<br>
-def: InstRW<[SKLWriteResGroup64_32]<wbr>, (instregex "MUL32m")>;<br>
-<br>
-def SKLWriteResGroup65 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,<wbr>SKLPort0156]> {<br>
let Latency = 3;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "ADD_F32m")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "ADD_F64m")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "ILD_F16m")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "ILD_F32m")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "ILD_F64m")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "MMX_PSADBWirm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "PCMPGTQrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "PSADBWrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "SUBR_F32m")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "SUBR_F64m")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "SUB_F32m")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "SUB_F64m")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPCMPGTQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPCMPGTQrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPERM2F128rm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPERM2I128rm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPERMDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPERMPDYmi")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPERMPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPERMQYmi")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXBDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXBQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXBWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXDQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXWDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXWQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXBDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXBQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXBWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXDQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXWDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXWQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPSADBWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup65], (instregex "VPSADBWrm")>;<br>
+def: InstRW<[SKLWriteResGroup32], (instregex "FNSTSW16r")>;<br>
<br>
-def SKLWriteResGroup66 : SchedWriteRes<[SKLPort06]> {<br>
+def SKLWriteResGroup33 : SchedWriteRes<[SKLPort06]> {<br>
let Latency = 3;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [3];<br>
}<br>
-def: InstRW<[SKLWriteResGroup66], (instregex "ROL(16|32|64)rCL")>;<br>
-def: InstRW<[SKLWriteResGroup66], (instregex "ROL8rCL")>;<br>
-def: InstRW<[SKLWriteResGroup66], (instregex "ROR(16|32|64)rCL")>;<br>
-def: InstRW<[SKLWriteResGroup66], (instregex "ROR8rCL")>;<br>
-def: InstRW<[SKLWriteResGroup66], (instregex "SAR(16|32|64)rCL")>;<br>
-def: InstRW<[SKLWriteResGroup66], (instregex "SAR8rCL")>;<br>
-def: InstRW<[SKLWriteResGroup66], (instregex "SHL(16|32|64)rCL")>;<br>
-def: InstRW<[SKLWriteResGroup66], (instregex "SHL8rCL")>;<br>
-def: InstRW<[SKLWriteResGroup66], (instregex "SHR(16|32|64)rCL")>;<br>
-def: InstRW<[SKLWriteResGroup66], (instregex "SHR8rCL")>;<br>
+def: InstRW<[SKLWriteResGroup33], (instregex "ROL(16|32|64)rCL")>;<br>
+def: InstRW<[SKLWriteResGroup33], (instregex "ROL8rCL")>;<br>
+def: InstRW<[SKLWriteResGroup33], (instregex "ROR(16|32|64)rCL")>;<br>
+def: InstRW<[SKLWriteResGroup33], (instregex "ROR8rCL")>;<br>
+def: InstRW<[SKLWriteResGroup33], (instregex "SAR(16|32|64)rCL")>;<br>
+def: InstRW<[SKLWriteResGroup33], (instregex "SAR8rCL")>;<br>
+def: InstRW<[SKLWriteResGroup33], (instregex "SHL(16|32|64)rCL")>;<br>
+def: InstRW<[SKLWriteResGroup33], (instregex "SHL8rCL")>;<br>
+def: InstRW<[SKLWriteResGroup33], (instregex "SHR(16|32|64)rCL")>;<br>
+def: InstRW<[SKLWriteResGroup33], (instregex "SHR8rCL")>;<br>
<br>
-def SKLWriteResGroup67 : SchedWriteRes<[SKLPort0156]> {<br>
+def SKLWriteResGroup34 : SchedWriteRes<[SKLPort0156]> {<br>
let Latency = 3;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [3];<br>
}<br>
-def: InstRW<[SKLWriteResGroup67], (instregex "XADD(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup67], (instregex "XADD8rr")>;<br>
-def: InstRW<[SKLWriteResGroup67], (instregex "XCHG8rr")>;<br>
+def: InstRW<[SKLWriteResGroup34], (instregex "XADD(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup34], (instregex "XADD8rr")>;<br>
+def: InstRW<[SKLWriteResGroup34], (instregex "XCHG8rr")>;<br>
<br>
-def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5]> {<br>
+def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5]> {<br>
let Latency = 3;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup68], (instregex "MMX_PHADDSWrr64")>;<br>
-def: InstRW<[SKLWriteResGroup68], (instregex "MMX_PHSUBSWrr64")>;<br>
+def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PHADDSWrr64")>;<br>
+def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PHSUBSWrr64")>;<br>
<br>
-def SKLWriteResGroup69 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01]> {<br>
+def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01]> {<br>
let Latency = 3;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [2,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup69], (instregex "PHADDSWrr128")>;<br>
-def: InstRW<[SKLWriteResGroup69], (instregex "PHSUBSWrr128")>;<br>
-def: InstRW<[SKLWriteResGroup69], (instregex "VPHADDSWrr128")>;<br>
-def: InstRW<[SKLWriteResGroup69], (instregex "VPHADDSWrr256")>;<br>
-def: InstRW<[SKLWriteResGroup69], (instregex "VPHSUBSWrr128")>;<br>
-def: InstRW<[SKLWriteResGroup69], (instregex "VPHSUBSWrr256")>;<br>
+def: InstRW<[SKLWriteResGroup36], (instregex "PHADDSWrr128")>;<br>
+def: InstRW<[SKLWriteResGroup36], (instregex "PHSUBSWrr128")>;<br>
+def: InstRW<[SKLWriteResGroup36], (instregex "VPHADDSWrr128")>;<br>
+def: InstRW<[SKLWriteResGroup36], (instregex "VPHADDSWrr256")>;<br>
+def: InstRW<[SKLWriteResGroup36], (instregex "VPHSUBSWrr128")>;<br>
+def: InstRW<[SKLWriteResGroup36], (instregex "VPHSUBSWrr256")>;<br>
<br>
-def SKLWriteResGroup70 : SchedWriteRes<[SKLPort5,<wbr>SKLPort05]> {<br>
+def SKLWriteResGroup37 : SchedWriteRes<[SKLPort5,<wbr>SKLPort05]> {<br>
let Latency = 3;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [2,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup70], (instregex "MMX_PHADDWrr64")>;<br>
-def: InstRW<[SKLWriteResGroup70], (instregex "MMX_PHADDrr64")>;<br>
-def: InstRW<[SKLWriteResGroup70], (instregex "MMX_PHSUBDrr64")>;<br>
-def: InstRW<[SKLWriteResGroup70], (instregex "MMX_PHSUBWrr64")>;<br>
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDWrr64")>;<br>
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDrr64")>;<br>
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHSUBDrr64")>;<br>
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHSUBWrr64")>;<br>
<br>
-def SKLWriteResGroup71 : SchedWriteRes<[SKLPort5,<wbr>SKLPort015]> {<br>
+def SKLWriteResGroup38 : SchedWriteRes<[SKLPort5,<wbr>SKLPort015]> {<br>
let Latency = 3;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [2,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup71], (instregex "PHADDDrr")>;<br>
-def: InstRW<[SKLWriteResGroup71], (instregex "PHADDWrr")>;<br>
-def: InstRW<[SKLWriteResGroup71], (instregex "PHSUBDrr")>;<br>
-def: InstRW<[SKLWriteResGroup71], (instregex "PHSUBWrr")>;<br>
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHADDDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHADDDrr")>;<br>
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHADDWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHADDWrr")>;<br>
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHSUBDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHSUBDrr")>;<br>
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHSUBWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHSUBWrr")>;<br>
+def: InstRW<[SKLWriteResGroup38], (instregex "PHADDDrr")>;<br>
+def: InstRW<[SKLWriteResGroup38], (instregex "PHADDWrr")>;<br>
+def: InstRW<[SKLWriteResGroup38], (instregex "PHSUBDrr")>;<br>
+def: InstRW<[SKLWriteResGroup38], (instregex "PHSUBWrr")>;<br>
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHADDDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHADDDrr")>;<br>
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHADDWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHADDWrr")>;<br>
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHSUBDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHSUBDrr")>;<br>
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHSUBWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHSUBWrr")>;<br>
<br>
-def SKLWriteResGroup72 : SchedWriteRes<[SKLPort5,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,<wbr>SKLPort0156]> {<br>
let Latency = 3;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [2,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup72], (instregex "MMX_PACKSSDWirr")>;<br>
-def: InstRW<[SKLWriteResGroup72], (instregex "MMX_PACKSSWBirr")>;<br>
-def: InstRW<[SKLWriteResGroup72], (instregex "MMX_PACKUSWBirr")>;<br>
+def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKSSDWirr")>;<br>
+def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKSSWBirr")>;<br>
+def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKUSWBirr")>;<br>
<br>
-def SKLWriteResGroup73 : SchedWriteRes<[SKLPort6,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,<wbr>SKLPort0156]> {<br>
let Latency = 3;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup73], (instregex "CLD")>;<br>
+def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;<br>
<br>
-def SKLWriteResGroup74 : SchedWriteRes<[SKLPort06,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,<wbr>SKLPort0156]> {<br>
let Latency = 3;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup74], (instregex "RCL(16|32|64)r1")>;<br>
-def: InstRW<[SKLWriteResGroup74], (instregex "RCL(16|32|64)ri")>;<br>
-def: InstRW<[SKLWriteResGroup74], (instregex "RCL8r1")>;<br>
-def: InstRW<[SKLWriteResGroup74], (instregex "RCL8ri")>;<br>
-def: InstRW<[SKLWriteResGroup74], (instregex "RCR(16|32|64)r1")>;<br>
-def: InstRW<[SKLWriteResGroup74], (instregex "RCR(16|32|64)ri")>;<br>
-def: InstRW<[SKLWriteResGroup74], (instregex "RCR8r1")>;<br>
-def: InstRW<[SKLWriteResGroup74], (instregex "RCR8ri")>;<br>
+def: InstRW<[SKLWriteResGroup41], (instregex "MFENCE")>;<br>
<br>
-def SKLWriteResGroup75 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
+def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,<wbr>SKLPort0156]> {<br>
let Latency = 3;<br>
let NumMicroOps = 3;<br>
- let ResourceCycles = [1,1,1];<br>
+ let ResourceCycles = [1,2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup75], (instregex "PTESTrm")>;<br>
-def: InstRW<[SKLWriteResGroup75], (instregex "VPTESTYrm")>;<br>
-def: InstRW<[SKLWriteResGroup75], (instregex "VPTESTrm")>;<br>
+def: InstRW<[SKLWriteResGroup42], (instregex "RCL(16|32|64)r1")>;<br>
+def: InstRW<[SKLWriteResGroup42], (instregex "RCL(16|32|64)ri")>;<br>
+def: InstRW<[SKLWriteResGroup42], (instregex "RCL8r1")>;<br>
+def: InstRW<[SKLWriteResGroup42], (instregex "RCL8ri")>;<br>
+def: InstRW<[SKLWriteResGroup42], (instregex "RCR(16|32|64)r1")>;<br>
+def: InstRW<[SKLWriteResGroup42], (instregex "RCR(16|32|64)ri")>;<br>
+def: InstRW<[SKLWriteResGroup42], (instregex "RCR8r1")>;<br>
+def: InstRW<[SKLWriteResGroup42], (instregex "RCR8ri")>;<br>
<br>
-def SKLWriteResGroup76 : SchedWriteRes<[SKLPort4,<wbr>SKLPort5,SKLPort237]> {<br>
+def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,<wbr>SKLPort4,SKLPort237]> {<br>
let Latency = 3;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup76], (instregex "ISTT_FP16m")>;<br>
-def: InstRW<[SKLWriteResGroup76], (instregex "ISTT_FP32m")>;<br>
-def: InstRW<[SKLWriteResGroup76], (instregex "ISTT_FP64m")>;<br>
-def: InstRW<[SKLWriteResGroup76], (instregex "IST_F16m")>;<br>
-def: InstRW<[SKLWriteResGroup76], (instregex "IST_F32m")>;<br>
-def: InstRW<[SKLWriteResGroup76], (instregex "IST_FP16m")>;<br>
-def: InstRW<[SKLWriteResGroup76], (instregex "IST_FP32m")>;<br>
-def: InstRW<[SKLWriteResGroup76], (instregex "IST_FP64m")>;<br>
-<br>
-def SKLWriteResGroup77 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
- let Latency = 3;<br>
- let NumMicroOps = 4;<br>
- let ResourceCycles = [1,2,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup77], (instregex "MMX_PHADDSWrm64")>;<br>
-def: InstRW<[SKLWriteResGroup77], (instregex "MMX_PHSUBSWrm64")>;<br>
+def: InstRW<[SKLWriteResGroup43], (instregex "FNSTSWm")>;<br>
<br>
-def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01,SKLPort23]> {<br>
+def SKLWriteResGroup44 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237,SKLPort06]> {<br>
let Latency = 3;<br>
let NumMicroOps = 4;<br>
- let ResourceCycles = [2,1,1];<br>
+ let ResourceCycles = [1,1,2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup78], (instregex "PHADDSWrm128")>;<br>
-def: InstRW<[SKLWriteResGroup78], (instregex "PHSUBSWrm128")>;<br>
-def: InstRW<[SKLWriteResGroup78], (instregex "VPHADDSWrm128")>;<br>
-def: InstRW<[SKLWriteResGroup78], (instregex "VPHADDSWrm256")>;<br>
-def: InstRW<[SKLWriteResGroup78], (instregex "VPHSUBSWrm128")>;<br>
-def: InstRW<[SKLWriteResGroup78], (instregex "VPHSUBSWrm256")>;<br>
+def: InstRW<[SKLWriteResGroup44], (instregex "SETAm")>;<br>
+def: InstRW<[SKLWriteResGroup44], (instregex "SETBEm")>;<br>
<br>
-def SKLWriteResGroup79 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23,SKLPort05]> {<br>
+def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort237,<wbr>SKLPort0156]> {<br>
let Latency = 3;<br>
let NumMicroOps = 4;<br>
- let ResourceCycles = [2,1,1];<br>
+ let ResourceCycles = [1,1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup79], (instregex "MMX_PHADDWrm64")>;<br>
-def: InstRW<[SKLWriteResGroup79], (instregex "MMX_PHADDrm64")>;<br>
-def: InstRW<[SKLWriteResGroup79], (instregex "MMX_PHSUBDrm64")>;<br>
-def: InstRW<[SKLWriteResGroup79], (instregex "MMX_PHSUBWrm64")>;<br>
+def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;<br>
<br>
-def SKLWriteResGroup80 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23,SKLPort015]> {<br>
+def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237,SKLPort06,<wbr>SKLPort0156]> {<br>
let Latency = 3;<br>
let NumMicroOps = 4;<br>
- let ResourceCycles = [2,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup80], (instregex "PHADDDrm")>;<br>
-def: InstRW<[SKLWriteResGroup80], (instregex "PHADDWrm")>;<br>
-def: InstRW<[SKLWriteResGroup80], (instregex "PHSUBDrm")>;<br>
-def: InstRW<[SKLWriteResGroup80], (instregex "PHSUBWrm")>;<br>
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHADDDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHADDDrm")>;<br>
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHADDWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHADDWrm")>;<br>
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHSUBDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHSUBDrm")>;<br>
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHSUBWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHSUBWrm")>;<br>
-<br>
-def SKLWriteResGroup81 : SchedWriteRes<[SKLPort23,<wbr>SKLPort237,SKLPort06]> {<br>
- let Latency = 3;<br>
- let NumMicroOps = 5;<br>
- let ResourceCycles = [1,1,3];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup81], (instregex "ROR(16|32|64)mCL")>;<br>
-def: InstRW<[SKLWriteResGroup81], (instregex "ROR8mCL")>;<br>
-<br>
-def SKLWriteResGroup82 : SchedWriteRes<[SKLPort23,<wbr>SKLPort237,SKLPort06,<wbr>SKLPort0156]> {<br>
- let Latency = 3;<br>
- let NumMicroOps = 5;<br>
- let ResourceCycles = [1,1,1,2];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup82], (instregex "RCL(16|32|64)m1")>;<br>
-def: InstRW<[SKLWriteResGroup82], (instregex "RCL(16|32|64)mi")>;<br>
-def: InstRW<[SKLWriteResGroup82], (instregex "RCL8m1")>;<br>
-def: InstRW<[SKLWriteResGroup82], (instregex "RCL8mi")>;<br>
-def: InstRW<[SKLWriteResGroup82], (instregex "RCR(16|32|64)m1")>;<br>
-def: InstRW<[SKLWriteResGroup82], (instregex "RCR(16|32|64)mi")>;<br>
-def: InstRW<[SKLWriteResGroup82], (instregex "RCR8m1")>;<br>
-def: InstRW<[SKLWriteResGroup82], (instregex "RCR8mi")>;<br>
-<br>
-def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06]> {<br>
- let Latency = 3;<br>
- let NumMicroOps = 6;<br>
- let ResourceCycles = [1,1,1,3];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup83], (instregex "ROL(16|32|64)mCL")>;<br>
-def: InstRW<[SKLWriteResGroup83], (instregex "ROL8mCL")>;<br>
-def: InstRW<[SKLWriteResGroup83], (instregex "SAR(16|32|64)mCL")>;<br>
-def: InstRW<[SKLWriteResGroup83], (instregex "SAR8mCL")>;<br>
-def: InstRW<[SKLWriteResGroup83], (instregex "SHL(16|32|64)mCL")>;<br>
-def: InstRW<[SKLWriteResGroup83], (instregex "SHL8mCL")>;<br>
-def: InstRW<[SKLWriteResGroup83], (instregex "SHR(16|32|64)mCL")>;<br>
-def: InstRW<[SKLWriteResGroup83], (instregex "SHR8mCL")>;<br>
-<br>
-def SKLWriteResGroup84 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
- let Latency = 3;<br>
- let NumMicroOps = 6;<br>
- let ResourceCycles = [1,1,1,3];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup84], (instregex "ADC(16|32|64)mi8")>;<br>
-def: InstRW<[SKLWriteResGroup84], (instregex "ADC8mi")>;<br>
-<br>
-def SKLWriteResGroup85 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort0156]> {<br>
- let Latency = 3;<br>
- let NumMicroOps = 6;<br>
- let ResourceCycles = [1,1,1,2,1];<br>
+ let ResourceCycles = [1,1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup85], (instregex "ADC(16|32|64)mr")>;<br>
-def: InstRW<[SKLWriteResGroup85], (instregex "ADC8mr")>;<br>
-def: InstRW<[SKLWriteResGroup85], (instregex "CMPXCHG(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup85], (instregex "CMPXCHG8rm")>;<br>
-def: InstRW<[SKLWriteResGroup85], (instregex "SBB(16|32|64)mi8")>;<br>
-def: InstRW<[SKLWriteResGroup85], (instregex "SBB(16|32|64)mr")>;<br>
-def: InstRW<[SKLWriteResGroup85], (instregex "SBB8mi")>;<br>
-def: InstRW<[SKLWriteResGroup85], (instregex "SBB8mr")>;<br>
+def: InstRW<[SKLWriteResGroup46], (instregex "CALL64pcrel32")>;<br>
<br>
-def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0]> {<br>
+def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {<br>
let Latency = 4;<br>
let NumMicroOps = 1;<br>
let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "AESDECLASTrr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "AESDECrr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "AESENCLASTrr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "AESENCrr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMADDUBSWrr64")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMADDWDirr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULHRSWrr64")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULHUWirr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULHWirr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULLWirr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULUDQirr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "MUL_FPrST0")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "MUL_FST0r")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "MUL_FrST0")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "RCPPSr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "RCPSSr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "RSQRTPSr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "RSQRTSSr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "VAESDECLASTrr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "VAESDECrr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "VAESENCLASTrr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "VAESENCrr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "VRCPPSYr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "VRCPPSr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "VRCPSSr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "VRSQRTPSYr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "VRSQRTPSr")>;<br>
-def: InstRW<[SKLWriteResGroup86], (instregex "VRSQRTSSr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "AESDECLASTrr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "AESDECrr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "AESENCLASTrr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "AESENCrr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMADDUBSWrr64")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMADDWDirr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULHRSWrr64")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULHUWirr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULHWirr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULLWirr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULUDQirr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "MUL_FPrST0")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "MUL_FST0r")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "MUL_FrST0")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "RCPPSr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "RCPSSr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "RSQRTPSr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "RSQRTSSr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "VAESDECLASTrr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "VAESDECrr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "VAESENCLASTrr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "VAESENCrr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "VRCPPSYr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "VRCPPSr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "VRCPSSr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "VRSQRTPSYr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "VRSQRTPSr")>;<br>
+def: InstRW<[SKLWriteResGroup47], (instregex "VRSQRTSSr")>;<br>
<br>
-def SKLWriteResGroup87 : SchedWriteRes<[SKLPort01]> {<br>
+def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {<br>
let Latency = 4;<br>
let NumMicroOps = 1;<br>
let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "ADDPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "ADDPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "ADDSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "ADDSSrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "ADDSUBPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "ADDSUBPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "MULPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "MULPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "MULSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "MULSSrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "SUBPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "SUBPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "SUBSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "SUBSSrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDSSrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDSUBPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDSUBPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDSUBPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDSUBPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132SDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132SSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213SDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213SSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231SDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231SSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB132PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB132PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB132PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB132PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB213PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB213PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB213PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB213PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB231PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB231PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB231PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB231PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132SDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132SSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213SDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213SSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231SDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231SSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD132PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD132PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD132PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD132PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD213PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD213PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD213PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD213PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD231PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD231PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD231PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD231PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132SDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132SSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213SDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213SSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231SDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231SSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132SDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132SSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213SDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213SSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231PDYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231PDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231PSYr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231PSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231SDr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231SSr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VMULPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VMULPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VMULPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VMULPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VMULSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VMULSSrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VSUBPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VSUBPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VSUBPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VSUBPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VSUBSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup87], (instregex "VSUBSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "ADDPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "ADDPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "ADDSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "ADDSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "ADDSUBPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "ADDSUBPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "MULPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "MULPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "MULSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "MULSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "SUBPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "SUBPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "SUBSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "SUBSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDSUBPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDSUBPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDSUBPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDSUBPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD132PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD132PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD132PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD132PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD132SDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD132SSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD213PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD213PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD213PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD213PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD213SDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD213SSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD231PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD231PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD231PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD231PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD231SDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD231SSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB132PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB132PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB132PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB132PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB213PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB213PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB213PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB213PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB231PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB231PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB231PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB231PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB132PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB132PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB132PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB132PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB132SDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB132SSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB213PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB213PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB213PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB213PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB213SDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB213SSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB231PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB231PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB231PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB231PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB231SDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB231SSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD132PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD132PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD132PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD132PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD213PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD213PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD213PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD213PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD231PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD231PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD231PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD231PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD132PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD132PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD132PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD132PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD132SDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD132SSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD213PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD213PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD213PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD213PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD213SDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD213SSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD231PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD231PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD231PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD231PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD231SDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD231SSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB132PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB132PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB132PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB132PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB132SDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB132SSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB213PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB213PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB213PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB213PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB213SDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB213SSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB231PDYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB231PDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB231PSYr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB231PSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB231SDr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB231SSr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VMULPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VMULPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VMULPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VMULPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VMULSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VMULSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VSUBPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VSUBPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VSUBPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VSUBPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VSUBSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup48], (instregex "VSUBSSrr")>;<br>
<br>
-def SKLWriteResGroup89 : SchedWriteRes<[SKLPort015]> {<br>
+def SKLWriteResGroup49 : SchedWriteRes<[SKLPort015]> {<br>
let Latency = 4;<br>
let NumMicroOps = 1;<br>
let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "CMPPDrri")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "CMPPSrri")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "CMPSSrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "CVTDQ2PSrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "CVTPS2DQrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "CVTTPS2DQrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "MAXPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "MAXPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "MAXSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "MAXSSrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "MINPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "MINPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "MINSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "MINSSrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "PHMINPOSUWrr128")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "PMADDUBSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "PMADDWDrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "PMULDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "PMULHRSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "PMULHUWrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "PMULHWrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "PMULLWrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "PMULUDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VCMPPDYrri")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VCMPPDrri")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VCMPPSYrri")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VCMPPSrri")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VCMPSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VCMPSSrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VCVTDQ2PSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VCVTDQ2PSrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPS2DQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPS2DQrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VCVTTPS2DQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VCVTTPS2DQrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VMAXPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VMAXPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VMAXPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VMAXPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VMAXSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VMAXSSrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VMINPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VMINPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VMINPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VMINPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VMINSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VMINSSrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPHMINPOSUWrr128")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMADDUBSWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMADDUBSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMADDWDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMADDWDrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULDQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHRSWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHRSWrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHUWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHUWrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHWrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULLWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULLWrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULUDQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULUDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "CMPPDrri")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "CMPPSrri")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "CMPSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "CVTDQ2PSrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "CVTPS2DQrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "CVTTPS2DQrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "MAXPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "MAXPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "MAXSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "MAXSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "MINPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "MINPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "MINSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "MINSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "PHMINPOSUWrr128")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "PMADDUBSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "PMADDWDrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "PMULDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "PMULHRSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "PMULHUWrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "PMULHWrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "PMULLWrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "PMULUDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VCMPPDYrri")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VCMPPDrri")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VCMPPSYrri")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VCMPPSrri")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VCMPSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VCMPSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VCVTDQ2PSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VCVTDQ2PSrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VCVTPS2DQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VCVTPS2DQrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VCVTTPS2DQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VCVTTPS2DQrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VMAXPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VMAXPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VMAXPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VMAXPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VMAXSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VMAXSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VMINPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VMINPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VMINPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VMINPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VMINSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VMINSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPHMINPOSUWrr128")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDUBSWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDUBSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDWDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDWDrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULDQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHRSWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHRSWrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHUWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHUWrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHWrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULLWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULLWrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULUDQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULUDQrr")>;<br>
<br>
-def SKLWriteResGroup90 : SchedWriteRes<[SKLPort5]> {<br>
+def SKLWriteResGroup50 : SchedWriteRes<[SKLPort5]> {<br>
let Latency = 4;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup90], (instregex "MPSADBWrri")>;<br>
-def: InstRW<[SKLWriteResGroup90], (instregex "VMPSADBWYrri")>;<br>
-def: InstRW<[SKLWriteResGroup90], (instregex "VMPSADBWrri")>;<br>
-<br>
-def SKLWriteResGroup91 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
- let Latency = 4;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "AESDECLASTrm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "AESDECrm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "AESENCLASTrm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "AESENCrm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_CVTPI2PSirm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMADDUBSWrm64")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMADDWDirm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULHRSWrm64")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULHUWirm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULHWirm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULLWirm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULUDQirm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "MUL_F32m")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "MUL_F64m")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "RCPPSm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "RCPSSm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "RSQRTPSm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "RSQRTSSm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "VAESDECLASTrm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "VAESDECrm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "VAESENCLASTrm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "VAESENCrm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "VRCPPSYm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "VRCPPSm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "VRCPSSm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "VRSQRTPSYm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "VRSQRTPSm")>;<br>
-def: InstRW<[SKLWriteResGroup91], (instregex "VRSQRTSSm")>;<br>
+def: InstRW<[SKLWriteResGroup50], (instregex "MPSADBWrri")>;<br>
+def: InstRW<[SKLWriteResGroup50], (instregex "VMPSADBWYrri")>;<br>
+def: InstRW<[SKLWriteResGroup50], (instregex "VMPSADBWrri")>;<br>
<br>
-def SKLWriteResGroup92 : SchedWriteRes<[SKLPort1,<wbr>SKLPort5]> {<br>
+def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,<wbr>SKLPort5]> {<br>
let Latency = 4;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup92], (instregex "IMUL64r")>;<br>
-def: InstRW<[SKLWriteResGroup92], (instregex "MUL64r")>;<br>
-def: InstRW<[SKLWriteResGroup92], (instregex "MULX64rr")>;<br>
+def: InstRW<[SKLWriteResGroup51], (instregex "IMUL64r")>;<br>
+def: InstRW<[SKLWriteResGroup51], (instregex "MUL64r")>;<br>
+def: InstRW<[SKLWriteResGroup51], (instregex "MULX64rr")>;<br>
<br>
-def SKLWriteResGroup92_16 : SchedWriteRes<[SKLPort1,<wbr>SKLPort06,SKLPort0156]> {<br>
+def SKLWriteResGroup51_16 : SchedWriteRes<[SKLPort1,<wbr>SKLPort06,SKLPort0156]> {<br>
let Latency = 4;<br>
- let NumMicroOps = 4;<br>
+ let NumMicroOps = 4;<br>
}<br>
-def: InstRW<[SKLWriteResGroup92_16]<wbr>, (instregex "IMUL16r")>;<br>
-def: InstRW<[SKLWriteResGroup92_16]<wbr>, (instregex "MUL16r")>;<br>
+def: InstRW<[SKLWriteResGroup51_16]<wbr>, (instregex "IMUL16r")>;<br>
+def: InstRW<[SKLWriteResGroup51_16]<wbr>, (instregex "MUL16r")>;<br>
<br>
-def SKLWriteResGroup93 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01]> {<br>
+def SKLWriteResGroup52 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01]> {<br>
let Latency = 4;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSLLDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSLLQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSLLWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSRADYrr")>;<br>
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSRAWYrr")>;<br>
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSRLDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSRLQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSRLWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSLLDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSLLQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSLLWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSRADYrr")>;<br>
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSRAWYrr")>;<br>
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSRLDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSRLQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSRLWYrr")>;<br>
<br>
-def SKLWriteResGroup94 : SchedWriteRes<[SKLPort01,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,<wbr>SKLPort5,SKLPort237]> {<br>
let Latency = 4;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "ADDPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "ADDPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "ADDSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "ADDSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "ADDSUBPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "ADDSUBPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "MULPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "MULPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "MULSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "MULSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "SUBPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "SUBPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "SUBSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "SUBSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDSUBPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDSUBPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDSUBPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDSUBPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132SDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132SSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213SDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213SSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231SDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231SSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB132PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB132PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB132PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB132PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB213PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB213PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB213PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB213PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB231PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB231PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB231PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB231PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132SDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132SSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213SDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213SSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231SDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231SSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD132PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD132PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD132PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD132PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD213PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD213PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD213PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD213PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD231PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD231PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD231PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD231PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132SDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132SSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213SDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213SSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231SDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231SSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132SDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132SSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213SDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213SSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231PDYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231PDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231PSYm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231PSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231SDm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231SSm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VMULPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VMULPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VMULPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VMULPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VMULSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VMULSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VSUBPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VSUBPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VSUBPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VSUBPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VSUBSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup94], (instregex "VSUBSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup53], (instregex "ISTT_FP16m")>;<br>
+def: InstRW<[SKLWriteResGroup53], (instregex "ISTT_FP32m")>;<br>
+def: InstRW<[SKLWriteResGroup53], (instregex "ISTT_FP64m")>;<br>
+def: InstRW<[SKLWriteResGroup53], (instregex "IST_F16m")>;<br>
+def: InstRW<[SKLWriteResGroup53], (instregex "IST_F32m")>;<br>
+def: InstRW<[SKLWriteResGroup53], (instregex "IST_FP16m")>;<br>
+def: InstRW<[SKLWriteResGroup53], (instregex "IST_FP32m")>;<br>
+def: InstRW<[SKLWriteResGroup53], (instregex "IST_FP64m")>;<br>
<br>
-def SKLWriteResGroup96 : SchedWriteRes<[SKLPort23,<wbr>SKLPort015]> {<br>
- let Latency = 4;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "CMPPDrmi")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "CMPPSrmi")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "CMPSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "CVTDQ2PSrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "CVTPS2DQrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "CVTPS2PDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "CVTSS2SDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "CVTTPS2DQrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "MAXPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "MAXPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "MAXSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "MAXSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "MINPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "MINPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "MINSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "MINSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "MMX_CVTPS2PIirm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "MMX_CVTTPS2PIirm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "PHMINPOSUWrm128")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "PMADDUBSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "PMADDWDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "PMULDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "PMULHRSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "PMULHUWrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "PMULHWrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "PMULLWrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "PMULUDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCMPPDYrmi")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCMPPDrmi")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCMPPSYrmi")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCMPPSrmi")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCMPSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCMPSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTDQ2PSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTDQ2PSrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPH2PSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPH2PSrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPS2DQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPS2DQrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPS2PDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPS2PDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTSS2SDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTTPS2DQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTTPS2DQrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VMAXPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VMAXPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VMAXPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VMAXPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VMAXSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VMAXSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VMINPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VMINPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VMINPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VMINPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VMINSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VMINSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPHMINPOSUWrm128")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMADDUBSWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMADDUBSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMADDWDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMADDWDrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULDQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHRSWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHRSWrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHUWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHUWrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHWrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULLWYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULLWrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULUDQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULUDQrm")>;<br>
-<br>
-def SKLWriteResGroup97 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
- let Latency = 4;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [2,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup97], (instregex "FICOM16m")>;<br>
-def: InstRW<[SKLWriteResGroup97], (instregex "FICOM32m")>;<br>
-def: InstRW<[SKLWriteResGroup97], (instregex "FICOMP16m")>;<br>
-def: InstRW<[SKLWriteResGroup97], (instregex "FICOMP32m")>;<br>
-def: InstRW<[SKLWriteResGroup97], (instregex "MPSADBWrmi")>;<br>
-def: InstRW<[SKLWriteResGroup97], (instregex "VMPSADBWYrmi")>;<br>
-def: InstRW<[SKLWriteResGroup97], (instregex "VMPSADBWrmi")>;<br>
-<br>
-def SKLWriteResGroup98 : SchedWriteRes<[SKLPort1,<wbr>SKLPort5,SKLPort23]> {<br>
- let Latency = 4;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup98], (instregex "MULX64rm")>;<br>
-<br>
-def SKLWriteResGroup100 : SchedWriteRes<[SKLPort0156]> {<br>
+def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {<br>
let Latency = 4;<br>
let NumMicroOps = 4;<br>
let ResourceCycles = [4];<br>
}<br>
-def: InstRW<[SKLWriteResGroup100], (instregex "FNCLEX")>;<br>
+def: InstRW<[SKLWriteResGroup54], (instregex "FNCLEX")>;<br>
<br>
-def SKLWriteResGroup101 : SchedWriteRes<[SKLPort6,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,<wbr>SKLPort0156]> {<br>
let Latency = 4;<br>
let NumMicroOps = 4;<br>
let ResourceCycles = [1,3];<br>
}<br>
-def: InstRW<[SKLWriteResGroup101], (instregex "PAUSE")>;<br>
+def: InstRW<[SKLWriteResGroup55], (instregex "PAUSE")>;<br>
<br>
-def SKLWriteResGroup102 : SchedWriteRes<[SKLPort015,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,<wbr>SKLPort0156]> {<br>
let Latency = 4;<br>
let NumMicroOps = 4;<br>
let ResourceCycles = [1,3];<br>
}<br>
-def: InstRW<[SKLWriteResGroup102], (instregex "VZEROUPPER")>;<br>
+def: InstRW<[SKLWriteResGroup56], (instregex "VZEROUPPER")>;<br>
<br>
-def SKLWriteResGroup103 : SchedWriteRes<[SKLPort1,<wbr>SKLPort6,SKLPort0156]> {<br>
+def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,<wbr>SKLPort6,SKLPort0156]> {<br>
let Latency = 4;<br>
let NumMicroOps = 4;<br>
let ResourceCycles = [1,1,2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup103], (instregex "LAR(16|32|64)rr")>;<br>
-<br>
-def SKLWriteResGroup105 : SchedWriteRes<[SKLPort1,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
- let Latency = 4;<br>
- let NumMicroOps = 4;<br>
- let ResourceCycles = [1,1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup105], (instregex "SHLD(16|32|64)mri8")>;<br>
-def: InstRW<[SKLWriteResGroup105], (instregex "SHRD(16|32|64)mri8")>;<br>
-<br>
-def SKLWriteResGroup106 : SchedWriteRes<[SKLPort1,<wbr>SKLPort6,SKLPort23,<wbr>SKLPort0156]> {<br>
- let Latency = 4;<br>
- let NumMicroOps = 5;<br>
- let ResourceCycles = [1,2,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup106], (instregex "LAR(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup106], (instregex "LSL(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;<br>
<br>
-def SKLWriteResGroup107 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237,SKLPort0156]> {<br>
- let Latency = 4;<br>
- let NumMicroOps = 6;<br>
- let ResourceCycles = [1,1,4];<br>
+def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {<br>
+ let Latency = 5;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup107], (instregex "PUSHF16")>;<br>
-def: InstRW<[SKLWriteResGroup107], (instregex "PUSHF64")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVD64from64rm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVD64rm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVD64to64rm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVQ64rm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MOV(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MOV64toPQIrm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MOV8rm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVDDUPrm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVDI2PDIrm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm16")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm32")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm8")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVZX(16|32|64)rm16")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVZX(16|32|64)rm8")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "PREFETCHNTA")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "PREFETCHT0")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "PREFETCHT1")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "PREFETCHT2")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "VMOV64toPQIrm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "VMOVDDUPrm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "VMOVDI2PDIrm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "VMOVQI2PQIrm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "VMOVSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup58], (instregex "VMOVSSrm")>;<br>
<br>
-def SKLWriteResGroup109 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5]> {<br>
+def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5]> {<br>
let Latency = 5;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup109], (instregex "CVTDQ2PDrr")>;<br>
-def: InstRW<[SKLWriteResGroup109], (instregex "MMX_CVTPI2PDirr")>;<br>
-def: InstRW<[SKLWriteResGroup109], (instregex "VCVTDQ2PDrr")>;<br>
+def: InstRW<[SKLWriteResGroup59], (instregex "CVTDQ2PDrr")>;<br>
+def: InstRW<[SKLWriteResGroup59], (instregex "MMX_CVTPI2PDirr")>;<br>
+def: InstRW<[SKLWriteResGroup59], (instregex "VCVTDQ2PDrr")>;<br>
<br>
-def SKLWriteResGroup110 : SchedWriteRes<[SKLPort5,<wbr>SKLPort015]> {<br>
+def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,<wbr>SKLPort015]> {<br>
let Latency = 5;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTPD2DQrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTPD2PSrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTPS2PDrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTSD2SSrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTSI2SD64rr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTSI2SDrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTSI2SSrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTSS2SDrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTTPD2DQrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "MMX_CVTPD2PIirr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "MMX_CVTPS2PIirr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "MMX_CVTTPD2PIirr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "MMX_CVTTPS2PIirr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPD2DQrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPD2PSrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPH2PSrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPS2PDrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPS2PHrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSD2SSrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSI2SD64rr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSI2SDrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSI2SSrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSS2SDrr")>;<br>
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTTPD2DQrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTPD2DQrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTPD2PSrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTPS2PDrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTSD2SSrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTSI2SD64rr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTSI2SDrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTSI2SSrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTSS2SDrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTTPD2DQrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVTPD2PIirr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVTPS2PIirr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVTTPD2PIirr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVTTPS2PIirr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTPD2DQrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTPD2PSrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTPH2PSrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTPS2PDrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTPS2PHrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTSD2SSrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTSI2SD64rr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTSI2SDrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTSI2SSrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTSS2SDrr")>;<br>
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTTPD2DQrr")>;<br>
<br>
-def SKLWriteResGroup113 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
+def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,<wbr>SKLPort6,SKLPort06]> {<br>
let Latency = 5;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup113], (instregex "CVTDQ2PDrm")>;<br>
-def: InstRW<[SKLWriteResGroup113], (instregex "MMX_CVTPI2PDirm")>;<br>
-def: InstRW<[SKLWriteResGroup113], (instregex "VCVTDQ2PDrm")>;<br>
+def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;<br>
<br>
-def SKLWriteResGroup114 : SchedWriteRes<[SKLPort1,<wbr>SKLPort6,SKLPort06]> {<br>
+def SKLWriteResGroup62 : SchedWriteRes<[SKLPort1,<wbr>SKLPort06,SKLPort0156]> {<br>
let Latency = 5;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup114], (instregex "STR(16|32|64)r")>;<br>
+def: InstRW<[SKLWriteResGroup62], (instregex "IMUL32r")>;<br>
+def: InstRW<[SKLWriteResGroup62], (instregex "MUL32r")>;<br>
+def: InstRW<[SKLWriteResGroup62], (instregex "MULX32rr")>;<br>
<br>
-def SKLWriteResGroup115 : SchedWriteRes<[SKLPort1,<wbr>SKLPort06,SKLPort0156]> {<br>
+def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,<wbr>SKLPort0156]> {<br>
let Latency = 5;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,1,1];<br>
+ let NumMicroOps = 5;<br>
+ let ResourceCycles = [1,4];<br>
}<br>
-def: InstRW<[SKLWriteResGroup115], (instregex "IMUL32r")>;<br>
-def: InstRW<[SKLWriteResGroup115], (instregex "MUL32r")>;<br>
-def: InstRW<[SKLWriteResGroup115], (instregex "MULX32rr")>;<br>
+def: InstRW<[SKLWriteResGroup63], (instregex "XSETBV")>;<br>
<br>
-def SKLWriteResGroup116 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23,SKLPort015]> {<br>
+def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,<wbr>SKLPort0156]> {<br>
let Latency = 5;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,1,1];<br>
+ let NumMicroOps = 5;<br>
+ let ResourceCycles = [2,3];<br>
}<br>
-def: InstRW<[SKLWriteResGroup116], (instregex "CVTPD2DQrm")>;<br>
-def: InstRW<[SKLWriteResGroup116], (instregex "CVTPD2PSrm")>;<br>
-def: InstRW<[SKLWriteResGroup116], (instregex "CVTSD2SSrm")>;<br>
-def: InstRW<[SKLWriteResGroup116], (instregex "CVTTPD2DQrm")>;<br>
-def: InstRW<[SKLWriteResGroup116], (instregex "MMX_CVTPD2PIirm")>;<br>
-def: InstRW<[SKLWriteResGroup116], (instregex "MMX_CVTTPD2PIirm")>;<br>
-def: InstRW<[SKLWriteResGroup116], (instregex "VCVTSD2SSrm")>;<br>
+def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(16|32|64)rr")>;<br>
+def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG8rr")>;<br>
<br>
-def SKLWriteResGroup118 : SchedWriteRes<[SKLPort1,<wbr>SKLPort23,SKLPort06,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,<wbr>SKLPort237,SKLPort0156]> {<br>
let Latency = 5;<br>
- let NumMicroOps = 4;<br>
- let ResourceCycles = [1,1,1,1];<br>
+ let NumMicroOps = 6;<br>
+ let ResourceCycles = [1,1,4];<br>
}<br>
-def: InstRW<[SKLWriteResGroup118], (instregex "MULX32rm")>;<br>
+def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF16")>;<br>
+def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF64")>;<br>
<br>
-def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,<wbr>SKLPort5,SKLPort237,<wbr>SKLPort015]> {<br>
- let Latency = 5;<br>
- let NumMicroOps = 4;<br>
- let ResourceCycles = [1,1,1,1];<br>
+def SKLWriteResGroup66 : SchedWriteRes<[SKLPort5]> {<br>
+ let Latency = 6;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup119], (instregex "VCVTPS2PHmr")>;<br>
+def: InstRW<[SKLWriteResGroup66], (instregex "PCLMULQDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup66], (instregex "VPCLMULQDQrr")>;<br>
<br>
-def SKLWriteResGroup120 : SchedWriteRes<[SKLPort06,<wbr>SKLPort0156]> {<br>
- let Latency = 5;<br>
- let NumMicroOps = 5;<br>
- let ResourceCycles = [1,4];<br>
+def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {<br>
+ let Latency = 6;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup120], (instregex "XSETBV")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "LDDQUrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVAPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVAPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVDQArm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVDQUrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVNTDQArm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVSHDUPrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVSLDUPrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVUPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVUPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "VBROADCASTSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "VLDDQUrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVAPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVAPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVDQArm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVDQUrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVNTDQArm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVSHDUPrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVSLDUPrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVUPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVUPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "VPBROADCASTDrm")>;<br>
+def: InstRW<[SKLWriteResGroup67], (instregex "VPBROADCASTQrm")>;<br>
<br>
-def SKLWriteResGroup121 : SchedWriteRes<[SKLPort06,<wbr>SKLPort0156]> {<br>
- let Latency = 5;<br>
- let NumMicroOps = 5;<br>
- let ResourceCycles = [2,3];<br>
+def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {<br>
+ let Latency = 6;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup121], (instregex "CMPXCHG(16|32|64)rr")>;<br>
-def: InstRW<[SKLWriteResGroup121], (instregex "CMPXCHG8rr")>;<br>
+def: InstRW<[SKLWriteResGroup68], (instregex "MMX_CVTPI2PSirr")>;<br>
<br>
-def SKLWriteResGroup122 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort0156]> {<br>
- let Latency = 5;<br>
- let NumMicroOps = 8;<br>
- let ResourceCycles = [1,1,1,1,1,3];<br>
+def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 6;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup122], (instregex "ADD8mi")>;<br>
-def: InstRW<[SKLWriteResGroup122], (instregex "AND8mi")>;<br>
-def: InstRW<[SKLWriteResGroup122], (instregex "OR8mi")>;<br>
-def: InstRW<[SKLWriteResGroup122], (instregex "SUB8mi")>;<br>
-def: InstRW<[SKLWriteResGroup122], (instregex "XCHG(16|32|64)rm")>;<br>
-def: InstRW<[SKLWriteResGroup122], (instregex "XCHG8rm")>;<br>
-def: InstRW<[SKLWriteResGroup122], (instregex "XOR8mi")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSBirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSWirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDUSBirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDUSWirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PAVGBirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PAVGWirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PCMPEQBirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PCMPEQDirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PCMPEQWirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PCMPGTBirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PCMPGTDirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PCMPGTWirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PMAXSWirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PMAXUBirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PMINSWirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PMINUBirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSLLDrm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSLLQrm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSLLWrm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSRADrm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSRAWrm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSRLDrm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSRLQrm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSRLWrm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSUBSBirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSUBSWirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSUBUSBirm")>;<br>
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSUBUSWirm")>;<br>
<br>
-def SKLWriteResGroup123 : SchedWriteRes<[SKLPort5]> {<br>
+def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,<wbr>SKLPort015]> {<br>
let Latency = 6;<br>
- let NumMicroOps = 1;<br>
- let ResourceCycles = [1];<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup123], (instregex "PCLMULQDQrr")>;<br>
-def: InstRW<[SKLWriteResGroup123], (instregex "VPCLMULQDQrr")>;<br>
+def: InstRW<[SKLWriteResGroup70], (instregex "CVTSD2SI64rr")>;<br>
+def: InstRW<[SKLWriteResGroup70], (instregex "CVTSD2SIrr")>;<br>
+def: InstRW<[SKLWriteResGroup70], (instregex "CVTSS2SI64rr")>;<br>
+def: InstRW<[SKLWriteResGroup70], (instregex "CVTSS2SIrr")>;<br>
+def: InstRW<[SKLWriteResGroup70], (instregex "CVTTSD2SI64rr")>;<br>
+def: InstRW<[SKLWriteResGroup70], (instregex "CVTTSD2SIrr")>;<br>
+def: InstRW<[SKLWriteResGroup70], (instregex "VCVTSD2SI64rr")>;<br>
+def: InstRW<[SKLWriteResGroup70], (instregex "VCVTSD2SIrr")>;<br>
+def: InstRW<[SKLWriteResGroup70], (instregex "VCVTSS2SI64rr")>;<br>
+def: InstRW<[SKLWriteResGroup70], (instregex "VCVTSS2SIrr")>;<br>
+def: InstRW<[SKLWriteResGroup70], (instregex "VCVTTSD2SI64rr")>;<br>
+def: InstRW<[SKLWriteResGroup70], (instregex "VCVTTSD2SIrr")>;<br>
<br>
-def SKLWriteResGroup124 : SchedWriteRes<[SKLPort0]> {<br>
+def SKLWriteResGroup71 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
let Latency = 6;<br>
let NumMicroOps = 2;<br>
- let ResourceCycles = [2];<br>
+ let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup124], (instregex "MMX_CVTPI2PSirr")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PALIGNR64irm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PINSRWirmi")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PSHUFBrm64")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PSHUFWmi")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKHBWirm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKHDQirm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKHWDirm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKLBWirm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKLDQirm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKLWDirm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MOVHPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MOVHPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MOVLPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "MOVLPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PINSRBrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PINSRDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PINSRQrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PINSRWrmi")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXBDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXBQrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXBWrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXWDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXWQrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVZXBDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVZXBQrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVZXBWrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVZXDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVZXWDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVZXWQrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VMOVHPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VMOVHPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VMOVLPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VMOVLPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPINSRBrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPINSRDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPINSRQrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPINSRWrmi")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXBDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXBQrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXBWrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXWDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXWQrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVZXBDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVZXBQrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVZXBWrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVZXDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVZXWDrm")>;<br>
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVZXWQrm")>;<br>
<br>
-def SKLWriteResGroup125 : SchedWriteRes<[SKLPort0,<wbr>SKLPort015]> {<br>
+def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,<wbr>SKLPort23]> {<br>
let Latency = 6;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup125], (instregex "CVTSD2SI64rr")>;<br>
-def: InstRW<[SKLWriteResGroup125], (instregex "CVTSD2SIrr")>;<br>
-def: InstRW<[SKLWriteResGroup125], (instregex "CVTSS2SI64rr")>;<br>
-def: InstRW<[SKLWriteResGroup125], (instregex "CVTSS2SIrr")>;<br>
-def: InstRW<[SKLWriteResGroup125], (instregex "CVTTSD2SI64rr")>;<br>
-def: InstRW<[SKLWriteResGroup125], (instregex "CVTTSD2SIrr")>;<br>
-def: InstRW<[SKLWriteResGroup125], (instregex "VCVTSD2SI64rr")>;<br>
-def: InstRW<[SKLWriteResGroup125], (instregex "VCVTSD2SIrr")>;<br>
-def: InstRW<[SKLWriteResGroup125], (instregex "VCVTSS2SI64rr")>;<br>
-def: InstRW<[SKLWriteResGroup125], (instregex "VCVTSS2SIrr")>;<br>
-def: InstRW<[SKLWriteResGroup125], (instregex "VCVTTSD2SI64rr")>;<br>
-def: InstRW<[SKLWriteResGroup125], (instregex "VCVTTSD2SIrr")>;<br>
+def: InstRW<[SKLWriteResGroup72], (instregex "FARJMP64")>;<br>
+def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;<br>
<br>
-def SKLWriteResGroup126 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup73 : SchedWriteRes<[SKLPort23,<wbr>SKLPort05]> {<br>
let Latency = 6;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup126], (instregex "PCLMULQDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup126], (instregex "VPCLMULQDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSBrm64")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSDrm64")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSWrm64")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PADDBirm")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PADDDirm")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PADDQirm")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PADDWirm")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PANDNirm")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PANDirm")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PORirm")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSIGNBrm64")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSIGNDrm64")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSIGNWrm64")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSUBBirm")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSUBDirm")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSUBQirm")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSUBWirm")>;<br>
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PXORirm")>;<br>
<br>
-def SKLWriteResGroup127 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01]> {<br>
+def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,<wbr>SKLPort06]> {<br>
let Latency = 6;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [2,1];<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup127], (instregex "HADDPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup127], (instregex "HADDPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup127], (instregex "HSUBPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup127], (instregex "HSUBPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup127], (instregex "VHADDPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup127], (instregex "VHADDPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup127], (instregex "VHADDPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup127], (instregex "VHADDPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup127], (instregex "VHSUBPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup127], (instregex "VHSUBPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup127], (instregex "VHSUBPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup127], (instregex "VHSUBPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "ADC(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "ADC8rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "ADCX32rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "ADCX64rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "ADOX32rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "ADOX64rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVAE(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVB(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVE(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVG(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVGE(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVL(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVLE(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVNE(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVNO(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVNP(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVNS(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVO(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVP(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVS(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "RORX32mi")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "RORX64mi")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "SARX32rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "SARX64rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "SBB(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "SBB8rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "SHLX32rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "SHLX64rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "SHRX32rm")>;<br>
+def: InstRW<[SKLWriteResGroup74], (instregex "SHRX64rm")>;<br>
<br>
-def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,<wbr>SKLPort15]> {<br>
let Latency = 6;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [2,1];<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup75], (instregex "ANDN32rm")>;<br>
+def: InstRW<[SKLWriteResGroup75], (instregex "ANDN64rm")>;<br>
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSI32rm")>;<br>
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSI64rm")>;<br>
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSMSK32rm")>;<br>
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSMSK64rm")>;<br>
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSR32rm")>;<br>
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSR64rm")>;<br>
+def: InstRW<[SKLWriteResGroup75], (instregex "BZHI32rm")>;<br>
+def: InstRW<[SKLWriteResGroup75], (instregex "BZHI64rm")>;<br>
+def: InstRW<[SKLWriteResGroup75], (instregex "MOVBE(16|32|64)rm")>;<br>
+<br>
+def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,<wbr>SKLPort0156]> {<br>
+ let Latency = 6;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup128], (instregex "ADD_FI16m")>;<br>
-def: InstRW<[SKLWriteResGroup128], (instregex "ADD_FI32m")>;<br>
-def: InstRW<[SKLWriteResGroup128], (instregex "SUBR_FI16m")>;<br>
-def: InstRW<[SKLWriteResGroup128], (instregex "SUBR_FI32m")>;<br>
-def: InstRW<[SKLWriteResGroup128], (instregex "SUB_FI16m")>;<br>
-def: InstRW<[SKLWriteResGroup128], (instregex "SUB_FI32m")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "ADD(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "ADD8rm")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "AND(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "AND8rm")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)mi8")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)mr")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP8mi")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP8mr")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP8rm")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "OR(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "OR8rm")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)r")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "SUB(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "SUB8rm")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "TEST(16|32|64)mr")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "TEST8mi")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "TEST8mr")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "XOR(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup76], (instregex "XOR8rm")>;<br>
<br>
-def SKLWriteResGroup129 : SchedWriteRes<[SKLPort5,<wbr>SKLPort015]> {<br>
+def SKLWriteResGroup77 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01]> {<br>
let Latency = 6;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [2,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup129], (instregex "CVTSI2SS64rr")>;<br>
-def: InstRW<[SKLWriteResGroup129], (instregex "VCVTSI2SS64rr")>;<br>
+def: InstRW<[SKLWriteResGroup77], (instregex "HADDPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup77], (instregex "HADDPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup77], (instregex "HSUBPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup77], (instregex "HSUBPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup77], (instregex "VHADDPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup77], (instregex "VHADDPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup77], (instregex "VHADDPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup77], (instregex "VHADDPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup77], (instregex "VHSUBPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup77], (instregex "VHSUBPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup77], (instregex "VHSUBPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup77], (instregex "VHSUBPSrr")>;<br>
<br>
-def SKLWriteResGroup130 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23,SKLPort015]> {<br>
+def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,<wbr>SKLPort015]> {<br>
let Latency = 6;<br>
let NumMicroOps = 3;<br>
- let ResourceCycles = [1,1,1];<br>
+ let ResourceCycles = [2,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTSD2SI64rm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTSD2SIrm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTSS2SI64rm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTSS2SIrm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTTSD2SI64rm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTTSD2SIrm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTTSS2SIrm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTSD2SI64rm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTSD2SIrm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTSS2SI64rm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTSS2SIrm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTTSD2SI64rm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTTSD2SIrm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTTSS2SI64rm")>;<br>
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTTSS2SIrm")>;<br>
+def: InstRW<[SKLWriteResGroup78], (instregex "CVTSI2SS64rr")>;<br>
+def: InstRW<[SKLWriteResGroup78], (instregex "VCVTSI2SS64rr")>;<br>
<br>
-def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,<wbr>SKLPort06,SKLPort0156]> {<br>
+def SKLWriteResGroup79 : SchedWriteRes<[SKLPort1,<wbr>SKLPort06,SKLPort0156]> {<br>
let Latency = 6;<br>
let NumMicroOps = 4;<br>
let ResourceCycles = [1,2,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup131], (instregex "SHLD(16|32|64)rrCL")>;<br>
-def: InstRW<[SKLWriteResGroup131], (instregex "SHRD(16|32|64)rrCL")>;<br>
+def: InstRW<[SKLWriteResGroup79], (instregex "SHLD(16|32|64)rrCL")>;<br>
+def: InstRW<[SKLWriteResGroup79], (instregex "SHRD(16|32|64)rrCL")>;<br>
<br>
-def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01,SKLPort23]> {<br>
+def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,<wbr>SKLPort6,SKLPort06,<wbr>SKLPort0156]> {<br>
let Latency = 6;<br>
let NumMicroOps = 4;<br>
- let ResourceCycles = [2,1,1];<br>
+ let ResourceCycles = [1,1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup133], (instregex "HADDPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup133], (instregex "HADDPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup133], (instregex "HSUBPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup133], (instregex "HSUBPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup133], (instregex "VHADDPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup133], (instregex "VHADDPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup133], (instregex "VHADDPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup133], (instregex "VHADDPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup133], (instregex "VHSUBPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup133], (instregex "VHSUBPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup133], (instregex "VHSUBPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup133], (instregex "VHSUBPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;<br>
<br>
-def SKLWriteResGroup134 : SchedWriteRes<[SKLPort1,<wbr>SKLPort6,SKLPort06,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup81 : SchedWriteRes<[SKLPort4,<wbr>SKLPort5,SKLPort237,<wbr>SKLPort015]> {<br>
let Latency = 6;<br>
let NumMicroOps = 4;<br>
let ResourceCycles = [1,1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup134], (instregex "SLDT(16|32|64)r")>;<br>
+def: InstRW<[SKLWriteResGroup81], (instregex "VCVTPS2PHmr")>;<br>
<br>
-def SKLWriteResGroup136 : SchedWriteRes<[SKLPort6,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06]> {<br>
let Latency = 6;<br>
- let NumMicroOps = 6;<br>
- let ResourceCycles = [1,5];<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [1,1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup136], (instregex "STD")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "BTC(16|32|64)mi8")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "BTR(16|32|64)mi8")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "BTS(16|32|64)mi8")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "SAR(16|32|64)m1")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "SAR(16|32|64)mi")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "SAR8m1")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "SAR8mi")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "SHL(16|32|64)m1")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "SHL(16|32|64)mi")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "SHL8m1")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "SHL8mi")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "SHR(16|32|64)m1")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "SHR(16|32|64)mi")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "SHR8m1")>;<br>
+def: InstRW<[SKLWriteResGroup82], (instregex "SHR8mi")>;<br>
<br>
-def SKLWriteResGroup137 : SchedWriteRes<[SKLPort1,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort0156]> {<br>
+def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
+ let Latency = 6;<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [1,1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "ADD(16|32|64)mi8")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "ADD(16|32|64)mr")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "ADD8mi")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "ADD8mr")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "AND(16|32|64)mi8")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "AND(16|32|64)mr")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "AND8mi")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "AND8mr")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "DEC(16|32|64)m")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "DEC8m")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "INC(16|32|64)m")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "INC8m")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "NEG(16|32|64)m")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "NEG8m")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "NOT(16|32|64)m")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "NOT8m")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "OR(16|32|64)mi8")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "OR(16|32|64)mr")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "OR8mi")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "OR8mr")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "PUSH(16|32|64)rmm")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "SUB(16|32|64)mi8")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "SUB(16|32|64)mr")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "SUB8mi")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "SUB8mr")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "XOR(16|32|64)mi8")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "XOR(16|32|64)mr")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "XOR8mi")>;<br>
+def: InstRW<[SKLWriteResGroup83], (instregex "XOR8mr")>;<br>
+<br>
+def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,<wbr>SKLPort0156]> {<br>
let Latency = 6;<br>
let NumMicroOps = 6;<br>
- let ResourceCycles = [1,1,1,2,1];<br>
+ let ResourceCycles = [1,5];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup84], (instregex "STD")>;<br>
+<br>
+def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {<br>
+ let Latency = 7;<br>
+ let NumMicroOps = 1;<br>
+ let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup137], (instregex "SHLD(16|32|64)mrCL")>;<br>
-def: InstRW<[SKLWriteResGroup137], (instregex "SHRD(16|32|64)mrCL")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "LD_F32m")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "LD_F64m")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "LD_F80m")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VBROADCASTF128")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VBROADCASTI128")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VBROADCASTSDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VBROADCASTSSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VLDDQUYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVAPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVAPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVDDUPYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVDQAYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVDQUYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVNTDQAYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVSHDUPYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVSLDUPYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVUPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVUPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VPBROADCASTDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup85], (instregex "VPBROADCASTQYrm")>;<br>
<br>
-def SKLWriteResGroup142 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5]> {<br>
+def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5]> {<br>
let Latency = 7;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup142], (instregex "VCVTDQ2PDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup86], (instregex "VCVTDQ2PDYrr")>;<br>
<br>
-def SKLWriteResGroup143 : SchedWriteRes<[SKLPort5,<wbr>SKLPort015]> {<br>
+def SKLWriteResGroup87 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
let Latency = 7;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPD2DQYrr")>;<br>
-def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPD2PSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPH2PSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPS2PDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPS2PHYrr")>;<br>
-def: InstRW<[SKLWriteResGroup143], (instregex "VCVTTPD2DQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup87], (instregex "COMISDrm")>;<br>
+def: InstRW<[SKLWriteResGroup87], (instregex "COMISSrm")>;<br>
+def: InstRW<[SKLWriteResGroup87], (instregex "UCOMISDrm")>;<br>
+def: InstRW<[SKLWriteResGroup87], (instregex "UCOMISSrm")>;<br>
+def: InstRW<[SKLWriteResGroup87], (instregex "VCOMISDrm")>;<br>
+def: InstRW<[SKLWriteResGroup87], (instregex "VCOMISSrm")>;<br>
+def: InstRW<[SKLWriteResGroup87], (instregex "VUCOMISDrm")>;<br>
+def: InstRW<[SKLWriteResGroup87], (instregex "VUCOMISSrm")>;<br>
+<br>
+def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
+ let Latency = 7;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "INSERTPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PACKSSDWrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PACKSSWBrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PACKUSDWrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PACKUSWBrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PALIGNRrmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PBLENDWrmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PSHUFBrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PSHUFDmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PSHUFHWmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PSHUFLWmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKHBWrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKHDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKHQDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKHWDrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKLBWrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKLDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKLQDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKLWDrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "SHUFPDrmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "SHUFPSrmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "UNPCKHPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "UNPCKHPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "UNPCKLPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "UNPCKLPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VINSERTPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPACKSSDWrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPACKSSWBrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPACKUSDWrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPACKUSWBrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPALIGNRrmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPBLENDWrmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPBROADCASTBrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPBROADCASTWrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPERMILPDmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPERMILPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPERMILPSmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPERMILPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPSHUFBrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPSHUFDmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPSHUFHWmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPSHUFLWmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKHBWrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKHDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKHQDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKHWDrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKLBWrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKLDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKLQDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKLWDrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VSHUFPDrmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VSHUFPSrmi")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VUNPCKHPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VUNPCKHPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VUNPCKLPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup88], (instregex "VUNPCKLPSrm")>;<br>
+<br>
+def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,<wbr>SKLPort015]> {<br>
+ let Latency = 7;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2DQYrr")>;<br>
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2PSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPH2PSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPS2PDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPS2PHYrr")>;<br>
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTTPD2DQYrr")>;<br>
+<br>
+def SKLWriteResGroup90 : SchedWriteRes<[SKLPort01,<wbr>SKLPort23]> {<br>
+ let Latency = 7;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PABSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PABSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PABSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PADDSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PADDSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PADDUSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PADDUSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PAVGBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PAVGWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPEQBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPEQDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPEQQrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPEQWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPGTBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPGTDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPGTWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PMAXSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PMAXSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PMAXSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PMAXUBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PMAXUDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PMAXUWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PMINSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PMINSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PMINSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PMINUBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PMINUDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PMINUWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSIGNBrm128")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSIGNDrm128")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSIGNWrm128")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSLLDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSLLQrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSLLWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSRADrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSRAWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSRLDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSRLQrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSRLWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSUBSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSUBSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSUBUSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "PSUBUSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPABSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPABSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPABSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPADDSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPADDSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPADDUSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPADDUSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPAVGBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPAVGWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPEQBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPEQDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPEQQrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPEQWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPGTBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPGTDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPGTWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMAXSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMAXSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMAXSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMAXUBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMAXUDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMAXUWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMINSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMINSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMINSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMINUBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMINUDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMINUWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSIGNBrm128")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSIGNDrm128")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSIGNWrm128")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSLLDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSLLQrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSLLVDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSLLVQrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSLLWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRADrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRAVDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRAWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRLDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRLQrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRLVDrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRLVQrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRLWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSUBSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSUBSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSUBUSBrm")>;<br>
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSUBUSWrm")>;<br>
+<br>
+def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,<wbr>SKLPort015]> {<br>
+ let Latency = 7;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "ANDNPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "ANDNPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "ANDPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "ANDPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "BLENDPDrmi")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "BLENDPSrmi")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "ORPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "ORPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "PADDBrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "PADDDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "PADDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "PADDWrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "PANDNrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "PANDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "PORrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "PSUBBrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "PSUBDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "PSUBQrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "PSUBWrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "PXORrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VANDNPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VANDNPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VANDPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VANDPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VBLENDPDrmi")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VBLENDPSrmi")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VINSERTF128rm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VINSERTI128rm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VMASKMOVPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VMASKMOVPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VORPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VORPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPADDBrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPADDDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPADDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPADDWrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPANDNrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPANDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPBLENDDrmi")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPMASKMOVDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPMASKMOVQrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPORrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPSUBBrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPSUBDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPSUBQrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPSUBWrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VPXORrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VXORPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "VXORPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "XORPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup91], (instregex "XORPSrm")>;<br>
+<br>
+def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
+ let Latency = 7;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [2,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKSSDWirm")>;<br>
+def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKSSWBirm")>;<br>
+def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKUSWBirm")>;<br>
<br>
-def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
+def SKLWriteResGroup93 : SchedWriteRes<[SKLPort23,<wbr>SKLPort06]> {<br>
+ let Latency = 7;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,2];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup93], (instregex "CMOVA(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup93], (instregex "CMOVBE(16|32|64)rm")>;<br>
+<br>
+def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,<wbr>SKLPort0156]> {<br>
+ let Latency = 7;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,2];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup94], (instregex "LEAVE64")>;<br>
+def: InstRW<[SKLWriteResGroup94], (instregex "SCASB")>;<br>
+def: InstRW<[SKLWriteResGroup94], (instregex "SCASL")>;<br>
+def: InstRW<[SKLWriteResGroup94], (instregex "SCASQ")>;<br>
+def: InstRW<[SKLWriteResGroup94], (instregex "SCASW")>;<br>
+<br>
+def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort015]> {<br>
let Latency = 7;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup145], (instregex "MUL_FI16m")>;<br>
-def: InstRW<[SKLWriteResGroup145], (instregex "MUL_FI32m")>;<br>
-def: InstRW<[SKLWriteResGroup145], (instregex "VCVTDQ2PDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup95], (instregex "CVTTSS2SI64rr")>;<br>
+def: InstRW<[SKLWriteResGroup95], (instregex "CVTTSS2SIrr")>;<br>
+def: InstRW<[SKLWriteResGroup95], (instregex "VCVTTSS2SI64rr")>;<br>
+def: InstRW<[SKLWriteResGroup95], (instregex "VCVTTSS2SIrr")>;<br>
<br>
-def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort015]> {<br>
+def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23,SKLPort05]> {<br>
let Latency = 7;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup146], (instregex "CVTTSS2SI64rr")>;<br>
-def: InstRW<[SKLWriteResGroup146], (instregex "CVTTSS2SIrr")>;<br>
-def: InstRW<[SKLWriteResGroup146], (instregex "VCVTTSS2SI64rr")>;<br>
-def: InstRW<[SKLWriteResGroup146], (instregex "VCVTTSS2SIrr")>;<br>
+def: InstRW<[SKLWriteResGroup96], (instregex "FLDCW16m")>;<br>
<br>
-def SKLWriteResGroup149 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23,SKLPort015]<wbr>> {<br>
+def SKLWriteResGroup97 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23,SKLPort0156]> {<br>
let Latency = 7;<br>
- let NumMicroOps = 4;<br>
- let ResourceCycles = [1,1,1,1];<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup149], (instregex "CVTTSS2SI64rm")>;<br>
+def: InstRW<[SKLWriteResGroup97], (instregex "LDMXCSR")>;<br>
+def: InstRW<[SKLWriteResGroup97], (instregex "VLDMXCSR")>;<br>
<br>
-def SKLWriteResGroup150 : SchedWriteRes<[SKLPort4,<wbr>SKLPort5,SKLPort237,<wbr>SKLPort015]> {<br>
+def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,<wbr>SKLPort23,SKLPort0156]> {<br>
let Latency = 7;<br>
- let NumMicroOps = 4;<br>
- let ResourceCycles = [1,1,1,1];<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup98], (instregex "LRETQ")>;<br>
+def: InstRW<[SKLWriteResGroup98], (instregex "RETQ")>;<br>
+<br>
+def SKLWriteResGroup99 : SchedWriteRes<[SKLPort23,<wbr>SKLPort06,SKLPort15]> {<br>
+ let Latency = 7;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup99], (instregex "BEXTR32rm")>;<br>
+def: InstRW<[SKLWriteResGroup99], (instregex "BEXTR64rm")>;<br>
+<br>
+def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06]> {<br>
+ let Latency = 7;<br>
+ let NumMicroOps = 5;<br>
+ let ResourceCycles = [1,1,1,2];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup100], (instregex "ROL(16|32|64)m1")>;<br>
+def: InstRW<[SKLWriteResGroup100], (instregex "ROL(16|32|64)mi")>;<br>
+def: InstRW<[SKLWriteResGroup100], (instregex "ROL8m1")>;<br>
+def: InstRW<[SKLWriteResGroup100], (instregex "ROL8mi")>;<br>
+def: InstRW<[SKLWriteResGroup100], (instregex "ROR(16|32|64)m1")>;<br>
+def: InstRW<[SKLWriteResGroup100], (instregex "ROR(16|32|64)mi")>;<br>
+def: InstRW<[SKLWriteResGroup100], (instregex "ROR8m1")>;<br>
+def: InstRW<[SKLWriteResGroup100], (instregex "ROR8mi")>;<br>
+<br>
+def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
+ let Latency = 7;<br>
+ let NumMicroOps = 5;<br>
+ let ResourceCycles = [1,1,1,2];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup101], (instregex "XADD(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup101], (instregex "XADD8rm")>;<br>
+<br>
+def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
+ let Latency = 7;<br>
+ let NumMicroOps = 5;<br>
+ let ResourceCycles = [1,1,1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup150], (instregex "VCVTPS2PHYmr")>;<br>
+def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>;<br>
+def: InstRW<[SKLWriteResGroup102], (instregex "FARCALL64")>;<br>
<br>
-def SKLWriteResGroup151 : SchedWriteRes<[SKLPort6,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
let Latency = 7;<br>
let NumMicroOps = 7;<br>
let ResourceCycles = [1,3,1,2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup151], (instregex "LOOP")>;<br>
+def: InstRW<[SKLWriteResGroup103], (instregex "LOOP")>;<br>
<br>
-def SKLWriteResGroup156 : SchedWriteRes<[SKLPort0]> {<br>
+def SKLWriteResGroup104 : SchedWriteRes<[SKLPort0]> {<br>
let Latency = 8;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup156], (instregex "AESIMCrr")>;<br>
-def: InstRW<[SKLWriteResGroup156], (instregex "VAESIMCrr")>;<br>
+def: InstRW<[SKLWriteResGroup104], (instregex "AESIMCrr")>;<br>
+def: InstRW<[SKLWriteResGroup104], (instregex "VAESIMCrr")>;<br>
<br>
-def SKLWriteResGroup157 : SchedWriteRes<[SKLPort015]> {<br>
+def SKLWriteResGroup105 : SchedWriteRes<[SKLPort015]> {<br>
let Latency = 8;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup157], (instregex "PMULLDrr")>;<br>
-def: InstRW<[SKLWriteResGroup157], (instregex "ROUNDPDr")>;<br>
-def: InstRW<[SKLWriteResGroup157], (instregex "ROUNDPSr")>;<br>
-def: InstRW<[SKLWriteResGroup157], (instregex "ROUNDSDr")>;<br>
-def: InstRW<[SKLWriteResGroup157], (instregex "ROUNDSSr")>;<br>
-def: InstRW<[SKLWriteResGroup157], (instregex "VPMULLDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup157], (instregex "VPMULLDrr")>;<br>
-def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDPDr")>;<br>
-def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDPSr")>;<br>
-def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDSDr")>;<br>
-def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDSSr")>;<br>
-def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDYPDr")>;<br>
-def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDYPSr")>;<br>
+def: InstRW<[SKLWriteResGroup105], (instregex "PMULLDrr")>;<br>
+def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDPDr")>;<br>
+def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDPSr")>;<br>
+def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDSDr")>;<br>
+def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDSSr")>;<br>
+def: InstRW<[SKLWriteResGroup105], (instregex "VPMULLDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup105], (instregex "VPMULLDrr")>;<br>
+def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDPDr")>;<br>
+def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDPSr")>;<br>
+def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDSDr")>;<br>
+def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDSSr")>;<br>
+def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDYPDr")>;<br>
+def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDYPSr")>;<br>
+<br>
+def SKLWriteResGroup106 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup106], (instregex "VTESTPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup106], (instregex "VTESTPSrm")>;<br>
+<br>
+def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,<wbr>SKLPort23]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "BSF(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "BSR(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "IMUL64m")>;<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "IMUL(32|64)rm(i8?)")>;<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "IMUL8m")>;<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "LZCNT(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "MUL(16|32|64)m")>;<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "MUL8m")>;<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "PDEP32rm")>;<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "PDEP64rm")>;<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "PEXT32rm")>;<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "PEXT64rm")>;<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "POPCNT(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup107], (instregex "TZCNT(16|32|64)rm")>;<br>
+<br>
+def SKLWriteResGroup107_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {<br>
+ let Latency = 3;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup107_<wbr>16], (instregex "IMUL16rm(i8?)")>;<br>
+<br>
+def SKLWriteResGroup107_16_2 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {<br>
+ let Latency = 3;<br>
+ let NumMicroOps = 5;<br>
+}<br>
+def: InstRW<[SKLWriteResGroup107_<wbr>16_2], (instregex "IMUL16m")>;<br>
+def: InstRW<[SKLWriteResGroup107_<wbr>16_2], (instregex "MUL16m")>;<br>
+<br>
+def SKLWriteResGroup107_32 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {<br>
+ let Latency = 3;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup107_<wbr>32], (instregex "IMUL32m")>;<br>
+def: InstRW<[SKLWriteResGroup107_<wbr>32], (instregex "MUL32m")>;<br>
+<br>
+def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "FCOM32m")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "FCOM64m")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "FCOMP32m")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "FCOMP64m")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "MMX_PSADBWirm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPACKSSDWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPACKSSWBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPACKUSDWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPACKUSWBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPALIGNRYrmi")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPBLENDWYrmi")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPBROADCASTBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPBROADCASTWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPERMILPDYmi")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPERMILPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPERMILPSYmi")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPERMILPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPMOVSXBDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPMOVSXBQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPMOVSXWQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPSHUFBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPSHUFDYmi")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPSHUFHWYmi")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPSHUFLWYmi")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKHBWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKHDQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKHQDQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKHWDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKLBWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKLDQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKLQDQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKLWDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VSHUFPDYrmi")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VSHUFPSYrmi")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VUNPCKHPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VUNPCKHPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VUNPCKLPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup108], (instregex "VUNPCKLPSYrm")>;<br>
+<br>
+def SKLWriteResGroup109 : SchedWriteRes<[SKLPort01,<wbr>SKLPort23]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPABSBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPABSDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPABSWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPADDSBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPADDSWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPADDUSBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPADDUSWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPAVGBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPAVGWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPEQBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPEQDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPEQQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPEQWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPGTBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPGTDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPGTWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMAXSBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMAXSDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMAXSWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMAXUBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMAXUDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMAXUWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMINSBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMINSDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMINSWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMINUBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMINUDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMINUWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSIGNBYrm256")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSIGNDYrm256")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSIGNWYrm256")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSLLDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSLLQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSLLVDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSLLVQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSLLWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRADYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRAVDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRAWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRLDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRLQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRLVDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRLVQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRLWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSUBSBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSUBSWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSUBUSBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSUBUSWYrm")>;<br>
+<br>
+def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,<wbr>SKLPort015]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VANDNPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VANDNPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VANDPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VANDPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VBLENDPDYrmi")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VBLENDPSYrmi")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VMASKMOVPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VMASKMOVPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VORPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VORPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPADDBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPADDDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPADDQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPADDWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPANDNYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPANDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPBLENDDYrmi")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPMASKMOVDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPMASKMOVQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPORYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPSUBBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPSUBDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPSUBQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPSUBWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VPXORYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VXORPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup110], (instregex "VXORPSYrm")>;<br>
+<br>
+def SKLWriteResGroup111 : SchedWriteRes<[SKLPort23,<wbr>SKLPort015]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,2];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup111], (instregex "BLENDVPDrm0")>;<br>
+def: InstRW<[SKLWriteResGroup111], (instregex "BLENDVPSrm0")>;<br>
+def: InstRW<[SKLWriteResGroup111], (instregex "PBLENDVBrm0")>;<br>
+def: InstRW<[SKLWriteResGroup111], (instregex "VBLENDVPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup111], (instregex "VBLENDVPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup111], (instregex "VPBLENDVBYrm")>;<br>
+def: InstRW<[SKLWriteResGroup111], (instregex "VPBLENDVBrm")>;<br>
+<br>
+def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [1,2,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PHADDSWrm64")>;<br>
+def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PHSUBSWrm64")>;<br>
+<br>
+def SKLWriteResGroup113 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23,SKLPort05]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [2,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDWrm64")>;<br>
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDrm64")>;<br>
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHSUBDrm64")>;<br>
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHSUBWrm64")>;<br>
+<br>
+def SKLWriteResGroup114 : SchedWriteRes<[SKLPort4,<wbr>SKLPort5,SKLPort237,<wbr>SKLPort015]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [1,1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup114], (instregex "VCVTPS2PHYmr")>;<br>
+<br>
+def SKLWriteResGroup115 : SchedWriteRes<[SKLPort23,<wbr>SKLPort237,SKLPort06]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 5;<br>
+ let ResourceCycles = [1,1,3];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup115], (instregex "ROR(16|32|64)mCL")>;<br>
+def: InstRW<[SKLWriteResGroup115], (instregex "ROR8mCL")>;<br>
+<br>
+def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,<wbr>SKLPort237,SKLPort06,<wbr>SKLPort0156]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 5;<br>
+ let ResourceCycles = [1,1,1,2];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup116], (instregex "RCL(16|32|64)m1")>;<br>
+def: InstRW<[SKLWriteResGroup116], (instregex "RCL(16|32|64)mi")>;<br>
+def: InstRW<[SKLWriteResGroup116], (instregex "RCL8m1")>;<br>
+def: InstRW<[SKLWriteResGroup116], (instregex "RCL8mi")>;<br>
+def: InstRW<[SKLWriteResGroup116], (instregex "RCR(16|32|64)m1")>;<br>
+def: InstRW<[SKLWriteResGroup116], (instregex "RCR(16|32|64)mi")>;<br>
+def: InstRW<[SKLWriteResGroup116], (instregex "RCR8m1")>;<br>
+def: InstRW<[SKLWriteResGroup116], (instregex "RCR8mi")>;<br>
+<br>
+def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 6;<br>
+ let ResourceCycles = [1,1,1,3];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup117], (instregex "ROL(16|32|64)mCL")>;<br>
+def: InstRW<[SKLWriteResGroup117], (instregex "ROL8mCL")>;<br>
+def: InstRW<[SKLWriteResGroup117], (instregex "SAR(16|32|64)mCL")>;<br>
+def: InstRW<[SKLWriteResGroup117], (instregex "SAR8mCL")>;<br>
+def: InstRW<[SKLWriteResGroup117], (instregex "SHL(16|32|64)mCL")>;<br>
+def: InstRW<[SKLWriteResGroup117], (instregex "SHL8mCL")>;<br>
+def: InstRW<[SKLWriteResGroup117], (instregex "SHR(16|32|64)mCL")>;<br>
+def: InstRW<[SKLWriteResGroup117], (instregex "SHR8mCL")>;<br>
+<br>
+def SKLWriteResGroup118 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 6;<br>
+ let ResourceCycles = [1,1,1,3];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup118], (instregex "ADC(16|32|64)mi8")>;<br>
+def: InstRW<[SKLWriteResGroup118], (instregex "ADC8mi")>;<br>
+<br>
+def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort0156]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 6;<br>
+ let ResourceCycles = [1,1,1,2,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup119], (instregex "ADC(16|32|64)mr")>;<br>
+def: InstRW<[SKLWriteResGroup119], (instregex "ADC8mr")>;<br>
+def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG8rm")>;<br>
+def: InstRW<[SKLWriteResGroup119], (instregex "SBB(16|32|64)mi8")>;<br>
+def: InstRW<[SKLWriteResGroup119], (instregex "SBB(16|32|64)mr")>;<br>
+def: InstRW<[SKLWriteResGroup119], (instregex "SBB8mi")>;<br>
+def: InstRW<[SKLWriteResGroup119], (instregex "SBB8mr")>;<br>
+<br>
+def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 9;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_CVTPI2PSirm")>;<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMADDUBSWrm64")>;<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMADDWDirm")>;<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULHRSWrm64")>;<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULHUWirm")>;<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULHWirm")>;<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULLWirm")>;<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULUDQirm")>;<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "RCPSSm")>;<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "RSQRTSSm")>;<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "VRCPSSm")>;<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "VRSQRTSSm")>;<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "VTESTPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup120], (instregex "VTESTPSYrm")>;<br>
+<br>
+def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
+ let Latency = 9;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup121], (instregex "PCMPGTQrm")>;<br>
+def: InstRW<[SKLWriteResGroup121], (instregex "PSADBWrm")>;<br>
+def: InstRW<[SKLWriteResGroup121], (instregex "VPCMPGTQrm")>;<br>
+def: InstRW<[SKLWriteResGroup121], (instregex "VPMOVSXBWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup121], (instregex "VPMOVSXDQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup121], (instregex "VPMOVSXWDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup121], (instregex "VPMOVZXWDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup121], (instregex "VPSADBWrm")>;<br>
+<br>
+def SKLWriteResGroup122 : SchedWriteRes<[SKLPort01,<wbr>SKLPort23]> {<br>
+ let Latency = 9;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "ADDSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "ADDSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "MULSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "MULSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "SUBSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "SUBSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VADDSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VADDSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMADD132SDm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMADD132SSm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMADD213SDm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMADD213SSm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMADD231SDm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMADD231SSm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMSUB132SDm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMSUB132SSm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMSUB213SDm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMSUB213SSm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMSUB231SDm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMSUB231SSm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMADD132SDm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMADD132SSm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMADD213SDm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMADD213SSm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMADD231SDm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMADD231SSm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMSUB132SDm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMSUB132SSm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMSUB213SDm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMSUB213SSm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMSUB231SDm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMSUB231SSm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VMULSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VMULSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VSUBSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup122], (instregex "VSUBSSrm")>;<br>
+<br>
+def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,<wbr>SKLPort015]> {<br>
+ let Latency = 9;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "CMPSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "CVTPS2PDrm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "MAXSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "MAXSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "MINSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "MINSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVTPS2PIirm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVTTPS2PIirm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "VCMPSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "VCMPSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "VCVTPH2PSrm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "VCVTPS2PDrm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "VMAXSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "VMAXSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "VMINSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup123], (instregex "VMINSSrm")>;<br>
+<br>
+def SKLWriteResGroup124 : SchedWriteRes<[SKLPort5,<wbr>SKLPort015]> {<br>
+ let Latency = 9;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,2];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup124], (instregex "DPPDrri")>;<br>
+def: InstRW<[SKLWriteResGroup124], (instregex "VDPPDrri")>;<br>
+<br>
+def SKLWriteResGroup125 : SchedWriteRes<[SKLPort23,<wbr>SKLPort015]> {<br>
+ let Latency = 9;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,2];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup125], (instregex "VBLENDVPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup125], (instregex "VBLENDVPSYrm")>;<br>
+<br>
+def SKLWriteResGroup126 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
+ let Latency = 9;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup126], (instregex "PTESTrm")>;<br>
+def: InstRW<[SKLWriteResGroup126], (instregex "VPTESTrm")>;<br>
+<br>
+def SKLWriteResGroup127 : SchedWriteRes<[SKLPort1,<wbr>SKLPort5,SKLPort23]> {<br>
+ let Latency = 9;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup127], (instregex "MULX64rm")>;<br>
+<br>
+def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01,SKLPort23]> {<br>
+ let Latency = 9;<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [2,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup128], (instregex "PHADDSWrm128")>;<br>
+def: InstRW<[SKLWriteResGroup128], (instregex "PHSUBSWrm128")>;<br>
+def: InstRW<[SKLWriteResGroup128], (instregex "VPHADDSWrm128")>;<br>
+def: InstRW<[SKLWriteResGroup128], (instregex "VPHSUBSWrm128")>;<br>
+<br>
+def SKLWriteResGroup129 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23,SKLPort015]> {<br>
+ let Latency = 9;<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [2,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup129], (instregex "PHADDDrm")>;<br>
+def: InstRW<[SKLWriteResGroup129], (instregex "PHADDWrm")>;<br>
+def: InstRW<[SKLWriteResGroup129], (instregex "PHSUBDrm")>;<br>
+def: InstRW<[SKLWriteResGroup129], (instregex "PHSUBWrm")>;<br>
+def: InstRW<[SKLWriteResGroup129], (instregex "VPHADDDrm")>;<br>
+def: InstRW<[SKLWriteResGroup129], (instregex "VPHADDWrm")>;<br>
+def: InstRW<[SKLWriteResGroup129], (instregex "VPHSUBDrm")>;<br>
+def: InstRW<[SKLWriteResGroup129], (instregex "VPHSUBWrm")>;<br>
+<br>
+def SKLWriteResGroup130 : SchedWriteRes<[SKLPort1,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
+ let Latency = 9;<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [1,1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup130], (instregex "SHLD(16|32|64)mri8")>;<br>
+def: InstRW<[SKLWriteResGroup130], (instregex "SHRD(16|32|64)mri8")>;<br>
+<br>
+def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,<wbr>SKLPort6,SKLPort23,<wbr>SKLPort0156]> {<br>
+ let Latency = 9;<br>
+ let NumMicroOps = 5;<br>
+ let ResourceCycles = [1,2,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup131], (instregex "LSL(16|32|64)rm")>;<br>
+<br>
+def SKLWriteResGroup132 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 10;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup132], (instregex "AESDECLASTrm")>;<br>
+def: InstRW<[SKLWriteResGroup132], (instregex "AESDECrm")>;<br>
+def: InstRW<[SKLWriteResGroup132], (instregex "AESENCLASTrm")>;<br>
+def: InstRW<[SKLWriteResGroup132], (instregex "AESENCrm")>;<br>
+def: InstRW<[SKLWriteResGroup132], (instregex "RCPPSm")>;<br>
+def: InstRW<[SKLWriteResGroup132], (instregex "RSQRTPSm")>;<br>
+def: InstRW<[SKLWriteResGroup132], (instregex "VAESDECLASTrm")>;<br>
+def: InstRW<[SKLWriteResGroup132], (instregex "VAESDECrm")>;<br>
+def: InstRW<[SKLWriteResGroup132], (instregex "VAESENCLASTrm")>;<br>
+def: InstRW<[SKLWriteResGroup132], (instregex "VAESENCrm")>;<br>
+def: InstRW<[SKLWriteResGroup132], (instregex "VRCPPSm")>;<br>
+def: InstRW<[SKLWriteResGroup132], (instregex "VRSQRTPSm")>;<br>
+<br>
+def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
+ let Latency = 10;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "ADD_F32m")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "ADD_F64m")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "ILD_F16m")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "ILD_F32m")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "ILD_F64m")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "SUBR_F32m")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "SUBR_F64m")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "SUB_F32m")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "SUB_F64m")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "VPCMPGTQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "VPERM2F128rm")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "VPERM2I128rm")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "VPERMDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "VPERMPDYmi")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "VPERMPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "VPERMQYmi")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "VPMOVZXBDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "VPMOVZXBQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "VPMOVZXBWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "VPMOVZXDQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "VPMOVZXWQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup133], (instregex "VPSADBWYrm")>;<br>
+<br>
+def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,<wbr>SKLPort23]> {<br>
+ let Latency = 10;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "ADDPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "ADDPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "ADDSUBPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "ADDSUBPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "MULPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "MULPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "SUBPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "SUBPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VADDPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VADDPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VADDSUBPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VADDSUBPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADD132PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADD132PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADD213PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADD213PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADD231PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADD231PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADDSUB132PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADDSUB132PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADDSUB213PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADDSUB213PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADDSUB231PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADDSUB231PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUB132PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUB132PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUB213PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUB213PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUB231PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUB231PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUBADD132PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUBADD132PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUBADD213PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUBADD213PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUBADD231PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUBADD231PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMADD132PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMADD132PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMADD213PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMADD213PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMADD231PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMADD231PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMSUB132PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMSUB132PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMSUB213PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMSUB213PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMSUB231PDm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMSUB231PSm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VMULPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VMULPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VSUBPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup134], (instregex "VSUBPSrm")>;<br>
+<br>
+def SKLWriteResGroup135 : SchedWriteRes<[SKLPort23,<wbr>SKLPort015]> {<br>
+ let Latency = 10;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "CMPPDrmi")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "CMPPSrmi")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "CVTDQ2PSrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "CVTPS2DQrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "CVTSS2SDrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "CVTTPS2DQrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "MAXPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "MAXPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "MINPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "MINPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "PHMINPOSUWrm128")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "PMADDUBSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "PMADDWDrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "PMULDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "PMULHRSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "PMULHUWrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "PMULHWrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "PMULLWrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "PMULUDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VCMPPDrmi")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VCMPPSrmi")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VCVTDQ2PSrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VCVTPH2PSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VCVTPS2DQrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VCVTSS2SDrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VCVTTPS2DQrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VMAXPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VMAXPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VMINPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VMINPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VPHMINPOSUWrm128")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMADDUBSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMADDWDrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMULDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMULHRSWrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMULHUWrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMULHWrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMULLWrm")>;<br>
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMULUDQrm")>;<br>
+<br>
+def SKLWriteResGroup136 : SchedWriteRes<[SKLPort0]> {<br>
+ let Latency = 10;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [3];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup136], (instregex "PCMPISTRIrr")>;<br>
+def: InstRW<[SKLWriteResGroup136], (instregex "PCMPISTRM128rr")>;<br>
+def: InstRW<[SKLWriteResGroup136], (instregex "VPCMPISTRIrr")>;<br>
+def: InstRW<[SKLWriteResGroup136], (instregex "VPCMPISTRM128rr")>;<br>
<br>
-def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
- let Latency = 8;<br>
+def SKLWriteResGroup137 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
+ let Latency = 10;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [2,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup160], (instregex "AESIMCrm")>;<br>
-def: InstRW<[SKLWriteResGroup160], (instregex "VAESIMCrm")>;<br>
+def: InstRW<[SKLWriteResGroup137], (instregex "MPSADBWrmi")>;<br>
+def: InstRW<[SKLWriteResGroup137], (instregex "VMPSADBWrmi")>;<br>
<br>
-def SKLWriteResGroup161 : SchedWriteRes<[SKLPort23,<wbr>SKLPort015]> {<br>
- let Latency = 8;<br>
+def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
+ let Latency = 10;<br>
let NumMicroOps = 3;<br>
- let ResourceCycles = [1,2];<br>
+ let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup161], (instregex "PMULLDrm")>;<br>
-def: InstRW<[SKLWriteResGroup161], (instregex "ROUNDPDm")>;<br>
-def: InstRW<[SKLWriteResGroup161], (instregex "ROUNDPSm")>;<br>
-def: InstRW<[SKLWriteResGroup161], (instregex "ROUNDSDm")>;<br>
-def: InstRW<[SKLWriteResGroup161], (instregex "ROUNDSSm")>;<br>
-def: InstRW<[SKLWriteResGroup161], (instregex "VPMULLDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup161], (instregex "VPMULLDrm")>;<br>
-def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDPDm")>;<br>
-def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDPSm")>;<br>
-def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDSDm")>;<br>
-def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDSSm")>;<br>
-def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDYPDm")>;<br>
-def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDYPSm")>;<br>
+def: InstRW<[SKLWriteResGroup138], (instregex "MMX_CVTPI2PDirm")>;<br>
+def: InstRW<[SKLWriteResGroup138], (instregex "VPTESTYrm")>;<br>
<br>
-def SKLWriteResGroup165 : SchedWriteRes<[SKLPort5,<wbr>SKLPort015]> {<br>
- let Latency = 9;<br>
+def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23,SKLPort015]> {<br>
+ let Latency = 10;<br>
let NumMicroOps = 3;<br>
- let ResourceCycles = [1,2];<br>
+ let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup165], (instregex "DPPDrri")>;<br>
-def: InstRW<[SKLWriteResGroup165], (instregex "VDPPDrri")>;<br>
+def: InstRW<[SKLWriteResGroup139], (instregex "CVTSD2SSrm")>;<br>
+def: InstRW<[SKLWriteResGroup139], (instregex "VCVTSD2SSrm")>;<br>
<br>
-def SKLWriteResGroup167 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23,SKLPort015]> {<br>
- let Latency = 9;<br>
+def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01,SKLPort23]> {<br>
+ let Latency = 10;<br>
let NumMicroOps = 4;<br>
- let ResourceCycles = [1,1,2];<br>
+ let ResourceCycles = [2,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup167], (instregex "DPPDrmi")>;<br>
-def: InstRW<[SKLWriteResGroup167], (instregex "VDPPDrmi")>;<br>
+def: InstRW<[SKLWriteResGroup140], (instregex "VPHADDSWrm256")>;<br>
+def: InstRW<[SKLWriteResGroup140], (instregex "VPHSUBSWrm256")>;<br>
<br>
-def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0]> {<br>
+def SKLWriteResGroup141 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23,SKLPort015]> {<br>
let Latency = 10;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [3];<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [2,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup169], (instregex "PCMPISTRIrr")>;<br>
-def: InstRW<[SKLWriteResGroup169], (instregex "PCMPISTRM128rr")>;<br>
-def: InstRW<[SKLWriteResGroup169], (instregex "VPCMPISTRIrr")>;<br>
-def: InstRW<[SKLWriteResGroup169], (instregex "VPCMPISTRM128rr")>;<br>
+def: InstRW<[SKLWriteResGroup141], (instregex "VPHADDDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup141], (instregex "VPHADDWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup141], (instregex "VPHSUBDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup141], (instregex "VPHSUBWYrm")>;<br>
<br>
-def SKLWriteResGroup170 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup142 : SchedWriteRes<[SKLPort1,<wbr>SKLPort23,SKLPort06,<wbr>SKLPort0156]> {<br>
let Latency = 10;<br>
let NumMicroOps = 4;<br>
- let ResourceCycles = [3,1];<br>
+ let ResourceCycles = [1,1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup170], (instregex "PCMPISTRIrm")>;<br>
-def: InstRW<[SKLWriteResGroup170], (instregex "PCMPISTRM128rm")>;<br>
-def: InstRW<[SKLWriteResGroup170], (instregex "VPCMPISTRIrm")>;<br>
-def: InstRW<[SKLWriteResGroup170], (instregex "VPCMPISTRM128rm")>;<br>
+def: InstRW<[SKLWriteResGroup142], (instregex "MULX32rm")>;<br>
<br>
-def SKLWriteResGroup171 : SchedWriteRes<[SKLPort05,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort0156]> {<br>
let Latency = 10;<br>
- let NumMicroOps = 10;<br>
- let ResourceCycles = [9,1];<br>
+ let NumMicroOps = 8;<br>
+ let ResourceCycles = [1,1,1,1,1,3];<br>
}<br>
-def: InstRW<[SKLWriteResGroup171], (instregex "MMX_EMMS")>;<br>
+def: InstRW<[SKLWriteResGroup143], (instregex "ADD8mi")>;<br>
+def: InstRW<[SKLWriteResGroup143], (instregex "AND8mi")>;<br>
+def: InstRW<[SKLWriteResGroup143], (instregex "OR8mi")>;<br>
+def: InstRW<[SKLWriteResGroup143], (instregex "SUB8mi")>;<br>
+def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(16|32|64)rm")>;<br>
+def: InstRW<[SKLWriteResGroup143], (instregex "XCHG8rm")>;<br>
+def: InstRW<[SKLWriteResGroup143], (instregex "XOR8mi")>;<br>
<br>
-def SKLWriteResGroup172 : SchedWriteRes<[SKLPort1,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup144 : SchedWriteRes<[SKLPort05,<wbr>SKLPort0156]> {<br>
let Latency = 10;<br>
let NumMicroOps = 10;<br>
- let ResourceCycles = [1,1,1,5,1,1];<br>
+ let ResourceCycles = [9,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup172], (instregex "RCL(16|32|64)mCL")>;<br>
-def: InstRW<[SKLWriteResGroup172], (instregex "RCL8mCL")>;<br>
+def: InstRW<[SKLWriteResGroup144], (instregex "MMX_EMMS")>;<br>
<br>
-def SKLWriteResGroup173 : SchedWriteRes<[SKLPort0]> {<br>
+def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0]> {<br>
let Latency = 11;<br>
let NumMicroOps = 1;<br>
let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup173], (instregex "DIVPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup173], (instregex "DIVSSrr")>;<br>
-def: InstRW<[SKLWriteResGroup173], (instregex "VDIVPSYrr")>;<br>
-def: InstRW<[SKLWriteResGroup173], (instregex "VDIVPSrr")>;<br>
-def: InstRW<[SKLWriteResGroup173], (instregex "VDIVSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup145], (instregex "DIVPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup145], (instregex "DIVSSrr")>;<br>
+def: InstRW<[SKLWriteResGroup145], (instregex "VDIVPSYrr")>;<br>
+def: InstRW<[SKLWriteResGroup145], (instregex "VDIVPSrr")>;<br>
+def: InstRW<[SKLWriteResGroup145], (instregex "VDIVSSrr")>;<br>
+<br>
+def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 11;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F32m")>;<br>
+def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F64m")>;<br>
+def: InstRW<[SKLWriteResGroup146], (instregex "VRCPPSYm")>;<br>
+def: InstRW<[SKLWriteResGroup146], (instregex "VRSQRTPSYm")>;<br>
+<br>
+def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,<wbr>SKLPort23]> {<br>
+ let Latency = 11;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VADDPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VADDPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VADDSUBPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VADDSUBPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADD132PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADD132PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADD213PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADD213PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADD231PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADD231PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADDSUB132PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADDSUB132PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADDSUB213PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADDSUB213PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADDSUB231PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADDSUB231PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUB132PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUB132PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUB213PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUB213PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUB231PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUB231PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUBADD132PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUBADD132PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUBADD213PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUBADD213PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUBADD231PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUBADD231PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMADD132PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMADD132PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMADD213PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMADD213PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMADD231PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMADD231PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMSUB132PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMSUB132PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMSUB213PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMSUB213PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMSUB231PDYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMSUB231PSYm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VMULPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VMULPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VSUBPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup147], (instregex "VSUBPSYrm")>;<br>
<br>
-def SKLWriteResGroup174 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup148 : SchedWriteRes<[SKLPort23,<wbr>SKLPort015]> {<br>
let Latency = 11;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup174], (instregex "DIVPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup174], (instregex "DIVSSrm")>;<br>
-def: InstRW<[SKLWriteResGroup174], (instregex "VDIVPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup174], (instregex "VDIVPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup174], (instregex "VDIVSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VCMPPDYrmi")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VCMPPSYrmi")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VCVTDQ2PSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VCVTPS2DQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VCVTPS2PDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VCVTTPS2DQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VMAXPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VMAXPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VMINPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VMINPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMADDUBSWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMADDWDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMULDQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMULHRSWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMULHUWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMULHWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMULLWYrm")>;<br>
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMULUDQYrm")>;<br>
+<br>
+def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
+ let Latency = 11;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [2,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup149], (instregex "FICOM16m")>;<br>
+def: InstRW<[SKLWriteResGroup149], (instregex "FICOM32m")>;<br>
+def: InstRW<[SKLWriteResGroup149], (instregex "FICOMP16m")>;<br>
+def: InstRW<[SKLWriteResGroup149], (instregex "FICOMP32m")>;<br>
+def: InstRW<[SKLWriteResGroup149], (instregex "VMPSADBWYrmi")>;<br>
+<br>
+def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
+ let Latency = 11;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup150], (instregex "CVTDQ2PDrm")>;<br>
+def: InstRW<[SKLWriteResGroup150], (instregex "VCVTDQ2PDrm")>;<br>
<br>
-def SKLWriteResGroup175 : SchedWriteRes<[SKLPort1,<wbr>SKLPort06,SKLPort0156]> {<br>
+def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23,SKLPort015]> {<br>
+ let Latency = 11;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTSD2SI64rm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTSD2SIrm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTSS2SI64rm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTSS2SIrm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTTSD2SI64rm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTTSD2SIrm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTTSS2SIrm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTSD2SI64rm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTSD2SIrm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTSS2SI64rm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTSS2SIrm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTTSD2SI64rm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTTSD2SIrm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTTSS2SI64rm")>;<br>
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTTSS2SIrm")>;<br>
+<br>
+def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23,SKLPort015]> {<br>
+ let Latency = 11;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2DQrm")>;<br>
+def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2PSrm")>;<br>
+def: InstRW<[SKLWriteResGroup152], (instregex "CVTTPD2DQrm")>;<br>
+def: InstRW<[SKLWriteResGroup152], (instregex "MMX_CVTPD2PIirm")>;<br>
+def: InstRW<[SKLWriteResGroup152], (instregex "MMX_CVTTPD2PIirm")>;<br>
+<br>
+def SKLWriteResGroup153 : SchedWriteRes<[SKLPort1,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort0156]> {<br>
+ let Latency = 11;<br>
+ let NumMicroOps = 6;<br>
+ let ResourceCycles = [1,1,1,2,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup153], (instregex "SHLD(16|32|64)mrCL")>;<br>
+def: InstRW<[SKLWriteResGroup153], (instregex "SHRD(16|32|64)mrCL")>;<br>
+<br>
+def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,<wbr>SKLPort06,SKLPort0156]> {<br>
let Latency = 11;<br>
let NumMicroOps = 7;<br>
let ResourceCycles = [2,3,2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup175], (instregex "RCL(16|32|64)rCL")>;<br>
-def: InstRW<[SKLWriteResGroup175], (instregex "RCR(16|32|64)rCL")>;<br>
+def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL")>;<br>
+def: InstRW<[SKLWriteResGroup154], (instregex "RCR(16|32|64)rCL")>;<br>
<br>
-def SKLWriteResGroup176 : SchedWriteRes<[SKLPort1,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
let Latency = 11;<br>
let NumMicroOps = 9;<br>
let ResourceCycles = [1,5,1,2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup176], (instregex "RCL8rCL")>;<br>
+def: InstRW<[SKLWriteResGroup155], (instregex "RCL8rCL")>;<br>
<br>
-def SKLWriteResGroup177 : SchedWriteRes<[SKLPort06,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,<wbr>SKLPort0156]> {<br>
let Latency = 11;<br>
let NumMicroOps = 11;<br>
let ResourceCycles = [2,9];<br>
}<br>
-def: InstRW<[SKLWriteResGroup177], (instregex "LOOPE")>;<br>
-def: InstRW<[SKLWriteResGroup177], (instregex "LOOPNE")>;<br>
-<br>
-def SKLWriteResGroup178 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
- let Latency = 11;<br>
- let NumMicroOps = 14;<br>
- let ResourceCycles = [1,1,1,4,2,5];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup178], (instregex "CMPXCHG8B")>;<br>
+def: InstRW<[SKLWriteResGroup156], (instregex "LOOPE")>;<br>
+def: InstRW<[SKLWriteResGroup156], (instregex "LOOPNE")>;<br>
<br>
-def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0]> {<br>
+def SKLWriteResGroup157 : SchedWriteRes<[SKLPort0]> {<br>
let Latency = 12;<br>
let NumMicroOps = 1;<br>
let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup179], (instregex "VSQRTPSYr")>;<br>
-def: InstRW<[SKLWriteResGroup179], (instregex "VSQRTPSr")>;<br>
-def: InstRW<[SKLWriteResGroup179], (instregex "VSQRTSSr")>;<br>
+def: InstRW<[SKLWriteResGroup157], (instregex "VSQRTPSYr")>;<br>
+def: InstRW<[SKLWriteResGroup157], (instregex "VSQRTPSr")>;<br>
+def: InstRW<[SKLWriteResGroup157], (instregex "VSQRTSSr")>;<br>
<br>
-def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup158 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
let Latency = 12;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup180], (instregex "VSQRTPSYm")>;<br>
-def: InstRW<[SKLWriteResGroup180], (instregex "VSQRTPSm")>;<br>
-def: InstRW<[SKLWriteResGroup180], (instregex "VSQRTSSm")>;<br>
+def: InstRW<[SKLWriteResGroup158], (instregex "PCLMULQDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup158], (instregex "VPCLMULQDQrm")>;<br>
<br>
-def SKLWriteResGroup181 : SchedWriteRes<[SKLPort0]> {<br>
+def SKLWriteResGroup159 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01,SKLPort23]> {<br>
+ let Latency = 12;<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [2,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup159], (instregex "HADDPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup159], (instregex "HADDPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup159], (instregex "HSUBPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup159], (instregex "HSUBPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup159], (instregex "VHADDPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup159], (instregex "VHADDPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup159], (instregex "VHSUBPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup159], (instregex "VHSUBPSrm")>;<br>
+<br>
+def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23,SKLPort015]<wbr>> {<br>
+ let Latency = 12;<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [1,1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;<br>
+<br>
+def SKLWriteResGroup161 : SchedWriteRes<[SKLPort0]> {<br>
let Latency = 13;<br>
let NumMicroOps = 1;<br>
let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup181], (instregex "SQRTPSr")>;<br>
-def: InstRW<[SKLWriteResGroup181], (instregex "SQRTSSr")>;<br>
+def: InstRW<[SKLWriteResGroup161], (instregex "SQRTPSr")>;<br>
+def: InstRW<[SKLWriteResGroup161], (instregex "SQRTSSr")>;<br>
<br>
-def SKLWriteResGroup182 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23]> {<br>
let Latency = 13;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [2,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup182], (instregex "SQRTPSm")>;<br>
-def: InstRW<[SKLWriteResGroup182], (instregex "SQRTSSm")>;<br>
+def: InstRW<[SKLWriteResGroup162], (instregex "ADD_FI16m")>;<br>
+def: InstRW<[SKLWriteResGroup162], (instregex "ADD_FI32m")>;<br>
+def: InstRW<[SKLWriteResGroup162], (instregex "SUBR_FI16m")>;<br>
+def: InstRW<[SKLWriteResGroup162], (instregex "SUBR_FI32m")>;<br>
+def: InstRW<[SKLWriteResGroup162], (instregex "SUB_FI16m")>;<br>
+def: InstRW<[SKLWriteResGroup162], (instregex "SUB_FI32m")>;<br>
<br>
-def SKLWriteResGroup187 : SchedWriteRes<[SKLPort5,<wbr>SKLPort015]> {<br>
+def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
let Latency = 13;<br>
- let NumMicroOps = 4;<br>
- let ResourceCycles = [1,3];<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup187], (instregex "DPPSrri")>;<br>
-def: InstRW<[SKLWriteResGroup187], (instregex "VDPPSYrri")>;<br>
-def: InstRW<[SKLWriteResGroup187], (instregex "VDPPSrri")>;<br>
+def: InstRW<[SKLWriteResGroup163], (instregex "VCVTDQ2PDYrm")>;<br>
<br>
-def SKLWriteResGroup188 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23,SKLPort015]> {<br>
+def SKLWriteResGroup164 : SchedWriteRes<[SKLPort5,<wbr>SKLPort015]> {<br>
let Latency = 13;<br>
- let NumMicroOps = 5;<br>
- let ResourceCycles = [1,1,3];<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [1,3];<br>
}<br>
-def: InstRW<[SKLWriteResGroup188], (instregex "DPPSrmi")>;<br>
-def: InstRW<[SKLWriteResGroup188], (instregex "VDPPSYrmi")>;<br>
-def: InstRW<[SKLWriteResGroup188], (instregex "VDPPSrmi")>;<br>
+def: InstRW<[SKLWriteResGroup164], (instregex "DPPSrri")>;<br>
+def: InstRW<[SKLWriteResGroup164], (instregex "VDPPSYrri")>;<br>
+def: InstRW<[SKLWriteResGroup164], (instregex "VDPPSrri")>;<br>
<br>
-def SKLWriteResGroup189 : SchedWriteRes<[SKLPort1,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup165 : SchedWriteRes<[SKLPort5,<wbr>SKLPort01,SKLPort23]> {<br>
let Latency = 13;<br>
- let NumMicroOps = 11;<br>
- let ResourceCycles = [2,1,1,4,1,2];<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [2,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup189], (instregex "RCR(16|32|64)mCL")>;<br>
-def: InstRW<[SKLWriteResGroup189], (instregex "RCR8mCL")>;<br>
+def: InstRW<[SKLWriteResGroup165], (instregex "VHADDPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup165], (instregex "VHADDPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup165], (instregex "VHSUBPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup165], (instregex "VHSUBPSYrm")>;<br>
<br>
-def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0]> {<br>
+def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0]> {<br>
let Latency = 14;<br>
let NumMicroOps = 1;<br>
let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup190], (instregex "DIVPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup190], (instregex "DIVSDrr")>;<br>
-def: InstRW<[SKLWriteResGroup190], (instregex "VDIVPDYrr")>;<br>
-def: InstRW<[SKLWriteResGroup190], (instregex "VDIVPDrr")>;<br>
-def: InstRW<[SKLWriteResGroup190], (instregex "VDIVSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup166], (instregex "DIVPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup166], (instregex "DIVSDrr")>;<br>
+def: InstRW<[SKLWriteResGroup166], (instregex "VDIVPDYrr")>;<br>
+def: InstRW<[SKLWriteResGroup166], (instregex "VDIVPDrr")>;<br>
+def: InstRW<[SKLWriteResGroup166], (instregex "VDIVSDrr")>;<br>
<br>
-def SKLWriteResGroup191 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup167 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
let Latency = 14;<br>
- let NumMicroOps = 2;<br>
- let ResourceCycles = [1,1];<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [2,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup167], (instregex "AESIMCrm")>;<br>
+def: InstRW<[SKLWriteResGroup167], (instregex "VAESIMCrm")>;<br>
+<br>
+def SKLWriteResGroup168 : SchedWriteRes<[SKLPort23,<wbr>SKLPort015]> {<br>
+ let Latency = 14;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,2];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup168], (instregex "PMULLDrm")>;<br>
+def: InstRW<[SKLWriteResGroup168], (instregex "ROUNDPDm")>;<br>
+def: InstRW<[SKLWriteResGroup168], (instregex "ROUNDPSm")>;<br>
+def: InstRW<[SKLWriteResGroup168], (instregex "ROUNDSDm")>;<br>
+def: InstRW<[SKLWriteResGroup168], (instregex "ROUNDSSm")>;<br>
+def: InstRW<[SKLWriteResGroup168], (instregex "VPMULLDrm")>;<br>
+def: InstRW<[SKLWriteResGroup168], (instregex "VROUNDPDm")>;<br>
+def: InstRW<[SKLWriteResGroup168], (instregex "VROUNDPSm")>;<br>
+def: InstRW<[SKLWriteResGroup168], (instregex "VROUNDSDm")>;<br>
+def: InstRW<[SKLWriteResGroup168], (instregex "VROUNDSSm")>;<br>
+<br>
+def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
+ let Latency = 14;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup191], (instregex "DIVPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup191], (instregex "DIVSDrm")>;<br>
-def: InstRW<[SKLWriteResGroup191], (instregex "VDIVPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup191], (instregex "VDIVPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup191], (instregex "VDIVSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI16m")>;<br>
+def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI32m")>;<br>
<br>
-def SKLWriteResGroup192 : SchedWriteRes<[SKLPort1,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
let Latency = 14;<br>
let NumMicroOps = 10;<br>
let ResourceCycles = [2,4,1,3];<br>
}<br>
-def: InstRW<[SKLWriteResGroup192], (instregex "RCR8rCL")>;<br>
+def: InstRW<[SKLWriteResGroup170], (instregex "RCR8rCL")>;<br>
<br>
-def SKLWriteResGroup193 : SchedWriteRes<[SKLPort0]> {<br>
+def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {<br>
let Latency = 15;<br>
let NumMicroOps = 1;<br>
let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup193], (instregex "DIVR_FPrST0")>;<br>
-def: InstRW<[SKLWriteResGroup193], (instregex "DIVR_FST0r")>;<br>
-def: InstRW<[SKLWriteResGroup193], (instregex "DIVR_FrST0")>;<br>
+def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_FPrST0")>;<br>
+def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_FST0r")>;<br>
+def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_FrST0")>;<br>
+<br>
+def SKLWriteResGroup172 : SchedWriteRes<[SKLPort23,<wbr>SKLPort015]> {<br>
+ let Latency = 15;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,2];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup172], (instregex "VPMULLDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup172], (instregex "VROUNDYPDm")>;<br>
+def: InstRW<[SKLWriteResGroup172], (instregex "VROUNDYPSm")>;<br>
+<br>
+def SKLWriteResGroup173 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23,SKLPort015]> {<br>
+ let Latency = 15;<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [1,1,2];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup173], (instregex "DPPDrmi")>;<br>
+def: InstRW<[SKLWriteResGroup173], (instregex "VDPPDrmi")>;<br>
<br>
-def SKLWriteResGroup194 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
let Latency = 15;<br>
+ let NumMicroOps = 10;<br>
+ let ResourceCycles = [1,1,1,5,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup174], (instregex "RCL(16|32|64)mCL")>;<br>
+def: InstRW<[SKLWriteResGroup174], (instregex "RCL8mCL")>;<br>
+<br>
+def SKLWriteResGroup175 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 16;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup194], (instregex "DIV_F32m")>;<br>
-def: InstRW<[SKLWriteResGroup194], (instregex "DIV_F64m")>;<br>
+def: InstRW<[SKLWriteResGroup175], (instregex "DIVSSrm")>;<br>
+def: InstRW<[SKLWriteResGroup175], (instregex "VDIVSSrm")>;<br>
<br>
-def SKLWriteResGroup195 : SchedWriteRes<[SKLPort4,<wbr>SKLPort5,SKLPort6,SKLPort23,<wbr>SKLPort237,SKLPort06,<wbr>SKLPort0156]> {<br>
- let Latency = 15;<br>
- let NumMicroOps = 8;<br>
- let ResourceCycles = [1,1,1,1,1,1,2];<br>
+def SKLWriteResGroup176 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 16;<br>
+ let NumMicroOps = 4;<br>
+ let ResourceCycles = [3,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup176], (instregex "PCMPISTRIrm")>;<br>
+def: InstRW<[SKLWriteResGroup176], (instregex "PCMPISTRM128rm")>;<br>
+def: InstRW<[SKLWriteResGroup176], (instregex "VPCMPISTRIrm")>;<br>
+def: InstRW<[SKLWriteResGroup176], (instregex "VPCMPISTRM128rm")>;<br>
+<br>
+def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
+ let Latency = 16;<br>
+ let NumMicroOps = 14;<br>
+ let ResourceCycles = [1,1,1,4,2,5];<br>
}<br>
-def: InstRW<[SKLWriteResGroup195], (instregex "INSB")>;<br>
-def: InstRW<[SKLWriteResGroup195], (instregex "INSL")>;<br>
-def: InstRW<[SKLWriteResGroup195], (instregex "INSW")>;<br>
+def: InstRW<[SKLWriteResGroup177], (instregex "CMPXCHG8B")>;<br>
<br>
-def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0156]> {<br>
+def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {<br>
let Latency = 16;<br>
let NumMicroOps = 16;<br>
let ResourceCycles = [16];<br>
}<br>
-def: InstRW<[SKLWriteResGroup196], (instregex "VZEROALL")>;<br>
+def: InstRW<[SKLWriteResGroup178], (instregex "VZEROALL")>;<br>
+<br>
+def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 17;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup179], (instregex "DIVPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup179], (instregex "VDIVPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup179], (instregex "VSQRTSSm")>;<br>
<br>
-def SKLWriteResGroup197 : SchedWriteRes<[SKLPort0,<wbr>SKLPort1,SKLPort5,SKLPort6,<wbr>SKLPort05,SKLPort0156]> {<br>
+def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,<wbr>SKLPort1,SKLPort5,SKLPort6,<wbr>SKLPort05,SKLPort0156]> {<br>
let Latency = 17;<br>
let NumMicroOps = 15;<br>
let ResourceCycles = [2,1,2,4,2,4];<br>
}<br>
-def: InstRW<[SKLWriteResGroup197], (instregex "XCH_F")>;<br>
+def: InstRW<[SKLWriteResGroup180], (instregex "XCH_F")>;<br>
<br>
-def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0]> {<br>
+def SKLWriteResGroup181 : SchedWriteRes<[SKLPort0]> {<br>
let Latency = 18;<br>
let NumMicroOps = 1;<br>
let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup198], (instregex "VSQRTPDYr")>;<br>
-def: InstRW<[SKLWriteResGroup198], (instregex "VSQRTPDr")>;<br>
-def: InstRW<[SKLWriteResGroup198], (instregex "VSQRTSDr")>;<br>
+def: InstRW<[SKLWriteResGroup181], (instregex "VSQRTPDYr")>;<br>
+def: InstRW<[SKLWriteResGroup181], (instregex "VSQRTPDr")>;<br>
+def: InstRW<[SKLWriteResGroup181], (instregex "VSQRTSDr")>;<br>
<br>
-def SKLWriteResGroup199 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup182 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
let Latency = 18;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTPDYm")>;<br>
-def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTPDm")>;<br>
-def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTSDm")>;<br>
-<br>
-def SKLWriteResGroup200 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
- let Latency = 18;<br>
- let NumMicroOps = 3;<br>
- let ResourceCycles = [1,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup200], (instregex "DIV_FI16m")>;<br>
-def: InstRW<[SKLWriteResGroup200], (instregex "DIV_FI32m")>;<br>
+def: InstRW<[SKLWriteResGroup182], (instregex "SQRTSSm")>;<br>
+def: InstRW<[SKLWriteResGroup182], (instregex "VDIVPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup182], (instregex "VSQRTPSm")>;<br>
<br>
-def SKLWriteResGroup201 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort0156]> {<br>
+def SKLWriteResGroup183 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort0156]> {<br>
let Latency = 18;<br>
let NumMicroOps = 8;<br>
let ResourceCycles = [4,3,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup201], (instregex "PCMPESTRIrr")>;<br>
-def: InstRW<[SKLWriteResGroup201], (instregex "VPCMPESTRIrr")>;<br>
+def: InstRW<[SKLWriteResGroup183], (instregex "PCMPESTRIrr")>;<br>
+def: InstRW<[SKLWriteResGroup183], (instregex "VPCMPESTRIrr")>;<br>
<br>
-def SKLWriteResGroup202 : SchedWriteRes<[SKLPort5,<wbr>SKLPort6,SKLPort06,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,<wbr>SKLPort6,SKLPort06,<wbr>SKLPort0156]> {<br>
let Latency = 18;<br>
let NumMicroOps = 8;<br>
let ResourceCycles = [1,1,1,5];<br>
}<br>
-def: InstRW<[SKLWriteResGroup202], (instregex "CPUID")>;<br>
-def: InstRW<[SKLWriteResGroup202], (instregex "RDTSC")>;<br>
+def: InstRW<[SKLWriteResGroup184], (instregex "CPUID")>;<br>
+def: InstRW<[SKLWriteResGroup184], (instregex "RDTSC")>;<br>
<br>
-def SKLWriteResGroup203 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
let Latency = 18;<br>
- let NumMicroOps = 9;<br>
- let ResourceCycles = [4,3,1,1];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup203], (instregex "PCMPESTRIrm")>;<br>
-def: InstRW<[SKLWriteResGroup203], (instregex "VPCMPESTRIrm")>;<br>
-<br>
-def SKLWriteResGroup204 : SchedWriteRes<[SKLPort0,<wbr>SKLPort4,SKLPort5,SKLPort23,<wbr>SKLPort237,SKLPort06,<wbr>SKLPort0156]> {<br>
- let Latency = 18;<br>
- let NumMicroOps = 19;<br>
- let ResourceCycles = [2,1,4,1,1,4,6];<br>
+ let NumMicroOps = 11;<br>
+ let ResourceCycles = [2,1,1,4,1,2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup204], (instregex "CMPXCHG16B")>;<br>
+def: InstRW<[SKLWriteResGroup185], (instregex "RCR(16|32|64)mCL")>;<br>
+def: InstRW<[SKLWriteResGroup185], (instregex "RCR8mCL")>;<br>
<br>
-def SKLWriteResGroup205 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort015,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
let Latency = 19;<br>
- let NumMicroOps = 9;<br>
- let ResourceCycles = [4,3,1,1];<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup205], (instregex "PCMPESTRM128rr")>;<br>
-def: InstRW<[SKLWriteResGroup205], (instregex "VPCMPESTRM128rr")>;<br>
+def: InstRW<[SKLWriteResGroup186], (instregex "DIVSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup186], (instregex "SQRTPSm")>;<br>
+def: InstRW<[SKLWriteResGroup186], (instregex "VDIVSDrm")>;<br>
+def: InstRW<[SKLWriteResGroup186], (instregex "VSQRTPSYm")>;<br>
<br>
-def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23,SKLPort015,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup187 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23,SKLPort015]> {<br>
let Latency = 19;<br>
- let NumMicroOps = 10;<br>
- let ResourceCycles = [4,3,1,1,1];<br>
+ let NumMicroOps = 5;<br>
+ let ResourceCycles = [1,1,3];<br>
}<br>
-def: InstRW<[SKLWriteResGroup206], (instregex "PCMPESTRM128rm")>;<br>
-def: InstRW<[SKLWriteResGroup206], (instregex "VPCMPESTRM128rm")>;<br>
+def: InstRW<[SKLWriteResGroup187], (instregex "DPPSrmi")>;<br>
+def: InstRW<[SKLWriteResGroup187], (instregex "VDPPSrmi")>;<br>
<br>
-def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23,SKLPort015]<wbr>> {<br>
+def SKLWriteResGroup188 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort015,<wbr>SKLPort0156]> {<br>
let Latency = 19;<br>
- let NumMicroOps = 11;<br>
- let ResourceCycles = [3,6,1,1];<br>
+ let NumMicroOps = 9;<br>
+ let ResourceCycles = [4,3,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup207], (instregex "AESKEYGENASSIST128rm")>;<br>
-def: InstRW<[SKLWriteResGroup207], (instregex "VAESKEYGENASSIST128rm")>;<br>
+def: InstRW<[SKLWriteResGroup188], (instregex "PCMPESTRM128rr")>;<br>
+def: InstRW<[SKLWriteResGroup188], (instregex "VPCMPESTRM128rr")>;<br>
<br>
-def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0]> {<br>
+def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {<br>
let Latency = 20;<br>
let NumMicroOps = 1;<br>
let ResourceCycles = [1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup208], (instregex "DIV_FPrST0")>;<br>
-def: InstRW<[SKLWriteResGroup208], (instregex "DIV_FST0r")>;<br>
-def: InstRW<[SKLWriteResGroup208], (instregex "DIV_FrST0")>;<br>
-def: InstRW<[SKLWriteResGroup208], (instregex "SQRTPDr")>;<br>
-def: InstRW<[SKLWriteResGroup208], (instregex "SQRTSDr")>;<br>
+def: InstRW<[SKLWriteResGroup189], (instregex "DIV_FPrST0")>;<br>
+def: InstRW<[SKLWriteResGroup189], (instregex "DIV_FST0r")>;<br>
+def: InstRW<[SKLWriteResGroup189], (instregex "DIV_FrST0")>;<br>
+def: InstRW<[SKLWriteResGroup189], (instregex "SQRTPDr")>;<br>
+def: InstRW<[SKLWriteResGroup189], (instregex "SQRTSDr")>;<br>
<br>
-def SKLWriteResGroup209 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
let Latency = 20;<br>
let NumMicroOps = 2;<br>
let ResourceCycles = [1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup209], (instregex "DIVR_F32m")>;<br>
-def: InstRW<[SKLWriteResGroup209], (instregex "DIVR_F64m")>;<br>
-def: InstRW<[SKLWriteResGroup209], (instregex "SQRTPDm")>;<br>
-def: InstRW<[SKLWriteResGroup209], (instregex "SQRTSDm")>;<br>
+def: InstRW<[SKLWriteResGroup190], (instregex "DIVPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup190], (instregex "VDIVPDrm")>;<br>
+<br>
+def SKLWriteResGroup191 : SchedWriteRes<[SKLPort5,<wbr>SKLPort23,SKLPort015]> {<br>
+ let Latency = 20;<br>
+ let NumMicroOps = 5;<br>
+ let ResourceCycles = [1,1,3];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup191], (instregex "VDPPSYrmi")>;<br>
+<br>
+def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,<wbr>SKLPort5,SKLPort6,SKLPort23,<wbr>SKLPort237,SKLPort06,<wbr>SKLPort0156]> {<br>
+ let Latency = 20;<br>
+ let NumMicroOps = 8;<br>
+ let ResourceCycles = [1,1,1,1,1,1,2];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup192], (instregex "INSB")>;<br>
+def: InstRW<[SKLWriteResGroup192], (instregex "INSL")>;<br>
+def: InstRW<[SKLWriteResGroup192], (instregex "INSW")>;<br>
<br>
-def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,<wbr>SKLPort6,SKLPort0156]> {<br>
+def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,<wbr>SKLPort6,SKLPort0156]> {<br>
let Latency = 20;<br>
let NumMicroOps = 10;<br>
let ResourceCycles = [1,2,7];<br>
}<br>
-def: InstRW<[SKLWriteResGroup210], (instregex "MWAITrr")>;<br>
+def: InstRW<[SKLWriteResGroup193], (instregex "MWAITrr")>;<br>
<br>
-def SKLWriteResGroup211 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort015]> {<br>
+def SKLWriteResGroup194 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort015]> {<br>
let Latency = 20;<br>
let NumMicroOps = 11;<br>
let ResourceCycles = [3,6,2];<br>
}<br>
-def: InstRW<[SKLWriteResGroup211], (instregex "AESKEYGENASSIST128rr")>;<br>
-def: InstRW<[SKLWriteResGroup211], (instregex "VAESKEYGENASSIST128rr")>;<br>
+def: InstRW<[SKLWriteResGroup194], (instregex "AESKEYGENASSIST128rr")>;<br>
+def: InstRW<[SKLWriteResGroup194], (instregex "VAESKEYGENASSIST128rr")>;<br>
<br>
-def SKLWriteResGroup212 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {<br>
- let Latency = 17;<br>
+def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 21;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup195], (instregex "VDIVPDYrm")>;<br>
+<br>
+def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 22;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F32m")>;<br>
+def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F64m")>;<br>
+<br>
+def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {<br>
+ let Latency = 22;<br>
let NumMicroOps = 5;<br>
let ResourceCycles = [1,2,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERDPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERDPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERQPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERQPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERDDrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERQDrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERQQrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERDDrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERQDrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERDQrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERQQrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERDPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERQPSrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERDPDrm")>;<br>
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERQPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VGATHERDPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VGATHERDPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VGATHERQPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VGATHERQPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VPGATHERDDrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VPGATHERDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VPGATHERQDrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VPGATHERQQrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VPGATHERDDrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VPGATHERQDrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VPGATHERDQrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VPGATHERQQrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VGATHERDPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VGATHERQPSrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VGATHERDPDrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_1]<wbr>, (instregex "VGATHERQPDrm")>;<br>
<br>
-def SKLWriteResGroup213 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {<br>
- let Latency = 20;<br>
+def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {<br>
+ let Latency = 25;<br>
let NumMicroOps = 5;<br>
let ResourceCycles = [1,2,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERDPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERQPDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERQPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERDDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERDQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERQDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERQQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERDDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERQDYrm")>;<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERDQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERQQYrm")>;<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERDPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERQPSYrm")>;<br>
-def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERDPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VGATHERDPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VGATHERQPDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VGATHERQPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VPGATHERDDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VPGATHERDQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VPGATHERQDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VPGATHERQQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VPGATHERDDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VPGATHERQDYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VPGATHERDQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VPGATHERQQYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VGATHERDPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VGATHERQPSYrm")>;<br>
+def: InstRW<[SKLWriteResGroup196_2]<wbr>, (instregex "VGATHERDPDYrm")>;<br>
+<br>
+def SKLWriteResGroup197 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 23;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup197], (instregex "VSQRTSDm")>;<br>
<br>
-def SKLWriteResGroup215 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
+def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,<wbr>SKLPort4,SKLPort5,SKLPort23,<wbr>SKLPort237,SKLPort06,<wbr>SKLPort0156]> {<br>
let Latency = 23;<br>
+ let NumMicroOps = 19;<br>
+ let ResourceCycles = [2,1,4,1,1,4,6];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup198], (instregex "CMPXCHG16B")>;<br>
+<br>
+def SKLWriteResGroup199 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 24;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTPDm")>;<br>
+<br>
+def SKLWriteResGroup200 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23,<wbr>SKLPort0156]> {<br>
+ let Latency = 24;<br>
+ let NumMicroOps = 9;<br>
+ let ResourceCycles = [4,3,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup200], (instregex "PCMPESTRIrm")>;<br>
+def: InstRW<[SKLWriteResGroup200], (instregex "VPCMPESTRIrm")>;<br>
+<br>
+def SKLWriteResGroup201 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 25;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup201], (instregex "SQRTSDm")>;<br>
+def: InstRW<[SKLWriteResGroup201], (instregex "VSQRTPDYm")>;<br>
+<br>
+def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
+ let Latency = 25;<br>
let NumMicroOps = 3;<br>
let ResourceCycles = [1,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup215], (instregex "DIVR_FI16m")>;<br>
-def: InstRW<[SKLWriteResGroup215], (instregex "DIVR_FI32m")>;<br>
+def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI16m")>;<br>
+def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI32m")>;<br>
<br>
-def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23,<wbr>SKLPort0156]> {<br>
- let Latency = 23;<br>
+def SKLWriteResGroup203 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23,SKLPort015,<wbr>SKLPort0156]> {<br>
+ let Latency = 25;<br>
+ let NumMicroOps = 10;<br>
+ let ResourceCycles = [4,3,1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup203], (instregex "PCMPESTRM128rm")>;<br>
+def: InstRW<[SKLWriteResGroup203], (instregex "VPCMPESTRM128rm")>;<br>
+<br>
+def SKLWriteResGroup204 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23,SKLPort015]<wbr>> {<br>
+ let Latency = 25;<br>
+ let NumMicroOps = 11;<br>
+ let ResourceCycles = [3,6,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup204], (instregex "AESKEYGENASSIST128rm")>;<br>
+def: InstRW<[SKLWriteResGroup204], (instregex "VAESKEYGENASSIST128rm")>;<br>
+<br>
+def SKLWriteResGroup205 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 26;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup205], (instregex "SQRTPDm")>;<br>
+<br>
+def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23]> {<br>
+ let Latency = 27;<br>
+ let NumMicroOps = 2;<br>
+ let ResourceCycles = [1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F32m")>;<br>
+def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F64m")>;<br>
+<br>
+def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23,<wbr>SKLPort0156]> {<br>
+ let Latency = 28;<br>
let NumMicroOps = 8;<br>
let ResourceCycles = [2,4,1,1];<br>
}<br>
-def: InstRW<[SKLWriteResGroup217], (instregex "IDIV(16|32|64)m")>;<br>
-def: InstRW<[SKLWriteResGroup217], (instregex "IDIV8m")>;<br>
+def: InstRW<[SKLWriteResGroup207], (instregex "IDIV(16|32|64)m")>;<br>
+def: InstRW<[SKLWriteResGroup207], (instregex "IDIV8m")>;<br>
<br>
-def SKLWriteResGroup222 : SchedWriteRes<[SKLPort5,<wbr>SKLPort6,SKLPort23,SKLPort06,<wbr>SKLPort0156]> {<br>
+def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,<wbr>SKLPort5,SKLPort23]> {<br>
let Latency = 30;<br>
+ let NumMicroOps = 3;<br>
+ let ResourceCycles = [1,1,1];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI16m")>;<br>
+def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI32m")>;<br>
+<br>
+def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,<wbr>SKLPort6,SKLPort23,SKLPort06,<wbr>SKLPort0156]> {<br>
+ let Latency = 35;<br>
let NumMicroOps = 23;<br>
let ResourceCycles = [1,5,3,4,10];<br>
}<br>
-def: InstRW<[SKLWriteResGroup222], (instregex "IN32ri")>;<br>
-def: InstRW<[SKLWriteResGroup222], (instregex "IN32rr")>;<br>
-def: InstRW<[SKLWriteResGroup222], (instregex "IN8ri")>;<br>
-def: InstRW<[SKLWriteResGroup222], (instregex "IN8rr")>;<br>
+def: InstRW<[SKLWriteResGroup209], (instregex "IN32ri")>;<br>
+def: InstRW<[SKLWriteResGroup209], (instregex "IN32rr")>;<br>
+def: InstRW<[SKLWriteResGroup209], (instregex "IN8ri")>;<br>
+def: InstRW<[SKLWriteResGroup209], (instregex "IN8rr")>;<br>
<br>
-def SKLWriteResGroup223 : SchedWriteRes<[SKLPort5,<wbr>SKLPort6,SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort0156]> {<br>
- let Latency = 30;<br>
+def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,<wbr>SKLPort6,SKLPort23,SKLPort237,<wbr>SKLPort06,SKLPort0156]> {<br>
+ let Latency = 35;<br>
let NumMicroOps = 23;<br>
let ResourceCycles = [1,5,2,1,4,10];<br>
}<br>
-def: InstRW<[SKLWriteResGroup223], (instregex "OUT32ir")>;<br>
-def: InstRW<[SKLWriteResGroup223], (instregex "OUT32rr")>;<br>
-def: InstRW<[SKLWriteResGroup223], (instregex "OUT8ir")>;<br>
-def: InstRW<[SKLWriteResGroup223], (instregex "OUT8rr")>;<br>
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT32ir")>;<br>
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT32rr")>;<br>
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT8ir")>;<br>
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT8rr")>;<br>
<br>
-def SKLWriteResGroup224 : SchedWriteRes<[SKLPort1,<wbr>SKLPort6,SKLPort23,<wbr>SKLPort0156]> {<br>
- let Latency = 32;<br>
+def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,<wbr>SKLPort6,SKLPort23,<wbr>SKLPort0156]> {<br>
+ let Latency = 37;<br>
let NumMicroOps = 31;<br>
let ResourceCycles = [1,8,1,21];<br>
}<br>
-def: InstRW<[SKLWriteResGroup224], (instregex "XRSTOR(64?)")>;<br>
+def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64?)")>;<br>
<br>
-def SKLWriteResGroup225 : SchedWriteRes<[SKLPort1,<wbr>SKLPort4,SKLPort5,SKLPort6,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort15,SKLPort0156]> {<br>
- let Latency = 35;<br>
+def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,<wbr>SKLPort4,SKLPort5,SKLPort6,<wbr>SKLPort23,SKLPort237,<wbr>SKLPort15,SKLPort0156]> {<br>
+ let Latency = 40;<br>
let NumMicroOps = 18;<br>
let ResourceCycles = [1,1,2,3,1,1,1,8];<br>
}<br>
-def: InstRW<[SKLWriteResGroup225], (instregex "VMCLEARm")>;<br>
+def: InstRW<[SKLWriteResGroup212], (instregex "VMCLEARm")>;<br>
<br>
-def SKLWriteResGroup226 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
- let Latency = 36;<br>
+def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
+ let Latency = 41;<br>
let NumMicroOps = 39;<br>
let ResourceCycles = [1,10,1,1,26];<br>
}<br>
-def: InstRW<[SKLWriteResGroup226], (instregex "XSAVE64")>;<br>
+def: InstRW<[SKLWriteResGroup213], (instregex "XSAVE64")>;<br>
<br>
-def SKLWriteResGroup231 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
- let Latency = 37;<br>
+def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,<wbr>SKLPort0156]> {<br>
+ let Latency = 42;<br>
+ let NumMicroOps = 22;<br>
+ let ResourceCycles = [2,20];<br>
+}<br>
+def: InstRW<[SKLWriteResGroup214], (instregex "RDTSCP")>;<br>
+<br>
+def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
+ let Latency = 42;<br>
let NumMicroOps = 40;<br>
let ResourceCycles = [1,11,1,1,26];<br>
}<br>
-def: InstRW<[SKLWriteResGroup231], (instregex "XSAVE")>;<br>
+def: InstRW<[SKLWriteResGroup215], (instregex "XSAVE")>;<br>
<br>
-def SKLWriteResGroup232 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
- let Latency = 41;<br>
+def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,<wbr>SKLPort6,SKLPort23,SKLPort237,<wbr>SKLPort0156]> {<br>
+ let Latency = 46;<br>
let NumMicroOps = 44;<br>
let ResourceCycles = [1,11,1,1,30];<br>
}<br>
-def: InstRW<[SKLWriteResGroup232], (instregex "XSAVEOPT")>;<br>
-<br>
-def SKLWriteResGroup233 : SchedWriteRes<[SKLPort5,<wbr>SKLPort0156]> {<br>
- let Latency = 42;<br>
- let NumMicroOps = 22;<br>
- let ResourceCycles = [2,20];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup233], (instregex "RDTSCP")>;<br>
+def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;<br>
<br>
-def SKLWriteResGroup234 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23,SKLPort05,SKLPort06,<wbr>SKLPort0156]> {<br>
- let Latency = 57;<br>
+def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,<wbr>SKLPort23,SKLPort05,SKLPort06,<wbr>SKLPort0156]> {<br>
+ let Latency = 62;<br>
let NumMicroOps = 64;<br>
let ResourceCycles = [2,8,5,10,39];<br>
}<br>
-def: InstRW<[SKLWriteResGroup234], (instregex "FLDENVm")>;<br>
-def: InstRW<[SKLWriteResGroup234], (instregex "FLDENVm")>;<br>
+def: InstRW<[SKLWriteResGroup217], (instregex "FLDENVm")>;<br>
+def: InstRW<[SKLWriteResGroup217], (instregex "FLDENVm")>;<br>
<br>
-def SKLWriteResGroup235 : SchedWriteRes<[SKLPort0,<wbr>SKLPort6,SKLPort23,SKLPort05,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
- let Latency = 58;<br>
+def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,<wbr>SKLPort6,SKLPort23,SKLPort05,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
+ let Latency = 63;<br>
let NumMicroOps = 88;<br>
let ResourceCycles = [4,4,31,1,2,1,45];<br>
}<br>
-def: InstRW<[SKLWriteResGroup235], (instregex "FXRSTOR64")>;<br>
+def: InstRW<[SKLWriteResGroup218], (instregex "FXRSTOR64")>;<br>
<br>
-def SKLWriteResGroup236 : SchedWriteRes<[SKLPort0,<wbr>SKLPort6,SKLPort23,SKLPort05,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
- let Latency = 58;<br>
+def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,<wbr>SKLPort6,SKLPort23,SKLPort05,<wbr>SKLPort06,SKLPort15,<wbr>SKLPort0156]> {<br>
+ let Latency = 63;<br>
let NumMicroOps = 90;<br>
let ResourceCycles = [4,2,33,1,2,1,47];<br>
}<br>
-def: InstRW<[SKLWriteResGroup236], (instregex "FXRSTOR")>;<br>
+def: InstRW<[SKLWriteResGroup219], (instregex "FXRSTOR")>;<br>
<br>
-def SKLWriteResGroup239 : SchedWriteRes<[SKLPort5,<wbr>SKLPort05,SKLPort0156]> {<br>
+def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,<wbr>SKLPort05,SKLPort0156]> {<br>
let Latency = 75;<br>
let NumMicroOps = 15;<br>
let ResourceCycles = [6,3,6];<br>
}<br>
-def: InstRW<[SKLWriteResGroup239], (instregex "FNINIT")>;<br>
+def: InstRW<[SKLWriteResGroup220], (instregex "FNINIT")>;<br>
<br>
-def SKLWriteResGroup240 : SchedWriteRes<[SKLPort0,<wbr>SKLPort1,SKLPort5,SKLPort6,<wbr>SKLPort05,SKLPort0156]> {<br>
+def SKLWriteResGroup221 : SchedWriteRes<[SKLPort0,<wbr>SKLPort1,SKLPort5,SKLPort6,<wbr>SKLPort05,SKLPort0156]> {<br>
let Latency = 76;<br>
let NumMicroOps = 32;<br>
let ResourceCycles = [7,2,8,3,1,11];<br>
}<br>
-def: InstRW<[SKLWriteResGroup240], (instregex "DIV(16|32|64)r")>;<br>
+def: InstRW<[SKLWriteResGroup221], (instregex "DIV(16|32|64)r")>;<br>
<br>
-def SKLWriteResGroup241 : SchedWriteRes<[SKLPort0,<wbr>SKLPort1,SKLPort5,SKLPort6,<wbr>SKLPort06,SKLPort0156]> {<br>
+def SKLWriteResGroup222 : SchedWriteRes<[SKLPort0,<wbr>SKLPort1,SKLPort5,SKLPort6,<wbr>SKLPort06,SKLPort0156]> {<br>
let Latency = 102;<br>
let NumMicroOps = 66;<br>
let ResourceCycles = [4,2,4,8,14,34];<br>
}<br>
-def: InstRW<[SKLWriteResGroup241], (instregex "IDIV(16|32|64)r")>;<br>
+def: InstRW<[SKLWriteResGroup222], (instregex "IDIV(16|32|64)r")>;<br>
<br>
-def SKLWriteResGroup242 : SchedWriteRes<[SKLPort0,<wbr>SKLPort1,SKLPort4,SKLPort5,<wbr>SKLPort6,SKLPort237,SKLPort06,<wbr>SKLPort0156]> {<br>
- let Latency = 105;<br>
+def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,<wbr>SKLPort1,SKLPort4,SKLPort5,<wbr>SKLPort6,SKLPort237,SKLPort06,<wbr>SKLPort0156]> {<br>
+ let Latency = 106;<br>
let NumMicroOps = 100;<br>
let ResourceCycles = [9,1,11,16,1,11,21,30];<br>
}<br>
-def: InstRW<[SKLWriteResGroup242], (instregex "FSTENVm")>;<br>
-def: InstRW<[SKLWriteResGroup242], (instregex "FSTENVm")>;<br>
+def: InstRW<[SKLWriteResGroup223], (instregex "FSTENVm")>;<br>
+def: InstRW<[SKLWriteResGroup223], (instregex "FSTENVm")>;<br>
<br>
} // SchedModel<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>aes-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/aes-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/aes-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>aes-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>aes-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -37,8 +37,8 @@ define <2 x i64> @test_aesdec(<2 x i64><br>
; SKYLAKE-LABEL: test_aesdec:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_aesdec:<br>
; BTVER2: # BB#0:<br>
@@ -86,8 +86,8 @@ define <2 x i64> @test_aesdeclast(<2 x i<br>
; SKYLAKE-LABEL: test_aesdeclast:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_aesdeclast:<br>
; BTVER2: # BB#0:<br>
@@ -135,8 +135,8 @@ define <2 x i64> @test_aesenc(<2 x i64><br>
; SKYLAKE-LABEL: test_aesenc:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_aesenc:<br>
; BTVER2: # BB#0:<br>
@@ -184,8 +184,8 @@ define <2 x i64> @test_aesenclast(<2 x i<br>
; SKYLAKE-LABEL: test_aesenclast:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [10:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_aesenclast:<br>
; BTVER2: # BB#0:<br>
@@ -237,9 +237,9 @@ define <2 x i64> @test_aesimc(<2 x i64><br>
; SKYLAKE-LABEL: test_aesimc:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaesimc %xmm0, %xmm0 # sched: [8:2.00]<br>
-; SKYLAKE-NEXT: vaesimc (%rdi), %xmm1 # sched: [8:2.00]<br>
-; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaesimc (%rdi), %xmm1 # sched: [14:2.00]<br>
+; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_aesimc:<br>
; BTVER2: # BB#0:<br>
@@ -294,9 +294,9 @@ define <2 x i64> @test_aeskeygenassist(<<br>
; SKYLAKE-LABEL: test_aeskeygenassist:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [20:6.00]<br>
-; SKYLAKE-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [19:6.00]<br>
-; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [25:6.00]<br>
+; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_aeskeygenassist:<br>
; BTVER2: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>avx-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/avx-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>avx-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>avx-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -30,8 +30,8 @@ define <4 x double> @test_addpd(<4 x dou<br>
; SKYLAKE-LABEL: test_addpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vaddpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaddpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_addpd:<br>
; SKX: # BB#0:<br>
@@ -78,8 +78,8 @@ define <8 x float> @test_addps(<8 x floa<br>
; SKYLAKE-LABEL: test_addps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vaddps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaddps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_addps:<br>
; SKX: # BB#0:<br>
@@ -126,8 +126,8 @@ define <4 x double> @test_addsubpd(<4 x<br>
; SKYLAKE-LABEL: test_addsubpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaddsubpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vaddsubpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaddsubpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_addsubpd:<br>
; SKX: # BB#0:<br>
@@ -175,8 +175,8 @@ define <8 x float> @test_addsubps(<8 x f<br>
; SKYLAKE-LABEL: test_addsubps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaddsubps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vaddsubps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaddsubps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_addsubps:<br>
; SKX: # BB#0:<br>
@@ -226,10 +226,10 @@ define <4 x double> @test_andnotpd(<4 x<br>
;<br>
; SKYLAKE-LABEL: test_andnotpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vandnpd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vandnpd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vandnpd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vandnpd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_andnotpd:<br>
; SKX: # BB#0:<br>
@@ -288,10 +288,10 @@ define <8 x float> @test_andnotps(<8 x f<br>
;<br>
; SKYLAKE-LABEL: test_andnotps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vandnps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vandnps (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vandnps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vandnps (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_andnotps:<br>
; SKX: # BB#0:<br>
@@ -350,10 +350,10 @@ define <4 x double> @test_andpd(<4 x dou<br>
;<br>
; SKYLAKE-LABEL: test_andpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vandpd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vandpd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vandpd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vandpd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_andpd:<br>
; SKX: # BB#0:<br>
@@ -410,10 +410,10 @@ define <8 x float> @test_andps(<8 x floa<br>
;<br>
; SKYLAKE-LABEL: test_andps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vandps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vandps (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vandps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vandps (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_andps:<br>
; SKX: # BB#0:<br>
@@ -470,10 +470,10 @@ define <4 x double> @test_blendpd(<4 x d<br>
;<br>
; SKYLAKE-LABEL: test_blendpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] sched: [1:0.33]<br>
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],mem[1,2],ymm0[3] sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],mem[1,2],ymm0[3] sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_blendpd:<br>
; SKX: # BB#0:<br>
@@ -523,9 +523,9 @@ define <8 x float> @test_blendps(<8 x fl<br>
;<br>
; SKYLAKE-LABEL: test_blendps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3,4,5,<wbr>6,7] sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],mem[2],ymm0[3],mem[<wbr>4,5,6],ymm0[7] sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3,4,5,<wbr>6,7] sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],mem[2],ymm0[3],mem[<wbr>4,5,6],ymm0[7] sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_blendps:<br>
; SKX: # BB#0:<br>
@@ -572,8 +572,8 @@ define <4 x double> @test_blendvpd(<4 x<br>
; SKYLAKE-LABEL: test_blendvpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:0.67]<br>
-; SKYLAKE-NEXT: vblendvpd %ymm2, (%rdi), %ymm0, %ymm0 # sched: [2:0.67]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vblendvpd %ymm2, (%rdi), %ymm0, %ymm0 # sched: [9:0.67]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_blendvpd:<br>
; SKX: # BB#0:<br>
@@ -621,8 +621,8 @@ define <8 x float> @test_blendvps(<8 x f<br>
; SKYLAKE-LABEL: test_blendvps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vblendvps %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:0.67]<br>
-; SKYLAKE-NEXT: vblendvps %ymm2, (%rdi), %ymm0, %ymm0 # sched: [2:0.67]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vblendvps %ymm2, (%rdi), %ymm0, %ymm0 # sched: [9:0.67]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_blendvps:<br>
; SKX: # BB#0:<br>
@@ -666,8 +666,8 @@ define <8 x float> @test_broadcastf128(<<br>
;<br>
; SKYLAKE-LABEL: test_broadcastf128:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_broadcastf128:<br>
; SKX: # BB#0:<br>
@@ -706,8 +706,8 @@ define <4 x double> @test_broadcastsd_ym<br>
;<br>
; SKYLAKE-LABEL: test_broadcastsd_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vbroadcastsd (%rdi), %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vbroadcastsd (%rdi), %ymm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_broadcastsd_ymm:<br>
; SKX: # BB#0:<br>
@@ -747,8 +747,8 @@ define <4 x float> @test_broadcastss(flo<br>
;<br>
; SKYLAKE-LABEL: test_broadcastss:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vbroadcastss (%rdi), %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vbroadcastss (%rdi), %xmm0 # sched: [6:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_broadcastss:<br>
; SKX: # BB#0:<br>
@@ -788,8 +788,8 @@ define <8 x float> @test_broadcastss_ymm<br>
;<br>
; SKYLAKE-LABEL: test_broadcastss_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vbroadcastss (%rdi), %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vbroadcastss (%rdi), %ymm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_broadcastss_ymm:<br>
; SKX: # BB#0:<br>
@@ -836,9 +836,9 @@ define <4 x double> @test_cmppd(<4 x dou<br>
; SKYLAKE-LABEL: test_cmppd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm1 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vcmpeqpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vorpd %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vcmpeqpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: vorpd %ymm0, %ymm1, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cmppd:<br>
; SKX: # BB#0:<br>
@@ -897,9 +897,9 @@ define <8 x float> @test_cmpps(<8 x floa<br>
; SKYLAKE-LABEL: test_cmpps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcmpeqps %ymm1, %ymm0, %ymm1 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vcmpeqps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vorps %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vcmpeqps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: vorps %ymm0, %ymm1, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cmpps:<br>
; SKX: # BB#0:<br>
@@ -958,9 +958,9 @@ define <4 x double> @test_cvtdq2pd(<4 x<br>
; SKYLAKE-LABEL: test_cvtdq2pd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtdq2pd %xmm0, %ymm0 # sched: [7:1.00]<br>
-; SKYLAKE-NEXT: vcvtdq2pd (%rdi), %ymm1 # sched: [7:1.00]<br>
+; SKYLAKE-NEXT: vcvtdq2pd (%rdi), %ymm1 # sched: [13:1.00]<br>
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtdq2pd:<br>
; SKX: # BB#0:<br>
@@ -1016,9 +1016,9 @@ define <8 x float> @test_cvtdq2ps(<8 x i<br>
; SKYLAKE-LABEL: test_cvtdq2ps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtdq2ps %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vcvtdq2ps (%rdi), %ymm1 # sched: [4:0.50]<br>
+; SKYLAKE-NEXT: vcvtdq2ps (%rdi), %ymm1 # sched: [11:0.50]<br>
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtdq2ps:<br>
; SKX: # BB#0:<br>
@@ -1074,7 +1074,7 @@ define <8 x i32> @test_cvtpd2dq(<4 x dou<br>
; SKYLAKE-NEXT: vcvttpd2dq %ymm0, %xmm0 # sched: [7:1.00]<br>
; SKYLAKE-NEXT: vcvttpd2dqy (%rdi), %xmm1 # sched: [8:1.00]<br>
; SKYLAKE-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtpd2dq:<br>
; SKX: # BB#0:<br>
@@ -1130,7 +1130,7 @@ define <8 x float> @test_cvtpd2ps(<4 x d<br>
; SKYLAKE-NEXT: vcvtpd2ps %ymm0, %xmm0 # sched: [7:1.00]<br>
; SKYLAKE-NEXT: vcvtpd2psy (%rdi), %xmm1 # sched: [8:1.00]<br>
; SKYLAKE-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtpd2ps:<br>
; SKX: # BB#0:<br>
@@ -1184,9 +1184,9 @@ define <8 x i32> @test_cvtps2dq(<8 x flo<br>
; SKYLAKE-LABEL: test_cvtps2dq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvttps2dq %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vcvttps2dq (%rdi), %ymm1 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vorps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vcvttps2dq (%rdi), %ymm1 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: vorps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtps2dq:<br>
; SKX: # BB#0:<br>
@@ -1237,8 +1237,8 @@ define <4 x double> @test_divpd(<4 x dou<br>
; SKYLAKE-LABEL: test_divpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [14:1.00]<br>
-; SKYLAKE-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [14:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [21:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_divpd:<br>
; SKX: # BB#0:<br>
@@ -1285,8 +1285,8 @@ define <8 x float> @test_divps(<8 x floa<br>
; SKYLAKE-LABEL: test_divps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [11:1.00]<br>
-; SKYLAKE-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [11:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [18:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_divps:<br>
; SKX: # BB#0:<br>
@@ -1333,8 +1333,8 @@ define <8 x float> @test_dpps(<8 x float<br>
; SKYLAKE-LABEL: test_dpps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [13:1.33]<br>
-; SKYLAKE-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [13:1.33]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [20:1.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_dpps:<br>
; SKX: # BB#0:<br>
@@ -1387,7 +1387,7 @@ define <4 x float> @test_extractf128(<8<br>
; SKYLAKE-NEXT: vextractf128 $1, %ymm0, %xmm0 # sched: [3:1.00]<br>
; SKYLAKE-NEXT: vextractf128 $1, %ymm1, (%rdi) # sched: [1:1.00]<br>
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_extractf128:<br>
; SKX: # BB#0:<br>
@@ -1436,8 +1436,8 @@ define <4 x double> @test_haddpd(<4 x do<br>
; SKYLAKE-LABEL: test_haddpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vhaddpd %ymm1, %ymm0, %ymm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: vhaddpd (%rdi), %ymm0, %ymm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vhaddpd (%rdi), %ymm0, %ymm0 # sched: [13:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_haddpd:<br>
; SKX: # BB#0:<br>
@@ -1485,8 +1485,8 @@ define <8 x float> @test_haddps(<8 x flo<br>
; SKYLAKE-LABEL: test_haddps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vhaddps %ymm1, %ymm0, %ymm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: vhaddps (%rdi), %ymm0, %ymm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vhaddps (%rdi), %ymm0, %ymm0 # sched: [13:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_haddps:<br>
; SKX: # BB#0:<br>
@@ -1534,8 +1534,8 @@ define <4 x double> @test_hsubpd(<4 x do<br>
; SKYLAKE-LABEL: test_hsubpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vhsubpd %ymm1, %ymm0, %ymm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: vhsubpd (%rdi), %ymm0, %ymm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vhsubpd (%rdi), %ymm0, %ymm0 # sched: [13:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_hsubpd:<br>
; SKX: # BB#0:<br>
@@ -1583,8 +1583,8 @@ define <8 x float> @test_hsubps(<8 x flo<br>
; SKYLAKE-LABEL: test_hsubps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vhsubps %ymm1, %ymm0, %ymm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: vhsubps (%rdi), %ymm0, %ymm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vhsubps (%rdi), %ymm0, %ymm0 # sched: [13:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_hsubps:<br>
; SKX: # BB#0:<br>
@@ -1635,9 +1635,9 @@ define <8 x float> @test_insertf128(<8 x<br>
; SKYLAKE-LABEL: test_insertf128:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vinsertf128 $1, (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vinsertf128 $1, (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br>
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_insertf128:<br>
; SKX: # BB#0:<br>
@@ -1686,8 +1686,8 @@ define <32 x i8> @test_lddqu(i8* %a0) {<br>
;<br>
; SKYLAKE-LABEL: test_lddqu:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vlddqu (%rdi), %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vlddqu (%rdi), %ymm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_lddqu:<br>
; SKX: # BB#0:<br>
@@ -1732,10 +1732,10 @@ define <2 x double> @test_maskmovpd(i8*<br>
;<br>
; SKYLAKE-LABEL: test_maskmovpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmaskmovpd (%rdi), %xmm0, %xmm2 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vmaskmovpd %xmm1, %xmm0, (%rdi) # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vmaskmovpd (%rdi), %xmm0, %xmm2 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vmaskmovpd %xmm1, %xmm0, (%rdi) # sched: [2:1.00]<br>
; SKYLAKE-NEXT: vmovapd %xmm2, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_maskmovpd:<br>
; SKX: # BB#0:<br>
@@ -1788,10 +1788,10 @@ define <4 x double> @test_maskmovpd_ymm(<br>
;<br>
; SKYLAKE-LABEL: test_maskmovpd_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmaskmovpd (%rdi), %ymm0, %ymm2 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vmaskmovpd %ymm1, %ymm0, (%rdi) # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vmaskmovpd (%rdi), %ymm0, %ymm2 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vmaskmovpd %ymm1, %ymm0, (%rdi) # sched: [2:1.00]<br>
; SKYLAKE-NEXT: vmovapd %ymm2, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_maskmovpd_ymm:<br>
; SKX: # BB#0:<br>
@@ -1844,10 +1844,10 @@ define <4 x float> @test_maskmovps(i8* %<br>
;<br>
; SKYLAKE-LABEL: test_maskmovps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmaskmovps (%rdi), %xmm0, %xmm2 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vmaskmovps %xmm1, %xmm0, (%rdi) # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vmaskmovps (%rdi), %xmm0, %xmm2 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vmaskmovps %xmm1, %xmm0, (%rdi) # sched: [2:1.00]<br>
; SKYLAKE-NEXT: vmovaps %xmm2, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_maskmovps:<br>
; SKX: # BB#0:<br>
@@ -1900,10 +1900,10 @@ define <8 x float> @test_maskmovps_ymm(i<br>
;<br>
; SKYLAKE-LABEL: test_maskmovps_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmaskmovps (%rdi), %ymm0, %ymm2 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vmaskmovps %ymm1, %ymm0, (%rdi) # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vmaskmovps (%rdi), %ymm0, %ymm2 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vmaskmovps %ymm1, %ymm0, (%rdi) # sched: [2:1.00]<br>
; SKYLAKE-NEXT: vmovaps %ymm2, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_maskmovps_ymm:<br>
; SKX: # BB#0:<br>
@@ -1954,8 +1954,8 @@ define <4 x double> @test_maxpd(<4 x dou<br>
; SKYLAKE-LABEL: test_maxpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmaxpd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vmaxpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmaxpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_maxpd:<br>
; SKX: # BB#0:<br>
@@ -2003,8 +2003,8 @@ define <8 x float> @test_maxps(<8 x floa<br>
; SKYLAKE-LABEL: test_maxps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmaxps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vmaxps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmaxps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_maxps:<br>
; SKX: # BB#0:<br>
@@ -2052,8 +2052,8 @@ define <4 x double> @test_minpd(<4 x dou<br>
; SKYLAKE-LABEL: test_minpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vminpd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vminpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vminpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_minpd:<br>
; SKX: # BB#0:<br>
@@ -2101,8 +2101,8 @@ define <8 x float> @test_minps(<8 x floa<br>
; SKYLAKE-LABEL: test_minps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vminps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vminps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vminps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_minps:<br>
; SKX: # BB#0:<br>
@@ -2152,10 +2152,10 @@ define <4 x double> @test_movapd(<4 x do<br>
;<br>
; SKYLAKE-LABEL: test_movapd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovapd (%rdi), %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovapd (%rdi), %ymm0 # sched: [7:0.50]<br>
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm0, %ymm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovapd %ymm0, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movapd:<br>
; SKX: # BB#0:<br>
@@ -2207,10 +2207,10 @@ define <8 x float> @test_movaps(<8 x flo<br>
;<br>
; SKYLAKE-LABEL: test_movaps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovaps (%rdi), %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovaps (%rdi), %ymm0 # sched: [7:0.50]<br>
; SKYLAKE-NEXT: vaddps %ymm0, %ymm0, %ymm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovaps %ymm0, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movaps:<br>
; SKX: # BB#0:<br>
@@ -2263,9 +2263,9 @@ define <4 x double> @test_movddup(<4 x d<br>
; SKYLAKE-LABEL: test_movddup:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vmovddup {{.*#+}} ymm1 = mem[0,0,2,2] sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovddup {{.*#+}} ymm1 = mem[0,0,2,2] sched: [7:0.50]<br>
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movddup:<br>
; SKX: # BB#0:<br>
@@ -2317,7 +2317,7 @@ define i32 @test_movmskpd(<4 x double> %<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovmskpd %ymm0, %eax # sched: [2:1.00]<br>
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movmskpd:<br>
; SKX: # BB#0:<br>
@@ -2363,7 +2363,7 @@ define i32 @test_movmskps(<8 x float> %a<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovmskps %ymm0, %eax # sched: [2:1.00]<br>
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movmskps:<br>
; SKX: # BB#0:<br>
@@ -2409,7 +2409,7 @@ define <4 x double> @test_movntpd(<4 x d<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm0, %ymm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovntpd %ymm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movntpd:<br>
; SKX: # BB#0:<br>
@@ -2456,7 +2456,7 @@ define <8 x float> @test_movntps(<8 x fl<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaddps %ymm0, %ymm0, %ymm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovntps %ymm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movntps:<br>
; SKX: # BB#0:<br>
@@ -2505,9 +2505,9 @@ define <8 x float> @test_movshdup(<8 x f<br>
; SKYLAKE-LABEL: test_movshdup:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vmovshdup {{.*#+}} ymm1 = mem[1,1,3,3,5,5,7,7] sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovshdup {{.*#+}} ymm1 = mem[1,1,3,3,5,5,7,7] sched: [7:0.50]<br>
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movshdup:<br>
; SKX: # BB#0:<br>
@@ -2561,9 +2561,9 @@ define <8 x float> @test_movsldup(<8 x f<br>
; SKYLAKE-LABEL: test_movsldup:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vmovsldup {{.*#+}} ymm1 = mem[0,0,2,2,4,4,6,6] sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovsldup {{.*#+}} ymm1 = mem[0,0,2,2,4,4,6,6] sched: [7:0.50]<br>
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movsldup:<br>
; SKX: # BB#0:<br>
@@ -2618,10 +2618,10 @@ define <4 x double> @test_movupd(<4 x do<br>
;<br>
; SKYLAKE-LABEL: test_movupd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovupd (%rdi), %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovupd (%rdi), %ymm0 # sched: [7:0.50]<br>
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm0, %ymm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovupd %ymm0, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movupd:<br>
; SKX: # BB#0:<br>
@@ -2675,10 +2675,10 @@ define <8 x float> @test_movups(<8 x flo<br>
;<br>
; SKYLAKE-LABEL: test_movups:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovups (%rdi), %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovups (%rdi), %ymm0 # sched: [7:0.50]<br>
; SKYLAKE-NEXT: vaddps %ymm0, %ymm0, %ymm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovups %ymm0, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movups:<br>
; SKX: # BB#0:<br>
@@ -2728,8 +2728,8 @@ define <4 x double> @test_mulpd(<4 x dou<br>
; SKYLAKE-LABEL: test_mulpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmulpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vmulpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmulpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_mulpd:<br>
; SKX: # BB#0:<br>
@@ -2776,8 +2776,8 @@ define <8 x float> @test_mulps(<8 x floa<br>
; SKYLAKE-LABEL: test_mulps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmulps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vmulps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmulps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_mulps:<br>
; SKX: # BB#0:<br>
@@ -2826,10 +2826,10 @@ define <4 x double> @orpd(<4 x double> %<br>
;<br>
; SKYLAKE-LABEL: orpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vorpd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vorpd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vorpd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vorpd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: orpd:<br>
; SKX: # BB#0:<br>
@@ -2886,10 +2886,10 @@ define <8 x float> @test_orps(<8 x float<br>
;<br>
; SKYLAKE-LABEL: test_orps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vorps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vorps (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vorps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vorps (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_orps:<br>
; SKX: # BB#0:<br>
@@ -2947,9 +2947,9 @@ define <4 x double> @test_perm2f128(<4 x<br>
; SKYLAKE-LABEL: test_perm2f128:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[0,1] sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [3:1.00]<br>
+; SKYLAKE-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [10:1.00]<br>
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_perm2f128:<br>
; SKX: # BB#0:<br>
@@ -3003,9 +3003,9 @@ define <2 x double> @test_permilpd(<2 x<br>
; SKYLAKE-LABEL: test_permilpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpermilpd {{.*#+}} xmm1 = mem[1,0] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vpermilpd {{.*#+}} xmm1 = mem[1,0] sched: [7:1.00]<br>
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_permilpd:<br>
; SKX: # BB#0:<br>
@@ -3059,9 +3059,9 @@ define <4 x double> @test_permilpd_ymm(<<br>
; SKYLAKE-LABEL: test_permilpd_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,3] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpermilpd {{.*#+}} ymm1 = mem[1,0,2,3] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vpermilpd {{.*#+}} ymm1 = mem[1,0,2,3] sched: [8:1.00]<br>
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_permilpd_ymm:<br>
; SKX: # BB#0:<br>
@@ -3115,9 +3115,9 @@ define <4 x float> @test_permilps(<4 x f<br>
; SKYLAKE-LABEL: test_permilps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpermilps {{.*#+}} xmm1 = mem[3,2,1,0] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vpermilps {{.*#+}} xmm1 = mem[3,2,1,0] sched: [7:1.00]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_permilps:<br>
; SKX: # BB#0:<br>
@@ -3171,9 +3171,9 @@ define <8 x float> @test_permilps_ymm(<8<br>
; SKYLAKE-LABEL: test_permilps_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpermilps {{.*#+}} ymm1 = mem[3,2,1,0,7,6,5,4] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vpermilps {{.*#+}} ymm1 = mem[3,2,1,0,7,6,5,4] sched: [8:1.00]<br>
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_permilps_ymm:<br>
; SKX: # BB#0:<br>
@@ -3224,8 +3224,8 @@ define <2 x double> @test_permilvarpd(<2<br>
; SKYLAKE-LABEL: test_permilvarpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpermilpd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpermilpd (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpermilpd (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_permilvarpd:<br>
; SKX: # BB#0:<br>
@@ -3273,8 +3273,8 @@ define <4 x double> @test_permilvarpd_ym<br>
; SKYLAKE-LABEL: test_permilvarpd_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpermilpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpermilpd (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpermilpd (%rdi), %ymm0, %ymm0 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_permilvarpd_ymm:<br>
; SKX: # BB#0:<br>
@@ -3322,8 +3322,8 @@ define <4 x float> @test_permilvarps(<4<br>
; SKYLAKE-LABEL: test_permilvarps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpermilps %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpermilps (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpermilps (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_permilvarps:<br>
; SKX: # BB#0:<br>
@@ -3371,8 +3371,8 @@ define <8 x float> @test_permilvarps_ymm<br>
; SKYLAKE-LABEL: test_permilvarps_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpermilps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpermilps (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpermilps (%rdi), %ymm0, %ymm0 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_permilvarps_ymm:<br>
; SKX: # BB#0:<br>
@@ -3423,9 +3423,9 @@ define <8 x float> @test_rcpps(<8 x floa<br>
; SKYLAKE-LABEL: test_rcpps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vrcpps %ymm0, %ymm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vrcpps (%rdi), %ymm1 # sched: [4:1.00]<br>
+; SKYLAKE-NEXT: vrcpps (%rdi), %ymm1 # sched: [11:1.00]<br>
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_rcpps:<br>
; SKX: # BB#0:<br>
@@ -3480,9 +3480,9 @@ define <4 x double> @test_roundpd(<4 x d<br>
; SKYLAKE-LABEL: test_roundpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vroundpd $7, %ymm0, %ymm0 # sched: [8:0.67]<br>
-; SKYLAKE-NEXT: vroundpd $7, (%rdi), %ymm1 # sched: [8:0.67]<br>
+; SKYLAKE-NEXT: vroundpd $7, (%rdi), %ymm1 # sched: [15:0.67]<br>
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_roundpd:<br>
; SKX: # BB#0:<br>
@@ -3537,9 +3537,9 @@ define <8 x float> @test_roundps(<8 x fl<br>
; SKYLAKE-LABEL: test_roundps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vroundps $7, %ymm0, %ymm0 # sched: [8:0.67]<br>
-; SKYLAKE-NEXT: vroundps $7, (%rdi), %ymm1 # sched: [8:0.67]<br>
+; SKYLAKE-NEXT: vroundps $7, (%rdi), %ymm1 # sched: [15:0.67]<br>
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_roundps:<br>
; SKX: # BB#0:<br>
@@ -3594,9 +3594,9 @@ define <8 x float> @test_rsqrtps(<8 x fl<br>
; SKYLAKE-LABEL: test_rsqrtps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vrsqrtps %ymm0, %ymm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vrsqrtps (%rdi), %ymm1 # sched: [4:1.00]<br>
+; SKYLAKE-NEXT: vrsqrtps (%rdi), %ymm1 # sched: [11:1.00]<br>
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_rsqrtps:<br>
; SKX: # BB#0:<br>
@@ -3651,9 +3651,9 @@ define <4 x double> @test_shufpd(<4 x do<br>
; SKYLAKE-LABEL: test_shufpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[1],ymm1[0],ymm0[2],ymm1[<wbr>3] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vshufpd {{.*#+}} ymm1 = ymm1[1],mem[0],ymm1[2],mem[3] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vshufpd {{.*#+}} ymm1 = ymm1[1],mem[0],ymm1[2],mem[3] sched: [8:1.00]<br>
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_shufpd:<br>
; SKX: # BB#0:<br>
@@ -3704,8 +3704,8 @@ define <8 x float> @test_shufps(<8 x flo<br>
; SKYLAKE-LABEL: test_shufps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,0],ymm1[0,0],ymm0[4,4],<wbr>ymm1[4,4] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,3],mem[0,0],ymm0[4,7],<wbr>mem[4,4] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,3],mem[0,0],ymm0[4,7],<wbr>mem[4,4] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_shufps:<br>
; SKX: # BB#0:<br>
@@ -3755,9 +3755,9 @@ define <4 x double> @test_sqrtpd(<4 x do<br>
; SKYLAKE-LABEL: test_sqrtpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [18:1.00]<br>
-; SKYLAKE-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [18:1.00]<br>
+; SKYLAKE-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [25:1.00]<br>
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_sqrtpd:<br>
; SKX: # BB#0:<br>
@@ -3812,9 +3812,9 @@ define <8 x float> @test_sqrtps(<8 x flo<br>
; SKYLAKE-LABEL: test_sqrtps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vsqrtps %ymm0, %ymm0 # sched: [12:1.00]<br>
-; SKYLAKE-NEXT: vsqrtps (%rdi), %ymm1 # sched: [12:1.00]<br>
+; SKYLAKE-NEXT: vsqrtps (%rdi), %ymm1 # sched: [19:1.00]<br>
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_sqrtps:<br>
; SKX: # BB#0:<br>
@@ -3866,8 +3866,8 @@ define <4 x double> @test_subpd(<4 x dou<br>
; SKYLAKE-LABEL: test_subpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vsubpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vsubpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vsubpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_subpd:<br>
; SKX: # BB#0:<br>
@@ -3914,8 +3914,8 @@ define <8 x float> @test_subps(<8 x floa<br>
; SKYLAKE-LABEL: test_subps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vsubps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vsubps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vsubps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_subps:<br>
; SKX: # BB#0:<br>
@@ -3972,10 +3972,10 @@ define i32 @test_testpd(<2 x double> %a0<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: xorl %eax, %eax # sched: [1:0.25]<br>
; SKYLAKE-NEXT: vtestpd %xmm1, %xmm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: setb %al # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vtestpd (%rdi), %xmm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: setb %al # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vtestpd (%rdi), %xmm0 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_testpd:<br>
; SKX: # BB#0:<br>
@@ -4046,11 +4046,11 @@ define i32 @test_testpd_ymm(<4 x double><br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: xorl %eax, %eax # sched: [1:0.25]<br>
; SKYLAKE-NEXT: vtestpd %ymm1, %ymm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: setb %al # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vtestpd (%rdi), %ymm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: setb %al # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vtestpd (%rdi), %ymm0 # sched: [9:1.00]<br>
+; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_testpd_ymm:<br>
; SKX: # BB#0:<br>
@@ -4120,10 +4120,10 @@ define i32 @test_testps(<4 x float> %a0,<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: xorl %eax, %eax # sched: [1:0.25]<br>
; SKYLAKE-NEXT: vtestps %xmm1, %xmm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: setb %al # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vtestps (%rdi), %xmm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: setb %al # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vtestps (%rdi), %xmm0 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_testps:<br>
; SKX: # BB#0:<br>
@@ -4194,11 +4194,11 @@ define i32 @test_testps_ymm(<8 x float><br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: xorl %eax, %eax # sched: [1:0.25]<br>
; SKYLAKE-NEXT: vtestps %ymm1, %ymm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: setb %al # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vtestps (%rdi), %ymm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: setb %al # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vtestps (%rdi), %ymm0 # sched: [9:1.00]<br>
+; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_testps_ymm:<br>
; SKX: # BB#0:<br>
@@ -4261,9 +4261,9 @@ define <4 x double> @test_unpckhpd(<4 x<br>
; SKYLAKE-LABEL: test_unpckhpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[<wbr>3] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vunpckhpd {{.*#+}} ymm1 = ymm1[1],mem[1],ymm1[3],mem[3] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vunpckhpd {{.*#+}} ymm1 = ymm1[1],mem[1],ymm1[3],mem[3] sched: [8:1.00]<br>
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_unpckhpd:<br>
; SKX: # BB#0:<br>
@@ -4314,8 +4314,8 @@ define <8 x float> @test_unpckhps(<8 x f<br>
; SKYLAKE-LABEL: test_unpckhps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[<wbr>3],ymm0[6],ymm1[6],ymm0[7],<wbr>ymm1[7] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],<wbr>ymm0[6],mem[6],ymm0[7],mem[7] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],<wbr>ymm0[6],mem[6],ymm0[7],mem[7] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_unpckhps:<br>
; SKX: # BB#0:<br>
@@ -4365,9 +4365,9 @@ define <4 x double> @test_unpcklpd(<4 x<br>
; SKYLAKE-LABEL: test_unpcklpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[<wbr>2] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vunpcklpd {{.*#+}} ymm1 = ymm1[0],mem[0],ymm1[2],mem[2] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vunpcklpd {{.*#+}} ymm1 = ymm1[0],mem[0],ymm1[2],mem[2] sched: [8:1.00]<br>
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_unpcklpd:<br>
; SKX: # BB#0:<br>
@@ -4418,8 +4418,8 @@ define <8 x float> @test_unpcklps(<8 x f<br>
; SKYLAKE-LABEL: test_unpcklps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[<wbr>1],ymm0[4],ymm1[4],ymm0[5],<wbr>ymm1[5] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],<wbr>ymm0[4],mem[4],ymm0[5],mem[5] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],<wbr>ymm0[4],mem[4],ymm0[5],mem[5] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_unpcklps:<br>
; SKX: # BB#0:<br>
@@ -4468,10 +4468,10 @@ define <4 x double> @test_xorpd(<4 x dou<br>
;<br>
; SKYLAKE-LABEL: test_xorpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vxorpd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vxorpd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vxorpd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vxorpd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_xorpd:<br>
; SKX: # BB#0:<br>
@@ -4528,10 +4528,10 @@ define <8 x float> @test_xorps(<8 x floa<br>
;<br>
; SKYLAKE-LABEL: test_xorps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vxorps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vxorps (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vxorps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vxorps (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_xorps:<br>
; SKX: # BB#0:<br>
@@ -4583,7 +4583,7 @@ define void @test_zeroall() {<br>
; SKYLAKE-LABEL: test_zeroall:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vzeroall # sched: [16:4.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_zeroall:<br>
; SKX: # BB#0:<br>
@@ -4623,7 +4623,7 @@ define void @test_zeroupper() {<br>
; SKYLAKE-LABEL: test_zeroupper:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_zeroupper:<br>
; SKX: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>avx2-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/avx2-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>avx2-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>avx2-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -20,9 +20,9 @@ define <8 x i32> @test_broadcasti128(<8<br>
;<br>
; SKYLAKE-LABEL: test_broadcasti128:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_broadcasti128:<br>
; SKX: # BB#0:<br>
@@ -58,7 +58,7 @@ define <4 x double> @test_broadcastsd_ym<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vbroadcastsd %xmm0, %ymm0 # sched: [3:1.00]<br>
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_broadcastsd_ymm:<br>
; SKX: # BB#0:<br>
@@ -93,7 +93,7 @@ define <4 x float> @test_broadcastss(<4<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vbroadcastss %xmm0, %xmm0 # sched: [1:1.00]<br>
; SKYLAKE-NEXT: vaddps %xmm0, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_broadcastss:<br>
; SKX: # BB#0:<br>
@@ -128,7 +128,7 @@ define <8 x float> @test_broadcastss_ymm<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vbroadcastss %xmm0, %ymm0 # sched: [3:1.00]<br>
; SKYLAKE-NEXT: vaddps %ymm0, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_broadcastss_ymm:<br>
; SKX: # BB#0:<br>
@@ -167,12 +167,12 @@ define <4 x i32> @test_extracti128(<8 x<br>
;<br>
; SKYLAKE-LABEL: test_extracti128:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm2 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm2 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
; SKYLAKE-NEXT: vextracti128 $1, %ymm0, %xmm0 # sched: [3:1.00]<br>
; SKYLAKE-NEXT: vextracti128 $1, %ymm2, (%rdi) # sched: [1:1.00]<br>
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_extracti128:<br>
; SKX: # BB#0:<br>
@@ -212,8 +212,8 @@ define <2 x double> @test_gatherdpd(<2 x<br>
;<br>
; SKYLAKE-LABEL: test_gatherdpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_gatherdpd:<br>
; SKX: # BB#0:<br>
@@ -242,8 +242,8 @@ define <4 x double> @test_gatherdpd_ymm(<br>
;<br>
; SKYLAKE-LABEL: test_gatherdpd_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vgatherdpd %ymm2, (%rdi,%xmm1,8), %ymm0 # sched: [20:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vgatherdpd %ymm2, (%rdi,%xmm1,8), %ymm0 # sched: [25:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_gatherdpd_ymm:<br>
; SKX: # BB#0:<br>
@@ -272,8 +272,8 @@ define <4 x float> @test_gatherdps(<4 x<br>
;<br>
; SKYLAKE-LABEL: test_gatherdps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_gatherdps:<br>
; SKX: # BB#0:<br>
@@ -302,8 +302,8 @@ define <8 x float> @test_gatherdps_ymm(<<br>
;<br>
; SKYLAKE-LABEL: test_gatherdps_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vgatherdps %ymm2, (%rdi,%ymm1,4), %ymm0 # sched: [20:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vgatherdps %ymm2, (%rdi,%ymm1,4), %ymm0 # sched: [25:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_gatherdps_ymm:<br>
; SKX: # BB#0:<br>
@@ -332,8 +332,8 @@ define <2 x double> @test_gatherqpd(<2 x<br>
;<br>
; SKYLAKE-LABEL: test_gatherqpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_gatherqpd:<br>
; SKX: # BB#0:<br>
@@ -362,8 +362,8 @@ define <4 x double> @test_gatherqpd_ymm(<br>
;<br>
; SKYLAKE-LABEL: test_gatherqpd_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vgatherqpd %ymm2, (%rdi,%ymm1,8), %ymm0 # sched: [20:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vgatherqpd %ymm2, (%rdi,%ymm1,8), %ymm0 # sched: [25:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_gatherqpd_ymm:<br>
; SKX: # BB#0:<br>
@@ -392,8 +392,8 @@ define <4 x float> @test_gatherqps(<4 x<br>
;<br>
; SKYLAKE-LABEL: test_gatherqps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_gatherqps:<br>
; SKX: # BB#0:<br>
@@ -424,9 +424,9 @@ define <4 x float> @test_gatherqps_ymm(<<br>
;<br>
; SKYLAKE-LABEL: test_gatherqps_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vgatherqps %xmm2, (%rdi,%ymm1,4), %xmm0 # sched: [20:1.00]<br>
+; SKYLAKE-NEXT: vgatherqps %xmm2, (%rdi,%ymm1,4), %xmm0 # sched: [25:1.00]<br>
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_gatherqps_ymm:<br>
; SKX: # BB#0:<br>
@@ -462,9 +462,9 @@ define <8 x i32> @test_inserti128(<8 x i<br>
; SKYLAKE-LABEL: test_inserti128:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm1 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vinserti128 $1, (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vinserti128 $1, (%rdi), %ymm0, %ymm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_inserti128:<br>
; SKX: # BB#0:<br>
@@ -501,8 +501,8 @@ define <4 x i64> @test_movntdqa(i8* %a0)<br>
;<br>
; SKYLAKE-LABEL: test_movntdqa:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovntdqa (%rdi), %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmovntdqa (%rdi), %ymm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movntdqa:<br>
; SKX: # BB#0:<br>
@@ -534,8 +534,8 @@ define <16 x i16> @test_mpsadbw(<32 x i8<br>
; SKYLAKE-LABEL: test_mpsadbw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0 # sched: [4:2.00]<br>
-; SKYLAKE-NEXT: vmpsadbw $7, (%rdi), %ymm0, %ymm0 # sched: [4:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmpsadbw $7, (%rdi), %ymm0, %ymm0 # sched: [11:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_mpsadbw:<br>
; SKX: # BB#0:<br>
@@ -573,10 +573,10 @@ define <32 x i8> @test_pabsb(<32 x i8> %<br>
;<br>
; SKYLAKE-LABEL: test_pabsb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpabsb %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpabsb (%rdi), %ymm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpabsb %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpabsb (%rdi), %ymm1 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pabsb:<br>
; SKX: # BB#0:<br>
@@ -616,10 +616,10 @@ define <8 x i32> @test_pabsd(<8 x i32> %<br>
;<br>
; SKYLAKE-LABEL: test_pabsd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpabsd %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpabsd (%rdi), %ymm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpabsd %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpabsd (%rdi), %ymm1 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pabsd:<br>
; SKX: # BB#0:<br>
@@ -659,10 +659,10 @@ define <16 x i16> @test_pabsw(<16 x i16><br>
;<br>
; SKYLAKE-LABEL: test_pabsw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpabsw %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpabsw (%rdi), %ymm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpabsw %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpabsw (%rdi), %ymm1 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pabsw:<br>
; SKX: # BB#0:<br>
@@ -701,8 +701,8 @@ define <16 x i16> @test_packssdw(<8 x i3<br>
; SKYLAKE-LABEL: test_packssdw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpackssdw (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpackssdw (%rdi), %ymm0, %ymm0 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_packssdw:<br>
; SKX: # BB#0:<br>
@@ -739,8 +739,8 @@ define <32 x i8> @test_packsswb(<16 x i1<br>
; SKYLAKE-LABEL: test_packsswb:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpacksswb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpacksswb (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpacksswb (%rdi), %ymm0, %ymm0 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_packsswb:<br>
; SKX: # BB#0:<br>
@@ -777,8 +777,8 @@ define <16 x i16> @test_packusdw(<8 x i3<br>
; SKYLAKE-LABEL: test_packusdw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpackusdw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpackusdw (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpackusdw (%rdi), %ymm0, %ymm0 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_packusdw:<br>
; SKX: # BB#0:<br>
@@ -815,8 +815,8 @@ define <32 x i8> @test_packuswb(<16 x i1<br>
; SKYLAKE-LABEL: test_packuswb:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpackuswb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpackuswb (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpackuswb (%rdi), %ymm0, %ymm0 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_packuswb:<br>
; SKX: # BB#0:<br>
@@ -852,9 +852,9 @@ define <32 x i8> @test_paddb(<32 x i8> %<br>
;<br>
; SKYLAKE-LABEL: test_paddb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddb %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpaddb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddb:<br>
; SKX: # BB#0:<br>
@@ -888,9 +888,9 @@ define <8 x i32> @test_paddd(<8 x i32> %<br>
;<br>
; SKYLAKE-LABEL: test_paddd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpaddd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddd:<br>
; SKX: # BB#0:<br>
@@ -924,9 +924,9 @@ define <4 x i64> @test_paddq(<4 x i64> %<br>
;<br>
; SKYLAKE-LABEL: test_paddq:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpaddq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddq:<br>
; SKX: # BB#0:<br>
@@ -960,9 +960,9 @@ define <32 x i8> @test_paddsb(<32 x i8><br>
;<br>
; SKYLAKE-LABEL: test_paddsb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpaddsb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddsb:<br>
; SKX: # BB#0:<br>
@@ -997,9 +997,9 @@ define <16 x i16> @test_paddsw(<16 x i16<br>
;<br>
; SKYLAKE-LABEL: test_paddsw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpaddsw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddsw:<br>
; SKX: # BB#0:<br>
@@ -1034,9 +1034,9 @@ define <32 x i8> @test_paddusb(<32 x i8><br>
;<br>
; SKYLAKE-LABEL: test_paddusb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddusb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpaddusb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddusb:<br>
; SKX: # BB#0:<br>
@@ -1071,9 +1071,9 @@ define <16 x i16> @test_paddusw(<16 x i1<br>
;<br>
; SKYLAKE-LABEL: test_paddusw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddusw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpaddusw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddusw:<br>
; SKX: # BB#0:<br>
@@ -1108,9 +1108,9 @@ define <16 x i16> @test_paddw(<16 x i16><br>
;<br>
; SKYLAKE-LABEL: test_paddw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpaddw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddw:<br>
; SKX: # BB#0:<br>
@@ -1145,8 +1145,8 @@ define <32 x i8> @test_palignr(<32 x i8><br>
; SKYLAKE-LABEL: test_palignr:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpalignr {{.*#+}} ymm0 = ymm1[1,2,3,4,5,6,7,8,9,10,11,<wbr>12,13,14,15],ymm0[0],ymm1[17,<wbr>18,19,20,21,22,23,24,25,26,27,<wbr>28,29,30,31],ymm0[16] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpalignr {{.*#+}} ymm0 = mem[1,2,3,4,5,6,7,8,9,10,11,<wbr>12,13,14,15],ymm0[0],mem[17,<wbr>18,19,20,21,22,23,24,25,26,27,<wbr>28,29,30,31],ymm0[16] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpalignr {{.*#+}} ymm0 = mem[1,2,3,4,5,6,7,8,9,10,11,<wbr>12,13,14,15],ymm0[0],mem[17,<wbr>18,19,20,21,22,23,24,25,26,27,<wbr>28,29,30,31],ymm0[16] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_palignr:<br>
; SKX: # BB#0:<br>
@@ -1182,10 +1182,10 @@ define <4 x i64> @test_pand(<4 x i64> %a<br>
;<br>
; SKYLAKE-LABEL: test_pand:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpand %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpand (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpand %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpand (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pand:<br>
; SKX: # BB#0:<br>
@@ -1224,10 +1224,10 @@ define <4 x i64> @test_pandn(<4 x i64> %<br>
;<br>
; SKYLAKE-LABEL: test_pandn:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpandn %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpandn (%rdi), %ymm0, %ymm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpandn %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpandn (%rdi), %ymm0, %ymm1 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pandn:<br>
; SKX: # BB#0:<br>
@@ -1266,9 +1266,9 @@ define <32 x i8> @test_pavgb(<32 x i8> %<br>
;<br>
; SKYLAKE-LABEL: test_pavgb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpavgb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpavgb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpavgb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpavgb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pavgb:<br>
; SKX: # BB#0:<br>
@@ -1312,9 +1312,9 @@ define <16 x i16> @test_pavgw(<16 x i16><br>
;<br>
; SKYLAKE-LABEL: test_pavgw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpavgw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpavgw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpavgw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpavgw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pavgw:<br>
; SKX: # BB#0:<br>
@@ -1360,10 +1360,10 @@ define <4 x i32> @test_pblendd(<4 x i32><br>
;<br>
; SKYLAKE-LABEL: test_pblendd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[3] sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpblendd {{.*#+}} xmm1 = mem[0],xmm1[1],mem[2],xmm1[3] sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[3] sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpblendd {{.*#+}} xmm1 = mem[0],xmm1[1],mem[2],xmm1[3] sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pblendd:<br>
; SKX: # BB#0:<br>
@@ -1402,10 +1402,10 @@ define <8 x i32> @test_pblendd_ymm(<8 x<br>
;<br>
; SKYLAKE-LABEL: test_pblendd_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2],ymm0[3,4,5,6],<wbr>ymm1[7] sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0],mem[1,2],ymm1[3,4,5,6,<wbr>7] sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2],ymm0[3,4,5,6],<wbr>ymm1[7] sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0],mem[1,2],ymm1[3,4,5,6,<wbr>7] sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pblendd_ymm:<br>
; SKX: # BB#0:<br>
@@ -1443,8 +1443,8 @@ define <32 x i8> @test_pblendvb(<32 x i8<br>
; SKYLAKE-LABEL: test_pblendvb:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:0.67]<br>
-; SKYLAKE-NEXT: vpblendvb %ymm3, (%rdi), %ymm0, %ymm0 # sched: [2:0.67]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpblendvb %ymm3, (%rdi), %ymm0, %ymm0 # sched: [8:0.67]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pblendvb:<br>
; SKX: # BB#0:<br>
@@ -1480,8 +1480,8 @@ define <16 x i16> @test_pblendw(<16 x i1<br>
; SKYLAKE-LABEL: test_pblendw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4],ymm0[5,<wbr>6,7,8,9],ymm1[10,11,12],ymm0[<wbr>13,14,15] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpblendw {{.*#+}} ymm0 = mem[0],ymm0[1],mem[2],ymm0[3],<wbr>mem[4],ymm0[5],mem[6],ymm0[7],<wbr>mem[8],ymm0[9],mem[10],ymm0[<wbr>11],mem[12],ymm0[13],mem[14],<wbr>ymm0[15] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpblendw {{.*#+}} ymm0 = mem[0],ymm0[1],mem[2],ymm0[3],<wbr>mem[4],ymm0[5],mem[6],ymm0[7],<wbr>mem[8],ymm0[9],mem[10],ymm0[<wbr>11],mem[12],ymm0[13],mem[14],<wbr>ymm0[15] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pblendw:<br>
; SKX: # BB#0:<br>
@@ -1518,9 +1518,9 @@ define <16 x i8> @test_pbroadcastb(<16 x<br>
; SKYLAKE-LABEL: test_pbroadcastb:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpbroadcastb %xmm0, %xmm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpbroadcastb (%rdi), %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpbroadcastb (%rdi), %xmm1 # sched: [7:1.00]<br>
+; SKYLAKE-NEXT: vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pbroadcastb:<br>
; SKX: # BB#0:<br>
@@ -1560,9 +1560,9 @@ define <32 x i8> @test_pbroadcastb_ymm(<<br>
; SKYLAKE-LABEL: test_pbroadcastb_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpbroadcastb %xmm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpbroadcastb (%rdi), %ymm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpbroadcastb (%rdi), %ymm1 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: vpaddb %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pbroadcastb_ymm:<br>
; SKX: # BB#0:<br>
@@ -1602,9 +1602,9 @@ define <4 x i32> @test_pbroadcastd(<4 x<br>
; SKYLAKE-LABEL: test_pbroadcastd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpbroadcastd %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpbroadcastd (%rdi), %xmm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpbroadcastd (%rdi), %xmm1 # sched: [6:0.50]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pbroadcastd:<br>
; SKX: # BB#0:<br>
@@ -1643,9 +1643,9 @@ define <8 x i32> @test_pbroadcastd_ymm(<<br>
; SKYLAKE-LABEL: test_pbroadcastd_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpbroadcastd %xmm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpbroadcastd (%rdi), %ymm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpbroadcastd (%rdi), %ymm1 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pbroadcastd_ymm:<br>
; SKX: # BB#0:<br>
@@ -1684,9 +1684,9 @@ define <2 x i64> @test_pbroadcastq(<2 x<br>
; SKYLAKE-LABEL: test_pbroadcastq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpbroadcastq %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpbroadcastq (%rdi), %xmm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpbroadcastq (%rdi), %xmm1 # sched: [6:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pbroadcastq:<br>
; SKX: # BB#0:<br>
@@ -1725,9 +1725,9 @@ define <4 x i64> @test_pbroadcastq_ymm(<<br>
; SKYLAKE-LABEL: test_pbroadcastq_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpbroadcastq %xmm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpbroadcastq (%rdi), %ymm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpbroadcastq (%rdi), %ymm1 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pbroadcastq_ymm:<br>
; SKX: # BB#0:<br>
@@ -1766,9 +1766,9 @@ define <8 x i16> @test_pbroadcastw(<8 x<br>
; SKYLAKE-LABEL: test_pbroadcastw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpbroadcastw %xmm0, %xmm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpbroadcastw (%rdi), %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpbroadcastw (%rdi), %xmm1 # sched: [7:1.00]<br>
+; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pbroadcastw:<br>
; SKX: # BB#0:<br>
@@ -1808,9 +1808,9 @@ define <16 x i16> @test_pbroadcastw_ymm(<br>
; SKYLAKE-LABEL: test_pbroadcastw_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpbroadcastw %xmm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpbroadcastw (%rdi), %ymm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpbroadcastw (%rdi), %ymm1 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pbroadcastw_ymm:<br>
; SKX: # BB#0:<br>
@@ -1847,9 +1847,9 @@ define <32 x i8> @test_pcmpeqb(<32 x i8><br>
;<br>
; SKYLAKE-LABEL: test_pcmpeqb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpeqb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpeqb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpeqb:<br>
; SKX: # BB#0:<br>
@@ -1887,9 +1887,9 @@ define <8 x i32> @test_pcmpeqd(<8 x i32><br>
;<br>
; SKYLAKE-LABEL: test_pcmpeqd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpeqd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpeqd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpeqd:<br>
; SKX: # BB#0:<br>
@@ -1927,9 +1927,9 @@ define <4 x i64> @test_pcmpeqq(<4 x i64><br>
;<br>
; SKYLAKE-LABEL: test_pcmpeqq:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpeqq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpeqq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpeqq:<br>
; SKX: # BB#0:<br>
@@ -1967,9 +1967,9 @@ define <16 x i16> @test_pcmpeqw(<16 x i1<br>
;<br>
; SKYLAKE-LABEL: test_pcmpeqw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpeqw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpeqw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpeqw:<br>
; SKX: # BB#0:<br>
@@ -2007,9 +2007,9 @@ define <32 x i8> @test_pcmpgtb(<32 x i8><br>
;<br>
; SKYLAKE-LABEL: test_pcmpgtb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpgtb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpgtb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpgtb:<br>
; SKX: # BB#0:<br>
@@ -2047,9 +2047,9 @@ define <8 x i32> @test_pcmpgtd(<8 x i32><br>
;<br>
; SKYLAKE-LABEL: test_pcmpgtd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpgtd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpgtd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpgtd:<br>
; SKX: # BB#0:<br>
@@ -2088,8 +2088,8 @@ define <4 x i64> @test_pcmpgtq(<4 x i64><br>
; SKYLAKE-LABEL: test_pcmpgtq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpcmpgtq (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpgtq (%rdi), %ymm0, %ymm0 # sched: [10:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpgtq:<br>
; SKX: # BB#0:<br>
@@ -2127,9 +2127,9 @@ define <16 x i16> @test_pcmpgtw(<16 x i1<br>
;<br>
; SKYLAKE-LABEL: test_pcmpgtw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpgtw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpgtw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpgtw:<br>
; SKX: # BB#0:<br>
@@ -2170,9 +2170,9 @@ define <4 x i64> @test_perm2i128(<4 x i6<br>
; SKYLAKE-LABEL: test_perm2i128:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[0,1] sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [10:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_perm2i128:<br>
; SKX: # BB#0:<br>
@@ -2212,9 +2212,9 @@ define <8 x i32> @test_permd(<8 x i32> %<br>
; SKYLAKE-LABEL: test_permd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpermd %ymm1, %ymm0, %ymm1 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpermd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpermd (%rdi), %ymm0, %ymm0 # sched: [10:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_permd:<br>
; SKX: # BB#0:<br>
@@ -2255,9 +2255,9 @@ define <4 x double> @test_permpd(<4 x do<br>
; SKYLAKE-LABEL: test_permpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,2,2,3] sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpermpd {{.*#+}} ymm1 = mem[0,2,2,3] sched: [3:1.00]<br>
+; SKYLAKE-NEXT: vpermpd {{.*#+}} ymm1 = mem[0,2,2,3] sched: [10:1.00]<br>
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_permpd:<br>
; SKX: # BB#0:<br>
@@ -2297,9 +2297,9 @@ define <8 x float> @test_permps(<8 x i32<br>
; SKYLAKE-LABEL: test_permps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpermps %ymm1, %ymm0, %ymm1 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpermps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: vpermps (%rdi), %ymm0, %ymm0 # sched: [10:1.00]<br>
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_permps:<br>
; SKX: # BB#0:<br>
@@ -2340,9 +2340,9 @@ define <4 x i64> @test_permq(<4 x i64> %<br>
; SKYLAKE-LABEL: test_permq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,2,3] sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpermq {{.*#+}} ymm1 = mem[0,2,2,3] sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpermq {{.*#+}} ymm1 = mem[0,2,2,3] sched: [10:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_permq:<br>
; SKX: # BB#0:<br>
@@ -2377,8 +2377,8 @@ define <4 x i32> @test_pgatherdd(<4 x i3<br>
;<br>
; SKYLAKE-LABEL: test_pgatherdd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pgatherdd:<br>
; SKX: # BB#0:<br>
@@ -2407,8 +2407,8 @@ define <8 x i32> @test_pgatherdd_ymm(<8<br>
;<br>
; SKYLAKE-LABEL: test_pgatherdd_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [20:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [25:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pgatherdd_ymm:<br>
; SKX: # BB#0:<br>
@@ -2437,8 +2437,8 @@ define <2 x i64> @test_pgatherdq(<2 x i6<br>
;<br>
; SKYLAKE-LABEL: test_pgatherdq:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pgatherdq:<br>
; SKX: # BB#0:<br>
@@ -2467,8 +2467,8 @@ define <4 x i64> @test_pgatherdq_ymm(<4<br>
;<br>
; SKYLAKE-LABEL: test_pgatherdq_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0 # sched: [20:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0 # sched: [25:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pgatherdq_ymm:<br>
; SKX: # BB#0:<br>
@@ -2497,8 +2497,8 @@ define <4 x i32> @test_pgatherqd(<4 x i3<br>
;<br>
; SKYLAKE-LABEL: test_pgatherqd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pgatherqd:<br>
; SKX: # BB#0:<br>
@@ -2529,9 +2529,9 @@ define <4 x i32> @test_pgatherqd_ymm(<4<br>
;<br>
; SKYLAKE-LABEL: test_pgatherqd_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0 # sched: [20:1.00]<br>
+; SKYLAKE-NEXT: vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0 # sched: [25:1.00]<br>
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pgatherqd_ymm:<br>
; SKX: # BB#0:<br>
@@ -2562,8 +2562,8 @@ define <2 x i64> @test_pgatherqq(<2 x i6<br>
;<br>
; SKYLAKE-LABEL: test_pgatherqq:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pgatherqq:<br>
; SKX: # BB#0:<br>
@@ -2592,8 +2592,8 @@ define <4 x i64> @test_pgatherqq_ymm(<4<br>
;<br>
; SKYLAKE-LABEL: test_pgatherqq_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [20:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [25:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pgatherqq_ymm:<br>
; SKX: # BB#0:<br>
@@ -2625,8 +2625,8 @@ define <8 x i32> @test_phaddd(<8 x i32><br>
; SKYLAKE-LABEL: test_phaddd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vphaddd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: vphaddd (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vphaddd (%rdi), %ymm0, %ymm0 # sched: [10:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_phaddd:<br>
; SKX: # BB#0:<br>
@@ -2662,8 +2662,8 @@ define <16 x i16> @test_phaddsw(<16 x i1<br>
; SKYLAKE-LABEL: test_phaddsw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vphaddsw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: vphaddsw (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vphaddsw (%rdi), %ymm0, %ymm0 # sched: [10:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_phaddsw:<br>
; SKX: # BB#0:<br>
@@ -2699,8 +2699,8 @@ define <16 x i16> @test_phaddw(<16 x i16<br>
; SKYLAKE-LABEL: test_phaddw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vphaddw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: vphaddw (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vphaddw (%rdi), %ymm0, %ymm0 # sched: [10:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_phaddw:<br>
; SKX: # BB#0:<br>
@@ -2736,8 +2736,8 @@ define <8 x i32> @test_phsubd(<8 x i32><br>
; SKYLAKE-LABEL: test_phsubd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vphsubd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: vphsubd (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vphsubd (%rdi), %ymm0, %ymm0 # sched: [10:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_phsubd:<br>
; SKX: # BB#0:<br>
@@ -2773,8 +2773,8 @@ define <16 x i16> @test_phsubsw(<16 x i1<br>
; SKYLAKE-LABEL: test_phsubsw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vphsubsw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: vphsubsw (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vphsubsw (%rdi), %ymm0, %ymm0 # sched: [10:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_phsubsw:<br>
; SKX: # BB#0:<br>
@@ -2810,8 +2810,8 @@ define <16 x i16> @test_phsubw(<16 x i16<br>
; SKYLAKE-LABEL: test_phsubw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vphsubw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: vphsubw (%rdi), %ymm0, %ymm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vphsubw (%rdi), %ymm0, %ymm0 # sched: [10:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_phsubw:<br>
; SKX: # BB#0:<br>
@@ -2847,8 +2847,8 @@ define <16 x i16> @test_pmaddubsw(<32 x<br>
; SKYLAKE-LABEL: test_pmaddubsw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmaddubsw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaddubsw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaddubsw:<br>
; SKX: # BB#0:<br>
@@ -2885,8 +2885,8 @@ define <8 x i32> @test_pmaddwd(<16 x i16<br>
; SKYLAKE-LABEL: test_pmaddwd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmaddwd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaddwd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaddwd:<br>
; SKX: # BB#0:<br>
@@ -2924,10 +2924,10 @@ define <4 x i32> @test_pmaskmovd(i8* %a0<br>
;<br>
; SKYLAKE-LABEL: test_pmaskmovd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [2:1.00]<br>
; SKYLAKE-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaskmovd:<br>
; SKX: # BB#0:<br>
@@ -2966,10 +2966,10 @@ define <8 x i32> @test_pmaskmovd_ymm(i8*<br>
;<br>
; SKYLAKE-LABEL: test_pmaskmovd_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [2:1.00]<br>
; SKYLAKE-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaskmovd_ymm:<br>
; SKX: # BB#0:<br>
@@ -3008,10 +3008,10 @@ define <2 x i64> @test_pmaskmovq(i8* %a0<br>
;<br>
; SKYLAKE-LABEL: test_pmaskmovq:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [2:1.00]<br>
; SKYLAKE-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaskmovq:<br>
; SKX: # BB#0:<br>
@@ -3050,10 +3050,10 @@ define <4 x i64> @test_pmaskmovq_ymm(i8*<br>
;<br>
; SKYLAKE-LABEL: test_pmaskmovq_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [2:1.00]<br>
; SKYLAKE-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaskmovq_ymm:<br>
; SKX: # BB#0:<br>
@@ -3090,9 +3090,9 @@ define <32 x i8> @test_pmaxsb(<32 x i8><br>
;<br>
; SKYLAKE-LABEL: test_pmaxsb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmaxsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpmaxsb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaxsb:<br>
; SKX: # BB#0:<br>
@@ -3127,9 +3127,9 @@ define <8 x i32> @test_pmaxsd(<8 x i32><br>
;<br>
; SKYLAKE-LABEL: test_pmaxsd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmaxsd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpmaxsd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaxsd:<br>
; SKX: # BB#0:<br>
@@ -3164,9 +3164,9 @@ define <16 x i16> @test_pmaxsw(<16 x i16<br>
;<br>
; SKYLAKE-LABEL: test_pmaxsw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmaxsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpmaxsw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaxsw:<br>
; SKX: # BB#0:<br>
@@ -3201,9 +3201,9 @@ define <32 x i8> @test_pmaxub(<32 x i8><br>
;<br>
; SKYLAKE-LABEL: test_pmaxub:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmaxub (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpmaxub (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaxub:<br>
; SKX: # BB#0:<br>
@@ -3238,9 +3238,9 @@ define <8 x i32> @test_pmaxud(<8 x i32><br>
;<br>
; SKYLAKE-LABEL: test_pmaxud:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmaxud (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpmaxud (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaxud:<br>
; SKX: # BB#0:<br>
@@ -3275,9 +3275,9 @@ define <16 x i16> @test_pmaxuw(<16 x i16<br>
;<br>
; SKYLAKE-LABEL: test_pmaxuw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmaxuw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpmaxuw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaxuw:<br>
; SKX: # BB#0:<br>
@@ -3312,9 +3312,9 @@ define <32 x i8> @test_pminsb(<32 x i8><br>
;<br>
; SKYLAKE-LABEL: test_pminsb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpminsb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpminsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpminsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpminsb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pminsb:<br>
; SKX: # BB#0:<br>
@@ -3349,9 +3349,9 @@ define <8 x i32> @test_pminsd(<8 x i32><br>
;<br>
; SKYLAKE-LABEL: test_pminsd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpminsd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpminsd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpminsd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpminsd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pminsd:<br>
; SKX: # BB#0:<br>
@@ -3386,9 +3386,9 @@ define <16 x i16> @test_pminsw(<16 x i16<br>
;<br>
; SKYLAKE-LABEL: test_pminsw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpminsw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpminsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpminsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpminsw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pminsw:<br>
; SKX: # BB#0:<br>
@@ -3423,9 +3423,9 @@ define <32 x i8> @test_pminub(<32 x i8><br>
;<br>
; SKYLAKE-LABEL: test_pminub:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpminub %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpminub (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpminub %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpminub (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pminub:<br>
; SKX: # BB#0:<br>
@@ -3460,9 +3460,9 @@ define <8 x i32> @test_pminud(<8 x i32><br>
;<br>
; SKYLAKE-LABEL: test_pminud:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpminud %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpminud (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpminud %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpminud (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pminud:<br>
; SKX: # BB#0:<br>
@@ -3497,9 +3497,9 @@ define <16 x i16> @test_pminuw(<16 x i16<br>
;<br>
; SKYLAKE-LABEL: test_pminuw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpminuw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpminuw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpminuw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpminuw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pminuw:<br>
; SKX: # BB#0:<br>
@@ -3536,7 +3536,7 @@ define i32 @test_pmovmskb(<32 x i8> %a0)<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovmskb %ymm0, %eax # sched: [2:1.00]<br>
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovmskb:<br>
; SKX: # BB#0:<br>
@@ -3572,9 +3572,9 @@ define <8 x i32> @test_pmovsxbd(<16 x i8<br>
; SKYLAKE-LABEL: test_pmovsxbd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovsxbd %xmm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpmovsxbd (%rdi), %ymm1 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovsxbd (%rdi), %ymm1 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovsxbd:<br>
; SKX: # BB#0:<br>
@@ -3616,9 +3616,9 @@ define <4 x i64> @test_pmovsxbq(<16 x i8<br>
; SKYLAKE-LABEL: test_pmovsxbq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovsxbq %xmm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpmovsxbq (%rdi), %ymm1 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovsxbq (%rdi), %ymm1 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovsxbq:<br>
; SKX: # BB#0:<br>
@@ -3660,9 +3660,9 @@ define <16 x i16> @test_pmovsxbw(<16 x i<br>
; SKYLAKE-LABEL: test_pmovsxbw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovsxbw %xmm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpmovsxbw (%rdi), %ymm1 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovsxbw (%rdi), %ymm1 # sched: [9:1.00]<br>
+; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovsxbw:<br>
; SKX: # BB#0:<br>
@@ -3702,9 +3702,9 @@ define <4 x i64> @test_pmovsxdq(<4 x i32<br>
; SKYLAKE-LABEL: test_pmovsxdq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovsxdq %xmm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpmovsxdq (%rdi), %ymm1 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovsxdq (%rdi), %ymm1 # sched: [9:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovsxdq:<br>
; SKX: # BB#0:<br>
@@ -3744,9 +3744,9 @@ define <8 x i32> @test_pmovsxwd(<8 x i16<br>
; SKYLAKE-LABEL: test_pmovsxwd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovsxwd %xmm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpmovsxwd (%rdi), %ymm1 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovsxwd (%rdi), %ymm1 # sched: [9:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovsxwd:<br>
; SKX: # BB#0:<br>
@@ -3786,9 +3786,9 @@ define <4 x i64> @test_pmovsxwq(<8 x i16<br>
; SKYLAKE-LABEL: test_pmovsxwq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovsxwq %xmm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpmovsxwq (%rdi), %ymm1 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovsxwq (%rdi), %ymm1 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovsxwq:<br>
; SKX: # BB#0:<br>
@@ -3830,9 +3830,9 @@ define <8 x i32> @test_pmovzxbd(<16 x i8<br>
; SKYLAKE-LABEL: test_pmovzxbd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1]<wbr>,zero,zero,zero,xmm0[2],zero,<wbr>zero,zero,xmm0[3],zero,zero,<wbr>zero,xmm0[4],zero,zero,zero,<wbr>xmm0[5],zero,zero,zero,xmm0[6]<wbr>,zero,zero,zero,xmm0[7],zero,<wbr>zero,zero sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],<wbr>zero,zero,zero,mem[2],zero,<wbr>zero,zero,mem[3],zero,zero,<wbr>zero,mem[4],zero,zero,zero,<wbr>mem[5],zero,zero,zero,mem[6],<wbr>zero,zero,zero,mem[7],zero,<wbr>zero,zero sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],<wbr>zero,zero,zero,mem[2],zero,<wbr>zero,zero,mem[3],zero,zero,<wbr>zero,mem[4],zero,zero,zero,<wbr>mem[5],zero,zero,zero,mem[6],<wbr>zero,zero,zero,mem[7],zero,<wbr>zero,zero sched: [10:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovzxbd:<br>
; SKX: # BB#0:<br>
@@ -3874,9 +3874,9 @@ define <4 x i64> @test_pmovzxbq(<16 x i8<br>
; SKYLAKE-LABEL: test_pmovzxbq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,<wbr>zero,zero,zero,xmm0[1],zero,<wbr>zero,zero,zero,zero,zero,zero,<wbr>xmm0[2],zero,zero,zero,zero,<wbr>zero,zero,zero,xmm0[3],zero,<wbr>zero,zero,zero,zero,zero,zero sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpmovzxbq {{.*#+}} ymm1 = mem[0],zero,zero,zero,zero,<wbr>zero,zero,zero,mem[1],zero,<wbr>zero,zero,zero,zero,zero,zero,<wbr>mem[2],zero,zero,zero,zero,<wbr>zero,zero,zero,mem[3],zero,<wbr>zero,zero,zero,zero,zero,zero sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovzxbq {{.*#+}} ymm1 = mem[0],zero,zero,zero,zero,<wbr>zero,zero,zero,mem[1],zero,<wbr>zero,zero,zero,zero,zero,zero,<wbr>mem[2],zero,zero,zero,zero,<wbr>zero,zero,zero,mem[3],zero,<wbr>zero,zero,zero,zero,zero,zero sched: [10:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovzxbq:<br>
; SKX: # BB#0:<br>
@@ -3918,9 +3918,9 @@ define <16 x i16> @test_pmovzxbw(<16 x i<br>
; SKYLAKE-LABEL: test_pmovzxbw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,<wbr>xmm0[2],zero,xmm0[3],zero,<wbr>xmm0[4],zero,xmm0[5],zero,<wbr>xmm0[6],zero,xmm0[7],zero,<wbr>xmm0[8],zero,xmm0[9],zero,<wbr>xmm0[10],zero,xmm0[11],zero,<wbr>xmm0[12],zero,xmm0[13],zero,<wbr>xmm0[14],zero,xmm0[15],zero sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpmovzxbw {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2]<wbr>,zero,mem[3],zero,mem[4],zero,<wbr>mem[5],zero,mem[6],zero,mem[7]<wbr>,zero,mem[8],zero,mem[9],zero,<wbr>mem[10],zero,mem[11],zero,mem[<wbr>12],zero,mem[13],zero,mem[14],<wbr>zero,mem[15],zero sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovzxbw {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2]<wbr>,zero,mem[3],zero,mem[4],zero,<wbr>mem[5],zero,mem[6],zero,mem[7]<wbr>,zero,mem[8],zero,mem[9],zero,<wbr>mem[10],zero,mem[11],zero,mem[<wbr>12],zero,mem[13],zero,mem[14],<wbr>zero,mem[15],zero sched: [10:1.00]<br>
+; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovzxbw:<br>
; SKX: # BB#0:<br>
@@ -3960,9 +3960,9 @@ define <4 x i64> @test_pmovzxdq(<4 x i32<br>
; SKYLAKE-LABEL: test_pmovzxdq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,<wbr>xmm0[2],zero,xmm0[3],zero sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpmovzxdq {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2]<wbr>,zero,mem[3],zero sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovzxdq {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2]<wbr>,zero,mem[3],zero sched: [10:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovzxdq:<br>
; SKX: # BB#0:<br>
@@ -4002,9 +4002,9 @@ define <8 x i32> @test_pmovzxwd(<8 x i16<br>
; SKYLAKE-LABEL: test_pmovzxwd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,<wbr>xmm0[2],zero,xmm0[3],zero,<wbr>xmm0[4],zero,xmm0[5],zero,<wbr>xmm0[6],zero,xmm0[7],zero sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2]<wbr>,zero,mem[3],zero,mem[4],zero,<wbr>mem[5],zero,mem[6],zero,mem[7]<wbr>,zero sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2]<wbr>,zero,mem[3],zero,mem[4],zero,<wbr>mem[5],zero,mem[6],zero,mem[7]<wbr>,zero sched: [9:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovzxwd:<br>
; SKX: # BB#0:<br>
@@ -4044,9 +4044,9 @@ define <4 x i64> @test_pmovzxwq(<8 x i16<br>
; SKYLAKE-LABEL: test_pmovzxwq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1]<wbr>,zero,zero,zero,xmm0[2],zero,<wbr>zero,zero,xmm0[3],zero,zero,<wbr>zero sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpmovzxwq {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],<wbr>zero,zero,zero,mem[2],zero,<wbr>zero,zero,mem[3],zero,zero,<wbr>zero sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovzxwq {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],<wbr>zero,zero,zero,mem[2],zero,<wbr>zero,zero,mem[3],zero,zero,<wbr>zero sched: [10:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovzxwq:<br>
; SKX: # BB#0:<br>
@@ -4086,8 +4086,8 @@ define <4 x i64> @test_pmuldq(<8 x i32><br>
; SKYLAKE-LABEL: test_pmuldq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmuldq %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmuldq (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmuldq (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmuldq:<br>
; SKX: # BB#0:<br>
@@ -4124,8 +4124,8 @@ define <16 x i16> @test_pmulhrsw(<16 x i<br>
; SKYLAKE-LABEL: test_pmulhrsw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmulhrsw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmulhrsw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmulhrsw:<br>
; SKX: # BB#0:<br>
@@ -4161,8 +4161,8 @@ define <16 x i16> @test_pmulhuw(<16 x i1<br>
; SKYLAKE-LABEL: test_pmulhuw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmulhuw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmulhuw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmulhuw:<br>
; SKX: # BB#0:<br>
@@ -4198,8 +4198,8 @@ define <16 x i16> @test_pmulhw(<16 x i16<br>
; SKYLAKE-LABEL: test_pmulhw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmulhw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmulhw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmulhw:<br>
; SKX: # BB#0:<br>
@@ -4235,8 +4235,8 @@ define <8 x i32> @test_pmulld(<8 x i32><br>
; SKYLAKE-LABEL: test_pmulld:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmulld %ymm1, %ymm0, %ymm0 # sched: [8:0.67]<br>
-; SKYLAKE-NEXT: vpmulld (%rdi), %ymm0, %ymm0 # sched: [8:0.67]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmulld (%rdi), %ymm0, %ymm0 # sched: [15:0.67]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmulld:<br>
; SKX: # BB#0:<br>
@@ -4271,8 +4271,8 @@ define <16 x i16> @test_pmullw(<16 x i16<br>
; SKYLAKE-LABEL: test_pmullw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmullw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmullw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmullw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmullw:<br>
; SKX: # BB#0:<br>
@@ -4307,8 +4307,8 @@ define <4 x i64> @test_pmuludq(<8 x i32><br>
; SKYLAKE-LABEL: test_pmuludq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmuludq (%rdi), %ymm0, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmuludq (%rdi), %ymm0, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmuludq:<br>
; SKX: # BB#0:<br>
@@ -4346,10 +4346,10 @@ define <4 x i64> @test_por(<4 x i64> %a0<br>
;<br>
; SKYLAKE-LABEL: test_por:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpor (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_por:<br>
; SKX: # BB#0:<br>
@@ -4387,8 +4387,8 @@ define <4 x i64> @test_psadbw(<32 x i8><br>
; SKYLAKE-LABEL: test_psadbw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpsadbw (%rdi), %ymm0, %ymm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsadbw (%rdi), %ymm0, %ymm0 # sched: [10:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psadbw:<br>
; SKX: # BB#0:<br>
@@ -4425,8 +4425,8 @@ define <32 x i8> @test_pshufb(<32 x i8><br>
; SKYLAKE-LABEL: test_pshufb:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpshufb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpshufb (%rdi), %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpshufb (%rdi), %ymm0, %ymm0 # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pshufb:<br>
; SKX: # BB#0:<br>
@@ -4464,9 +4464,9 @@ define <8 x i32> @test_pshufd(<8 x i32><br>
; SKYLAKE-LABEL: test_pshufd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpshufd {{.*#+}} ymm1 = mem[1,0,3,2,5,4,7,6] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpshufd {{.*#+}} ymm1 = mem[1,0,3,2,5,4,7,6] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pshufd:<br>
; SKX: # BB#0:<br>
@@ -4506,9 +4506,9 @@ define <16 x i16> @test_pshufhw(<16 x i1<br>
; SKYLAKE-LABEL: test_pshufhw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,5,4,8,9,10,<wbr>11,15,14,13,12] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpshufhw {{.*#+}} ymm1 = mem[0,1,2,3,5,4,7,6,8,9,10,11,<wbr>13,12,15,14] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpshufhw {{.*#+}} ymm1 = mem[0,1,2,3,5,4,7,6,8,9,10,11,<wbr>13,12,15,14] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pshufhw:<br>
; SKX: # BB#0:<br>
@@ -4548,9 +4548,9 @@ define <16 x i16> @test_pshuflw(<16 x i1<br>
; SKYLAKE-LABEL: test_pshuflw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[3,2,1,0,4,5,6,7,11,10,9,<wbr>8,12,13,14,15] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpshuflw {{.*#+}} ymm1 = mem[1,0,3,2,4,5,6,7,9,8,11,10,<wbr>12,13,14,15] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpshuflw {{.*#+}} ymm1 = mem[1,0,3,2,4,5,6,7,9,8,11,10,<wbr>12,13,14,15] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pshuflw:<br>
; SKX: # BB#0:<br>
@@ -4587,9 +4587,9 @@ define <32 x i8> @test_psignb(<32 x i8><br>
;<br>
; SKYLAKE-LABEL: test_psignb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsignb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsignb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsignb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsignb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psignb:<br>
; SKX: # BB#0:<br>
@@ -4624,9 +4624,9 @@ define <8 x i32> @test_psignd(<8 x i32><br>
;<br>
; SKYLAKE-LABEL: test_psignd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsignd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsignd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsignd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsignd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psignd:<br>
; SKX: # BB#0:<br>
@@ -4661,9 +4661,9 @@ define <16 x i16> @test_psignw(<16 x i16<br>
;<br>
; SKYLAKE-LABEL: test_psignw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsignw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsignw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsignw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsignw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psignw:<br>
; SKX: # BB#0:<br>
@@ -4701,9 +4701,9 @@ define <8 x i32> @test_pslld(<8 x i32> %<br>
; SKYLAKE-LABEL: test_pslld:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpslld %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vpslld (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpslld $2, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpslld (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpslld $2, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pslld:<br>
; SKX: # BB#0:<br>
@@ -4740,7 +4740,7 @@ define <32 x i8> @test_pslldq(<32 x i8><br>
; SKYLAKE-LABEL: test_pslldq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,<wbr>5,6,7,8,9,10,11,12],zero,zero,<wbr>zero,ymm0[16,17,18,19,20,21,<wbr>22,23,24,25,26,27,28] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pslldq:<br>
; SKX: # BB#0:<br>
@@ -4773,9 +4773,9 @@ define <4 x i64> @test_psllq(<4 x i64> %<br>
; SKYLAKE-LABEL: test_psllq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsllq %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vpsllq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsllq $2, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsllq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpsllq $2, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psllq:<br>
; SKX: # BB#0:<br>
@@ -4813,9 +4813,9 @@ define <4 x i32> @test_psllvd(<4 x i32><br>
;<br>
; SKYLAKE-LABEL: test_psllvd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsllvd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsllvd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psllvd:<br>
; SKX: # BB#0:<br>
@@ -4850,9 +4850,9 @@ define <8 x i32> @test_psllvd_ymm(<8 x i<br>
;<br>
; SKYLAKE-LABEL: test_psllvd_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsllvd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsllvd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psllvd_ymm:<br>
; SKX: # BB#0:<br>
@@ -4887,9 +4887,9 @@ define <2 x i64> @test_psllvq(<2 x i64><br>
;<br>
; SKYLAKE-LABEL: test_psllvq:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsllvq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsllvq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psllvq:<br>
; SKX: # BB#0:<br>
@@ -4924,9 +4924,9 @@ define <4 x i64> @test_psllvq_ymm(<4 x i<br>
;<br>
; SKYLAKE-LABEL: test_psllvq_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsllvq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsllvq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psllvq_ymm:<br>
; SKX: # BB#0:<br>
@@ -4964,9 +4964,9 @@ define <16 x i16> @test_psllw(<16 x i16><br>
; SKYLAKE-LABEL: test_psllw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsllw %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vpsllw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsllw $2, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsllw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpsllw $2, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psllw:<br>
; SKX: # BB#0:<br>
@@ -5007,9 +5007,9 @@ define <8 x i32> @test_psrad(<8 x i32> %<br>
; SKYLAKE-LABEL: test_psrad:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsrad %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vpsrad (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsrad $2, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsrad (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpsrad $2, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrad:<br>
; SKX: # BB#0:<br>
@@ -5047,9 +5047,9 @@ define <4 x i32> @test_psravd(<4 x i32><br>
;<br>
; SKYLAKE-LABEL: test_psravd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsravd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsravd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsravd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsravd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psravd:<br>
; SKX: # BB#0:<br>
@@ -5084,9 +5084,9 @@ define <8 x i32> @test_psravd_ymm(<8 x i<br>
;<br>
; SKYLAKE-LABEL: test_psravd_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsravd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsravd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsravd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsravd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psravd_ymm:<br>
; SKX: # BB#0:<br>
@@ -5124,9 +5124,9 @@ define <16 x i16> @test_psraw(<16 x i16><br>
; SKYLAKE-LABEL: test_psraw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsraw %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vpsraw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsraw $2, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsraw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpsraw $2, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psraw:<br>
; SKX: # BB#0:<br>
@@ -5167,9 +5167,9 @@ define <8 x i32> @test_psrld(<8 x i32> %<br>
; SKYLAKE-LABEL: test_psrld:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsrld %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vpsrld (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsrld $2, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsrld (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpsrld $2, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrld:<br>
; SKX: # BB#0:<br>
@@ -5206,7 +5206,7 @@ define <32 x i8> @test_psrldq(<32 x i8><br>
; SKYLAKE-LABEL: test_psrldq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,<wbr>13,14,15],zero,zero,zero,ymm0[<wbr>19,20,21,22,23,24,25,26,27,28,<wbr>29,30,31],zero,zero,zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrldq:<br>
; SKX: # BB#0:<br>
@@ -5239,9 +5239,9 @@ define <4 x i64> @test_psrlq(<4 x i64> %<br>
; SKYLAKE-LABEL: test_psrlq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vpsrlq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsrlq $2, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsrlq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpsrlq $2, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrlq:<br>
; SKX: # BB#0:<br>
@@ -5279,9 +5279,9 @@ define <4 x i32> @test_psrlvd(<4 x i32><br>
;<br>
; SKYLAKE-LABEL: test_psrlvd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsrlvd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsrlvd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrlvd:<br>
; SKX: # BB#0:<br>
@@ -5316,9 +5316,9 @@ define <8 x i32> @test_psrlvd_ymm(<8 x i<br>
;<br>
; SKYLAKE-LABEL: test_psrlvd_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsrlvd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsrlvd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrlvd_ymm:<br>
; SKX: # BB#0:<br>
@@ -5353,9 +5353,9 @@ define <2 x i64> @test_psrlvq(<2 x i64><br>
;<br>
; SKYLAKE-LABEL: test_psrlvq:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsrlvq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsrlvq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrlvq:<br>
; SKX: # BB#0:<br>
@@ -5390,9 +5390,9 @@ define <4 x i64> @test_psrlvq_ymm(<4 x i<br>
;<br>
; SKYLAKE-LABEL: test_psrlvq_ymm:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsrlvq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsrlvq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrlvq_ymm:<br>
; SKX: # BB#0:<br>
@@ -5430,9 +5430,9 @@ define <16 x i16> @test_psrlw(<16 x i16><br>
; SKYLAKE-LABEL: test_psrlw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vpsrlw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsrlw $2, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsrlw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpsrlw $2, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrlw:<br>
; SKX: # BB#0:<br>
@@ -5470,9 +5470,9 @@ define <32 x i8> @test_psubb(<32 x i8> %<br>
;<br>
; SKYLAKE-LABEL: test_psubb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsubb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubb %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpsubb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubb:<br>
; SKX: # BB#0:<br>
@@ -5506,9 +5506,9 @@ define <8 x i32> @test_psubd(<8 x i32> %<br>
;<br>
; SKYLAKE-LABEL: test_psubd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsubd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpsubd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubd:<br>
; SKX: # BB#0:<br>
@@ -5542,9 +5542,9 @@ define <4 x i64> @test_psubq(<4 x i64> %<br>
;<br>
; SKYLAKE-LABEL: test_psubq:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsubq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpsubq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubq:<br>
; SKX: # BB#0:<br>
@@ -5578,9 +5578,9 @@ define <32 x i8> @test_psubsb(<32 x i8><br>
;<br>
; SKYLAKE-LABEL: test_psubsb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsubsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsubsb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubsb:<br>
; SKX: # BB#0:<br>
@@ -5615,9 +5615,9 @@ define <16 x i16> @test_psubsw(<16 x i16<br>
;<br>
; SKYLAKE-LABEL: test_psubsw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsubsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsubsw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubsw:<br>
; SKX: # BB#0:<br>
@@ -5652,9 +5652,9 @@ define <32 x i8> @test_psubusb(<32 x i8><br>
;<br>
; SKYLAKE-LABEL: test_psubusb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsubusb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsubusb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubusb:<br>
; SKX: # BB#0:<br>
@@ -5689,9 +5689,9 @@ define <16 x i16> @test_psubusw(<16 x i1<br>
;<br>
; SKYLAKE-LABEL: test_psubusw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsubusw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsubusw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubusw:<br>
; SKX: # BB#0:<br>
@@ -5726,9 +5726,9 @@ define <16 x i16> @test_psubw(<16 x i16><br>
;<br>
; SKYLAKE-LABEL: test_psubw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsubw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubw %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpsubw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubw:<br>
; SKX: # BB#0:<br>
@@ -5763,8 +5763,8 @@ define <32 x i8> @test_punpckhbw(<32 x i<br>
; SKYLAKE-LABEL: test_punpckhbw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm0[8],ymm1[8],ymm0[9],ymm1[<wbr>9],ymm0[10],ymm1[10],ymm0[11],<wbr>ymm1[11],ymm0[12],ymm1[12],<wbr>ymm0[13],ymm1[13],ymm0[14],<wbr>ymm1[14],ymm0[15],ymm1[15],<wbr>ymm0[24],ymm1[24],ymm0[25],<wbr>ymm1[25],ymm0[26],ymm1[26],<wbr>ymm0[27],ymm1[27],ymm0[28],<wbr>ymm1[28],ymm0[29],ymm1[29],<wbr>ymm0[30],ymm1[30],ymm0[31],<wbr>ymm1[31] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm0[8],mem[8],ymm0[9],mem[9],<wbr>ymm0[10],mem[10],ymm0[11],mem[<wbr>11],ymm0[12],mem[12],ymm0[13],<wbr>mem[13],ymm0[14],mem[14],ymm0[<wbr>15],mem[15],ymm0[24],mem[24],<wbr>ymm0[25],mem[25],ymm0[26],mem[<wbr>26],ymm0[27],mem[27],ymm0[28],<wbr>mem[28],ymm0[29],mem[29],ymm0[<wbr>30],mem[30],ymm0[31],mem[31] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm0[8],mem[8],ymm0[9],mem[9],<wbr>ymm0[10],mem[10],ymm0[11],mem[<wbr>11],ymm0[12],mem[12],ymm0[13],<wbr>mem[13],ymm0[14],mem[14],ymm0[<wbr>15],mem[15],ymm0[24],mem[24],<wbr>ymm0[25],mem[25],ymm0[26],mem[<wbr>26],ymm0[27],mem[27],ymm0[28],<wbr>mem[28],ymm0[29],mem[29],ymm0[<wbr>30],mem[30],ymm0[31],mem[31] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpckhbw:<br>
; SKX: # BB#0:<br>
@@ -5803,10 +5803,10 @@ define <8 x i32> @test_punpckhdq(<8 x i3<br>
; SKYLAKE-LABEL: test_punpckhdq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpckhdq {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[<wbr>3],ymm0[6],ymm1[6],ymm0[7],<wbr>ymm1[7] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpckhdq {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],<wbr>ymm0[6],mem[6],ymm0[7],mem[7] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpckhdq {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],<wbr>ymm0[6],mem[6],ymm0[7],mem[7] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpckhdq:<br>
; SKX: # BB#0:<br>
@@ -5848,9 +5848,9 @@ define <4 x i64> @test_punpckhqdq(<4 x i<br>
; SKYLAKE-LABEL: test_punpckhqdq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm0[1],ymm1[1],ymm0[3],ymm1[<wbr>3] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpckhqdq:<br>
; SKX: # BB#0:<br>
@@ -5888,8 +5888,8 @@ define <16 x i16> @test_punpckhwd(<16 x<br>
; SKYLAKE-LABEL: test_punpckhwd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm1[4],ymm0[5],ymm1[<wbr>5],ymm0[6],ymm1[6],ymm0[7],<wbr>ymm1[7],ymm0[12],ymm1[12],<wbr>ymm0[13],ymm1[13],ymm0[14],<wbr>ymm1[14],ymm0[15],ymm1[15] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],mem[4],ymm0[5],mem[5],<wbr>ymm0[6],mem[6],ymm0[7],mem[7],<wbr>ymm0[12],mem[12],ymm0[13],mem[<wbr>13],ymm0[14],mem[14],ymm0[15],<wbr>mem[15] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],mem[4],ymm0[5],mem[5],<wbr>ymm0[6],mem[6],ymm0[7],mem[7],<wbr>ymm0[12],mem[12],ymm0[13],mem[<wbr>13],ymm0[14],mem[14],ymm0[15],<wbr>mem[15] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpckhwd:<br>
; SKX: # BB#0:<br>
@@ -5924,8 +5924,8 @@ define <32 x i8> @test_punpcklbw(<32 x i<br>
; SKYLAKE-LABEL: test_punpcklbw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[<wbr>1],ymm0[2],ymm1[2],ymm0[3],<wbr>ymm1[3],ymm0[4],ymm1[4],ymm0[<wbr>5],ymm1[5],ymm0[6],ymm1[6],<wbr>ymm0[7],ymm1[7],ymm0[16],ymm1[<wbr>16],ymm0[17],ymm1[17],ymm0[18]<wbr>,ymm1[18],ymm0[19],ymm1[19],<wbr>ymm0[20],ymm1[20],ymm0[21],<wbr>ymm1[21],ymm0[22],ymm1[22],<wbr>ymm0[23],ymm1[23] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],<wbr>ymm0[2],mem[2],ymm0[3],mem[3],<wbr>ymm0[4],mem[4],ymm0[5],mem[5],<wbr>ymm0[6],mem[6],ymm0[7],mem[7],<wbr>ymm0[16],mem[16],ymm0[17],mem[<wbr>17],ymm0[18],mem[18],ymm0[19],<wbr>mem[19],ymm0[20],mem[20],ymm0[<wbr>21],mem[21],ymm0[22],mem[22],<wbr>ymm0[23],mem[23] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],<wbr>ymm0[2],mem[2],ymm0[3],mem[3],<wbr>ymm0[4],mem[4],ymm0[5],mem[5],<wbr>ymm0[6],mem[6],ymm0[7],mem[7],<wbr>ymm0[16],mem[16],ymm0[17],mem[<wbr>17],ymm0[18],mem[18],ymm0[19],<wbr>mem[19],ymm0[20],mem[20],ymm0[<wbr>21],mem[21],ymm0[22],mem[22],<wbr>ymm0[23],mem[23] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpcklbw:<br>
; SKX: # BB#0:<br>
@@ -5964,10 +5964,10 @@ define <8 x i32> @test_punpckldq(<8 x i3<br>
; SKYLAKE-LABEL: test_punpckldq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[<wbr>1],ymm0[4],ymm1[4],ymm0[5],<wbr>ymm1[5] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],<wbr>ymm0[4],mem[4],ymm0[5],mem[5] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],<wbr>ymm0[4],mem[4],ymm0[5],mem[5] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpckldq:<br>
; SKX: # BB#0:<br>
@@ -6009,9 +6009,9 @@ define <4 x i64> @test_punpcklqdq(<4 x i<br>
; SKYLAKE-LABEL: test_punpcklqdq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpcklqdq {{.*#+}} ymm1 = ymm0[0],ymm1[0],ymm0[2],ymm1[<wbr>2] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[2],mem[2] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[2],mem[2] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpcklqdq:<br>
; SKX: # BB#0:<br>
@@ -6049,8 +6049,8 @@ define <16 x i16> @test_punpcklwd(<16 x<br>
; SKYLAKE-LABEL: test_punpcklwd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[<wbr>1],ymm0[2],ymm1[2],ymm0[3],<wbr>ymm1[3],ymm0[8],ymm1[8],ymm0[<wbr>9],ymm1[9],ymm0[10],ymm1[10],<wbr>ymm0[11],ymm1[11] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],<wbr>ymm0[2],mem[2],ymm0[3],mem[3],<wbr>ymm0[8],mem[8],ymm0[9],mem[9],<wbr>ymm0[10],mem[10],ymm0[11],mem[<wbr>11] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],<wbr>ymm0[2],mem[2],ymm0[3],mem[3],<wbr>ymm0[8],mem[8],ymm0[9],mem[9],<wbr>ymm0[10],mem[10],ymm0[11],mem[<wbr>11] sched: [8:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpcklwd:<br>
; SKX: # BB#0:<br>
@@ -6086,10 +6086,10 @@ define <4 x i64> @test_pxor(<4 x i64> %a<br>
;<br>
; SKYLAKE-LABEL: test_pxor:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpxor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpxor (%rdi), %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpxor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpxor (%rdi), %ymm0, %ymm0 # sched: [8:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pxor:<br>
; SKX: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>bmi-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/bmi-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>bmi-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>bmi-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -29,10 +29,10 @@ define i16 @test_andn_i16(i16 zeroext %a<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: andnl %esi, %edi, %eax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: notl %edi # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: andw (%rdx), %di # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: andw (%rdx), %di # sched: [6:0.50]<br>
; SKYLAKE-NEXT: addl %edi, %eax # sched: [1:0.25]<br>
; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill><br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_andn_i16:<br>
; BTVER2: # BB#0:<br>
@@ -77,9 +77,9 @@ define i32 @test_andn_i32(i32 %a0, i32 %<br>
; SKYLAKE-LABEL: test_andn_i32:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: andnl %esi, %edi, %ecx # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: andnl (%rdx), %edi, %eax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: andnl (%rdx), %edi, %eax # sched: [6:0.50]<br>
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_andn_i32:<br>
; BTVER2: # BB#0:<br>
@@ -120,9 +120,9 @@ define i64 @test_andn_i64(i64 %a0, i64 %<br>
; SKYLAKE-LABEL: test_andn_i64:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: andnq %rsi, %rdi, %rcx # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: andnq (%rdx), %rdi, %rax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: andnq (%rdx), %rdi, %rax # sched: [6:0.50]<br>
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_andn_i64:<br>
; BTVER2: # BB#0:<br>
@@ -162,10 +162,10 @@ define i32 @test_bextr_i32(i32 %a0, i32<br>
;<br>
; SKYLAKE-LABEL: test_bextr_i32:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: bextrl %edi, (%rdx), %ecx # sched: [2:0.50]<br>
+; SKYLAKE-NEXT: bextrl %edi, (%rdx), %ecx # sched: [7:0.50]<br>
; SKYLAKE-NEXT: bextrl %edi, %esi, %eax # sched: [2:0.50]<br>
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_bextr_i32:<br>
; BTVER2: # BB#0:<br>
@@ -205,10 +205,10 @@ define i64 @test_bextr_i64(i64 %a0, i64<br>
;<br>
; SKYLAKE-LABEL: test_bextr_i64:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: bextrq %rdi, (%rdx), %rcx # sched: [2:0.50]<br>
+; SKYLAKE-NEXT: bextrq %rdi, (%rdx), %rcx # sched: [7:0.50]<br>
; SKYLAKE-NEXT: bextrq %rdi, %rsi, %rax # sched: [2:0.50]<br>
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_bextr_i64:<br>
; BTVER2: # BB#0:<br>
@@ -248,10 +248,10 @@ define i32 @test_blsi_i32(i32 %a0, i32 *<br>
;<br>
; SKYLAKE-LABEL: test_blsi_i32:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: blsil (%rsi), %ecx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: blsil (%rsi), %ecx # sched: [6:0.50]<br>
; SKYLAKE-NEXT: blsil %edi, %eax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_blsi_i32:<br>
; BTVER2: # BB#0:<br>
@@ -292,10 +292,10 @@ define i64 @test_blsi_i64(i64 %a0, i64 *<br>
;<br>
; SKYLAKE-LABEL: test_blsi_i64:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: blsiq (%rsi), %rcx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: blsiq (%rsi), %rcx # sched: [6:0.50]<br>
; SKYLAKE-NEXT: blsiq %rdi, %rax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_blsi_i64:<br>
; BTVER2: # BB#0:<br>
@@ -336,10 +336,10 @@ define i32 @test_blsmsk_i32(i32 %a0, i32<br>
;<br>
; SKYLAKE-LABEL: test_blsmsk_i32:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: blsmskl (%rsi), %ecx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: blsmskl (%rsi), %ecx # sched: [6:0.50]<br>
; SKYLAKE-NEXT: blsmskl %edi, %eax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_blsmsk_i32:<br>
; BTVER2: # BB#0:<br>
@@ -380,10 +380,10 @@ define i64 @test_blsmsk_i64(i64 %a0, i64<br>
;<br>
; SKYLAKE-LABEL: test_blsmsk_i64:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: blsmskq (%rsi), %rcx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: blsmskq (%rsi), %rcx # sched: [6:0.50]<br>
; SKYLAKE-NEXT: blsmskq %rdi, %rax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_blsmsk_i64:<br>
; BTVER2: # BB#0:<br>
@@ -424,10 +424,10 @@ define i32 @test_blsr_i32(i32 %a0, i32 *<br>
;<br>
; SKYLAKE-LABEL: test_blsr_i32:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: blsrl (%rsi), %ecx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: blsrl (%rsi), %ecx # sched: [6:0.50]<br>
; SKYLAKE-NEXT: blsrl %edi, %eax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_blsr_i32:<br>
; BTVER2: # BB#0:<br>
@@ -468,10 +468,10 @@ define i64 @test_blsr_i64(i64 %a0, i64 *<br>
;<br>
; SKYLAKE-LABEL: test_blsr_i64:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: blsrq (%rsi), %rcx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: blsrq (%rsi), %rcx # sched: [6:0.50]<br>
; SKYLAKE-NEXT: blsrq %rdi, %rax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_blsr_i64:<br>
; BTVER2: # BB#0:<br>
@@ -514,11 +514,11 @@ define i16 @test_cttz_i16(i16 zeroext %a<br>
;<br>
; SKYLAKE-LABEL: test_cttz_i16:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: tzcntw (%rsi), %cx # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: tzcntw (%rsi), %cx # sched: [8:1.00]<br>
; SKYLAKE-NEXT: tzcntw %di, %ax # sched: [3:1.00]<br>
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]<br>
; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill><br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_cttz_i16:<br>
; BTVER2: # BB#0:<br>
@@ -560,10 +560,10 @@ define i32 @test_cttz_i32(i32 %a0, i32 *<br>
;<br>
; SKYLAKE-LABEL: test_cttz_i32:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: tzcntl (%rsi), %ecx # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: tzcntl (%rsi), %ecx # sched: [8:1.00]<br>
; SKYLAKE-NEXT: tzcntl %edi, %eax # sched: [3:1.00]<br>
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_cttz_i32:<br>
; BTVER2: # BB#0:<br>
@@ -603,10 +603,10 @@ define i64 @test_cttz_i64(i64 %a0, i64 *<br>
;<br>
; SKYLAKE-LABEL: test_cttz_i64:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: tzcntq (%rsi), %rcx # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: tzcntq (%rsi), %rcx # sched: [8:1.00]<br>
; SKYLAKE-NEXT: tzcntq %rdi, %rax # sched: [3:1.00]<br>
; SKYLAKE-NEXT: orq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_cttz_i64:<br>
; BTVER2: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>bmi2-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/bmi2-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>bmi2-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>bmi2-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -13,12 +13,26 @@ define i32 @test_bzhi_i32(i32 %a0, i32 %<br>
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
-; COMMON-LABEL: test_bzhi_i32:<br>
-; COMMON: # BB#0:<br>
-; COMMON-NEXT: bzhil %edi, (%rdx), %ecx # sched: [1:0.50]<br>
-; COMMON-NEXT: bzhil %edi, %esi, %eax # sched: [1:0.50]<br>
-; COMMON-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; COMMON-NEXT: retq # sched: [2:1.00]<br>
+; HASWELL-LABEL: test_bzhi_i32:<br>
+; HASWELL: # BB#0:<br>
+; HASWELL-NEXT: bzhil %edi, (%rdx), %ecx # sched: [1:0.50]<br>
+; HASWELL-NEXT: bzhil %edi, %esi, %eax # sched: [1:0.50]<br>
+; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
+; HASWELL-NEXT: retq # sched: [2:1.00]<br>
+;<br>
+; SKYLAKE-LABEL: test_bzhi_i32:<br>
+; SKYLAKE: # BB#0:<br>
+; SKYLAKE-NEXT: bzhil %edi, (%rdx), %ecx # sched: [6:0.50]<br>
+; SKYLAKE-NEXT: bzhil %edi, %esi, %eax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
+;<br>
+; KNL-LABEL: test_bzhi_i32:<br>
+; KNL: # BB#0:<br>
+; KNL-NEXT: bzhil %edi, (%rdx), %ecx # sched: [1:0.50]<br>
+; KNL-NEXT: bzhil %edi, %esi, %eax # sched: [1:0.50]<br>
+; KNL-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
+; KNL-NEXT: retq # sched: [2:1.00]<br>
;<br>
; ZNVER1-LABEL: test_bzhi_i32:<br>
; ZNVER1: # BB#0:<br>
@@ -42,12 +56,26 @@ define i64 @test_bzhi_i64(i64 %a0, i64 %<br>
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
-; COMMON-LABEL: test_bzhi_i64:<br>
-; COMMON: # BB#0:<br>
-; COMMON-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [1:0.50]<br>
-; COMMON-NEXT: bzhiq %rdi, %rsi, %rax # sched: [1:0.50]<br>
-; COMMON-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; COMMON-NEXT: retq # sched: [2:1.00]<br>
+; HASWELL-LABEL: test_bzhi_i64:<br>
+; HASWELL: # BB#0:<br>
+; HASWELL-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [1:0.50]<br>
+; HASWELL-NEXT: bzhiq %rdi, %rsi, %rax # sched: [1:0.50]<br>
+; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
+; HASWELL-NEXT: retq # sched: [2:1.00]<br>
+;<br>
+; SKYLAKE-LABEL: test_bzhi_i64:<br>
+; SKYLAKE: # BB#0:<br>
+; SKYLAKE-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [6:0.50]<br>
+; SKYLAKE-NEXT: bzhiq %rdi, %rsi, %rax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
+;<br>
+; KNL-LABEL: test_bzhi_i64:<br>
+; KNL: # BB#0:<br>
+; KNL-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [1:0.50]<br>
+; KNL-NEXT: bzhiq %rdi, %rsi, %rax # sched: [1:0.50]<br>
+; KNL-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
+; KNL-NEXT: retq # sched: [2:1.00]<br>
;<br>
; ZNVER1-LABEL: test_bzhi_i64:<br>
; ZNVER1: # BB#0:<br>
@@ -75,14 +103,32 @@ define i64 @test_mulx_i64(i64 %a0, i64 %<br>
; GENERIC-NEXT: orq %rcx, %rax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
-; COMMON-LABEL: test_mulx_i64:<br>
-; COMMON: # BB#0:<br>
-; COMMON-NEXT: movq %rdx, %rax # sched: [1:0.25]<br>
-; COMMON-NEXT: movq %rdi, %rdx # sched: [1:0.25]<br>
-; COMMON-NEXT: mulxq %rsi, %rsi, %rcx # sched: [4:1.00]<br>
-; COMMON-NEXT: mulxq (%rax), %rdx, %rax # sched: [4:1.00]<br>
-; COMMON-NEXT: orq %rcx, %rax # sched: [1:0.25]<br>
-; COMMON-NEXT: retq # sched: [2:1.00]<br>
+; HASWELL-LABEL: test_mulx_i64:<br>
+; HASWELL: # BB#0:<br>
+; HASWELL-NEXT: movq %rdx, %rax # sched: [1:0.25]<br>
+; HASWELL-NEXT: movq %rdi, %rdx # sched: [1:0.25]<br>
+; HASWELL-NEXT: mulxq %rsi, %rsi, %rcx # sched: [4:1.00]<br>
+; HASWELL-NEXT: mulxq (%rax), %rdx, %rax # sched: [4:1.00]<br>
+; HASWELL-NEXT: orq %rcx, %rax # sched: [1:0.25]<br>
+; HASWELL-NEXT: retq # sched: [2:1.00]<br>
+;<br>
+; SKYLAKE-LABEL: test_mulx_i64:<br>
+; SKYLAKE: # BB#0:<br>
+; SKYLAKE-NEXT: movq %rdx, %rax # sched: [1:0.25]<br>
+; SKYLAKE-NEXT: movq %rdi, %rdx # sched: [1:0.25]<br>
+; SKYLAKE-NEXT: mulxq %rsi, %rsi, %rcx # sched: [4:1.00]<br>
+; SKYLAKE-NEXT: mulxq (%rax), %rdx, %rax # sched: [9:1.00]<br>
+; SKYLAKE-NEXT: orq %rcx, %rax # sched: [1:0.25]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
+;<br>
+; KNL-LABEL: test_mulx_i64:<br>
+; KNL: # BB#0:<br>
+; KNL-NEXT: movq %rdx, %rax # sched: [1:0.25]<br>
+; KNL-NEXT: movq %rdi, %rdx # sched: [1:0.25]<br>
+; KNL-NEXT: mulxq %rsi, %rsi, %rcx # sched: [4:1.00]<br>
+; KNL-NEXT: mulxq (%rax), %rdx, %rax # sched: [4:1.00]<br>
+; KNL-NEXT: orq %rcx, %rax # sched: [1:0.25]<br>
+; KNL-NEXT: retq # sched: [2:1.00]<br>
;<br>
; ZNVER1-LABEL: test_mulx_i64:<br>
; ZNVER1: # BB#0:<br>
@@ -114,12 +160,26 @@ define i32 @test_pdep_i32(i32 %a0, i32 %<br>
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
-; COMMON-LABEL: test_pdep_i32:<br>
-; COMMON: # BB#0:<br>
-; COMMON-NEXT: pdepl (%rdx), %edi, %ecx # sched: [3:1.00]<br>
-; COMMON-NEXT: pdepl %esi, %edi, %eax # sched: [3:1.00]<br>
-; COMMON-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; COMMON-NEXT: retq # sched: [2:1.00]<br>
+; HASWELL-LABEL: test_pdep_i32:<br>
+; HASWELL: # BB#0:<br>
+; HASWELL-NEXT: pdepl (%rdx), %edi, %ecx # sched: [3:1.00]<br>
+; HASWELL-NEXT: pdepl %esi, %edi, %eax # sched: [3:1.00]<br>
+; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
+; HASWELL-NEXT: retq # sched: [2:1.00]<br>
+;<br>
+; SKYLAKE-LABEL: test_pdep_i32:<br>
+; SKYLAKE: # BB#0:<br>
+; SKYLAKE-NEXT: pdepl (%rdx), %edi, %ecx # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: pdepl %esi, %edi, %eax # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
+;<br>
+; KNL-LABEL: test_pdep_i32:<br>
+; KNL: # BB#0:<br>
+; KNL-NEXT: pdepl (%rdx), %edi, %ecx # sched: [3:1.00]<br>
+; KNL-NEXT: pdepl %esi, %edi, %eax # sched: [3:1.00]<br>
+; KNL-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
+; KNL-NEXT: retq # sched: [2:1.00]<br>
;<br>
; ZNVER1-LABEL: test_pdep_i32:<br>
; ZNVER1: # BB#0:<br>
@@ -143,12 +203,26 @@ define i64 @test_pdep_i64(i64 %a0, i64 %<br>
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
-; COMMON-LABEL: test_pdep_i64:<br>
-; COMMON: # BB#0:<br>
-; COMMON-NEXT: pdepq (%rdx), %rdi, %rcx # sched: [3:1.00]<br>
-; COMMON-NEXT: pdepq %rsi, %rdi, %rax # sched: [3:1.00]<br>
-; COMMON-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; COMMON-NEXT: retq # sched: [2:1.00]<br>
+; HASWELL-LABEL: test_pdep_i64:<br>
+; HASWELL: # BB#0:<br>
+; HASWELL-NEXT: pdepq (%rdx), %rdi, %rcx # sched: [3:1.00]<br>
+; HASWELL-NEXT: pdepq %rsi, %rdi, %rax # sched: [3:1.00]<br>
+; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
+; HASWELL-NEXT: retq # sched: [2:1.00]<br>
+;<br>
+; SKYLAKE-LABEL: test_pdep_i64:<br>
+; SKYLAKE: # BB#0:<br>
+; SKYLAKE-NEXT: pdepq (%rdx), %rdi, %rcx # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: pdepq %rsi, %rdi, %rax # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
+;<br>
+; KNL-LABEL: test_pdep_i64:<br>
+; KNL: # BB#0:<br>
+; KNL-NEXT: pdepq (%rdx), %rdi, %rcx # sched: [3:1.00]<br>
+; KNL-NEXT: pdepq %rsi, %rdi, %rax # sched: [3:1.00]<br>
+; KNL-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
+; KNL-NEXT: retq # sched: [2:1.00]<br>
;<br>
; ZNVER1-LABEL: test_pdep_i64:<br>
; ZNVER1: # BB#0:<br>
@@ -172,12 +246,26 @@ define i32 @test_pext_i32(i32 %a0, i32 %<br>
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
-; COMMON-LABEL: test_pext_i32:<br>
-; COMMON: # BB#0:<br>
-; COMMON-NEXT: pextl (%rdx), %edi, %ecx # sched: [3:1.00]<br>
-; COMMON-NEXT: pextl %esi, %edi, %eax # sched: [3:1.00]<br>
-; COMMON-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; COMMON-NEXT: retq # sched: [2:1.00]<br>
+; HASWELL-LABEL: test_pext_i32:<br>
+; HASWELL: # BB#0:<br>
+; HASWELL-NEXT: pextl (%rdx), %edi, %ecx # sched: [3:1.00]<br>
+; HASWELL-NEXT: pextl %esi, %edi, %eax # sched: [3:1.00]<br>
+; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
+; HASWELL-NEXT: retq # sched: [2:1.00]<br>
+;<br>
+; SKYLAKE-LABEL: test_pext_i32:<br>
+; SKYLAKE: # BB#0:<br>
+; SKYLAKE-NEXT: pextl (%rdx), %edi, %ecx # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: pextl %esi, %edi, %eax # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
+;<br>
+; KNL-LABEL: test_pext_i32:<br>
+; KNL: # BB#0:<br>
+; KNL-NEXT: pextl (%rdx), %edi, %ecx # sched: [3:1.00]<br>
+; KNL-NEXT: pextl %esi, %edi, %eax # sched: [3:1.00]<br>
+; KNL-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
+; KNL-NEXT: retq # sched: [2:1.00]<br>
;<br>
; ZNVER1-LABEL: test_pext_i32:<br>
; ZNVER1: # BB#0:<br>
@@ -201,12 +289,26 @@ define i64 @test_pext_i64(i64 %a0, i64 %<br>
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
-; COMMON-LABEL: test_pext_i64:<br>
-; COMMON: # BB#0:<br>
-; COMMON-NEXT: pextq (%rdx), %rdi, %rcx # sched: [3:1.00]<br>
-; COMMON-NEXT: pextq %rsi, %rdi, %rax # sched: [3:1.00]<br>
-; COMMON-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; COMMON-NEXT: retq # sched: [2:1.00]<br>
+; HASWELL-LABEL: test_pext_i64:<br>
+; HASWELL: # BB#0:<br>
+; HASWELL-NEXT: pextq (%rdx), %rdi, %rcx # sched: [3:1.00]<br>
+; HASWELL-NEXT: pextq %rsi, %rdi, %rax # sched: [3:1.00]<br>
+; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
+; HASWELL-NEXT: retq # sched: [2:1.00]<br>
+;<br>
+; SKYLAKE-LABEL: test_pext_i64:<br>
+; SKYLAKE: # BB#0:<br>
+; SKYLAKE-NEXT: pextq (%rdx), %rdi, %rcx # sched: [8:1.00]<br>
+; SKYLAKE-NEXT: pextq %rsi, %rdi, %rax # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
+;<br>
+; KNL-LABEL: test_pext_i64:<br>
+; KNL: # BB#0:<br>
+; KNL-NEXT: pextq (%rdx), %rdi, %rcx # sched: [3:1.00]<br>
+; KNL-NEXT: pextq %rsi, %rdi, %rax # sched: [3:1.00]<br>
+; KNL-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
+; KNL-NEXT: retq # sched: [2:1.00]<br>
;<br>
; ZNVER1-LABEL: test_pext_i64:<br>
; ZNVER1: # BB#0:<br>
@@ -239,10 +341,10 @@ define i32 @test_rorx_i32(i32 %a0, i32 %<br>
;<br>
; SKYLAKE-LABEL: test_rorx_i32:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: rorxl $5, %edi, %ecx # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: rorxl $5, (%rdx), %eax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: rorxl $5, %edi, %ecx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: rorxl $5, (%rdx), %eax # sched: [6:0.50]<br>
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_rorx_i32:<br>
; KNL: # BB#0:<br>
@@ -285,10 +387,10 @@ define i64 @test_rorx_i64(i64 %a0, i64 %<br>
;<br>
; SKYLAKE-LABEL: test_rorx_i64:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: rorxq $5, %rdi, %rcx # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: rorxq $5, (%rdx), %rax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: rorxq $5, %rdi, %rcx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: rorxq $5, (%rdx), %rax # sched: [6:0.50]<br>
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_rorx_i64:<br>
; KNL: # BB#0:<br>
@@ -331,10 +433,10 @@ define i32 @test_sarx_i32(i32 %a0, i32 %<br>
;<br>
; SKYLAKE-LABEL: test_sarx_i32:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: sarxl %esi, %edi, %ecx # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: sarxl %esi, (%rdx), %eax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: sarxl %esi, %edi, %ecx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: sarxl %esi, (%rdx), %eax # sched: [6:0.50]<br>
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_sarx_i32:<br>
; KNL: # BB#0:<br>
@@ -373,10 +475,10 @@ define i64 @test_sarx_i64(i64 %a0, i64 %<br>
;<br>
; SKYLAKE-LABEL: test_sarx_i64:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: sarxq %rsi, %rdi, %rcx # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: sarxq %rsi, (%rdx), %rax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: sarxq %rsi, %rdi, %rcx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: sarxq %rsi, (%rdx), %rax # sched: [6:0.50]<br>
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_sarx_i64:<br>
; KNL: # BB#0:<br>
@@ -415,10 +517,10 @@ define i32 @test_shlx_i32(i32 %a0, i32 %<br>
;<br>
; SKYLAKE-LABEL: test_shlx_i32:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: shlxl %esi, %edi, %ecx # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: shlxl %esi, (%rdx), %eax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: shlxl %esi, %edi, %ecx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: shlxl %esi, (%rdx), %eax # sched: [6:0.50]<br>
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_shlx_i32:<br>
; KNL: # BB#0:<br>
@@ -457,10 +559,10 @@ define i64 @test_shlx_i64(i64 %a0, i64 %<br>
;<br>
; SKYLAKE-LABEL: test_shlx_i64:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: shlxq %rsi, %rdi, %rcx # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: shlxq %rsi, (%rdx), %rax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: shlxq %rsi, %rdi, %rcx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: shlxq %rsi, (%rdx), %rax # sched: [6:0.50]<br>
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_shlx_i64:<br>
; KNL: # BB#0:<br>
@@ -499,10 +601,10 @@ define i32 @test_shrx_i32(i32 %a0, i32 %<br>
;<br>
; SKYLAKE-LABEL: test_shrx_i32:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: shrxl %esi, %edi, %ecx # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: shrxl %esi, (%rdx), %eax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: shrxl %esi, %edi, %ecx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: shrxl %esi, (%rdx), %eax # sched: [6:0.50]<br>
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_shrx_i32:<br>
; KNL: # BB#0:<br>
@@ -541,10 +643,10 @@ define i64 @test_shrx_i64(i64 %a0, i64 %<br>
;<br>
; SKYLAKE-LABEL: test_shrx_i64:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: shrxq %rsi, %rdi, %rcx # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: shrxq %rsi, (%rdx), %rax # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: shrxq %rsi, %rdi, %rcx # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: shrxq %rsi, (%rdx), %rax # sched: [6:0.50]<br>
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_shrx_i64:<br>
; KNL: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>f16c-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/f16c-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/f16c-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>f16c-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>f16c-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -30,10 +30,10 @@ define <4 x float> @test_vcvtph2ps_128(<<br>
;<br>
; SKYLAKE-LABEL: test_vcvtph2ps_128:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [4:0.50]<br>
+; SKYLAKE-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [9:0.50]<br>
; SKYLAKE-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [5:1.00]<br>
; SKYLAKE-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_vcvtph2ps_128:<br>
; BTVER2: # BB#0:<br>
@@ -80,10 +80,10 @@ define <8 x float> @test_vcvtph2ps_256(<<br>
;<br>
; SKYLAKE-LABEL: test_vcvtph2ps_256:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [4:0.50]<br>
+; SKYLAKE-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [10:0.50]<br>
; SKYLAKE-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [7:1.00]<br>
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_vcvtph2ps_256:<br>
; BTVER2: # BB#0:<br>
@@ -128,8 +128,8 @@ define <8 x i16> @test_vcvtps2ph_128(<4<br>
; SKYLAKE-LABEL: test_vcvtps2ph_128:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [5:1.00]<br>
-; SKYLAKE-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [5:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_vcvtps2ph_128:<br>
; BTVER2: # BB#0:<br>
@@ -175,9 +175,9 @@ define <8 x i16> @test_vcvtps2ph_256(<8<br>
; SKYLAKE-LABEL: test_vcvtps2ph_256:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [7:1.00]<br>
-; SKYLAKE-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [7:1.00]<br>
+; SKYLAKE-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [8:1.00]<br>
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_vcvtps2ph_256:<br>
; BTVER2: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>fma-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fma-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/fma-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>fma-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>fma-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -30,8 +30,8 @@ define <2 x double> @test_vfmadd213pd(<2<br>
; SKYLAKE-LABEL: test_vfmadd213pd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmadd213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmadd213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmadd213pd:<br>
; KNL: # BB#0:<br>
@@ -72,8 +72,8 @@ define <4 x double> @test_vfmadd213pd_ym<br>
; SKYLAKE-LABEL: test_vfmadd213pd_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmadd213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmadd213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmadd213pd_ymm:<br>
; KNL: # BB#0:<br>
@@ -114,8 +114,8 @@ define <4 x float> @test_vfmadd213ps(<4<br>
; SKYLAKE-LABEL: test_vfmadd213ps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmadd213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmadd213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmadd213ps:<br>
; KNL: # BB#0:<br>
@@ -156,8 +156,8 @@ define <8 x float> @test_vfmadd213ps_ymm<br>
; SKYLAKE-LABEL: test_vfmadd213ps_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmadd213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmadd213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmadd213ps_ymm:<br>
; KNL: # BB#0:<br>
@@ -198,8 +198,8 @@ define <2 x double> @test_vfmadd213sd(<2<br>
; SKYLAKE-LABEL: test_vfmadd213sd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmadd213sd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmadd213sd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmadd213sd:<br>
; KNL: # BB#0:<br>
@@ -240,8 +240,8 @@ define <4 x float> @test_vfmadd213ss(<4<br>
; SKYLAKE-LABEL: test_vfmadd213ss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmadd213ss (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmadd213ss (%rdi), %xmm1, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmadd213ss:<br>
; KNL: # BB#0:<br>
@@ -294,8 +294,8 @@ define <2 x double> @test_vfmaddsubpd(<2<br>
; SKYLAKE-LABEL: test_vfmaddsubpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmaddsub213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmaddsub213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmaddsubpd:<br>
; KNL: # BB#0:<br>
@@ -336,8 +336,8 @@ define <4 x double> @test_vfmaddsubpd_ym<br>
; SKYLAKE-LABEL: test_vfmaddsubpd_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmaddsub213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmaddsub213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmaddsubpd_ymm:<br>
; KNL: # BB#0:<br>
@@ -378,8 +378,8 @@ define <4 x float> @test_vfmaddsubps(<4<br>
; SKYLAKE-LABEL: test_vfmaddsubps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmaddsub213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmaddsub213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmaddsubps:<br>
; KNL: # BB#0:<br>
@@ -420,8 +420,8 @@ define <8 x float> @test_vfmaddsubps_ymm<br>
; SKYLAKE-LABEL: test_vfmaddsubps_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmaddsub213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmaddsub213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmaddsubps_ymm:<br>
; KNL: # BB#0:<br>
@@ -474,8 +474,8 @@ define <2 x double> @test_vfmsubaddpd(<2<br>
; SKYLAKE-LABEL: test_vfmsubaddpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmsubadd213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmsubadd213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmsubadd213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmsubaddpd:<br>
; KNL: # BB#0:<br>
@@ -516,8 +516,8 @@ define <4 x double> @test_vfmsubaddpd_ym<br>
; SKYLAKE-LABEL: test_vfmsubaddpd_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmsubadd213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmsubadd213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmsubadd213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmsubaddpd_ymm:<br>
; KNL: # BB#0:<br>
@@ -558,8 +558,8 @@ define <4 x float> @test_vfmsubaddps(<4<br>
; SKYLAKE-LABEL: test_vfmsubaddps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmsubadd213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmsubadd213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmsubadd213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmsubaddps:<br>
; KNL: # BB#0:<br>
@@ -600,8 +600,8 @@ define <8 x float> @test_vfmsubaddps_ymm<br>
; SKYLAKE-LABEL: test_vfmsubaddps_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmsubadd213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmsubadd213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmsubadd213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmsubaddps_ymm:<br>
; KNL: # BB#0:<br>
@@ -654,8 +654,8 @@ define <2 x double> @test_vfmsub213pd(<2<br>
; SKYLAKE-LABEL: test_vfmsub213pd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmsub213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmsub213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmsub213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmsub213pd:<br>
; KNL: # BB#0:<br>
@@ -696,8 +696,8 @@ define <4 x double> @test_vfmsub213pd_ym<br>
; SKYLAKE-LABEL: test_vfmsub213pd_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmsub213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmsub213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmsub213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmsub213pd_ymm:<br>
; KNL: # BB#0:<br>
@@ -738,8 +738,8 @@ define <4 x float> @test_vfmsub213ps(<4<br>
; SKYLAKE-LABEL: test_vfmsub213ps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmsub213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmsub213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmsub213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmsub213ps:<br>
; KNL: # BB#0:<br>
@@ -780,8 +780,8 @@ define <8 x float> @test_vfmsub213ps_ymm<br>
; SKYLAKE-LABEL: test_vfmsub213ps_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmsub213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmsub213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmsub213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmsub213ps_ymm:<br>
; KNL: # BB#0:<br>
@@ -822,8 +822,8 @@ define <2 x double> @test_vfmsub213sd(<2<br>
; SKYLAKE-LABEL: test_vfmsub213sd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmsub213sd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmsub213sd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmsub213sd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmsub213sd:<br>
; KNL: # BB#0:<br>
@@ -864,8 +864,8 @@ define <4 x float> @test_vfmsub213ss(<4<br>
; SKYLAKE-LABEL: test_vfmsub213ss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfmsub213ss %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfmsub213ss (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfmsub213ss (%rdi), %xmm1, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfmsub213ss:<br>
; KNL: # BB#0:<br>
@@ -918,8 +918,8 @@ define <2 x double> @test_vfnmadd213pd(<<br>
; SKYLAKE-LABEL: test_vfnmadd213pd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfnmadd213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfnmadd213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfnmadd213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfnmadd213pd:<br>
; KNL: # BB#0:<br>
@@ -960,8 +960,8 @@ define <4 x double> @test_vfnmadd213pd_y<br>
; SKYLAKE-LABEL: test_vfnmadd213pd_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfnmadd213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfnmadd213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfnmadd213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfnmadd213pd_ymm:<br>
; KNL: # BB#0:<br>
@@ -1002,8 +1002,8 @@ define <4 x float> @test_vfnmadd213ps(<4<br>
; SKYLAKE-LABEL: test_vfnmadd213ps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfnmadd213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfnmadd213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfnmadd213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfnmadd213ps:<br>
; KNL: # BB#0:<br>
@@ -1044,8 +1044,8 @@ define <8 x float> @test_vfnmadd213ps_ym<br>
; SKYLAKE-LABEL: test_vfnmadd213ps_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfnmadd213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfnmadd213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfnmadd213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfnmadd213ps_ymm:<br>
; KNL: # BB#0:<br>
@@ -1086,8 +1086,8 @@ define <2 x double> @test_vfnmadd213sd(<<br>
; SKYLAKE-LABEL: test_vfnmadd213sd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfnmadd213sd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfnmadd213sd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfnmadd213sd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfnmadd213sd:<br>
; KNL: # BB#0:<br>
@@ -1128,8 +1128,8 @@ define <4 x float> @test_vfnmadd213ss(<4<br>
; SKYLAKE-LABEL: test_vfnmadd213ss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfnmadd213ss %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfnmadd213ss (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfnmadd213ss (%rdi), %xmm1, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfnmadd213ss:<br>
; KNL: # BB#0:<br>
@@ -1182,8 +1182,8 @@ define <2 x double> @test_vfnmsub213pd(<<br>
; SKYLAKE-LABEL: test_vfnmsub213pd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfnmsub213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfnmsub213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfnmsub213pd:<br>
; KNL: # BB#0:<br>
@@ -1224,8 +1224,8 @@ define <4 x double> @test_vfnmsub213pd_y<br>
; SKYLAKE-LABEL: test_vfnmsub213pd_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfnmsub213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfnmsub213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfnmsub213pd_ymm:<br>
; KNL: # BB#0:<br>
@@ -1266,8 +1266,8 @@ define <4 x float> @test_vfnmsub213ps(<4<br>
; SKYLAKE-LABEL: test_vfnmsub213ps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfnmsub213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfnmsub213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfnmsub213ps:<br>
; KNL: # BB#0:<br>
@@ -1308,8 +1308,8 @@ define <8 x float> @test_vfnmsub213ps_ym<br>
; SKYLAKE-LABEL: test_vfnmsub213ps_ymm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfnmsub213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfnmsub213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfnmsub213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfnmsub213ps_ymm:<br>
; KNL: # BB#0:<br>
@@ -1350,8 +1350,8 @@ define <2 x double> @test_vfnmsub213sd(<<br>
; SKYLAKE-LABEL: test_vfnmsub213sd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfnmsub213sd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfnmsub213sd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfnmsub213sd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfnmsub213sd:<br>
; KNL: # BB#0:<br>
@@ -1392,8 +1392,8 @@ define <4 x float> @test_vfnmsub213ss(<4<br>
; SKYLAKE-LABEL: test_vfnmsub213ss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vfnmsub213ss %xmm2, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vfnmsub213ss (%rdi), %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vfnmsub213ss (%rdi), %xmm1, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; KNL-LABEL: test_vfnmsub213ss:<br>
; KNL: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>lea32-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea32-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/lea32-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>lea32-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>lea32-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -51,7 +51,7 @@ define i32 @test_lea_offset(i32) {<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
; SKYLAKE-NEXT: leal -24(%rdi), %eax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_offset:<br>
; BTVER2: # BB#0:<br>
@@ -109,7 +109,7 @@ define i32 @test_lea_offset_big(i32) {<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
; SKYLAKE-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_offset_big:<br>
; BTVER2: # BB#0:<br>
@@ -174,7 +174,7 @@ define i32 @test_lea_add(i32, i32) {<br>
; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def><br>
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
; SKYLAKE-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_add:<br>
; BTVER2: # BB#0:<br>
@@ -244,7 +244,7 @@ define i32 @test_lea_add_offset(i32, i32<br>
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
; SKYLAKE-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addl $16, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_add_offset:<br>
; BTVER2: # BB#0:<br>
@@ -319,7 +319,7 @@ define i32 @test_lea_add_offset_big(i32,<br>
; SKYLAKE-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addl $-4096, %eax # imm = 0xF000<br>
; SKYLAKE-NEXT: # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_add_offset_big:<br>
; BTVER2: # BB#0:<br>
@@ -380,7 +380,7 @@ define i32 @test_lea_mul(i32) {<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
; SKYLAKE-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_mul:<br>
; BTVER2: # BB#0:<br>
@@ -442,7 +442,7 @@ define i32 @test_lea_mul_offset(i32) {<br>
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
; SKYLAKE-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addl $-32, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_mul_offset:<br>
; BTVER2: # BB#0:<br>
@@ -509,7 +509,7 @@ define i32 @test_lea_mul_offset_big(i32)<br>
; SKYLAKE-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addl $10000, %eax # imm = 0x2710<br>
; SKYLAKE-NEXT: # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_mul_offset_big:<br>
; BTVER2: # BB#0:<br>
@@ -574,7 +574,7 @@ define i32 @test_lea_add_scale(i32, i32)<br>
; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def><br>
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
; SKYLAKE-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_add_scale:<br>
; BTVER2: # BB#0:<br>
@@ -645,7 +645,7 @@ define i32 @test_lea_add_scale_offset(i3<br>
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
; SKYLAKE-NEXT: leal (%rdi,%rsi,4), %eax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addl $96, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_add_scale_offset:<br>
; BTVER2: # BB#0:<br>
@@ -721,7 +721,7 @@ define i32 @test_lea_add_scale_offset_bi<br>
; SKYLAKE-NEXT: leal (%rdi,%rsi,8), %eax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addl $-1200, %eax # imm = 0xFB50<br>
; SKYLAKE-NEXT: # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_add_scale_offset_big:<br>
; BTVER2: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>lea64-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea64-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/lea64-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>lea64-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>lea64-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -45,7 +45,7 @@ define i64 @test_lea_offset(i64) {<br>
; SKYLAKE-LABEL: test_lea_offset:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: leaq -24(%rdi), %rax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_offset:<br>
; BTVER2: # BB#0:<br>
@@ -95,7 +95,7 @@ define i64 @test_lea_offset_big(i64) {<br>
; SKYLAKE-LABEL: test_lea_offset_big:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: leaq 1024(%rdi), %rax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_offset_big:<br>
; BTVER2: # BB#0:<br>
@@ -146,7 +146,7 @@ define i64 @test_lea_add(i64, i64) {<br>
; SKYLAKE-LABEL: test_lea_add:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: leaq (%rdi,%rsi), %rax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_add:<br>
; BTVER2: # BB#0:<br>
@@ -200,7 +200,7 @@ define i64 @test_lea_add_offset(i64, i64<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: leaq (%rdi,%rsi), %rax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addq $16, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_add_offset:<br>
; BTVER2: # BB#0:<br>
@@ -259,7 +259,7 @@ define i64 @test_lea_add_offset_big(i64,<br>
; SKYLAKE-NEXT: leaq (%rdi,%rsi), %rax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addq $-4096, %rax # imm = 0xF000<br>
; SKYLAKE-NEXT: # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_add_offset_big:<br>
; BTVER2: # BB#0:<br>
@@ -310,7 +310,7 @@ define i64 @test_lea_mul(i64) {<br>
; SKYLAKE-LABEL: test_lea_mul:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_mul:<br>
; BTVER2: # BB#0:<br>
@@ -364,7 +364,7 @@ define i64 @test_lea_mul_offset(i64) {<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addq $-32, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_mul_offset:<br>
; BTVER2: # BB#0:<br>
@@ -423,7 +423,7 @@ define i64 @test_lea_mul_offset_big(i64)<br>
; SKYLAKE-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addq $10000, %rax # imm = 0x2710<br>
; SKYLAKE-NEXT: # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_mul_offset_big:<br>
; BTVER2: # BB#0:<br>
@@ -474,7 +474,7 @@ define i64 @test_lea_add_scale(i64, i64)<br>
; SKYLAKE-LABEL: test_lea_add_scale:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: leaq (%rdi,%rsi,2), %rax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_add_scale:<br>
; BTVER2: # BB#0:<br>
@@ -529,7 +529,7 @@ define i64 @test_lea_add_scale_offset(i6<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: leaq (%rdi,%rsi,4), %rax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addq $96, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_add_scale_offset:<br>
; BTVER2: # BB#0:<br>
@@ -589,7 +589,7 @@ define i64 @test_lea_add_scale_offset_bi<br>
; SKYLAKE-NEXT: leaq (%rdi,%rsi,8), %rax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: addq $-1200, %rax # imm = 0xFB50<br>
; SKYLAKE-NEXT: # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_lea_add_scale_offset_big:<br>
; BTVER2: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>lzcnt-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/lzcnt-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>lzcnt-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>lzcnt-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -25,11 +25,11 @@ define i16 @test_ctlz_i16(i16 zeroext %a<br>
;<br>
; SKYLAKE-LABEL: test_ctlz_i16:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: lzcntw (%rsi), %cx # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: lzcntw (%rsi), %cx # sched: [8:1.00]<br>
; SKYLAKE-NEXT: lzcntw %di, %ax # sched: [3:1.00]<br>
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]<br>
; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill><br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_ctlz_i16:<br>
; BTVER2: # BB#0:<br>
@@ -71,10 +71,10 @@ define i32 @test_ctlz_i32(i32 %a0, i32 *<br>
;<br>
; SKYLAKE-LABEL: test_ctlz_i32:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: lzcntl (%rsi), %ecx # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: lzcntl (%rsi), %ecx # sched: [8:1.00]<br>
; SKYLAKE-NEXT: lzcntl %edi, %eax # sched: [3:1.00]<br>
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_ctlz_i32:<br>
; BTVER2: # BB#0:<br>
@@ -114,10 +114,10 @@ define i64 @test_ctlz_i64(i64 %a0, i64 *<br>
;<br>
; SKYLAKE-LABEL: test_ctlz_i64:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: lzcntq (%rsi), %rcx # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: lzcntq (%rsi), %rcx # sched: [8:1.00]<br>
; SKYLAKE-NEXT: lzcntq %rdi, %rax # sched: [3:1.00]<br>
; SKYLAKE-NEXT: orq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_ctlz_i64:<br>
; BTVER2: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>movbe-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movbe-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/movbe-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>movbe-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>movbe-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -39,9 +39,9 @@ define i16 @test_movbe_i16(i16 *%a0, i16<br>
;<br>
; SKYLAKE-LABEL: test_movbe_i16:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: movbew (%rdi), %ax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: movbew %si, (%rdx) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: movbew (%rdi), %ax # sched: [6:0.50]<br>
+; SKYLAKE-NEXT: movbew %si, (%rdx) # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_movbe_i16:<br>
; BTVER2: # BB#0:<br>
@@ -93,9 +93,9 @@ define i32 @test_movbe_i32(i32 *%a0, i32<br>
;<br>
; SKYLAKE-LABEL: test_movbe_i32:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: movbel (%rdi), %eax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: movbel %esi, (%rdx) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: movbel (%rdi), %eax # sched: [6:0.50]<br>
+; SKYLAKE-NEXT: movbel %esi, (%rdx) # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_movbe_i32:<br>
; BTVER2: # BB#0:<br>
@@ -147,9 +147,9 @@ define i64 @test_movbe_i64(i64 *%a0, i64<br>
;<br>
; SKYLAKE-LABEL: test_movbe_i64:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: movbeq (%rdi), %rax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: movbeq %rsi, (%rdx) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: movbeq (%rdi), %rax # sched: [6:0.50]<br>
+; SKYLAKE-NEXT: movbeq %rsi, (%rdx) # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_movbe_i64:<br>
; BTVER2: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>popcnt-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/popcnt-schedule.<wbr>ll?rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>popcnt-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>popcnt-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -45,11 +45,11 @@ define i16 @test_ctpop_i16(i16 zeroext %<br>
;<br>
; SKYLAKE-LABEL: test_ctpop_i16:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: popcntw (%rsi), %cx # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: popcntw (%rsi), %cx # sched: [8:1.00]<br>
; SKYLAKE-NEXT: popcntw %di, %ax # sched: [3:1.00]<br>
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]<br>
; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill><br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_ctpop_i16:<br>
; BTVER2: # BB#0:<br>
@@ -105,10 +105,10 @@ define i32 @test_ctpop_i32(i32 %a0, i32<br>
;<br>
; SKYLAKE-LABEL: test_ctpop_i32:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: popcntl (%rsi), %ecx # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: popcntl (%rsi), %ecx # sched: [8:1.00]<br>
; SKYLAKE-NEXT: popcntl %edi, %eax # sched: [3:1.00]<br>
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_ctpop_i32:<br>
; BTVER2: # BB#0:<br>
@@ -162,10 +162,10 @@ define i64 @test_ctpop_i64(i64 %a0, i64<br>
;<br>
; SKYLAKE-LABEL: test_ctpop_i64:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: popcntq (%rsi), %rcx # sched: [3:1.00]<br>
+; SKYLAKE-NEXT: popcntq (%rsi), %rcx # sched: [8:1.00]<br>
; SKYLAKE-NEXT: popcntq %rdi, %rax # sched: [3:1.00]<br>
; SKYLAKE-NEXT: orq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; BTVER2-LABEL: test_ctpop_i64:<br>
; BTVER2: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>sse-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/sse-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>sse-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>sse-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -44,8 +44,8 @@ define <4 x float> @test_addps(<4 x floa<br>
; SKYLAKE-LABEL: test_addps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vaddps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaddps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_addps:<br>
; SKX: # BB#0:<br>
@@ -104,8 +104,8 @@ define float @test_addss(float %a0, floa<br>
; SKYLAKE-LABEL: test_addss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vaddss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaddss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_addss:<br>
; SKX: # BB#0:<br>
@@ -167,9 +167,9 @@ define <4 x float> @test_andps(<4 x floa<br>
;<br>
; SKYLAKE-LABEL: test_andps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vandps %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vandps (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vandps %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vandps (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_andps:<br>
; SKX: # BB#0:<br>
@@ -235,9 +235,9 @@ define <4 x float> @test_andnotps(<4 x f<br>
;<br>
; SKYLAKE-LABEL: test_andnotps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vandnps %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vandnps (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vandnps %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vandnps (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_andnotps:<br>
; SKX: # BB#0:<br>
@@ -307,9 +307,9 @@ define <4 x float> @test_cmpps(<4 x floa<br>
; SKYLAKE-LABEL: test_cmpps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcmpeqps %xmm1, %xmm0, %xmm1 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vcmpeqps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vorps %xmm0, %xmm1, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vcmpeqps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: vorps %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cmpps:<br>
; SKX: # BB#0:<br>
@@ -376,7 +376,7 @@ define float @test_cmpss(float %a0, floa<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br>
; SKYLAKE-NEXT: vcmpeqss (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cmpss:<br>
; SKX: # BB#0:<br>
@@ -480,16 +480,16 @@ define i32 @test_comiss(<4 x float> %a0,<br>
; SKYLAKE-LABEL: test_comiss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcomiss %xmm1, %xmm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: sete %cl # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: sete %cl # sched: [1:0.50]<br>
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]<br>
; SKYLAKE-NEXT: vcomiss (%rdi), %xmm0 # sched: [8:1.00]<br>
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: sete %dl # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: sete %dl # sched: [1:0.50]<br>
; SKYLAKE-NEXT: andb %al, %dl # sched: [1:0.25]<br>
; SKYLAKE-NEXT: orb %cl, %dl # sched: [1:0.25]<br>
; SKYLAKE-NEXT: movzbl %dl, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_comiss:<br>
; SKX: # BB#0:<br>
@@ -581,7 +581,7 @@ define float @test_cvtsi2ss(i32 %a0, i32<br>
; SKYLAKE-NEXT: vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [5:1.00]<br>
; SKYLAKE-NEXT: vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]<br>
; SKYLAKE-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtsi2ss:<br>
; SKX: # BB#0:<br>
@@ -651,7 +651,7 @@ define float @test_cvtsi2ssq(i64 %a0, i6<br>
; SKYLAKE-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0 # sched: [6:2.00]<br>
; SKYLAKE-NEXT: vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]<br>
; SKYLAKE-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtsi2ssq:<br>
; SKX: # BB#0:<br>
@@ -719,9 +719,9 @@ define i32 @test_cvtss2si(float %a0, flo<br>
; SKYLAKE-LABEL: test_cvtss2si:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtss2si %xmm0, %ecx # sched: [6:1.00]<br>
-; SKYLAKE-NEXT: vcvtss2si (%rdi), %eax # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vcvtss2si (%rdi), %eax # sched: [11:1.00]<br>
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtss2si:<br>
; SKX: # BB#0:<br>
@@ -792,9 +792,9 @@ define i64 @test_cvtss2siq(float %a0, fl<br>
; SKYLAKE-LABEL: test_cvtss2siq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtss2si %xmm0, %rcx # sched: [6:1.00]<br>
-; SKYLAKE-NEXT: vcvtss2si (%rdi), %rax # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vcvtss2si (%rdi), %rax # sched: [11:1.00]<br>
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtss2siq:<br>
; SKX: # BB#0:<br>
@@ -865,9 +865,9 @@ define i32 @test_cvttss2si(float %a0, fl<br>
; SKYLAKE-LABEL: test_cvttss2si:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvttss2si %xmm0, %ecx # sched: [7:1.00]<br>
-; SKYLAKE-NEXT: vcvttss2si (%rdi), %eax # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vcvttss2si (%rdi), %eax # sched: [11:1.00]<br>
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvttss2si:<br>
; SKX: # BB#0:<br>
@@ -935,9 +935,9 @@ define i64 @test_cvttss2siq(float %a0, f<br>
; SKYLAKE-LABEL: test_cvttss2siq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvttss2si %xmm0, %rcx # sched: [7:1.00]<br>
-; SKYLAKE-NEXT: vcvttss2si (%rdi), %rax # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vcvttss2si (%rdi), %rax # sched: [11:1.00]<br>
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvttss2siq:<br>
; SKX: # BB#0:<br>
@@ -1000,8 +1000,8 @@ define <4 x float> @test_divps(<4 x floa<br>
; SKYLAKE-LABEL: test_divps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vdivps %xmm1, %xmm0, %xmm0 # sched: [11:1.00]<br>
-; SKYLAKE-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [11:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [17:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_divps:<br>
; SKX: # BB#0:<br>
@@ -1060,8 +1060,8 @@ define float @test_divss(float %a0, floa<br>
; SKYLAKE-LABEL: test_divss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vdivss %xmm1, %xmm0, %xmm0 # sched: [11:1.00]<br>
-; SKYLAKE-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [11:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [16:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_divss:<br>
; SKX: # BB#0:<br>
@@ -1120,8 +1120,8 @@ define void @test_ldmxcsr(i32 %a0) {<br>
; SKYLAKE-LABEL: test_ldmxcsr:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: movl %edi, -{{[0-9]+}}(%rsp) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vldmxcsr -{{[0-9]+}}(%rsp) # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vldmxcsr -{{[0-9]+}}(%rsp) # sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_ldmxcsr:<br>
; SKX: # BB#0:<br>
@@ -1182,8 +1182,8 @@ define <4 x float> @test_maxps(<4 x floa<br>
; SKYLAKE-LABEL: test_maxps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmaxps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vmaxps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmaxps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_maxps:<br>
; SKX: # BB#0:<br>
@@ -1243,8 +1243,8 @@ define <4 x float> @test_maxss(<4 x floa<br>
; SKYLAKE-LABEL: test_maxss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmaxss %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vmaxss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmaxss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_maxss:<br>
; SKX: # BB#0:<br>
@@ -1304,8 +1304,8 @@ define <4 x float> @test_minps(<4 x floa<br>
; SKYLAKE-LABEL: test_minps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vminps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vminps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vminps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_minps:<br>
; SKX: # BB#0:<br>
@@ -1365,8 +1365,8 @@ define <4 x float> @test_minss(<4 x floa<br>
; SKYLAKE-LABEL: test_minss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vminss %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vminss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vminss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_minss:<br>
; SKX: # BB#0:<br>
@@ -1430,10 +1430,10 @@ define void @test_movaps(<4 x float> *%a<br>
;<br>
; SKYLAKE-LABEL: test_movaps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovaps (%rdi), %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovaps (%rdi), %xmm0 # sched: [6:0.50]<br>
; SKYLAKE-NEXT: vaddps %xmm0, %xmm0, %xmm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovaps %xmm0, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movaps:<br>
; SKX: # BB#0:<br>
@@ -1498,7 +1498,7 @@ define <4 x float> @test_movhlps(<4 x fl<br>
; SKYLAKE-LABEL: test_movhlps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movhlps:<br>
; SKX: # BB#0:<br>
@@ -1560,10 +1560,10 @@ define void @test_movhps(<4 x float> %a0<br>
;<br>
; SKYLAKE-LABEL: test_movhps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [6:1.00]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vpextrq $1, %xmm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpextrq $1, %xmm0, (%rdi) # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movhps:<br>
; SKX: # BB#0:<br>
@@ -1632,7 +1632,7 @@ define <4 x float> @test_movlhps(<4 x fl<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] sched: [1:1.00]<br>
; SKYLAKE-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movlhps:<br>
; SKX: # BB#0:<br>
@@ -1694,10 +1694,10 @@ define void @test_movlps(<4 x float> %a0<br>
;<br>
; SKYLAKE-LABEL: test_movlps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [6:1.00]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovlps %xmm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movlps:<br>
; SKX: # BB#0:<br>
@@ -1760,7 +1760,7 @@ define i32 @test_movmskps(<4 x float> %a<br>
; SKYLAKE-LABEL: test_movmskps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovmskps %xmm0, %eax # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movmskps:<br>
; SKX: # BB#0:<br>
@@ -1816,7 +1816,7 @@ define void @test_movntps(<4 x float> %a<br>
; SKYLAKE-LABEL: test_movntps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovntps %xmm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movntps:<br>
; SKX: # BB#0:<br>
@@ -1874,10 +1874,10 @@ define void @test_movss_mem(float* %a0,<br>
;<br>
; SKYLAKE-LABEL: test_movss_mem:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero sched: [5:0.50]<br>
; SKYLAKE-NEXT: vaddss %xmm0, %xmm0, %xmm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovss %xmm0, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movss_mem:<br>
; SKX: # BB#0:<br>
@@ -1939,8 +1939,8 @@ define <4 x float> @test_movss_reg(<4 x<br>
;<br>
; SKYLAKE-LABEL: test_movss_reg:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movss_reg:<br>
; SKX: # BB#0:<br>
@@ -1998,10 +1998,10 @@ define void @test_movups(<4 x float> *%a<br>
;<br>
; SKYLAKE-LABEL: test_movups:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovups (%rdi), %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovups (%rdi), %xmm0 # sched: [6:0.50]<br>
; SKYLAKE-NEXT: vaddps %xmm0, %xmm0, %xmm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovups %xmm0, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movups:<br>
; SKX: # BB#0:<br>
@@ -2063,8 +2063,8 @@ define <4 x float> @test_mulps(<4 x floa<br>
; SKYLAKE-LABEL: test_mulps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmulps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vmulps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmulps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_mulps:<br>
; SKX: # BB#0:<br>
@@ -2123,8 +2123,8 @@ define float @test_mulss(float %a0, floa<br>
; SKYLAKE-LABEL: test_mulss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmulss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vmulss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmulss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_mulss:<br>
; SKX: # BB#0:<br>
@@ -2186,9 +2186,9 @@ define <4 x float> @test_orps(<4 x float<br>
;<br>
; SKYLAKE-LABEL: test_orps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vorps %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vorps (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vorps %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vorps (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_orps:<br>
; SKX: # BB#0:<br>
@@ -2251,8 +2251,8 @@ define void @test_prefetchnta(i8* %a0) {<br>
;<br>
; SKYLAKE-LABEL: test_prefetchnta:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: prefetchnta (%rdi) # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: prefetchnta (%rdi) # sched: [5:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_prefetchnta:<br>
; SKX: # BB#0:<br>
@@ -2314,9 +2314,9 @@ define <4 x float> @test_rcpps(<4 x floa<br>
; SKYLAKE-LABEL: test_rcpps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vrcpps %xmm0, %xmm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vrcpps (%rdi), %xmm1 # sched: [4:1.00]<br>
+; SKYLAKE-NEXT: vrcpps (%rdi), %xmm1 # sched: [10:1.00]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_rcpps:<br>
; SKX: # BB#0:<br>
@@ -2392,10 +2392,10 @@ define <4 x float> @test_rcpss(float %a0<br>
; SKYLAKE-LABEL: test_rcpss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vrcpss %xmm0, %xmm0, %xmm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:0.50]<br>
; SKYLAKE-NEXT: vrcpss %xmm1, %xmm1, %xmm1 # sched: [4:1.00]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_rcpss:<br>
; SKX: # BB#0:<br>
@@ -2471,9 +2471,9 @@ define <4 x float> @test_rsqrtps(<4 x fl<br>
; SKYLAKE-LABEL: test_rsqrtps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vrsqrtps %xmm0, %xmm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vrsqrtps (%rdi), %xmm1 # sched: [4:1.00]<br>
+; SKYLAKE-NEXT: vrsqrtps (%rdi), %xmm1 # sched: [10:1.00]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_rsqrtps:<br>
; SKX: # BB#0:<br>
@@ -2549,10 +2549,10 @@ define <4 x float> @test_rsqrtss(float %<br>
; SKYLAKE-LABEL: test_rsqrtss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vrsqrtss %xmm0, %xmm0, %xmm0 # sched: [4:1.00]<br>
-; SKYLAKE-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:0.50]<br>
; SKYLAKE-NEXT: vrsqrtss %xmm1, %xmm1, %xmm1 # sched: [4:1.00]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_rsqrtss:<br>
; SKX: # BB#0:<br>
@@ -2621,8 +2621,8 @@ define void @test_sfence() {<br>
;<br>
; SKYLAKE-LABEL: test_sfence:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: sfence # sched: [1:0.33]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: sfence # sched: [2:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_sfence:<br>
; SKX: # BB#0:<br>
@@ -2681,8 +2681,8 @@ define <4 x float> @test_shufps(<4 x flo<br>
; SKYLAKE-LABEL: test_shufps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,3],mem[0,0] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,3],mem[0,0] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_shufps:<br>
; SKX: # BB#0:<br>
@@ -2747,9 +2747,9 @@ define <4 x float> @test_sqrtps(<4 x flo<br>
; SKYLAKE-LABEL: test_sqrtps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vsqrtps %xmm0, %xmm0 # sched: [12:1.00]<br>
-; SKYLAKE-NEXT: vsqrtps (%rdi), %xmm1 # sched: [12:1.00]<br>
+; SKYLAKE-NEXT: vsqrtps (%rdi), %xmm1 # sched: [18:1.00]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_sqrtps:<br>
; SKX: # BB#0:<br>
@@ -2825,10 +2825,10 @@ define <4 x float> @test_sqrtss(<4 x flo<br>
; SKYLAKE-LABEL: test_sqrtss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [12:1.00]<br>
-; SKYLAKE-NEXT: vmovaps (%rdi), %xmm1 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovaps (%rdi), %xmm1 # sched: [6:0.50]<br>
; SKYLAKE-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [12:1.00]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_sqrtss:<br>
; SKX: # BB#0:<br>
@@ -2894,9 +2894,9 @@ define i32 @test_stmxcsr() {<br>
;<br>
; SKYLAKE-LABEL: test_stmxcsr:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vstmxcsr -{{[0-9]+}}(%rsp) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: movl -{{[0-9]+}}(%rsp), %eax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vstmxcsr -{{[0-9]+}}(%rsp) # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: movl -{{[0-9]+}}(%rsp), %eax # sched: [5:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_stmxcsr:<br>
; SKX: # BB#0:<br>
@@ -2957,8 +2957,8 @@ define <4 x float> @test_subps(<4 x floa<br>
; SKYLAKE-LABEL: test_subps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vsubps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vsubps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vsubps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_subps:<br>
; SKX: # BB#0:<br>
@@ -3017,8 +3017,8 @@ define float @test_subss(float %a0, floa<br>
; SKYLAKE-LABEL: test_subss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vsubss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vsubss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vsubss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_subss:<br>
; SKX: # BB#0:<br>
@@ -3117,16 +3117,16 @@ define i32 @test_ucomiss(<4 x float> %a0<br>
; SKYLAKE-LABEL: test_ucomiss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vucomiss %xmm1, %xmm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: sete %cl # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: sete %cl # sched: [1:0.50]<br>
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]<br>
; SKYLAKE-NEXT: vucomiss (%rdi), %xmm0 # sched: [8:1.00]<br>
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: sete %dl # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: sete %dl # sched: [1:0.50]<br>
; SKYLAKE-NEXT: andb %al, %dl # sched: [1:0.25]<br>
; SKYLAKE-NEXT: orb %cl, %dl # sched: [1:0.25]<br>
; SKYLAKE-NEXT: movzbl %dl, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_ucomiss:<br>
; SKX: # BB#0:<br>
@@ -3215,8 +3215,8 @@ define <4 x float> @test_unpckhps(<4 x f<br>
; SKYLAKE-LABEL: test_unpckhps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[<wbr>3] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],mem[2],xmm0[3],mem[3] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],mem[2],xmm0[3],mem[3] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_unpckhps:<br>
; SKX: # BB#0:<br>
@@ -3279,8 +3279,8 @@ define <4 x float> @test_unpcklps(<4 x f<br>
; SKYLAKE-LABEL: test_unpcklps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_unpcklps:<br>
; SKX: # BB#0:<br>
@@ -3342,9 +3342,9 @@ define <4 x float> @test_xorps(<4 x floa<br>
;<br>
; SKYLAKE-LABEL: test_xorps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vxorps %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vxorps (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vxorps %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vxorps (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_xorps:<br>
; SKX: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>sse2-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/sse2-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>sse2-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>sse2-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -44,8 +44,8 @@ define <2 x double> @test_addpd(<2 x dou<br>
; SKYLAKE-LABEL: test_addpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vaddpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaddpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_addpd:<br>
; SKX: # BB#0:<br>
@@ -104,8 +104,8 @@ define double @test_addsd(double %a0, do<br>
; SKYLAKE-LABEL: test_addsd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vaddsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaddsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_addsd:<br>
; SKX: # BB#0:<br>
@@ -168,10 +168,10 @@ define <2 x double> @test_andpd(<2 x dou<br>
;<br>
; SKYLAKE-LABEL: test_andpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vandpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vandpd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vandpd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vandpd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_andpd:<br>
; SKX: # BB#0:<br>
@@ -242,10 +242,10 @@ define <2 x double> @test_andnotpd(<2 x<br>
;<br>
; SKYLAKE-LABEL: test_andnotpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vandnpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vandnpd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vandnpd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vandnpd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_andnotpd:<br>
; SKX: # BB#0:<br>
@@ -319,9 +319,9 @@ define <2 x double> @test_cmppd(<2 x dou<br>
; SKYLAKE-LABEL: test_cmppd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm1 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vcmpeqpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vorpd %xmm0, %xmm1, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vcmpeqpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: vorpd %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cmppd:<br>
; SKX: # BB#0:<br>
@@ -388,7 +388,7 @@ define double @test_cmpsd(double %a0, do<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br>
; SKYLAKE-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cmpsd:<br>
; SKX: # BB#0:<br>
@@ -492,16 +492,16 @@ define i32 @test_comisd(<2 x double> %a0<br>
; SKYLAKE-LABEL: test_comisd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcomisd %xmm1, %xmm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: sete %cl # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: sete %cl # sched: [1:0.50]<br>
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]<br>
; SKYLAKE-NEXT: vcomisd (%rdi), %xmm0 # sched: [8:1.00]<br>
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: sete %dl # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: sete %dl # sched: [1:0.50]<br>
; SKYLAKE-NEXT: andb %al, %dl # sched: [1:0.25]<br>
; SKYLAKE-NEXT: orb %cl, %dl # sched: [1:0.25]<br>
; SKYLAKE-NEXT: movzbl %dl, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_comisd:<br>
; SKX: # BB#0:<br>
@@ -591,9 +591,9 @@ define <2 x double> @test_cvtdq2pd(<4 x<br>
; SKYLAKE-LABEL: test_cvtdq2pd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtdq2pd %xmm0, %xmm0 # sched: [5:1.00]<br>
-; SKYLAKE-NEXT: vcvtdq2pd (%rdi), %xmm1 # sched: [5:1.00]<br>
+; SKYLAKE-NEXT: vcvtdq2pd (%rdi), %xmm1 # sched: [11:1.00]<br>
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtdq2pd:<br>
; SKX: # BB#0:<br>
@@ -664,9 +664,9 @@ define <4 x float> @test_cvtdq2ps(<4 x i<br>
; SKYLAKE-LABEL: test_cvtdq2ps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtdq2ps %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vcvtdq2ps (%rdi), %xmm1 # sched: [4:0.50]<br>
+; SKYLAKE-NEXT: vcvtdq2ps (%rdi), %xmm1 # sched: [10:0.50]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtdq2ps:<br>
; SKX: # BB#0:<br>
@@ -736,8 +736,8 @@ define <4 x i32> @test_cvtpd2dq(<2 x dou<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtpd2dq %xmm0, %xmm0 # sched: [5:1.00]<br>
; SKYLAKE-NEXT: vcvtpd2dqx (%rdi), %xmm1 # sched: [8:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtpd2dq:<br>
; SKX: # BB#0:<br>
@@ -809,7 +809,7 @@ define <4 x float> @test_cvtpd2ps(<2 x d<br>
; SKYLAKE-NEXT: vcvtpd2ps %xmm0, %xmm0 # sched: [5:1.00]<br>
; SKYLAKE-NEXT: vcvtpd2psx (%rdi), %xmm1 # sched: [8:1.00]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtpd2ps:<br>
; SKX: # BB#0:<br>
@@ -879,9 +879,9 @@ define <4 x i32> @test_cvtps2dq(<4 x flo<br>
; SKYLAKE-LABEL: test_cvtps2dq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtps2dq %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vcvtps2dq (%rdi), %xmm1 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vcvtps2dq (%rdi), %xmm1 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtps2dq:<br>
; SKX: # BB#0:<br>
@@ -951,9 +951,9 @@ define <2 x double> @test_cvtps2pd(<4 x<br>
; SKYLAKE-LABEL: test_cvtps2pd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtps2pd %xmm0, %xmm0 # sched: [5:1.00]<br>
-; SKYLAKE-NEXT: vcvtps2pd (%rdi), %xmm1 # sched: [4:0.50]<br>
+; SKYLAKE-NEXT: vcvtps2pd (%rdi), %xmm1 # sched: [9:0.50]<br>
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtps2pd:<br>
; SKX: # BB#0:<br>
@@ -1023,9 +1023,9 @@ define i32 @test_cvtsd2si(double %a0, do<br>
; SKYLAKE-LABEL: test_cvtsd2si:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtsd2si %xmm0, %ecx # sched: [6:1.00]<br>
-; SKYLAKE-NEXT: vcvtsd2si (%rdi), %eax # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vcvtsd2si (%rdi), %eax # sched: [11:1.00]<br>
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtsd2si:<br>
; SKX: # BB#0:<br>
@@ -1096,9 +1096,9 @@ define i64 @test_cvtsd2siq(double %a0, d<br>
; SKYLAKE-LABEL: test_cvtsd2siq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtsd2si %xmm0, %rcx # sched: [6:1.00]<br>
-; SKYLAKE-NEXT: vcvtsd2si (%rdi), %rax # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vcvtsd2si (%rdi), %rax # sched: [11:1.00]<br>
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtsd2siq:<br>
; SKX: # BB#0:<br>
@@ -1175,10 +1175,10 @@ define float @test_cvtsd2ss(double %a0,<br>
; SKYLAKE-LABEL: test_cvtsd2ss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0 # sched: [5:1.00]<br>
-; SKYLAKE-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [5:0.50]<br>
; SKYLAKE-NEXT: vcvtsd2ss %xmm1, %xmm1, %xmm1 # sched: [5:1.00]<br>
; SKYLAKE-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtsd2ss:<br>
; SKX: # BB#0:<br>
@@ -1251,7 +1251,7 @@ define double @test_cvtsi2sd(i32 %a0, i3<br>
; SKYLAKE-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [5:1.00]<br>
; SKYLAKE-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]<br>
; SKYLAKE-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtsi2sd:<br>
; SKX: # BB#0:<br>
@@ -1321,7 +1321,7 @@ define double @test_cvtsi2sdq(i64 %a0, i<br>
; SKYLAKE-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [5:1.00]<br>
; SKYLAKE-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]<br>
; SKYLAKE-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtsi2sdq:<br>
; SKX: # BB#0:<br>
@@ -1397,10 +1397,10 @@ define double @test_cvtss2sd(float %a0,<br>
; SKYLAKE-LABEL: test_cvtss2sd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0 # sched: [5:1.00]<br>
-; SKYLAKE-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:0.50]<br>
; SKYLAKE-NEXT: vcvtss2sd %xmm1, %xmm1, %xmm1 # sched: [5:1.00]<br>
; SKYLAKE-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvtss2sd:<br>
; SKX: # BB#0:<br>
@@ -1473,8 +1473,8 @@ define <4 x i32> @test_cvttpd2dq(<2 x do<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvttpd2dq %xmm0, %xmm0 # sched: [5:1.00]<br>
; SKYLAKE-NEXT: vcvttpd2dqx (%rdi), %xmm1 # sched: [8:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvttpd2dq:<br>
; SKX: # BB#0:<br>
@@ -1545,9 +1545,9 @@ define <4 x i32> @test_cvttps2dq(<4 x fl<br>
; SKYLAKE-LABEL: test_cvttps2dq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvttps2dq %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vcvttps2dq (%rdi), %xmm1 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vcvttps2dq (%rdi), %xmm1 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvttps2dq:<br>
; SKX: # BB#0:<br>
@@ -1615,9 +1615,9 @@ define i32 @test_cvttsd2si(double %a0, d<br>
; SKYLAKE-LABEL: test_cvttsd2si:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvttsd2si %xmm0, %ecx # sched: [6:1.00]<br>
-; SKYLAKE-NEXT: vcvttsd2si (%rdi), %eax # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vcvttsd2si (%rdi), %eax # sched: [11:1.00]<br>
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvttsd2si:<br>
; SKX: # BB#0:<br>
@@ -1685,9 +1685,9 @@ define i64 @test_cvttsd2siq(double %a0,<br>
; SKYLAKE-LABEL: test_cvttsd2siq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vcvttsd2si %xmm0, %rcx # sched: [6:1.00]<br>
-; SKYLAKE-NEXT: vcvttsd2si (%rdi), %rax # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vcvttsd2si (%rdi), %rax # sched: [11:1.00]<br>
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_cvttsd2siq:<br>
; SKX: # BB#0:<br>
@@ -1750,8 +1750,8 @@ define <2 x double> @test_divpd(<2 x dou<br>
; SKYLAKE-LABEL: test_divpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]<br>
-; SKYLAKE-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [14:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [20:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_divpd:<br>
; SKX: # BB#0:<br>
@@ -1810,8 +1810,8 @@ define double @test_divsd(double %a0, do<br>
; SKYLAKE-LABEL: test_divsd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]<br>
-; SKYLAKE-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [14:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [19:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_divsd:<br>
; SKX: # BB#0:<br>
@@ -1871,7 +1871,7 @@ define void @test_lfence() {<br>
; SKYLAKE-LABEL: test_lfence:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: lfence # sched: [2:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_lfence:<br>
; SKX: # BB#0:<br>
@@ -1926,8 +1926,8 @@ define void @test_mfence() {<br>
;<br>
; SKYLAKE-LABEL: test_mfence:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: mfence # sched: [2:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: mfence # sched: [3:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_mfence:<br>
; SKX: # BB#0:<br>
@@ -1980,8 +1980,8 @@ define void @test_maskmovdqu(<16 x i8> %<br>
;<br>
; SKYLAKE-LABEL: test_maskmovdqu:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_maskmovdqu:<br>
; SKX: # BB#0:<br>
@@ -2036,8 +2036,8 @@ define <2 x double> @test_maxpd(<2 x dou<br>
; SKYLAKE-LABEL: test_maxpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vmaxpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmaxpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_maxpd:<br>
; SKX: # BB#0:<br>
@@ -2097,8 +2097,8 @@ define <2 x double> @test_maxsd(<2 x dou<br>
; SKYLAKE-LABEL: test_maxsd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vmaxsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmaxsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_maxsd:<br>
; SKX: # BB#0:<br>
@@ -2158,8 +2158,8 @@ define <2 x double> @test_minpd(<2 x dou<br>
; SKYLAKE-LABEL: test_minpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vminpd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vminpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vminpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_minpd:<br>
; SKX: # BB#0:<br>
@@ -2219,8 +2219,8 @@ define <2 x double> @test_minsd(<2 x dou<br>
; SKYLAKE-LABEL: test_minsd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vminsd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vminsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vminsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_minsd:<br>
; SKX: # BB#0:<br>
@@ -2284,10 +2284,10 @@ define void @test_movapd(<2 x double> *%<br>
;<br>
; SKYLAKE-LABEL: test_movapd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovapd (%rdi), %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovapd (%rdi), %xmm0 # sched: [6:0.50]<br>
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovapd %xmm0, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movapd:<br>
; SKX: # BB#0:<br>
@@ -2353,10 +2353,10 @@ define void @test_movdqa(<2 x i64> *%a0,<br>
;<br>
; SKYLAKE-LABEL: test_movdqa:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovdqa (%rdi), %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovdqa (%rdi), %xmm0 # sched: [6:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.33]<br>
; SKYLAKE-NEXT: vmovdqa %xmm0, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movdqa:<br>
; SKX: # BB#0:<br>
@@ -2422,10 +2422,10 @@ define void @test_movdqu(<2 x i64> *%a0,<br>
;<br>
; SKYLAKE-LABEL: test_movdqu:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovdqu (%rdi), %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovdqu (%rdi), %xmm0 # sched: [6:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.33]<br>
; SKYLAKE-NEXT: vmovdqu %xmm0, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movdqu:<br>
; SKX: # BB#0:<br>
@@ -2507,12 +2507,12 @@ define i32 @test_movd(<4 x i32> %a0, i32<br>
; SKYLAKE-LABEL: test_movd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovd %edi, %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddd %xmm2, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [5:0.50]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm1 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpaddd %xmm2, %xmm0, %xmm0 # sched: [1:0.33]<br>
; SKYLAKE-NEXT: vmovd %xmm0, %eax # sched: [2:1.00]<br>
; SKYLAKE-NEXT: vmovd %xmm1, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movd:<br>
; SKX: # BB#0:<br>
@@ -2608,12 +2608,12 @@ define i64 @test_movd_64(<2 x i64> %a0,<br>
; SKYLAKE-LABEL: test_movd_64:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovq %rdi, %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %xmm2, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero sched: [5:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm1 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpaddq %xmm2, %xmm0, %xmm0 # sched: [1:0.33]<br>
; SKYLAKE-NEXT: vmovq %xmm0, %rax # sched: [2:1.00]<br>
; SKYLAKE-NEXT: vmovq %xmm1, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movd_64:<br>
; SKX: # BB#0:<br>
@@ -2693,10 +2693,10 @@ define void @test_movhpd(<2 x double> %a<br>
;<br>
; SKYLAKE-LABEL: test_movhpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [6:1.00]<br>
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovhpd %xmm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movhpd:<br>
; SKX: # BB#0:<br>
@@ -2765,10 +2765,10 @@ define void @test_movlpd(<2 x double> %a<br>
;<br>
; SKYLAKE-LABEL: test_movlpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [6:1.00]<br>
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovlpd %xmm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movlpd:<br>
; SKX: # BB#0:<br>
@@ -2830,7 +2830,7 @@ define i32 @test_movmskpd(<2 x double> %<br>
; SKYLAKE-LABEL: test_movmskpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovmskpd %xmm0, %eax # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movmskpd:<br>
; SKX: # BB#0:<br>
@@ -2886,9 +2886,9 @@ define void @test_movntdqa(<2 x i64> %a0<br>
;<br>
; SKYLAKE-LABEL: test_movntdqa:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.33]<br>
; SKYLAKE-NEXT: vmovntdq %xmm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movntdqa:<br>
; SKX: # BB#0:<br>
@@ -2947,7 +2947,7 @@ define void @test_movntpd(<2 x double> %<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovntpd %xmm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movntpd:<br>
; SKX: # BB#0:<br>
@@ -3009,10 +3009,10 @@ define <2 x i64> @test_movq_mem(<2 x i64<br>
;<br>
; SKYLAKE-LABEL: test_movq_mem:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero sched: [5:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
; SKYLAKE-NEXT: vmovq %xmm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movq_mem:<br>
; SKX: # BB#0:<br>
@@ -3077,9 +3077,9 @@ define <2 x i64> @test_movq_reg(<2 x i64<br>
;<br>
; SKYLAKE-LABEL: test_movq_reg:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %xmm0, %xmm1, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpaddq %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movq_reg:<br>
; SKX: # BB#0:<br>
@@ -3141,10 +3141,10 @@ define void @test_movsd_mem(double* %a0,<br>
;<br>
; SKYLAKE-LABEL: test_movsd_mem:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero sched: [5:0.50]<br>
; SKYLAKE-NEXT: vaddsd %xmm0, %xmm0, %xmm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovsd %xmm0, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movsd_mem:<br>
; SKX: # BB#0:<br>
@@ -3208,7 +3208,7 @@ define <2 x double> @test_movsd_reg(<2 x<br>
; SKYLAKE-LABEL: test_movsd_reg:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movsd_reg:<br>
; SKX: # BB#0:<br>
@@ -3266,10 +3266,10 @@ define void @test_movupd(<2 x double> *%<br>
;<br>
; SKYLAKE-LABEL: test_movupd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovupd (%rdi), %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovupd (%rdi), %xmm0 # sched: [6:0.50]<br>
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [4:0.50]<br>
; SKYLAKE-NEXT: vmovupd %xmm0, (%rsi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movupd:<br>
; SKX: # BB#0:<br>
@@ -3331,8 +3331,8 @@ define <2 x double> @test_mulpd(<2 x dou<br>
; SKYLAKE-LABEL: test_mulpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmulpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vmulpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmulpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_mulpd:<br>
; SKX: # BB#0:<br>
@@ -3391,8 +3391,8 @@ define double @test_mulsd(double %a0, do<br>
; SKYLAKE-LABEL: test_mulsd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmulsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vmulsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmulsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_mulsd:<br>
; SKX: # BB#0:<br>
@@ -3455,10 +3455,10 @@ define <2 x double> @test_orpd(<2 x doub<br>
;<br>
; SKYLAKE-LABEL: test_orpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vorpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vorpd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vorpd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vorpd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_orpd:<br>
; SKX: # BB#0:<br>
@@ -3529,8 +3529,8 @@ define <8 x i16> @test_packssdw(<4 x i32<br>
; SKYLAKE-LABEL: test_packssdw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpackssdw (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpackssdw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_packssdw:<br>
; SKX: # BB#0:<br>
@@ -3595,8 +3595,8 @@ define <16 x i8> @test_packsswb(<8 x i16<br>
; SKYLAKE-LABEL: test_packsswb:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpacksswb (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpacksswb (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_packsswb:<br>
; SKX: # BB#0:<br>
@@ -3661,8 +3661,8 @@ define <16 x i8> @test_packuswb(<8 x i16<br>
; SKYLAKE-LABEL: test_packuswb:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpackuswb (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpackuswb (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_packuswb:<br>
; SKX: # BB#0:<br>
@@ -3726,9 +3726,9 @@ define <16 x i8> @test_paddb(<16 x i8> %<br>
;<br>
; SKYLAKE-LABEL: test_paddb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpaddb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddb:<br>
; SKX: # BB#0:<br>
@@ -3790,9 +3790,9 @@ define <4 x i32> @test_paddd(<4 x i32> %<br>
;<br>
; SKYLAKE-LABEL: test_paddd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpaddd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddd:<br>
; SKX: # BB#0:<br>
@@ -3850,9 +3850,9 @@ define <2 x i64> @test_paddq(<2 x i64> %<br>
;<br>
; SKYLAKE-LABEL: test_paddq:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpaddq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddq:<br>
; SKX: # BB#0:<br>
@@ -3914,9 +3914,9 @@ define <16 x i8> @test_paddsb(<16 x i8><br>
;<br>
; SKYLAKE-LABEL: test_paddsb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddsb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpaddsb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddsb:<br>
; SKX: # BB#0:<br>
@@ -3979,9 +3979,9 @@ define <8 x i16> @test_paddsw(<8 x i16><br>
;<br>
; SKYLAKE-LABEL: test_paddsw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpaddsw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddsw:<br>
; SKX: # BB#0:<br>
@@ -4044,9 +4044,9 @@ define <16 x i8> @test_paddusb(<16 x i8><br>
;<br>
; SKYLAKE-LABEL: test_paddusb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddusb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddusb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpaddusb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddusb:<br>
; SKX: # BB#0:<br>
@@ -4109,9 +4109,9 @@ define <8 x i16> @test_paddusw(<8 x i16><br>
;<br>
; SKYLAKE-LABEL: test_paddusw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddusw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddusw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpaddusw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddusw:<br>
; SKX: # BB#0:<br>
@@ -4174,9 +4174,9 @@ define <8 x i16> @test_paddw(<8 x i16> %<br>
;<br>
; SKYLAKE-LABEL: test_paddw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpaddw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_paddw:<br>
; SKX: # BB#0:<br>
@@ -4239,10 +4239,10 @@ define <2 x i64> @test_pand(<2 x i64> %a<br>
;<br>
; SKYLAKE-LABEL: test_pand:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpand %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpand (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpand %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpand (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pand:<br>
; SKX: # BB#0:<br>
@@ -4315,10 +4315,10 @@ define <2 x i64> @test_pandn(<2 x i64> %<br>
;<br>
; SKYLAKE-LABEL: test_pandn:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpandn %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpandn (%rdi), %xmm0, %xmm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpandn %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpandn (%rdi), %xmm0, %xmm1 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pandn:<br>
; SKX: # BB#0:<br>
@@ -4386,9 +4386,9 @@ define <16 x i8> @test_pavgb(<16 x i8> %<br>
;<br>
; SKYLAKE-LABEL: test_pavgb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpavgb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpavgb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pavgb:<br>
; SKX: # BB#0:<br>
@@ -4460,9 +4460,9 @@ define <8 x i16> @test_pavgw(<8 x i16> %<br>
;<br>
; SKYLAKE-LABEL: test_pavgw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpavgw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpavgw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpavgw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpavgw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pavgw:<br>
; SKX: # BB#0:<br>
@@ -4537,10 +4537,10 @@ define <16 x i8> @test_pcmpeqb(<16 x i8><br>
;<br>
; SKYLAKE-LABEL: test_pcmpeqb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpeqb:<br>
; SKX: # BB#0:<br>
@@ -4611,10 +4611,10 @@ define <4 x i32> @test_pcmpeqd(<4 x i32><br>
;<br>
; SKYLAKE-LABEL: test_pcmpeqd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpeqd:<br>
; SKX: # BB#0:<br>
@@ -4685,10 +4685,10 @@ define <8 x i16> @test_pcmpeqw(<8 x i16><br>
;<br>
; SKYLAKE-LABEL: test_pcmpeqw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpeqw:<br>
; SKX: # BB#0:<br>
@@ -4760,10 +4760,10 @@ define <16 x i8> @test_pcmpgtb(<16 x i8><br>
;<br>
; SKYLAKE-LABEL: test_pcmpgtb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpgtb:<br>
; SKX: # BB#0:<br>
@@ -4835,10 +4835,10 @@ define <4 x i32> @test_pcmpgtd(<4 x i32><br>
;<br>
; SKYLAKE-LABEL: test_pcmpgtd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpgtd:<br>
; SKX: # BB#0:<br>
@@ -4910,10 +4910,10 @@ define <8 x i16> @test_pcmpgtw(<8 x i16><br>
;<br>
; SKYLAKE-LABEL: test_pcmpgtw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpgtw:<br>
; SKX: # BB#0:<br>
@@ -4979,7 +4979,7 @@ define i16 @test_pextrw(<8 x i16> %a0) {<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpextrw $6, %xmm0, %eax # sched: [3:1.00]<br>
; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill><br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pextrw:<br>
; SKX: # BB#0:<br>
@@ -5040,8 +5040,8 @@ define <8 x i16> @test_pinsrw(<8 x i16><br>
; SKYLAKE-LABEL: test_pinsrw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [2:2.00]<br>
-; SKYLAKE-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pinsrw:<br>
; SKX: # BB#0:<br>
@@ -5108,8 +5108,8 @@ define <4 x i32> @test_pmaddwd(<8 x i16><br>
; SKYLAKE-LABEL: test_pmaddwd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaddwd:<br>
; SKX: # BB#0:<br>
@@ -5173,9 +5173,9 @@ define <8 x i16> @test_pmaxsw(<8 x i16><br>
;<br>
; SKYLAKE-LABEL: test_pmaxsw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaxsw:<br>
; SKX: # BB#0:<br>
@@ -5238,9 +5238,9 @@ define <16 x i8> @test_pmaxub(<16 x i8><br>
;<br>
; SKYLAKE-LABEL: test_pmaxub:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmaxub (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpmaxub (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaxub:<br>
; SKX: # BB#0:<br>
@@ -5303,9 +5303,9 @@ define <8 x i16> @test_pminsw(<8 x i16><br>
;<br>
; SKYLAKE-LABEL: test_pminsw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpminsw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpminsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpminsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpminsw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pminsw:<br>
; SKX: # BB#0:<br>
@@ -5368,9 +5368,9 @@ define <16 x i8> @test_pminub(<16 x i8><br>
;<br>
; SKYLAKE-LABEL: test_pminub:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpminub %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpminub (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpminub %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpminub (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pminub:<br>
; SKX: # BB#0:<br>
@@ -5427,7 +5427,7 @@ define i32 @test_pmovmskb(<16 x i8> %a0)<br>
; SKYLAKE-LABEL: test_pmovmskb:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovmskb %xmm0, %eax # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovmskb:<br>
; SKX: # BB#0:<br>
@@ -5482,8 +5482,8 @@ define <8 x i16> @test_pmulhuw(<8 x i16><br>
; SKYLAKE-LABEL: test_pmulhuw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmulhuw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmulhuw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmulhuw:<br>
; SKX: # BB#0:<br>
@@ -5543,8 +5543,8 @@ define <8 x i16> @test_pmulhw(<8 x i16><br>
; SKYLAKE-LABEL: test_pmulhw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmulhw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmulhw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmulhw:<br>
; SKX: # BB#0:<br>
@@ -5604,8 +5604,8 @@ define <8 x i16> @test_pmullw(<8 x i16><br>
; SKYLAKE-LABEL: test_pmullw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmullw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmullw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmullw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmullw:<br>
; SKX: # BB#0:<br>
@@ -5672,8 +5672,8 @@ define <2 x i64> @test_pmuludq(<4 x i32><br>
; SKYLAKE-LABEL: test_pmuludq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmuludq (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmuludq (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmuludq:<br>
; SKX: # BB#0:<br>
@@ -5738,10 +5738,10 @@ define <2 x i64> @test_por(<2 x i64> %a0<br>
;<br>
; SKYLAKE-LABEL: test_por:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpor (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_por:<br>
; SKX: # BB#0:<br>
@@ -5812,8 +5812,8 @@ define <2 x i64> @test_psadbw(<16 x i8><br>
; SKYLAKE-LABEL: test_psadbw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpsadbw (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsadbw (%rdi), %xmm0, %xmm0 # sched: [9:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psadbw:<br>
; SKX: # BB#0:<br>
@@ -5881,9 +5881,9 @@ define <4 x i32> @test_pshufd(<4 x i32><br>
; SKYLAKE-LABEL: test_pshufd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpshufd {{.*#+}} xmm1 = mem[3,2,1,0] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpshufd {{.*#+}} xmm1 = mem[3,2,1,0] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pshufd:<br>
; SKX: # BB#0:<br>
@@ -5953,9 +5953,9 @@ define <8 x i16> @test_pshufhw(<8 x i16><br>
; SKYLAKE-LABEL: test_pshufhw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpshufhw {{.*#+}} xmm1 = mem[0,1,2,3,7,6,5,4] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpshufhw {{.*#+}} xmm1 = mem[0,1,2,3,7,6,5,4] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pshufhw:<br>
; SKX: # BB#0:<br>
@@ -6025,9 +6025,9 @@ define <8 x i16> @test_pshuflw(<8 x i16><br>
; SKYLAKE-LABEL: test_pshuflw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpshuflw {{.*#+}} xmm1 = mem[3,2,1,0,4,5,6,7] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpshuflw {{.*#+}} xmm1 = mem[3,2,1,0,4,5,6,7] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pshuflw:<br>
; SKX: # BB#0:<br>
@@ -6095,9 +6095,9 @@ define <4 x i32> @test_pslld(<4 x i32> %<br>
; SKYLAKE-LABEL: test_pslld:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpslld %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: vpslld (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpslld $2, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpslld (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpslld $2, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pslld:<br>
; SKX: # BB#0:<br>
@@ -6163,7 +6163,7 @@ define <4 x i32> @test_pslldq(<4 x i32><br>
; SKYLAKE-LABEL: test_pslldq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,<wbr>2,3,4,5,6,7,8,9,10,11] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pslldq:<br>
; SKX: # BB#0:<br>
@@ -6222,9 +6222,9 @@ define <2 x i64> @test_psllq(<2 x i64> %<br>
; SKYLAKE-LABEL: test_psllq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsllq %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: vpsllq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsllq $2, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsllq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpsllq $2, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psllq:<br>
; SKX: # BB#0:<br>
@@ -6294,9 +6294,9 @@ define <8 x i16> @test_psllw(<8 x i16> %<br>
; SKYLAKE-LABEL: test_psllw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsllw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: vpsllw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsllw $2, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsllw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpsllw $2, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psllw:<br>
; SKX: # BB#0:<br>
@@ -6366,9 +6366,9 @@ define <4 x i32> @test_psrad(<4 x i32> %<br>
; SKYLAKE-LABEL: test_psrad:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsrad %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: vpsrad (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsrad $2, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsrad (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpsrad $2, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrad:<br>
; SKX: # BB#0:<br>
@@ -6438,9 +6438,9 @@ define <8 x i16> @test_psraw(<8 x i16> %<br>
; SKYLAKE-LABEL: test_psraw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsraw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: vpsraw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsraw $2, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsraw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpsraw $2, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psraw:<br>
; SKX: # BB#0:<br>
@@ -6510,9 +6510,9 @@ define <4 x i32> @test_psrld(<4 x i32> %<br>
; SKYLAKE-LABEL: test_psrld:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsrld %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: vpsrld (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsrld $2, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsrld (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpsrld $2, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrld:<br>
; SKX: # BB#0:<br>
@@ -6578,7 +6578,7 @@ define <4 x i32> @test_psrldq(<4 x i32><br>
; SKYLAKE-LABEL: test_psrldq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[4,5,6,7,8,9,10,11,12,13,<wbr>14,15],zero,zero,zero,zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrldq:<br>
; SKX: # BB#0:<br>
@@ -6637,9 +6637,9 @@ define <2 x i64> @test_psrlq(<2 x i64> %<br>
; SKYLAKE-LABEL: test_psrlq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: vpsrlq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsrlq $2, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsrlq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpsrlq $2, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrlq:<br>
; SKX: # BB#0:<br>
@@ -6709,9 +6709,9 @@ define <8 x i16> @test_psrlw(<8 x i16> %<br>
; SKYLAKE-LABEL: test_psrlw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]<br>
-; SKYLAKE-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsrlw $2, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpsrlw $2, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psrlw:<br>
; SKX: # BB#0:<br>
@@ -6779,9 +6779,9 @@ define <16 x i8> @test_psubb(<16 x i8> %<br>
;<br>
; SKYLAKE-LABEL: test_psubb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsubb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubb %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpsubb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubb:<br>
; SKX: # BB#0:<br>
@@ -6843,9 +6843,9 @@ define <4 x i32> @test_psubd(<4 x i32> %<br>
;<br>
; SKYLAKE-LABEL: test_psubd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsubd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpsubd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubd:<br>
; SKX: # BB#0:<br>
@@ -6903,9 +6903,9 @@ define <2 x i64> @test_psubq(<2 x i64> %<br>
;<br>
; SKYLAKE-LABEL: test_psubq:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsubq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpsubq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubq:<br>
; SKX: # BB#0:<br>
@@ -6967,9 +6967,9 @@ define <16 x i8> @test_psubsb(<16 x i8><br>
;<br>
; SKYLAKE-LABEL: test_psubsb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubsb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsubsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsubsb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubsb:<br>
; SKX: # BB#0:<br>
@@ -7032,9 +7032,9 @@ define <8 x i16> @test_psubsw(<8 x i16><br>
;<br>
; SKYLAKE-LABEL: test_psubsw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubsw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsubsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsubsw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubsw:<br>
; SKX: # BB#0:<br>
@@ -7097,9 +7097,9 @@ define <16 x i8> @test_psubusb(<16 x i8><br>
;<br>
; SKYLAKE-LABEL: test_psubusb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsubusb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsubusb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubusb:<br>
; SKX: # BB#0:<br>
@@ -7162,9 +7162,9 @@ define <8 x i16> @test_psubusw(<8 x i16><br>
;<br>
; SKYLAKE-LABEL: test_psubusw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsubusw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsubusw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubusw:<br>
; SKX: # BB#0:<br>
@@ -7227,9 +7227,9 @@ define <8 x i16> @test_psubw(<8 x i16> %<br>
;<br>
; SKYLAKE-LABEL: test_psubw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsubw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpsubw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsubw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpsubw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psubw:<br>
; SKX: # BB#0:<br>
@@ -7292,8 +7292,8 @@ define <16 x i8> @test_punpckhbw(<16 x i<br>
; SKYLAKE-LABEL: test_punpckhbw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[<wbr>9],xmm0[10],xmm1[10],xmm0[11],<wbr>xmm1[11],xmm0[12],xmm1[12],<wbr>xmm0[13],xmm1[13],xmm0[14],<wbr>xmm1[14],xmm0[15],xmm1[15] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],mem[8],xmm0[9],mem[9],<wbr>xmm0[10],mem[10],xmm0[11],mem[<wbr>11],xmm0[12],mem[12],xmm0[13],<wbr>mem[13],xmm0[14],mem[14],xmm0[<wbr>15],mem[15] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],mem[8],xmm0[9],mem[9],<wbr>xmm0[10],mem[10],xmm0[11],mem[<wbr>11],xmm0[12],mem[12],xmm0[13],<wbr>mem[13],xmm0[14],mem[14],xmm0[<wbr>15],mem[15] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpckhbw:<br>
; SKX: # BB#0:<br>
@@ -7359,9 +7359,9 @@ define <4 x i32> @test_punpckhdq(<4 x i3<br>
; SKYLAKE-LABEL: test_punpckhdq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpckhdq {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[<wbr>3] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm1[2],mem[2],xmm1[3],mem[3] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm1[2],mem[2],xmm1[3],mem[3] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpckhdq:<br>
; SKX: # BB#0:<br>
@@ -7429,9 +7429,9 @@ define <2 x i64> @test_punpckhqdq(<2 x i<br>
; SKYLAKE-LABEL: test_punpckhqdq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpckhqdq {{.*#+}} xmm1 = xmm1[1],mem[1] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpckhqdq {{.*#+}} xmm1 = xmm1[1],mem[1] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpckhqdq:<br>
; SKX: # BB#0:<br>
@@ -7498,8 +7498,8 @@ define <8 x i16> @test_punpckhwd(<8 x i1<br>
; SKYLAKE-LABEL: test_punpckhwd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[<wbr>5],xmm0[6],xmm1[6],xmm0[7],<wbr>xmm1[7] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],mem[4],xmm0[5],mem[5],<wbr>xmm0[6],mem[6],xmm0[7],mem[7] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],mem[4],xmm0[5],mem[5],<wbr>xmm0[6],mem[6],xmm0[7],mem[7] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpckhwd:<br>
; SKX: # BB#0:<br>
@@ -7562,8 +7562,8 @@ define <16 x i8> @test_punpcklbw(<16 x i<br>
; SKYLAKE-LABEL: test_punpcklbw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3],xmm0[4],xmm1[4],xmm0[<wbr>5],xmm1[5],xmm0[6],xmm1[6],<wbr>xmm0[7],xmm1[7] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],<wbr>xmm0[2],mem[2],xmm0[3],mem[3],<wbr>xmm0[4],mem[4],xmm0[5],mem[5],<wbr>xmm0[6],mem[6],xmm0[7],mem[7] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],<wbr>xmm0[2],mem[2],xmm0[3],mem[3],<wbr>xmm0[4],mem[4],xmm0[5],mem[5],<wbr>xmm0[6],mem[6],xmm0[7],mem[7] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpcklbw:<br>
; SKX: # BB#0:<br>
@@ -7629,9 +7629,9 @@ define <4 x i32> @test_punpckldq(<4 x i3<br>
; SKYLAKE-LABEL: test_punpckldq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpckldq:<br>
; SKX: # BB#0:<br>
@@ -7699,9 +7699,9 @@ define <2 x i64> @test_punpcklqdq(<2 x i<br>
; SKYLAKE-LABEL: test_punpcklqdq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpcklqdq:<br>
; SKX: # BB#0:<br>
@@ -7768,8 +7768,8 @@ define <8 x i16> @test_punpcklwd(<8 x i1<br>
; SKYLAKE-LABEL: test_punpcklwd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],<wbr>xmm0[2],mem[2],xmm0[3],mem[3] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],<wbr>xmm0[2],mem[2],xmm0[3],mem[3] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_punpcklwd:<br>
; SKX: # BB#0:<br>
@@ -7832,10 +7832,10 @@ define <2 x i64> @test_pxor(<2 x i64> %a<br>
;<br>
; SKYLAKE-LABEL: test_pxor:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpxor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpxor (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpxor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vpxor (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pxor:<br>
; SKX: # BB#0:<br>
@@ -7903,9 +7903,9 @@ define <2 x double> @test_shufpd(<2 x do<br>
; SKYLAKE-LABEL: test_shufpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1],xmm1[0] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1],mem[0] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1],mem[0] sched: [7:1.00]<br>
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_shufpd:<br>
; SKX: # BB#0:<br>
@@ -7974,9 +7974,9 @@ define <2 x double> @test_sqrtpd(<2 x do<br>
; SKYLAKE-LABEL: test_sqrtpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vsqrtpd %xmm0, %xmm0 # sched: [18:1.00]<br>
-; SKYLAKE-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [18:1.00]<br>
+; SKYLAKE-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [24:1.00]<br>
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_sqrtpd:<br>
; SKX: # BB#0:<br>
@@ -8052,10 +8052,10 @@ define <2 x double> @test_sqrtsd(<2 x do<br>
; SKYLAKE-LABEL: test_sqrtsd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [18:1.00]<br>
-; SKYLAKE-NEXT: vmovapd (%rdi), %xmm1 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovapd (%rdi), %xmm1 # sched: [6:0.50]<br>
; SKYLAKE-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [18:1.00]<br>
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_sqrtsd:<br>
; SKX: # BB#0:<br>
@@ -8122,8 +8122,8 @@ define <2 x double> @test_subpd(<2 x dou<br>
; SKYLAKE-LABEL: test_subpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vsubpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vsubpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vsubpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_subpd:<br>
; SKX: # BB#0:<br>
@@ -8182,8 +8182,8 @@ define double @test_subsd(double %a0, do<br>
; SKYLAKE-LABEL: test_subsd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vsubsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vsubsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vsubsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_subsd:<br>
; SKX: # BB#0:<br>
@@ -8282,16 +8282,16 @@ define i32 @test_ucomisd(<2 x double> %a<br>
; SKYLAKE-LABEL: test_ucomisd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vucomisd %xmm1, %xmm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: sete %cl # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: sete %cl # sched: [1:0.50]<br>
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]<br>
; SKYLAKE-NEXT: vucomisd (%rdi), %xmm0 # sched: [8:1.00]<br>
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: sete %dl # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: sete %dl # sched: [1:0.50]<br>
; SKYLAKE-NEXT: andb %al, %dl # sched: [1:0.25]<br>
; SKYLAKE-NEXT: orb %cl, %dl # sched: [1:0.25]<br>
; SKYLAKE-NEXT: movzbl %dl, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_ucomisd:<br>
; SKX: # BB#0:<br>
@@ -8381,9 +8381,9 @@ define <2 x double> @test_unpckhpd(<2 x<br>
; SKYLAKE-LABEL: test_unpckhpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm1[1],mem[1] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm1[1],mem[1] sched: [7:1.00]<br>
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_unpckhpd:<br>
; SKX: # BB#0:<br>
@@ -8457,9 +8457,9 @@ define <2 x double> @test_unpcklpd(<2 x<br>
; SKYLAKE-LABEL: test_unpcklpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm0[0],mem[0] sched: [1:1.00]<br>
+; SKYLAKE-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm0[0],mem[0] sched: [7:1.00]<br>
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_unpcklpd:<br>
; SKX: # BB#0:<br>
@@ -8526,10 +8526,10 @@ define <2 x double> @test_xorpd(<2 x dou<br>
;<br>
; SKYLAKE-LABEL: test_xorpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vxorpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vxorpd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vxorpd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vxorpd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_xorpd:<br>
; SKX: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>sse3-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/sse3-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>sse3-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>sse3-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -44,8 +44,8 @@ define <2 x double> @test_addsubpd(<2 x<br>
; SKYLAKE-LABEL: test_addsubpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_addsubpd:<br>
; SKX: # BB#0:<br>
@@ -105,8 +105,8 @@ define <4 x float> @test_addsubps(<4 x f<br>
; SKYLAKE-LABEL: test_addsubps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vaddsubps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vaddsubps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vaddsubps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_addsubps:<br>
; SKX: # BB#0:<br>
@@ -166,8 +166,8 @@ define <2 x double> @test_haddpd(<2 x do<br>
; SKYLAKE-LABEL: test_haddpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vhaddpd %xmm1, %xmm0, %xmm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: vhaddpd (%rdi), %xmm0, %xmm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vhaddpd (%rdi), %xmm0, %xmm0 # sched: [12:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_haddpd:<br>
; SKX: # BB#0:<br>
@@ -227,8 +227,8 @@ define <4 x float> @test_haddps(<4 x flo<br>
; SKYLAKE-LABEL: test_haddps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vhaddps %xmm1, %xmm0, %xmm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: vhaddps (%rdi), %xmm0, %xmm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vhaddps (%rdi), %xmm0, %xmm0 # sched: [12:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_haddps:<br>
; SKX: # BB#0:<br>
@@ -288,8 +288,8 @@ define <2 x double> @test_hsubpd(<2 x do<br>
; SKYLAKE-LABEL: test_hsubpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vhsubpd %xmm1, %xmm0, %xmm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: vhsubpd (%rdi), %xmm0, %xmm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vhsubpd (%rdi), %xmm0, %xmm0 # sched: [12:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_hsubpd:<br>
; SKX: # BB#0:<br>
@@ -349,8 +349,8 @@ define <4 x float> @test_hsubps(<4 x flo<br>
; SKYLAKE-LABEL: test_hsubps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vhsubps %xmm1, %xmm0, %xmm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: vhsubps (%rdi), %xmm0, %xmm0 # sched: [6:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vhsubps (%rdi), %xmm0, %xmm0 # sched: [12:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_hsubps:<br>
; SKX: # BB#0:<br>
@@ -406,8 +406,8 @@ define <16 x i8> @test_lddqu(i8* %a0) {<br>
;<br>
; SKYLAKE-LABEL: test_lddqu:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vlddqu (%rdi), %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vlddqu (%rdi), %xmm0 # sched: [6:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_lddqu:<br>
; SKX: # BB#0:<br>
@@ -469,7 +469,7 @@ define void @test_monitor(i8* %a0, i32 %<br>
; SKYLAKE-NEXT: leaq (%rdi), %rax # sched: [1:0.50]<br>
; SKYLAKE-NEXT: movl %esi, %ecx # sched: [1:0.25]<br>
; SKYLAKE-NEXT: monitor # sched: [100:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_monitor:<br>
; SKX: # BB#0:<br>
@@ -536,9 +536,9 @@ define <2 x double> @test_movddup(<2 x d<br>
; SKYLAKE-LABEL: test_movddup:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [5:0.50]<br>
; SKYLAKE-NEXT: vsubpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movddup:<br>
; SKX: # BB#0:<br>
@@ -607,9 +607,9 @@ define <4 x float> @test_movshdup(<4 x f<br>
; SKYLAKE-LABEL: test_movshdup:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [6:0.50]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movshdup:<br>
; SKX: # BB#0:<br>
@@ -678,9 +678,9 @@ define <4 x float> @test_movsldup(<4 x f<br>
; SKYLAKE-LABEL: test_movsldup:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [6:0.50]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movsldup:<br>
; SKX: # BB#0:<br>
@@ -750,7 +750,7 @@ define void @test_mwait(i32 %a0, i32 %a1<br>
; SKYLAKE-NEXT: movl %edi, %ecx # sched: [1:0.25]<br>
; SKYLAKE-NEXT: movl %esi, %eax # sched: [1:0.25]<br>
; SKYLAKE-NEXT: mwait # sched: [20:2.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_mwait:<br>
; SKX: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>sse41-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/sse41-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>sse41-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>sse41-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -40,10 +40,10 @@ define <2 x double> @test_blendpd(<2 x d<br>
;<br>
; SKYLAKE-LABEL: test_blendpd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1] sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1] sched: [1:0.33]<br>
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],mem[1] sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],mem[1] sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_blendpd:<br>
; SKX: # BB#0:<br>
@@ -100,9 +100,9 @@ define <4 x float> @test_blendps(<4 x fl<br>
;<br>
; SKYLAKE-LABEL: test_blendps:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3] sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2,3] sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3] sched: [1:0.33]<br>
+; SKYLAKE-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2,3] sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_blendps:<br>
; SKX: # BB#0:<br>
@@ -161,8 +161,8 @@ define <2 x double> @test_blendvpd(<2 x<br>
; SKYLAKE-LABEL: test_blendvpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:0.67]<br>
-; SKYLAKE-NEXT: vblendvpd %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:0.67]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vblendvpd %xmm2, (%rdi), %xmm0, %xmm0 # sched: [8:0.67]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_blendvpd:<br>
; SKX: # BB#0:<br>
@@ -222,8 +222,8 @@ define <4 x float> @test_blendvps(<4 x f<br>
; SKYLAKE-LABEL: test_blendvps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:0.67]<br>
-; SKYLAKE-NEXT: vblendvps %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:0.67]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vblendvps %xmm2, (%rdi), %xmm0, %xmm0 # sched: [8:0.67]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_blendvps:<br>
; SKX: # BB#0:<br>
@@ -277,8 +277,8 @@ define <2 x double> @test_dppd(<2 x doub<br>
; SKYLAKE-LABEL: test_dppd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vdppd $7, %xmm1, %xmm0, %xmm0 # sched: [9:1.00]<br>
-; SKYLAKE-NEXT: vdppd $7, (%rdi), %xmm0, %xmm0 # sched: [9:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vdppd $7, (%rdi), %xmm0, %xmm0 # sched: [15:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_dppd:<br>
; SKX: # BB#0:<br>
@@ -332,8 +332,8 @@ define <4 x float> @test_dpps(<4 x float<br>
; SKYLAKE-LABEL: test_dpps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vdpps $7, %xmm1, %xmm0, %xmm0 # sched: [13:1.33]<br>
-; SKYLAKE-NEXT: vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [13:1.33]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [19:1.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_dpps:<br>
; SKX: # BB#0:<br>
@@ -387,8 +387,8 @@ define <4 x float> @test_insertps(<4 x f<br>
; SKYLAKE-LABEL: test_insertps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm1[0],xmm0[2,3] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_insertps:<br>
; SKX: # BB#0:<br>
@@ -437,8 +437,8 @@ define <2 x i64> @test_movntdqa(i8* %a0)<br>
;<br>
; SKYLAKE-LABEL: test_movntdqa:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vmovntdqa (%rdi), %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmovntdqa (%rdi), %xmm0 # sched: [6:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_movntdqa:<br>
; SKX: # BB#0:<br>
@@ -487,8 +487,8 @@ define <8 x i16> @test_mpsadbw(<16 x i8><br>
; SKYLAKE-LABEL: test_mpsadbw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vmpsadbw $7, %xmm1, %xmm0, %xmm0 # sched: [4:2.00]<br>
-; SKYLAKE-NEXT: vmpsadbw $7, (%rdi), %xmm0, %xmm0 # sched: [4:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vmpsadbw $7, (%rdi), %xmm0, %xmm0 # sched: [10:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_mpsadbw:<br>
; SKX: # BB#0:<br>
@@ -543,8 +543,8 @@ define <8 x i16> @test_packusdw(<4 x i32<br>
; SKYLAKE-LABEL: test_packusdw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpackusdw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpackusdw (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpackusdw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_packusdw:<br>
; SKX: # BB#0:<br>
@@ -605,8 +605,8 @@ define <16 x i8> @test_pblendvb(<16 x i8<br>
; SKYLAKE-LABEL: test_pblendvb:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:0.67]<br>
-; SKYLAKE-NEXT: vpblendvb %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:0.67]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpblendvb %xmm2, (%rdi), %xmm0, %xmm0 # sched: [8:0.67]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pblendvb:<br>
; SKX: # BB#0:<br>
@@ -660,8 +660,8 @@ define <8 x i16> @test_pblendw(<8 x i16><br>
; SKYLAKE-LABEL: test_pblendw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[<wbr>3],xmm0[4],xmm1[5],xmm0[6],<wbr>xmm1[7] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3],xmm0[4,5,6]<wbr>,mem[7] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3],xmm0[4,5,6]<wbr>,mem[7] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pblendw:<br>
; SKX: # BB#0:<br>
@@ -713,9 +713,9 @@ define <2 x i64> @test_pcmpeqq(<2 x i64><br>
;<br>
; SKYLAKE-LABEL: test_pcmpeqq:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpcmpeqq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpcmpeqq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpeqq:<br>
; SKX: # BB#0:<br>
@@ -772,8 +772,8 @@ define i32 @test_pextrb(<16 x i8> %a0, i<br>
; SKYLAKE-LABEL: test_pextrb:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpextrb $3, %xmm0, %eax # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpextrb $1, %xmm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpextrb $1, %xmm0, (%rdi) # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pextrb:<br>
; SKX: # BB#0:<br>
@@ -827,8 +827,8 @@ define i32 @test_pextrd(<4 x i32> %a0, i<br>
; SKYLAKE-LABEL: test_pextrd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpextrd $3, %xmm0, %eax # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpextrd $1, %xmm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpextrd $1, %xmm0, (%rdi) # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pextrd:<br>
; SKX: # BB#0:<br>
@@ -881,8 +881,8 @@ define i64 @test_pextrq(<2 x i64> %a0, <<br>
; SKYLAKE-LABEL: test_pextrq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpextrq $1, %xmm0, %rax # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpextrq $1, %xmm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpextrq $1, %xmm0, (%rdi) # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pextrq:<br>
; SKX: # BB#0:<br>
@@ -935,8 +935,8 @@ define i32 @test_pextrw(<8 x i16> %a0, i<br>
; SKYLAKE-LABEL: test_pextrw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpextrw $3, %xmm0, %eax # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpextrw $1, %xmm0, (%rdi) # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpextrw $1, %xmm0, (%rdi) # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pextrw:<br>
; SKX: # BB#0:<br>
@@ -989,9 +989,9 @@ define <8 x i16> @test_phminposuw(<8 x i<br>
;<br>
; SKYLAKE-LABEL: test_phminposuw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vphminposuw (%rdi), %xmm0 # sched: [4:0.50]<br>
+; SKYLAKE-NEXT: vphminposuw (%rdi), %xmm0 # sched: [10:0.50]<br>
; SKYLAKE-NEXT: vphminposuw %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_phminposuw:<br>
; SKX: # BB#0:<br>
@@ -1045,8 +1045,8 @@ define <16 x i8> @test_pinsrb(<16 x i8><br>
; SKYLAKE-LABEL: test_pinsrb:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpinsrb $1, %edi, %xmm0, %xmm0 # sched: [2:2.00]<br>
-; SKYLAKE-NEXT: vpinsrb $3, (%rsi), %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpinsrb $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pinsrb:<br>
; SKX: # BB#0:<br>
@@ -1099,8 +1099,8 @@ define <4 x i32> @test_pinsrd(<4 x i32><br>
; SKYLAKE-LABEL: test_pinsrd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0 # sched: [2:2.00]<br>
-; SKYLAKE-NEXT: vpinsrd $3, (%rsi), %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpinsrd $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pinsrd:<br>
; SKX: # BB#0:<br>
@@ -1157,9 +1157,9 @@ define <2 x i64> @test_pinsrq(<2 x i64><br>
; SKYLAKE-LABEL: test_pinsrq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0 # sched: [2:2.00]<br>
-; SKYLAKE-NEXT: vpinsrq $1, (%rsi), %xmm1, %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpinsrq $1, (%rsi), %xmm1, %xmm1 # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pinsrq:<br>
; SKX: # BB#0:<br>
@@ -1215,9 +1215,9 @@ define <16 x i8> @test_pmaxsb(<16 x i8><br>
;<br>
; SKYLAKE-LABEL: test_pmaxsb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmaxsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpmaxsb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaxsb:<br>
; SKX: # BB#0:<br>
@@ -1270,9 +1270,9 @@ define <4 x i32> @test_pmaxsd(<4 x i32><br>
;<br>
; SKYLAKE-LABEL: test_pmaxsd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmaxsd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpmaxsd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaxsd:<br>
; SKX: # BB#0:<br>
@@ -1325,9 +1325,9 @@ define <4 x i32> @test_pmaxud(<4 x i32><br>
;<br>
; SKYLAKE-LABEL: test_pmaxud:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmaxud (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpmaxud (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaxud:<br>
; SKX: # BB#0:<br>
@@ -1380,9 +1380,9 @@ define <8 x i16> @test_pmaxuw(<8 x i16><br>
;<br>
; SKYLAKE-LABEL: test_pmaxuw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmaxuw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpmaxuw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaxuw:<br>
; SKX: # BB#0:<br>
@@ -1435,9 +1435,9 @@ define <16 x i8> @test_pminsb(<16 x i8><br>
;<br>
; SKYLAKE-LABEL: test_pminsb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpminsb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpminsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpminsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpminsb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pminsb:<br>
; SKX: # BB#0:<br>
@@ -1490,9 +1490,9 @@ define <4 x i32> @test_pminsd(<4 x i32><br>
;<br>
; SKYLAKE-LABEL: test_pminsd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpminsd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpminsd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpminsd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpminsd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pminsd:<br>
; SKX: # BB#0:<br>
@@ -1545,9 +1545,9 @@ define <4 x i32> @test_pminud(<4 x i32><br>
;<br>
; SKYLAKE-LABEL: test_pminud:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpminud %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpminud (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpminud %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpminud (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pminud:<br>
; SKX: # BB#0:<br>
@@ -1600,9 +1600,9 @@ define <8 x i16> @test_pminuw(<8 x i16><br>
;<br>
; SKYLAKE-LABEL: test_pminuw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpminuw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpminuw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpminuw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpminuw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pminuw:<br>
; SKX: # BB#0:<br>
@@ -1661,9 +1661,9 @@ define <8 x i16> @test_pmovsxbw(<16 x i8<br>
; SKYLAKE-LABEL: test_pmovsxbw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovsxbw %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmovsxbw (%rdi), %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovsxbw (%rdi), %xmm1 # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovsxbw:<br>
; SKX: # BB#0:<br>
@@ -1726,9 +1726,9 @@ define <4 x i32> @test_pmovsxbd(<16 x i8<br>
; SKYLAKE-LABEL: test_pmovsxbd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovsxbd %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmovsxbd (%rdi), %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovsxbd (%rdi), %xmm1 # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovsxbd:<br>
; SKX: # BB#0:<br>
@@ -1791,9 +1791,9 @@ define <2 x i64> @test_pmovsxbq(<16 x i8<br>
; SKYLAKE-LABEL: test_pmovsxbq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovsxbq %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmovsxbq (%rdi), %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovsxbq (%rdi), %xmm1 # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovsxbq:<br>
; SKX: # BB#0:<br>
@@ -1856,9 +1856,9 @@ define <2 x i64> @test_pmovsxdq(<4 x i32<br>
; SKYLAKE-LABEL: test_pmovsxdq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovsxdq %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmovsxdq (%rdi), %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovsxdq (%rdi), %xmm1 # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovsxdq:<br>
; SKX: # BB#0:<br>
@@ -1921,9 +1921,9 @@ define <4 x i32> @test_pmovsxwd(<8 x i16<br>
; SKYLAKE-LABEL: test_pmovsxwd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovsxwd %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmovsxwd (%rdi), %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovsxwd (%rdi), %xmm1 # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovsxwd:<br>
; SKX: # BB#0:<br>
@@ -1986,9 +1986,9 @@ define <2 x i64> @test_pmovsxwq(<8 x i16<br>
; SKYLAKE-LABEL: test_pmovsxwq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovsxwq %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmovsxwq (%rdi), %xmm1 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovsxwq (%rdi), %xmm1 # sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovsxwq:<br>
; SKX: # BB#0:<br>
@@ -2051,9 +2051,9 @@ define <8 x i16> @test_pmovzxbw(<16 x i8<br>
; SKYLAKE-LABEL: test_pmovzxbw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,<wbr>xmm0[2],zero,xmm0[3],zero,<wbr>xmm0[4],zero,xmm0[5],zero,<wbr>xmm0[6],zero,xmm0[7],zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmovzxbw {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2]<wbr>,zero,mem[3],zero,mem[4],zero,<wbr>mem[5],zero,mem[6],zero,mem[7]<wbr>,zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovzxbw {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2]<wbr>,zero,mem[3],zero,mem[4],zero,<wbr>mem[5],zero,mem[6],zero,mem[7]<wbr>,zero sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovzxbw:<br>
; SKX: # BB#0:<br>
@@ -2116,9 +2116,9 @@ define <4 x i32> @test_pmovzxbd(<16 x i8<br>
; SKYLAKE-LABEL: test_pmovzxbd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1]<wbr>,zero,zero,zero,xmm0[2],zero,<wbr>zero,zero,xmm0[3],zero,zero,<wbr>zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],<wbr>zero,zero,zero,mem[2],zero,<wbr>zero,zero,mem[3],zero,zero,<wbr>zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],<wbr>zero,zero,zero,mem[2],zero,<wbr>zero,zero,mem[3],zero,zero,<wbr>zero sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovzxbd:<br>
; SKX: # BB#0:<br>
@@ -2181,9 +2181,9 @@ define <2 x i64> @test_pmovzxbq(<16 x i8<br>
; SKYLAKE-LABEL: test_pmovzxbq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,<wbr>zero,zero,zero,xmm0[1],zero,<wbr>zero,zero,zero,zero,zero,zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmovzxbq {{.*#+}} xmm1 = mem[0],zero,zero,zero,zero,<wbr>zero,zero,zero,mem[1],zero,<wbr>zero,zero,zero,zero,zero,zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovzxbq {{.*#+}} xmm1 = mem[0],zero,zero,zero,zero,<wbr>zero,zero,zero,mem[1],zero,<wbr>zero,zero,zero,zero,zero,zero sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovzxbq:<br>
; SKX: # BB#0:<br>
@@ -2246,9 +2246,9 @@ define <2 x i64> @test_pmovzxdq(<4 x i32<br>
; SKYLAKE-LABEL: test_pmovzxdq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovzxdq:<br>
; SKX: # BB#0:<br>
@@ -2311,9 +2311,9 @@ define <4 x i32> @test_pmovzxwd(<8 x i16<br>
; SKYLAKE-LABEL: test_pmovzxwd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,<wbr>xmm0[2],zero,xmm0[3],zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2]<wbr>,zero,mem[3],zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2]<wbr>,zero,mem[3],zero sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovzxwd:<br>
; SKX: # BB#0:<br>
@@ -2376,9 +2376,9 @@ define <2 x i64> @test_pmovzxwq(<8 x i16<br>
; SKYLAKE-LABEL: test_pmovzxwq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1]<wbr>,zero,zero,zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpmovzxwq {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],<wbr>zero,zero,zero sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmovzxwq {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],<wbr>zero,zero,zero sched: [6:1.00]<br>
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmovzxwq:<br>
; SKX: # BB#0:<br>
@@ -2436,8 +2436,8 @@ define <2 x i64> @test_pmuldq(<4 x i32><br>
; SKYLAKE-LABEL: test_pmuldq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmuldq %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmuldq (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmuldq (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmuldq:<br>
; SKX: # BB#0:<br>
@@ -2492,8 +2492,8 @@ define <4 x i32> @test_pmulld(<4 x i32><br>
; SKYLAKE-LABEL: test_pmulld:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmulld %xmm1, %xmm0, %xmm0 # sched: [8:0.67]<br>
-; SKYLAKE-NEXT: vpmulld (%rdi), %xmm0, %xmm0 # sched: [8:0.67]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmulld (%rdi), %xmm0, %xmm0 # sched: [14:0.67]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmulld:<br>
; SKX: # BB#0:<br>
@@ -2562,12 +2562,12 @@ define i32 @test_ptest(<2 x i64> %a0, <2<br>
; SKYLAKE-LABEL: test_ptest:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vptest %xmm1, %xmm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: setb %al # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vptest (%rdi), %xmm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: setb %cl # sched: [1:1.00]<br>
+; SKYLAKE-NEXT: setb %al # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vptest (%rdi), %xmm0 # sched: [9:1.00]<br>
+; SKYLAKE-NEXT: setb %cl # sched: [1:0.50]<br>
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]<br>
; SKYLAKE-NEXT: movzbl %cl, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_ptest:<br>
; SKX: # BB#0:<br>
@@ -2639,9 +2639,9 @@ define <2 x double> @test_roundpd(<2 x d<br>
; SKYLAKE-LABEL: test_roundpd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vroundpd $7, %xmm0, %xmm0 # sched: [8:0.67]<br>
-; SKYLAKE-NEXT: vroundpd $7, (%rdi), %xmm1 # sched: [8:0.67]<br>
+; SKYLAKE-NEXT: vroundpd $7, (%rdi), %xmm1 # sched: [14:0.67]<br>
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_roundpd:<br>
; SKX: # BB#0:<br>
@@ -2704,9 +2704,9 @@ define <4 x float> @test_roundps(<4 x fl<br>
; SKYLAKE-LABEL: test_roundps:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vroundps $7, %xmm0, %xmm0 # sched: [8:0.67]<br>
-; SKYLAKE-NEXT: vroundps $7, (%rdi), %xmm1 # sched: [8:0.67]<br>
+; SKYLAKE-NEXT: vroundps $7, (%rdi), %xmm1 # sched: [14:0.67]<br>
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_roundps:<br>
; SKX: # BB#0:<br>
@@ -2770,9 +2770,9 @@ define <2 x double> @test_roundsd(<2 x d<br>
; SKYLAKE-LABEL: test_roundsd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vroundsd $7, %xmm1, %xmm0, %xmm1 # sched: [8:0.67]<br>
-; SKYLAKE-NEXT: vroundsd $7, (%rdi), %xmm0, %xmm0 # sched: [8:0.67]<br>
+; SKYLAKE-NEXT: vroundsd $7, (%rdi), %xmm0, %xmm0 # sched: [14:0.67]<br>
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_roundsd:<br>
; SKX: # BB#0:<br>
@@ -2836,9 +2836,9 @@ define <4 x float> @test_roundss(<4 x fl<br>
; SKYLAKE-LABEL: test_roundss:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vroundss $7, %xmm1, %xmm0, %xmm1 # sched: [8:0.67]<br>
-; SKYLAKE-NEXT: vroundss $7, (%rdi), %xmm0, %xmm0 # sched: [8:0.67]<br>
+; SKYLAKE-NEXT: vroundss $7, (%rdi), %xmm0, %xmm0 # sched: [14:0.67]<br>
; SKYLAKE-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_roundss:<br>
; SKX: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>sse42-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/sse42-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>sse42-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>sse42-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -43,7 +43,7 @@ define i32 @crc32_32_8(i32 %a0, i8 %a1,<br>
; SKYLAKE-NEXT: crc32b %sil, %edi # sched: [3:1.00]<br>
; SKYLAKE-NEXT: crc32b (%rdx), %edi # sched: [8:1.00]<br>
; SKYLAKE-NEXT: movl %edi, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: crc32_32_8:<br>
; SKX: # BB#0:<br>
@@ -106,7 +106,7 @@ define i32 @crc32_32_16(i32 %a0, i16 %a1<br>
; SKYLAKE-NEXT: crc32w %si, %edi # sched: [3:1.00]<br>
; SKYLAKE-NEXT: crc32w (%rdx), %edi # sched: [8:1.00]<br>
; SKYLAKE-NEXT: movl %edi, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: crc32_32_16:<br>
; SKX: # BB#0:<br>
@@ -169,7 +169,7 @@ define i32 @crc32_32_32(i32 %a0, i32 %a1<br>
; SKYLAKE-NEXT: crc32l %esi, %edi # sched: [3:1.00]<br>
; SKYLAKE-NEXT: crc32l (%rdx), %edi # sched: [8:1.00]<br>
; SKYLAKE-NEXT: movl %edi, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: crc32_32_32:<br>
; SKX: # BB#0:<br>
@@ -232,7 +232,7 @@ define i64 @crc32_64_8(i64 %a0, i8 %a1,<br>
; SKYLAKE-NEXT: crc32b %sil, %edi # sched: [3:1.00]<br>
; SKYLAKE-NEXT: crc32b (%rdx), %edi # sched: [8:1.00]<br>
; SKYLAKE-NEXT: movq %rdi, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: crc32_64_8:<br>
; SKX: # BB#0:<br>
@@ -295,7 +295,7 @@ define i64 @crc32_64_64(i64 %a0, i64 %a1<br>
; SKYLAKE-NEXT: crc32q %rsi, %rdi # sched: [3:1.00]<br>
; SKYLAKE-NEXT: crc32q (%rdx), %rdi # sched: [8:1.00]<br>
; SKYLAKE-NEXT: movq %rdi, %rax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: crc32_64_64:<br>
; SKX: # BB#0:<br>
@@ -385,10 +385,10 @@ define i32 @test_pcmpestri(<16 x i8> %a0<br>
; SKYLAKE-NEXT: movl %ecx, %esi # sched: [1:0.25]<br>
; SKYLAKE-NEXT: movl $7, %eax # sched: [1:0.25]<br>
; SKYLAKE-NEXT: movl $7, %edx # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: vpcmpestri $7, (%rdi), %xmm0 # sched: [18:4.00]<br>
+; SKYLAKE-NEXT: vpcmpestri $7, (%rdi), %xmm0 # sched: [24:4.00]<br>
; SKYLAKE-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def><br>
; SKYLAKE-NEXT: leal (%rcx,%rsi), %eax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpestri:<br>
; SKX: # BB#0:<br>
@@ -484,8 +484,8 @@ define <16 x i8> @test_pcmpestrm(<16 x i<br>
; SKYLAKE-NEXT: vpcmpestrm $7, %xmm1, %xmm0 # sched: [19:4.00]<br>
; SKYLAKE-NEXT: movl $7, %eax # sched: [1:0.25]<br>
; SKYLAKE-NEXT: movl $7, %edx # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: vpcmpestrm $7, (%rdi), %xmm0 # sched: [19:4.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpestrm $7, (%rdi), %xmm0 # sched: [25:4.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpestrm:<br>
; SKX: # BB#0:<br>
@@ -564,10 +564,10 @@ define i32 @test_pcmpistri(<16 x i8> %a0<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpcmpistri $7, %xmm1, %xmm0 # sched: [10:3.00]<br>
; SKYLAKE-NEXT: movl %ecx, %eax # sched: [1:0.25]<br>
-; SKYLAKE-NEXT: vpcmpistri $7, (%rdi), %xmm0 # sched: [10:3.00]<br>
+; SKYLAKE-NEXT: vpcmpistri $7, (%rdi), %xmm0 # sched: [16:3.00]<br>
; SKYLAKE-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def><br>
; SKYLAKE-NEXT: leal (%rcx,%rax), %eax # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpistri:<br>
; SKX: # BB#0:<br>
@@ -631,8 +631,8 @@ define <16 x i8> @test_pcmpistrm(<16 x i<br>
; SKYLAKE-LABEL: test_pcmpistrm:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpcmpistrm $7, %xmm1, %xmm0 # sched: [10:3.00]<br>
-; SKYLAKE-NEXT: vpcmpistrm $7, (%rdi), %xmm0 # sched: [10:3.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpistrm $7, (%rdi), %xmm0 # sched: [16:3.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpistrm:<br>
; SKX: # BB#0:<br>
@@ -686,8 +686,8 @@ define <2 x i64> @test_pcmpgtq(<2 x i64><br>
; SKYLAKE-LABEL: test_pcmpgtq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: vpcmpgtq (%rdi), %xmm0, %xmm0 # sched: [3:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpcmpgtq (%rdi), %xmm0, %xmm0 # sched: [9:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pcmpgtq:<br>
; SKX: # BB#0:<br>
@@ -744,8 +744,8 @@ define <2 x i64> @test_pclmulqdq(<2 x i6<br>
; SKYLAKE-LABEL: test_pclmulqdq:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # sched: [6:1.00]<br>
-; SKYLAKE-NEXT: vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [6:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [12:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pclmulqdq:<br>
; SKX: # BB#0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>ssse3-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/ssse3-schedule.ll?<wbr>rev=315978&r1=315977&r2=<wbr>315978&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>ssse3-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>ssse3-schedule.ll Mon Oct 16 23:47:04 2017<br>
@@ -49,10 +49,10 @@ define <16 x i8> @test_pabsb(<16 x i8> %<br>
;<br>
; SKYLAKE-LABEL: test_pabsb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpabsb %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpabsb (%rdi), %xmm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpabsb %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpabsb (%rdi), %xmm1 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pabsb:<br>
; SKX: # BB#0:<br>
@@ -121,10 +121,10 @@ define <4 x i32> @test_pabsd(<4 x i32> %<br>
;<br>
; SKYLAKE-LABEL: test_pabsd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpabsd %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpabsd (%rdi), %xmm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpabsd %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpabsd (%rdi), %xmm1 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pabsd:<br>
; SKX: # BB#0:<br>
@@ -193,10 +193,10 @@ define <8 x i16> @test_pabsw(<8 x i16> %<br>
;<br>
; SKYLAKE-LABEL: test_pabsw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpabsw %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpabsw (%rdi), %xmm1 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpabsw %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpabsw (%rdi), %xmm1 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pabsw:<br>
; SKX: # BB#0:<br>
@@ -265,8 +265,8 @@ define <8 x i16> @test_palignr(<8 x i16><br>
; SKYLAKE-LABEL: test_palignr:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,<wbr>15],xmm1[0,1,2,3,4,5] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpalignr {{.*#+}} xmm0 = mem[14,15],xmm0[0,1,2,3,4,5,6,<wbr>7,8,9,10,11,12,13] sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpalignr {{.*#+}} xmm0 = mem[14,15],xmm0[0,1,2,3,4,5,6,<wbr>7,8,9,10,11,12,13] sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_palignr:<br>
; SKX: # BB#0:<br>
@@ -325,8 +325,8 @@ define <4 x i32> @test_phaddd(<4 x i32><br>
; SKYLAKE-LABEL: test_phaddd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vphaddd %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: vphaddd (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vphaddd (%rdi), %xmm0, %xmm0 # sched: [9:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_phaddd:<br>
; SKX: # BB#0:<br>
@@ -386,8 +386,8 @@ define <8 x i16> @test_phaddsw(<8 x i16><br>
; SKYLAKE-LABEL: test_phaddsw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vphaddsw %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: vphaddsw (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vphaddsw (%rdi), %xmm0, %xmm0 # sched: [9:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_phaddsw:<br>
; SKX: # BB#0:<br>
@@ -447,8 +447,8 @@ define <8 x i16> @test_phaddw(<8 x i16><br>
; SKYLAKE-LABEL: test_phaddw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vphaddw %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: vphaddw (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vphaddw (%rdi), %xmm0, %xmm0 # sched: [9:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_phaddw:<br>
; SKX: # BB#0:<br>
@@ -508,8 +508,8 @@ define <4 x i32> @test_phsubd(<4 x i32><br>
; SKYLAKE-LABEL: test_phsubd:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vphsubd %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: vphsubd (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vphsubd (%rdi), %xmm0, %xmm0 # sched: [9:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_phsubd:<br>
; SKX: # BB#0:<br>
@@ -569,8 +569,8 @@ define <8 x i16> @test_phsubsw(<8 x i16><br>
; SKYLAKE-LABEL: test_phsubsw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vphsubsw %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: vphsubsw (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vphsubsw (%rdi), %xmm0, %xmm0 # sched: [9:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_phsubsw:<br>
; SKX: # BB#0:<br>
@@ -630,8 +630,8 @@ define <8 x i16> @test_phsubw(<8 x i16><br>
; SKYLAKE-LABEL: test_phsubw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vphsubw %xmm1, %xmm0, %xmm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: vphsubw (%rdi), %xmm0, %xmm0 # sched: [3:2.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vphsubw (%rdi), %xmm0, %xmm0 # sched: [9:2.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_phsubw:<br>
; SKX: # BB#0:<br>
@@ -691,8 +691,8 @@ define <8 x i16> @test_pmaddubsw(<16 x i<br>
; SKYLAKE-LABEL: test_pmaddubsw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmaddubsw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmaddubsw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmaddubsw:<br>
; SKX: # BB#0:<br>
@@ -753,8 +753,8 @@ define <8 x i16> @test_pmulhrsw(<8 x i16<br>
; SKYLAKE-LABEL: test_pmulhrsw:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpmulhrsw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]<br>
-; SKYLAKE-NEXT: vpmulhrsw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpmulhrsw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pmulhrsw:<br>
; SKX: # BB#0:<br>
@@ -814,8 +814,8 @@ define <16 x i8> @test_pshufb(<16 x i8><br>
; SKYLAKE-LABEL: test_pshufb:<br>
; SKYLAKE: # BB#0:<br>
; SKYLAKE-NEXT: vpshufb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpshufb (%rdi), %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpshufb (%rdi), %xmm0, %xmm0 # sched: [7:1.00]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_pshufb:<br>
; SKX: # BB#0:<br>
@@ -878,9 +878,9 @@ define <16 x i8> @test_psignb(<16 x i8><br>
;<br>
; SKYLAKE-LABEL: test_psignb:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsignb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsignb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsignb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsignb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psignb:<br>
; SKX: # BB#0:<br>
@@ -943,9 +943,9 @@ define <4 x i32> @test_psignd(<4 x i32><br>
;<br>
; SKYLAKE-LABEL: test_psignd:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsignd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsignd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsignd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsignd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psignd:<br>
; SKX: # BB#0:<br>
@@ -1008,9 +1008,9 @@ define <8 x i16> @test_psignw(<8 x i16><br>
;<br>
; SKYLAKE-LABEL: test_psignw:<br>
; SKYLAKE: # BB#0:<br>
-; SKYLAKE-NEXT: vpsignw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]<br>
-; SKYLAKE-NEXT: vpsignw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]<br>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]<br>
+; SKYLAKE-NEXT: vpsignw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]<br>
+; SKYLAKE-NEXT: vpsignw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]<br>
+; SKYLAKE-NEXT: retq # sched: [7:1.00]<br>
;<br>
; SKX-LABEL: test_psignw:<br>
; SKX: # BB#0:<br>
<br>
<br>
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