<div dir="ltr">This broke the MSVC 2017 build. It has something to do with the relative order of instantiation and specialization of addPredicate. I tried to fix this in r315930, which was broken, and r315932, which should fix it without breaking the build elsewhere.</div><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Oct 15, 2017 at 5:56 PM, Daniel Sanders via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: dsanders<br>
Date: Sun Oct 15 17:56:30 2017<br>
New Revision: 315884<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=315884&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=315884&view=rev</a><br>
Log:<br>
[globalisel][tablegen] Implement unindexed load, non-extending load, and MemVT checks<br>
<br>
Summary:<br>
This includes some context-sensitivity in the MVT to LLT conversion so that<br>
pointer types are tested correctly.<br>
FIXME: I'm not happy with the way this is done since everything is a<br>
special-case. I've yet to find a reasonable way to implement it.<br>
<br>
select-load.mir fails because <1 x s64> loads in tablegen get priority over s64<br>
loads. This is fixed in the next patch and as such they should be committed<br>
together, I've posted them separately to help with the review.<br>
<br>
Depends on D37456<br>
<br>
Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar<br>
<br>
Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D37457" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D37457</a><br>
<br>
Modified:<br>
llvm/trunk/include/llvm/<wbr>CodeGen/GlobalISel/<wbr>InstructionSelector.h<br>
llvm/trunk/include/llvm/<wbr>CodeGen/GlobalISel/<wbr>InstructionSelectorImpl.h<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/GlobalISel/select-<wbr>load.mir<br>
llvm/trunk/test/TableGen/<wbr>GlobalISelEmitter.td<br>
llvm/trunk/utils/TableGen/<wbr>GlobalISelEmitter.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/<wbr>CodeGen/GlobalISel/<wbr>InstructionSelector.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h?rev=315884&r1=315883&r2=315884&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/include/<wbr>llvm/CodeGen/GlobalISel/<wbr>InstructionSelector.h?rev=<wbr>315884&r1=315883&r2=315884&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/<wbr>CodeGen/GlobalISel/<wbr>InstructionSelector.h (original)<br>
+++ llvm/trunk/include/llvm/<wbr>CodeGen/GlobalISel/<wbr>InstructionSelector.h Sun Oct 15 17:56:30 2017<br>
@@ -117,6 +117,11 @@ enum {<br>
/// - OpIdx - Operand index<br>
/// - Expected type<br>
GIM_CheckType,<br>
+ /// Check the type of a pointer to any address space.<br>
+ /// - InsnID - Instruction ID<br>
+ /// - OpIdx - Operand index<br>
+ /// - SizeInBits - The size of the pointer value in bits.<br>
+ GIM_CheckPointerToAny,<br>
/// Check the register bank for the specified operand<br>
/// - InsnID - Instruction ID<br>
/// - OpIdx - Operand index<br>
<br>
Modified: llvm/trunk/include/llvm/<wbr>CodeGen/GlobalISel/<wbr>InstructionSelectorImpl.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h?rev=315884&r1=315883&r2=315884&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/include/<wbr>llvm/CodeGen/GlobalISel/<wbr>InstructionSelectorImpl.h?rev=<wbr>315884&r1=315883&r2=315884&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/<wbr>CodeGen/GlobalISel/<wbr>InstructionSelectorImpl.h (original)<br>
+++ llvm/trunk/include/llvm/<wbr>CodeGen/GlobalISel/<wbr>InstructionSelectorImpl.h Sun Oct 15 17:56:30 2017<br>
@@ -244,7 +244,21 @@ bool InstructionSelector::<wbr>executeMatchTa<br>
}<br>
break;<br>
}<br>
-<br>
+ case GIM_CheckPointerToAny: {<br>
+ int64_t InsnID = MatchTable[CurrentIdx++];<br>
+ int64_t OpIdx = MatchTable[CurrentIdx++];<br>
+ int64_t SizeInBits = MatchTable[CurrentIdx++];<br>
+ DEBUG(dbgs() << CurrentIdx << ": GIM_CheckPointerToAny(MIs[" << InsnID<br>
+ << "]->getOperand(" << OpIdx<br>
+ << "), SizeInBits=" << SizeInBits << ")\n");<br>
+ assert(State.MIs[InsnID] != nullptr && "Used insn before defined");<br>
+ const LLT &Ty = MRI.getType(State.MIs[InsnID]-<wbr>>getOperand(OpIdx).getReg());<br>
+ if (!Ty.isPointer() || Ty.getSizeInBits() != SizeInBits) {<br>
+ if (handleReject() == RejectAndGiveUp)<br>
+ return false;<br>
+ }<br>
+ break;<br>
+ }<br>
case GIM_CheckRegBankForClass: {<br>
int64_t InsnID = MatchTable[CurrentIdx++];<br>
int64_t OpIdx = MatchTable[CurrentIdx++];<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/GlobalISel/select-<wbr>load.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir?rev=315884&r1=315883&r2=315884&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/GlobalISel/<wbr>select-load.mir?rev=315884&r1=<wbr>315883&r2=315884&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/GlobalISel/select-<wbr>load.mir (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/GlobalISel/select-<wbr>load.mir Sun Oct 15 17:56:30 2017<br>
@@ -1,5 +1,9 @@<br>
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s<br>
<br>
+# This patch temporarily causes LD1Onev1d to match instead of LDRDui on a<br>
+# couple functions. A patch to support iPTR will follow that fixes this.<br>
+# XFAIL: *<br>
+<br>
--- |<br>
target datalayout = "e-m:o-i64:64-i128:128-n32:64-<wbr>S128"<br>
<br>
@@ -28,6 +32,7 @@<br>
define void @load_gep_64_s16_fpr(i16* %addr) { ret void }<br>
define void @load_gep_32_s8_fpr(i8* %addr) { ret void }<br>
<br>
+ define void @load_v2s32(i64 *%addr) { ret void }<br>
...<br>
<br>
---<br>
@@ -513,3 +518,28 @@ body: |<br>
%3(s8) = G_LOAD %2 :: (load 1 from %ir.addr)<br>
%b0 = COPY %3<br>
...<br>
+---<br>
+# CHECK-LABEL: name: load_v2s32<br>
+name: load_v2s32<br>
+legalized: true<br>
+regBankSelected: true<br>
+<br>
+# CHECK: registers:<br>
+# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }<br>
+# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }<br>
+registers:<br>
+ - { id: 0, class: gpr }<br>
+ - { id: 1, class: fpr }<br>
+<br>
+# CHECK: body:<br>
+# CHECK: %0 = COPY %x0<br>
+# CHECK: %1 = LD1Onev2s %0<br>
+# CHECK: %d0 = COPY %1<br>
+body: |<br>
+ bb.0:<br>
+ liveins: %x0<br>
+<br>
+ %0(p0) = COPY %x0<br>
+ %1(<2 x s32>) = G_LOAD %0 :: (load 4 from %ir.addr)<br>
+ %d0 = COPY %1(<2 x s32>)<br>
+...<br>
<br>
Modified: llvm/trunk/test/TableGen/<wbr>GlobalISelEmitter.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/GlobalISelEmitter.td?rev=315884&r1=315883&r2=315884&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>TableGen/GlobalISelEmitter.td?<wbr>rev=315884&r1=315883&r2=<wbr>315884&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/TableGen/<wbr>GlobalISelEmitter.td (original)<br>
+++ llvm/trunk/test/TableGen/<wbr>GlobalISelEmitter.td Sun Oct 15 17:56:30 2017<br>
@@ -814,9 +814,29 @@ def MOVimm : I<(outs GPR32:$dst), (ins i<br>
def fpimmz : FPImmLeaf<f32, [{ return Imm->isExactlyValue(0.0); }]>;<br>
def MOVfpimmz : I<(outs FPR32:$dst), (ins f32imm:$imm), [(set FPR32:$dst, fpimmz:$imm)]>;<br>
<br>
-//===- Test a pattern with an MBB operand. ------------------------------<wbr>--===//<br>
+//===- Test a simple pattern with inferred pointer operands. ---------------===//<br>
<br>
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 22*/ [[LABEL:[0-9]+]],<br>
+// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,<br>
+// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,<br>
+// CHECK-NEXT: GIM_CheckNonAtomic, /*MI*/0,<br>
+// CHECK-NEXT: // MIs[0] dst<br>
+// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,<br>
+// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::<wbr>GPR32RegClassID,<br>
+// CHECK-NEXT: // MIs[0] src1<br>
+// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,<br>
+// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::<wbr>GPR32RegClassID,<br>
+// CHECK-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<<P:Predicate_<wbr>unindexedload>><<P:Predicate_<wbr>load>> => (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<br>
+// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD,<br>
+// CHECK-NEXT: GIR_<wbr>ConstrainSelectedInstOperands, /*InsnID*/0,<br>
+// CHECK-NEXT: GIR_Done,<br>
+// CHECK-NEXT: // Label 22: @[[LABEL]]<br>
+<br>
+def LOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),<br>
+ [(set GPR32:$dst, (load GPR32:$src1))]>;<br>
+//===- Test a pattern with an MBB operand. ------------------------------<wbr>--===//<br>
+<br>
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 23*/ [[LABEL:[0-9]+]],<br>
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,<br>
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_BR,<br>
// CHECK-NEXT: // MIs[0] target<br>
@@ -825,7 +845,7 @@ def MOVfpimmz : I<(outs FPR32:$dst), (in<br>
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::BR,<br>
// CHECK-NEXT: GIR_<wbr>ConstrainSelectedInstOperands, /*InsnID*/0,<br>
// CHECK-NEXT: GIR_Done,<br>
-// CHECK-NEXT: // Label 22: @[[LABEL]]<br>
+// CHECK-NEXT: // Label 23: @[[LABEL]]<br>
<br>
def BR : I<(outs), (ins unknown:$target),<br>
[(br bb:$target)]>;<br>
<br>
Modified: llvm/trunk/utils/TableGen/<wbr>GlobalISelEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp?rev=315884&r1=315883&r2=315884&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/utils/<wbr>TableGen/GlobalISelEmitter.<wbr>cpp?rev=315884&r1=315883&r2=<wbr>315884&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/<wbr>GlobalISelEmitter.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/<wbr>GlobalISelEmitter.cpp Sun Oct 15 17:56:30 2017<br>
@@ -103,6 +103,12 @@ public:<br>
OS << "GILLT_v" << Ty.getNumElements() << "s" << Ty.getScalarSizeInBits();<br>
return;<br>
}<br>
+ if (Ty.isPointer()) {<br>
+ OS << "GILLT_p" << Ty.getAddressSpace();<br>
+ if (Ty.getSizeInBits() > 0)<br>
+ OS << "s" << Ty.getSizeInBits();<br>
+ return;<br>
+ }<br>
llvm_unreachable("Unhandled LLT");<br>
}<br>
<br>
@@ -116,6 +122,11 @@ public:<br>
<< Ty.getScalarSizeInBits() << ")";<br>
return;<br>
}<br>
+ if (Ty.isPointer() && Ty.getSizeInBits() > 0) {<br>
+ OS << "LLT::pointer(" << Ty.getAddressSpace() << ", "<br>
+ << Ty.getSizeInBits() << ")";<br>
+ return;<br>
+ }<br>
llvm_unreachable("Unhandled LLT");<br>
}<br>
<br>
@@ -152,9 +163,11 @@ class InstructionMatcher;<br>
/// MVTs that don't map cleanly to an LLT (e.g., iPTR, *any, ...).<br>
static Optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT) {<br>
MVT VT(SVT);<br>
+<br>
if (VT.isVector() && VT.getVectorNumElements() != 1)<br>
return LLTCodeGen(<br>
LLT::vector(VT.<wbr>getVectorNumElements(), VT.getScalarSizeInBits()));<br>
+<br>
if (VT.isInteger() || VT.isFloatingPoint())<br>
return LLTCodeGen(LLT::scalar(VT.<wbr>getSizeInBits()));<br>
return None;<br>
@@ -228,6 +241,11 @@ static Error isTrivialOperatorNode(const<br>
if (Predicate.isImmediatePattern(<wbr>))<br>
continue;<br>
<br>
+ if (Predicate.isLoad() && Predicate.isUnindexed())<br>
+ continue;<br>
+<br>
+ if (Predicate.isNonExtLoad())<br>
+ continue;<br>
HasUnsupportedPredicate = true;<br>
Explanation = Separator + "Has a predicate (" + explainPredicates(N) + ")";<br>
Separator = ", ";<br>
@@ -661,6 +679,7 @@ public:<br>
OPM_Int,<br>
OPM_LiteralInt,<br>
OPM_LLT,<br>
+ OPM_PointerToAny,<br>
OPM_RegBank,<br>
OPM_MBB,<br>
};<br>
@@ -748,6 +767,37 @@ public:<br>
<br>
std::set<LLTCodeGen> LLTOperandMatcher::KnownTypes;<br>
<br>
+/// Generates code to check that an operand is a pointer to any address space.<br>
+///<br>
+/// In SelectionDAG, the types did not describe pointers or address spaces. As a<br>
+/// result, iN is used to describe a pointer of N bits to any address space and<br>
+/// PatFrag predicates are typically used to constrain the address space. There's<br>
+/// no reliable means to derive the missing type information from the pattern so<br>
+/// imported rules must test the components of a pointer separately.<br>
+///<br>
+/// SizeInBits must be non-zero and the matched pointer must be that size.<br>
+/// TODO: Add support for iPTR via SizeInBits==0 and a subtarget query.<br>
+class PointerToAnyOperandMatcher : public OperandPredicateMatcher {<br>
+protected:<br>
+ unsigned SizeInBits;<br>
+<br>
+public:<br>
+ PointerToAnyOperandMatcher(<wbr>unsigned SizeInBits)<br>
+ : OperandPredicateMatcher(OPM_<wbr>PointerToAny), SizeInBits(SizeInBits) {}<br>
+<br>
+ static bool classof(const OperandPredicateMatcher *P) {<br>
+ return P->getKind() == OPM_PointerToAny;<br>
+ }<br>
+<br>
+ void emitPredicateOpcodes(<wbr>MatchTable &Table, RuleMatcher &Rule,<br>
+ unsigned InsnVarID, unsigned OpIdx) const override {<br>
+ Table << MatchTable::Opcode("GIM_<wbr>CheckPointerToAny") << MatchTable::Comment("MI")<br>
+ << MatchTable::IntValue(<wbr>InsnVarID) << MatchTable::Comment("Op")<br>
+ << MatchTable::IntValue(OpIdx) << MatchTable::Comment("<wbr>SizeInBits")<br>
+ << MatchTable::IntValue(<wbr>SizeInBits) << MatchTable::LineBreak;<br>
+ }<br>
+};<br>
+<br>
/// Generates code to check that an operand is a particular target constant.<br>
class ComplexPatternOperandMatcher : public OperandPredicateMatcher {<br>
protected:<br>
@@ -927,6 +977,22 @@ public:<br>
<br>
InstructionMatcher &getInstructionMatcher() const { return Insn; }<br>
<br>
+ Error addTypeCheckPredicate(const TypeSetByHwMode &VTy,<br>
+ bool OperandIsAPointer) {<br>
+ auto OpTyOrNone = VTy.isMachineValueType()<br>
+ ? MVTToLLT(VTy.<wbr>getMachineValueType().<wbr>SimpleTy)<br>
+ : None;<br>
+ if (!OpTyOrNone)<br>
+ return failedImport("unsupported type");<br>
+<br>
+ if (OperandIsAPointer)<br>
+ addPredicate<<wbr>PointerToAnyOperandMatcher>(<br>
+ OpTyOrNone->get().<wbr>getSizeInBits());<br>
+ else<br>
+ addPredicate<<wbr>LLTOperandMatcher>(*<wbr>OpTyOrNone);<br>
+ return Error::success();<br>
+ }<br>
+<br>
/// Emit MatchTable opcodes to capture instructions into the MIs table.<br>
void emitCaptureOpcodes(MatchTable &Table, RuleMatcher &Rule,<br>
unsigned InsnVarID) const {<br>
@@ -2070,7 +2136,8 @@ private:<br>
Error importComplexPatternOperandMat<wbr>cher(OperandMatcher &OM, Record *R,<br>
unsigned &TempOpIdx) const;<br>
Error importChildMatcher(RuleMatcher &Rule, InstructionMatcher &InsnMatcher,<br>
- const TreePatternNode *SrcChild, unsigned OpIdx,<br>
+ const TreePatternNode *SrcChild,<br>
+ bool OperandIsAPointer, unsigned OpIdx,<br>
unsigned &TempOpIdx) const;<br>
Expected<BuildMIAction &><br>
createAndImportInstructionRend<wbr>erer(RuleMatcher &M, const TreePatternNode *Dst,<br>
@@ -2164,17 +2231,12 @@ Expected<InstructionMatcher &> GlobalISe<br>
<br>
unsigned OpIdx = 0;<br>
for (const TypeSetByHwMode &VTy : Src->getExtTypes()) {<br>
- auto OpTyOrNone = VTy.isMachineValueType()<br>
- ? MVTToLLT(VTy.<wbr>getMachineValueType().<wbr>SimpleTy)<br>
- : None;<br>
- if (!OpTyOrNone)<br>
- return failedImport(<br>
- "Result of Src pattern operator has an unsupported type");<br>
-<br>
// Results don't have a name unless they are the root node. The caller will<br>
// set the name if appropriate.<br>
OperandMatcher &OM = InsnMatcher.addOperand(OpIdx++<wbr>, "", TempOpIdx);<br>
- OM.addPredicate<<wbr>LLTOperandMatcher>(*<wbr>OpTyOrNone);<br>
+ if (auto Error = OM.addTypeCheckPredicate(VTy, false /* OperandIsAPointer */))<br>
+ return failedImport(toString(std::<wbr>move(Error)) +<br>
+ " for result of Src pattern operator");<br>
}<br>
<br>
for (const auto &Predicate : Src->getPredicateFns()) {<br>
@@ -2186,6 +2248,25 @@ Expected<InstructionMatcher &> GlobalISe<br>
continue;<br>
}<br>
<br>
+ // No check required. A G_LOAD is an unindexed load.<br>
+ if (Predicate.isLoad() && Predicate.isUnindexed())<br>
+ continue;<br>
+<br>
+ // No check required. G_LOAD by itself is a non-extending load.<br>
+ if (Predicate.isNonExtLoad())<br>
+ continue;<br>
+<br>
+ if (Predicate.isLoad() && Predicate.getMemoryVT() != nullptr) {<br>
+ Optional<LLTCodeGen> MemTyOrNone =<br>
+ MVTToLLT(getValueType(<wbr>Predicate.getMemoryVT()));<br>
+<br>
+ if (!MemTyOrNone)<br>
+ return failedImport("MemVT could not be converted to LLT");<br>
+<br>
+ InsnMatcher.getOperand(0).<wbr>addPredicate<<wbr>LLTOperandMatcher>(<wbr>MemTyOrNone.getValue());<br>
+ continue;<br>
+ }<br>
+<br>
return failedImport("Src pattern child has predicate (" +<br>
explainPredicates(Src) + ")");<br>
}<br>
@@ -2217,6 +2298,13 @@ Expected<InstructionMatcher &> GlobalISe<br>
for (unsigned i = 0, e = Src->getNumChildren(); i != e; ++i) {<br>
TreePatternNode *SrcChild = Src->getChild(i);<br>
<br>
+ // SelectionDAG allows pointers to be represented with iN since it doesn't<br>
+ // distinguish between pointers and integers but they are different types in GlobalISel.<br>
+ // Coerce integers to pointers to address space 0 if the context indicates a pointer.<br>
+ // TODO: Find a better way to do this, SDTCisPtrTy?<br>
+ bool OperandIsAPointer =<br>
+ SrcGIOrNull->TheDef->getName() == "G_LOAD" && i == 0;<br>
+<br>
// For G_INTRINSIC/G_INTRINSIC_W_<wbr>SIDE_EFFECTS, the operand immediately<br>
// following the defs is an intrinsic ID.<br>
if ((SrcGIOrNull->TheDef-><wbr>getName() == "G_INTRINSIC" ||<br>
@@ -2232,8 +2320,9 @@ Expected<InstructionMatcher &> GlobalISe<br>
return failedImport("Expected IntInit containing instrinsic ID)");<br>
}<br>
<br>
- if (auto Error = importChildMatcher(Rule, InsnMatcher, SrcChild, OpIdx++,<br>
- TempOpIdx))<br>
+ if (auto Error =<br>
+ importChildMatcher(Rule, InsnMatcher, SrcChild, OperandIsAPointer,<br>
+ OpIdx++, TempOpIdx))<br>
return std::move(Error);<br>
}<br>
}<br>
@@ -2256,6 +2345,7 @@ Error GlobalISelEmitter::<wbr>importComplexPa<br>
Error GlobalISelEmitter::<wbr>importChildMatcher(RuleMatcher &Rule,<br>
InstructionMatcher &InsnMatcher,<br>
const TreePatternNode *SrcChild,<br>
+ bool OperandIsAPointer,<br>
unsigned OpIdx,<br>
unsigned &TempOpIdx) const {<br>
OperandMatcher &OM =<br>
@@ -2278,12 +2368,10 @@ Error GlobalISelEmitter::<wbr>importChildMatc<br>
}<br>
}<br>
<br>
- Optional<LLTCodeGen> OpTyOrNone = None;<br>
- if (ChildTypes.front().<wbr>isMachineValueType())<br>
- OpTyOrNone = MVTToLLT(ChildTypes.front().<wbr>getMachineValueType().<wbr>SimpleTy);<br>
- if (!OpTyOrNone)<br>
- return failedImport("Src operand has an unsupported type (" + to_string(*SrcChild) + ")");<br>
- OM.addPredicate<<wbr>LLTOperandMatcher>(*<wbr>OpTyOrNone);<br>
+ if (auto Error =<br>
+ OM.addTypeCheckPredicate(<wbr>ChildTypes.front(), OperandIsAPointer))<br>
+ return failedImport(toString(std::<wbr>move(Error)) + " for Src operand (" +<br>
+ to_string(*SrcChild) + ")");<br>
<br>
// Check for nested instructions.<br>
if (!SrcChild->isLeaf()) {<br>
<br>
<br>
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</blockquote></div><br></div>