<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">Re-committed as <span style="font-family: Menlo; font-size: 11px; background-color: rgb(255, 255, 255);" class="">r315947</span><div><br class=""></div><div>The mapping of G_BITCAST was not dealing with scalar type bigger than 64-bit<br class=""><blockquote type="cite" class=""><div class="">On Oct 16, 2017, at 8:47 AM, Quentin Colombet via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="">Thanks Bruno.<br class=""><br class="">I’ll take a look.<br class=""><br class=""><blockquote type="cite" class="">On Oct 14, 2017, at 12:31 PM, Bruno Cardoso Lopes <<a href="mailto:bruno.cardoso@gmail.com" class="">bruno.cardoso@gmail.com</a>> wrote:<br class=""><br class="">Hi Quentin,<br class=""><br class="">Reverted this in r315823 because it broke:<br class=""><a href="http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/9882" class="">http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/9882</a><br class=""><br class="">On Fri, Oct 13, 2017 at 5:43 PM, Quentin Colombet via llvm-commits<br class=""><llvm-commits@lists.llvm.org> wrote:<br class=""><blockquote type="cite" class="">Author: qcolombet<br class="">Date: Fri Oct 13 17:43:48 2017<br class="">New Revision: 315781<br class=""><br class="">URL: http://llvm.org/viewvc/llvm-project?rev=315781&view=rev<br class="">Log:<br class="">[AArch64][RegisterBankInfo] Use the statically computed mappings for COPY<br class=""><br class="">We use to resort on the generic implementation to get the mappings for<br class="">COPYs. The generic implementation resorts on table lookup and<br class="">dynamically allocated objects to get the valid mappings.<br class=""><br class="">Given we already know how to map G_BITCAST and have the static mappings<br class="">for them, use that code path for COPY as well. This is much more<br class="">efficient.<br class=""><br class="">Improve the compile time of RegBankSelect by up to 20%.<br class=""><br class="">Note: When we eventually generate all the mappings via TableGen, we<br class="">wouldn't have to do that dance to shave compile time. The intent of this<br class="">change was to make sure that moving to static structure really pays off.<br class=""><br class="">NFC.<br class=""><br class="">Modified:<br class=""> llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp<br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp<br class="">URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=315781&r1=315780&r2=315781&view=diff<br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Fri Oct 13 17:43:48 2017<br class="">@@ -415,12 +415,10 @@ AArch64RegisterBankInfo::getSameKindOfOp<br class="">const RegisterBankInfo::InstructionMapping &<br class="">AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {<br class=""> const unsigned Opc = MI.getOpcode();<br class="">- const MachineFunction &MF = *MI.getParent()->getParent();<br class="">- const MachineRegisterInfo &MRI = MF.getRegInfo();<br class=""><br class=""> // Try the default logic for non-generic instructions that are either copies<br class=""> // or already have some operands assigned to banks.<br class="">- if (!isPreISelGenericOpcode(Opc) ||<br class="">+ if ((Opc != TargetOpcode::COPY && !isPreISelGenericOpcode(Opc)) ||<br class=""> Opc == TargetOpcode::G_PHI) {<br class=""> const RegisterBankInfo::InstructionMapping &Mapping =<br class=""> getInstrMappingImpl(MI);<br class="">@@ -428,6 +426,11 @@ AArch64RegisterBankInfo::getInstrMapping<br class=""> return Mapping;<br class=""> }<br class=""><br class="">+ const MachineFunction &MF = *MI.getParent()->getParent();<br class="">+ const MachineRegisterInfo &MRI = MF.getRegInfo();<br class="">+ const TargetSubtargetInfo &STI = MF.getSubtarget();<br class="">+ const TargetRegisterInfo &TRI = *STI.getRegisterInfo();<br class="">+<br class=""> switch (Opc) {<br class=""> // G_{F|S|U}REM are not listed because they are not legal.<br class=""> // Arithmetic ops.<br class="">@@ -451,6 +454,30 @@ AArch64RegisterBankInfo::getInstrMapping<br class=""> case TargetOpcode::G_FMUL:<br class=""> case TargetOpcode::G_FDIV:<br class=""> return getSameKindOfOperandsMapping(MI);<br class="">+ case TargetOpcode::COPY: {<br class="">+ unsigned DstReg = MI.getOperand(0).getReg();<br class="">+ unsigned SrcReg = MI.getOperand(1).getReg();<br class="">+ if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||<br class="">+ TargetRegisterInfo::isPhysicalRegister(SrcReg)) {<br class="">+ const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI);<br class="">+ const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);<br class="">+ if (!DstRB)<br class="">+ DstRB = SrcRB;<br class="">+ else if (!SrcRB)<br class="">+ SrcRB = DstRB;<br class="">+ // If both RB are null that means both registers are generic.<br class="">+ // We shouldn't be here.<br class="">+ assert(DstRB && SrcRB && "Both RegBank were nullptr");<br class="">+ unsigned Size = getSizeInBits(DstReg, MRI, TRI);<br class="">+ return getInstructionMapping(<br class="">+ DefaultMappingID, copyCost(*DstRB, *SrcRB, Size),<br class="">+ getCopyMapping(DstRB->getID(), SrcRB->getID(), Size),<br class="">+ // We only care about the mapping of the destination.<br class="">+ /*NumOperands*/ 1);<br class="">+ }<br class="">+ // Both registers are generic, use G_BITCAST.<br class="">+ LLVM_FALLTHROUGH;<br class="">+ }<br class=""> case TargetOpcode::G_BITCAST: {<br class=""> LLT DstTy = MRI.getType(MI.getOperand(0).getReg());<br class=""> LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());<br class="">@@ -464,7 +491,8 @@ AArch64RegisterBankInfo::getInstrMapping<br class=""> return getInstructionMapping(<br class=""> DefaultMappingID, copyCost(DstRB, SrcRB, Size),<br class=""> getCopyMapping(DstRB.getID(), SrcRB.getID(), Size),<br class="">- /*NumOperands*/ 2);<br class="">+ // We only care about the mapping of the destination for COPY.<br class="">+ /*NumOperands*/ Opc == TargetOpcode::G_BITCAST ? 2 : 1);<br class=""> }<br class=""> default:<br class=""> break;<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class="">llvm-commits@lists.llvm.org<br class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits<br class=""></blockquote><br class=""><br class=""><br class="">-- <br class="">Bruno Cardoso Lopes<br class="">http://www.brunocardoso.cc<br class=""></blockquote><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits<br class=""></div></div></blockquote></div><br class=""></body></html>