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<p>Yes indeed, I agree. Will make the change.</p>
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<div id="x_divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> aemerson@apple.com <aemerson@apple.com> on behalf of Amara Emerson <aemerson@apple.com><br>
<b>Sent:</b> 08 October 2017 20:32:18<br>
<b>To:</b> Javed Absar<br>
<b>Cc:</b> llvm-commits@lists.llvm.org<br>
<b>Subject:</b> Re: [llvm] r315183 - [TableGen] Simplify, add range_loop in CodeGenSchedule</font>
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> @@ -830,16 +830,16 @@ void CodeGenSchedModels::collectProcItin<br>
> void CodeGenSchedModels::collectProcItinRW() {<br>
> RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");<br>
> std::sort(ItinRWDefs.begin(), ItinRWDefs.end(), LessRecord());<br>
> - for (RecIter II = ItinRWDefs.begin(), IE = ItinRWDefs.end(); II != IE; ++II) {<br>
> - if (!(*II)->getValueInit("SchedModel")->isComplete())<br>
> - PrintFatalError((*II)->getLoc(), "SchedModel is undefined");<br>
> - Record *ModelDef = (*II)->getValueAsDef("SchedModel");<br>
> + for (Record *RWDef : make_range(ItinRWDefs.begin(), ItinRWDefs.end())) {<br>
You don’t need a make_range here.<br>
<br>
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