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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Is 34175 still failing post l311255. <o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">>> No. Everything seems to pass successfully. Thanks</span><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Review D35788 is in accepted state. <o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">>> I should have probably blocked it with a ‘Request change’ when re-opening. If the latest changes looks good to Simon then its fine by me.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Thanks, Elad</span><o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></a></p>
<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Jatin Bhateja [mailto:jatin.bhateja@gmail.com]
<br>
<b>Sent:</b> Sunday, August 20, 2017 13:48<br>
<b>To:</b> Blank, Guy <guy.blank@intel.com><br>
<b>Cc:</b> llvm-commits <llvm-commits@lists.llvm.org>; Cohen, Elad2 <elad2.cohen@intel.com>; llvm-dev@redking.me.uk<br>
<b>Subject:</b> Re: [llvm] r311255 - [DAGCombiner] Extending pattern detection for vector shuffle.<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Hi Guy, Elad,<o:p></o:p></p>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<p class="MsoNormal">Is 34175 still failing post l311255. <o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
<div>
<p class="MsoNormal">Review D35788 is in accepted state. <o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
<div>
<p class="MsoNormal">Thanks,<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal">Jatin<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"><br>
On Sunday, August 20, 2017, Blank, Guy <<a href="mailto:guy.blank@intel.com">guy.blank@intel.com</a>> wrote:<o:p></o:p></p>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-right:0cm">
<p class="MsoNormal">Why has this been committed? I don't any review/approval for the changes handling PR34175.<br>
<br>
<br>
-----Original Message-----<br>
From: llvm-commits [mailto:<a href="javascript:;">llvm-commits-bounces@lists.llvm.org</a>] On Behalf Of Jatin Bhateja via llvm-commits<br>
Sent: Saturday, August 19, 2017 21:09<br>
To: <a href="javascript:;">llvm-commits@lists.llvm.org</a><br>
Subject: [llvm] r311255 - [DAGCombiner] Extending pattern detection for vector shuffle.<br>
<br>
Author: jbhateja<br>
Date: Sat Aug 19 11:08:59 2017<br>
New Revision: 311255<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=311255&view=rev" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=311255&view=rev</a><br>
Log:<br>
[DAGCombiner] Extending pattern detection for vector shuffle.<br>
<br>
Summary:<br>
If all the operands of a BUILD_VECTOR extract elements from same vector then split the<br>
vector efficiently based on the maximum vector access index.<br>
<br>
Reviewers: zvi, delena, RKSimon, thakis<br>
<br>
Reviewed By: RKSimon<br>
<br>
Subscribers: chandlerc, eladcohen, llvm-commits<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D35788" target="_blank">
https://reviews.llvm.org/D35788</a><br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
llvm/trunk/test/CodeGen/X86/shuffle-vs-trunc-512.ll<br>
llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v16.ll<br>
llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v8.ll<br>
llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=311255&r1=311254&r2=311255&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=311255&r1=311254&r2=311255&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Aug 19<br>
+++ 11:08:59 2017<br>
@@ -14190,10 +14190,18 @@ SDValue DAGCombiner::createBuildVecShuff<br>
EVT InVT1 = VecIn1.getValueType();<br>
EVT InVT2 = VecIn2.getNode() ? VecIn2.getValueType() : InVT1;<br>
<br>
- unsigned Vec2Offset = InVT1.getVectorNumElements();<br>
+ unsigned Vec2Offset = 0;<br>
unsigned NumElems = VT.getVectorNumElements();<br>
unsigned ShuffleNumElems = NumElems;<br>
<br>
+ // In case both the input vectors are extracted from same base //<br>
+ vector we do not need extra addend (Vec2Offset) while // computing<br>
+ shuffle mask.<br>
+ if (!VecIn2 || !(VecIn1.getOpcode() == ISD::EXTRACT_SUBVECTOR) ||<br>
+ !(VecIn2.getOpcode() == ISD::EXTRACT_SUBVECTOR) ||<br>
+ !(VecIn1.getOperand(0) == VecIn2.getOperand(0)))<br>
+ Vec2Offset = InVT1.getVectorNumElements();<br>
+<br>
// We can't generate a shuffle node with mismatched input and output types.<br>
// Try to make the types match the type of the output.<br>
if (InVT1 != VT || InVT2 != VT) {<br>
@@ -14340,7 +14348,6 @@ SDValue DAGCombiner::reduceBuildVecToShu<br>
if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||<br>
!isa<ConstantSDNode>(Op.getOperand(1)))<br>
return SDValue();<br>
-<br>
SDValue ExtractedFromVec = Op.getOperand(0);<br>
<br>
// All inputs must have the same element type as the output.<br>
@@ -14363,6 +14370,50 @@ SDValue DAGCombiner::reduceBuildVecToShu<br>
if (VecIn.size() < 2)<br>
return SDValue();<br>
<br>
+ // If all the Operands of BUILD_VECTOR extract from same // vector,<br>
+ then split the vector efficiently based on the maximum // vector<br>
+ access index and adjust the VectorMask and // VecIn accordingly.<br>
+ if (VecIn.size() == 2) {<br>
+ unsigned MaxIndex = 0;<br>
+ unsigned NearestPow2 = 0;<br>
+ SDValue Vec = VecIn.back();<br>
+ EVT InVT = Vec.getValueType();<br>
+ MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());<br>
+ SmallVector<unsigned, 8> IndexVec(NumElems, 0);<br>
+<br>
+ for (unsigned i = 0; i < NumElems; i++) {<br>
+ if (VectorMask[i] <= 0)<br>
+ continue;<br>
+ unsigned Index = N->getOperand(i).getConstantOperandVal(1);<br>
+ IndexVec[i] = Index;<br>
+ MaxIndex = std::max(MaxIndex, Index);<br>
+ }<br>
+<br>
+ NearestPow2 = PowerOf2Ceil(MaxIndex);<br>
+ if (InVT.isSimple() && (NearestPow2 > 2) &&<br>
+ ((NumElems * 2) < NearestPow2)) {<br>
+ unsigned SplitSize = NearestPow2 / 2;<br>
+ EVT SplitVT = EVT::getVectorVT(*DAG.getContext(),<br>
+ InVT.getVectorElementType(), SplitSize);<br>
+ if (TLI.isTypeLegal(SplitVT)) {<br>
+ SDValue VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec,<br>
+ DAG.getConstant(SplitSize, DL, IdxTy));<br>
+ SDValue VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec,<br>
+ DAG.getConstant(0, DL, IdxTy));<br>
+ VecIn.pop_back();<br>
+ VecIn.push_back(VecIn1);<br>
+ VecIn.push_back(VecIn2);<br>
+<br>
+ for (unsigned i = 0; i < NumElems; i++) {<br>
+ if (VectorMask[i] <= 0)<br>
+ continue;<br>
+ VectorMask[i] = (IndexVec[i] < SplitSize) ? 1 : 2;<br>
+ }<br>
+ }<br>
+ }<br>
+ }<br>
+<br>
// TODO: We want to sort the vectors by descending length, so that adjacent<br>
// pairs have similar length, and the longer vector is always first in the<br>
// pair.<br>
@@ -14451,7 +14502,6 @@ SDValue DAGCombiner::reduceBuildVecToShu<br>
DAG.getVectorShuffle(VT, DL, Shuffles[Left], Shuffles[Right], Mask);<br>
}<br>
}<br>
-<br>
return Shuffles[0];<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/shuffle-vs-trunc-512.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shuffle-vs-trunc-512.ll?rev=311255&r1=311254&r2=311255&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shuffle-vs-trunc-512.ll?rev=311255&r1=311254&r2=311255&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/shuffle-vs-trunc-512.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/shuffle-vs-trunc-512.ll Sat Aug 19<br>
+++ 11:08:59 2017<br>
@@ -311,83 +311,93 @@ define <16 x i8> @trunc_shuffle_v64i8_01 ; ; AVX512BW-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_62:<br>
; AVX512BW: # BB#0:<br>
-; AVX512BW-NEXT: vpextrb $5, %xmm0, %eax<br>
-; AVX512BW-NEXT: vpextrb $1, %xmm0, %ecx<br>
-; AVX512BW-NEXT: vmovd %ecx, %xmm1<br>
-; AVX512BW-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vpextrb $9, %xmm0, %eax<br>
-; AVX512BW-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vpextrb $13, %xmm0, %eax<br>
-; AVX512BW-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vextracti32x4 $1, %zmm0, %xmm2<br>
-; AVX512BW-NEXT: vpextrb $1, %xmm2, %eax<br>
-; AVX512BW-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vpextrb $5, %xmm2, %eax<br>
-; AVX512BW-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vpextrb $9, %xmm2, %eax<br>
-; AVX512BW-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vpextrb $13, %xmm2, %eax<br>
-; AVX512BW-NEXT: vpinsrb $7, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vextracti32x4 $2, %zmm0, %xmm2<br>
-; AVX512BW-NEXT: vpextrb $1, %xmm2, %eax<br>
-; AVX512BW-NEXT: vpinsrb $8, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vpextrb $5, %xmm2, %eax<br>
-; AVX512BW-NEXT: vpinsrb $9, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vpextrb $9, %xmm2, %eax<br>
-; AVX512BW-NEXT: vpinsrb $10, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vpextrb $13, %xmm2, %eax<br>
-; AVX512BW-NEXT: vpinsrb $11, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vextracti32x4 $3, %zmm0, %xmm0<br>
-; AVX512BW-NEXT: vpextrb $1, %xmm0, %eax<br>
-; AVX512BW-NEXT: vpinsrb $12, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vpextrb $5, %xmm0, %eax<br>
-; AVX512BW-NEXT: vpinsrb $13, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vpextrb $9, %xmm0, %eax<br>
-; AVX512BW-NEXT: vpinsrb $14, %eax, %xmm1, %xmm1<br>
-; AVX512BW-NEXT: vpextrb $14, %xmm0, %eax<br>
-; AVX512BW-NEXT: vpinsrb $15, %eax, %xmm1, %xmm0<br>
+; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1<br>
+; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm2 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u><br>
+; AVX512BW-NEXT: vpshufb %xmm2, %xmm1, %xmm1<br>
+; AVX512BW-NEXT: vpshufb %xmm2, %xmm0, %xmm2<br>
+; AVX512BW-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]<br>
+; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm0<br>
+; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm2<br>
+; AVX512BW-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[u,u,u,u,1,5,9,14,u,u,u,u,u,u,u,u]<br>
+; AVX512BW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u]<br>
+; AVX512BW-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]<br>
+; AVX512BW-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]<br>
; AVX512BW-NEXT: vzeroupper<br>
; AVX512BW-NEXT: retq<br>
;<br>
; AVX512BWVL-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_62:<br>
; AVX512BWVL: # BB#0:<br>
-; AVX512BWVL-NEXT: vpextrb $5, %xmm0, %eax<br>
-; AVX512BWVL-NEXT: vpextrb $1, %xmm0, %ecx<br>
-; AVX512BWVL-NEXT: vmovd %ecx, %xmm1<br>
-; AVX512BWVL-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vpextrb $9, %xmm0, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vpextrb $13, %xmm0, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vextracti32x4 $1, %zmm0, %xmm2<br>
-; AVX512BWVL-NEXT: vpextrb $1, %xmm2, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vpextrb $5, %xmm2, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vpextrb $9, %xmm2, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vpextrb $13, %xmm2, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $7, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vextracti32x4 $2, %zmm0, %xmm2<br>
-; AVX512BWVL-NEXT: vpextrb $1, %xmm2, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $8, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vpextrb $5, %xmm2, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $9, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vpextrb $9, %xmm2, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $10, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vpextrb $13, %xmm2, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $11, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vextracti32x4 $3, %zmm0, %xmm0<br>
-; AVX512BWVL-NEXT: vpextrb $1, %xmm0, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $12, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vpextrb $5, %xmm0, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $13, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vpextrb $9, %xmm0, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $14, %eax, %xmm1, %xmm1<br>
-; AVX512BWVL-NEXT: vpextrb $14, %xmm0, %eax<br>
-; AVX512BWVL-NEXT: vpinsrb $15, %eax, %xmm1, %xmm0<br>
+; AVX512BWVL-NEXT: vextracti128 $1, %ymm0, %xmm1<br>
+; AVX512BWVL-NEXT: vmovdqa {{.*#+}} xmm2 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u><br>
+; AVX512BWVL-NEXT: vpshufb %xmm2, %xmm1, %xmm1<br>
+; AVX512BWVL-NEXT: vpshufb %xmm2, %xmm0, %xmm2<br>
+; AVX512BWVL-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]<br>
+; AVX512BWVL-NEXT: vextracti64x4 $1, %zmm0, %ymm0<br>
+; AVX512BWVL-NEXT: vextracti128 $1, %ymm0, %xmm2<br>
+; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[u,u,u,u,1,5,9,14,u,u,u,u,u,u,u,u]<br>
+; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u]<br>
+; AVX512BWVL-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]<br>
+; AVX512BWVL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]<br>
; AVX512BWVL-NEXT: vzeroupper<br>
; AVX512BWVL-NEXT: retq<br>
%res = shufflevector <64 x i8> %x, <64 x i8> %x, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 62><br>
ret <16 x i8> %res<br>
}<br>
+<br>
+define <4 x double> @PR34175(<32 x i16>* %p) { ; AVX512F-LABEL:<br>
+PR34175:<br>
+; AVX512F: # BB#0:<br>
+; AVX512F-NEXT: vmovdqu (%rdi), %ymm0<br>
+; AVX512F-NEXT: vmovdqu 32(%rdi), %ymm1<br>
+; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm2<br>
+; AVX512F-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]<br>
+; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm2<br>
+; AVX512F-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]<br>
+; AVX512F-NEXT: vpbroadcastd %xmm1, %xmm1<br>
+; AVX512F-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]<br>
+; AVX512F-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero<br>
+; AVX512F-NEXT: vcvtdq2pd %xmm0, %ymm0<br>
+; AVX512F-NEXT: retq<br>
+;<br>
+; AVX512VL-LABEL: PR34175:<br>
+; AVX512VL: # BB#0:<br>
+; AVX512VL-NEXT: vmovdqu (%rdi), %ymm0<br>
+; AVX512VL-NEXT: vmovdqu 32(%rdi), %ymm1<br>
+; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm2<br>
+; AVX512VL-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]<br>
+; AVX512VL-NEXT: vextracti128 $1, %ymm1, %xmm2<br>
+; AVX512VL-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]<br>
+; AVX512VL-NEXT: vpbroadcastd %xmm1, %xmm1<br>
+; AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]<br>
+; AVX512VL-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero<br>
+; AVX512VL-NEXT: vcvtdq2pd %xmm0, %ymm0<br>
+; AVX512VL-NEXT: retq<br>
+;<br>
+; AVX512BW-LABEL: PR34175:<br>
+; AVX512BW: # BB#0:<br>
+; AVX512BW-NEXT: vmovdqu64 (%rdi), %zmm0<br>
+; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1<br>
+; AVX512BW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]<br>
+; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm0<br>
+; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm2<br>
+; AVX512BW-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]<br>
+; AVX512BW-NEXT: vpbroadcastd %xmm0, %xmm0<br>
+; AVX512BW-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]<br>
+; AVX512BW-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero<br>
+; AVX512BW-NEXT: vcvtdq2pd %xmm0, %ymm0<br>
+; AVX512BW-NEXT: retq<br>
+;<br>
+; AVX512BWVL-LABEL: PR34175:<br>
+; AVX512BWVL: # BB#0:<br>
+; AVX512BWVL-NEXT: vmovdqu64 (%rdi), %zmm0<br>
+; AVX512BWVL-NEXT: vextracti64x4 $1, %zmm0, %ymm1<br>
+; AVX512BWVL-NEXT: vmovdqa {{.*#+}} ymm2 = <0,8,16,24,u,u,u,u,u,u,u,u,u,u,u,u><br>
+; AVX512BWVL-NEXT: vpermi2w %ymm1, %ymm0, %ymm2<br>
+; AVX512BWVL-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero<br>
+; AVX512BWVL-NEXT: vcvtdq2pd %xmm0, %ymm0<br>
+; AVX512BWVL-NEXT: retq<br>
+ %v = load <32 x i16>, <32 x i16>* %p, align 2<br>
+ %shuf = shufflevector <32 x i16> %v, <32 x i16> undef, <4 x i32> <i32<br>
+0, i32 8, i32 16, i32 24><br>
+ %tofp = uitofp <4 x i16> %shuf to <4 x double><br>
+ ret <4 x double> %tofp<br>
+}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v16.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v16.ll?rev=311255&r1=311254&r2=311255&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v16.ll?rev=311255&r1=311254&r2=311255&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v16.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v16.ll Sat Aug 19<br>
+++ 11:08:59 2017<br>
@@ -286,13 +286,10 @@ define <8 x i32> @test_v16i32_1_3_5_7_9_ define <4 x i32> @test_v16i32_0_1_2_12 (<16 x i32> %v) { ; ALL-LABEL: test_v16i32_0_1_2_12:<br>
; ALL: # BB#0:<br>
-; ALL-NEXT: vpextrd $1, %xmm0, %eax<br>
-; ALL-NEXT: vpinsrd $1, %eax, %xmm0, %xmm1<br>
-; ALL-NEXT: vpextrd $2, %xmm0, %eax<br>
-; ALL-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1<br>
-; ALL-NEXT: vextracti32x4 $3, %zmm0, %xmm0<br>
-; ALL-NEXT: vmovd %xmm0, %eax<br>
-; ALL-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0<br>
+; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm1<br>
+; ALL-NEXT: vextracti128 $1, %ymm1, %xmm1<br>
+; ALL-NEXT: vpbroadcastd %xmm1, %xmm1<br>
+; ALL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]<br>
; ALL-NEXT: vzeroupper<br>
; ALL-NEXT: retq<br>
%res = shufflevector <16 x i32> %v, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 12><br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v8.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v8.ll?rev=311255&r1=311254&r2=311255&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v8.ll?rev=311255&r1=311254&r2=311255&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v8.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v8.ll Sat Aug 19<br>
+++ 11:08:59 2017<br>
@@ -2726,20 +2726,17 @@ define <4 x i64> @test_v8i64_1257 (<8 x define <2 x i64> @test_v8i64_2_5 (<8 x i64> %v) { ; AVX512F-LABEL: test_v8i64_2_5:<br>
; AVX512F: # BB#0:<br>
-; AVX512F-NEXT: vextracti32x4 $2, %zmm0, %xmm1<br>
-; AVX512F-NEXT: vextracti32x4 $1, %zmm0, %xmm0<br>
+; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm1<br>
+; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0<br>
; AVX512F-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]<br>
; AVX512F-NEXT: vzeroupper<br>
; AVX512F-NEXT: retq<br>
;<br>
; AVX512F-32-LABEL: test_v8i64_2_5:<br>
; AVX512F-32: # BB#0:<br>
-; AVX512F-32-NEXT: vextracti32x4 $1, %zmm0, %xmm1<br>
-; AVX512F-32-NEXT: vextracti32x4 $2, %zmm0, %xmm0<br>
-; AVX512F-32-NEXT: vpextrd $2, %xmm0, %eax<br>
-; AVX512F-32-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1<br>
-; AVX512F-32-NEXT: vpextrd $3, %xmm0, %eax<br>
-; AVX512F-32-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0<br>
+; AVX512F-32-NEXT: vextracti64x4 $1, %zmm0, %ymm1<br>
+; AVX512F-32-NEXT: vextracti128 $1, %ymm0, %xmm0<br>
+; AVX512F-32-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]<br>
; AVX512F-32-NEXT: vzeroupper<br>
; AVX512F-32-NEXT: retl<br>
%res = shufflevector <8 x i64> %v, <8 x i64> undef, <2 x i32> <i32 2, i32 5><br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll?rev=311255&r1=311254&r2=311255&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll?rev=311255&r1=311254&r2=311255&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll Sat Aug 19<br>
+++ 11:08:59 2017<br>
@@ -567,37 +567,37 @@ define <16 x i1> @interleaved_load_vf16_<br>
; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]<br>
; AVX2-NEXT: vpshufb %xmm4, %xmm2, %xmm2<br>
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]<br>
-; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm3<br>
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u><br>
-; AVX2-NEXT: vpshufb %xmm4, %xmm3, %xmm5<br>
-; AVX2-NEXT: vpshufb %xmm4, %xmm1, %xmm4<br>
-; AVX2-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]<br>
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm5<br>
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm6 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u><br>
-; AVX2-NEXT: vpshufb %xmm6, %xmm5, %xmm7<br>
-; AVX2-NEXT: vpshufb %xmm6, %xmm0, %xmm6<br>
-; AVX2-NEXT: vpunpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]<br>
-; AVX2-NEXT: vpblendd {{.*#+}} xmm4 = xmm6[0,1],xmm4[2,3]<br>
-; AVX2-NEXT: vpcmpeqb %xmm4, %xmm2, %xmm2<br>
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <u,u,u,u,2,6,10,14,u,u,u,u,u,u,u,u><br>
-; AVX2-NEXT: vpshufb %xmm4, %xmm3, %xmm6<br>
-; AVX2-NEXT: vpshufb %xmm4, %xmm1, %xmm4<br>
-; AVX2-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm4[0],xmm6[0],xmm4[1],xmm6[1]<br>
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm6 = <2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u><br>
-; AVX2-NEXT: vpshufb %xmm6, %xmm5, %xmm7<br>
-; AVX2-NEXT: vpshufb %xmm6, %xmm0, %xmm6<br>
-; AVX2-NEXT: vpunpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]<br>
-; AVX2-NEXT: vpblendd {{.*#+}} xmm4 = xmm6[0,1],xmm4[2,3]<br>
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm6 = <u,u,u,u,3,7,11,15,u,u,u,u,u,u,u,u><br>
-; AVX2-NEXT: vpshufb %xmm6, %xmm3, %xmm3<br>
-; AVX2-NEXT: vpshufb %xmm6, %xmm1, %xmm1<br>
-; AVX2-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]<br>
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <3,7,11,15,u,u,u,u,u,u,u,u,u,u,u,u><br>
-; AVX2-NEXT: vpshufb %xmm3, %xmm5, %xmm5<br>
-; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0<br>
+; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u><br>
+; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm4<br>
+; AVX2-NEXT: vpshufb %xmm3, %xmm4, %xmm5<br>
+; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm3<br>
+; AVX2-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1]<br>
+; AVX2-NEXT: vmovdqa {{.*#+}} xmm5 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u><br>
+; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm6<br>
+; AVX2-NEXT: vpshufb %xmm5, %xmm6, %xmm7<br>
+; AVX2-NEXT: vpshufb %xmm5, %xmm0, %xmm5<br>
+; AVX2-NEXT: vpunpckldq {{.*#+}} xmm5 = xmm5[0],xmm7[0],xmm5[1],xmm7[1]<br>
+; AVX2-NEXT: vpblendd {{.*#+}} xmm3 = xmm5[0,1],xmm3[2,3]<br>
+; AVX2-NEXT: vpcmpeqb %xmm3, %xmm2, %xmm2<br>
+; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <u,u,u,u,2,6,10,14,u,u,u,u,u,u,u,u><br>
+; AVX2-NEXT: vpshufb %xmm3, %xmm4, %xmm5<br>
+; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm3<br>
+; AVX2-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1]<br>
+; AVX2-NEXT: vmovdqa {{.*#+}} xmm5 = <2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u><br>
+; AVX2-NEXT: vpshufb %xmm5, %xmm6, %xmm7<br>
+; AVX2-NEXT: vpshufb %xmm5, %xmm0, %xmm5<br>
+; AVX2-NEXT: vpunpckldq {{.*#+}} xmm5 = xmm5[0],xmm7[0],xmm5[1],xmm7[1]<br>
+; AVX2-NEXT: vpblendd {{.*#+}} xmm3 = xmm5[0,1],xmm3[2,3]<br>
+; AVX2-NEXT: vmovdqa {{.*#+}} xmm5 = <u,u,u,u,3,7,11,15,u,u,u,u,u,u,u,u><br>
+; AVX2-NEXT: vpshufb %xmm5, %xmm4, %xmm4<br>
+; AVX2-NEXT: vpshufb %xmm5, %xmm1, %xmm1<br>
+; AVX2-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1]<br>
+; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <3,7,11,15,u,u,u,u,u,u,u,u,u,u,u,u><br>
+; AVX2-NEXT: vpshufb %xmm4, %xmm6, %xmm5<br>
+; AVX2-NEXT: vpshufb %xmm4, %xmm0, %xmm0<br>
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]<br>
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]<br>
-; AVX2-NEXT: vpcmpeqb %xmm0, %xmm4, %xmm0<br>
+; AVX2-NEXT: vpcmpeqb %xmm0, %xmm3, %xmm0<br>
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]<br>
; AVX2-NEXT: vpand %xmm1, %xmm2, %xmm2<br>
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0<br>
@@ -836,15 +836,15 @@ define <32 x i1> @interleaved_load_vf32_<br>
; AVX512-NEXT: vpmovdw %zmm1, %ymm3<br>
; AVX512-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2<br>
; AVX512-NEXT: vpmovwb %zmm2, %ymm8<br>
-; AVX512-NEXT: vmovdqa {{.*#+}} xmm7 = <u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u><br>
; AVX512-NEXT: vextracti64x4 $1, %zmm1, %ymm14<br>
; AVX512-NEXT: vextracti128 $1, %ymm14, %xmm9<br>
+; AVX512-NEXT: vmovdqa {{.*#+}} xmm7 = <u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u><br>
; AVX512-NEXT: vpshufb %xmm7, %xmm9, %xmm4<br>
; AVX512-NEXT: vpshufb %xmm7, %xmm14, %xmm5<br>
; AVX512-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]<br>
; AVX512-NEXT: vinserti128 $1, %xmm4, %ymm0, %ymm5<br>
-; AVX512-NEXT: vmovdqa {{.*#+}} xmm3 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u><br>
; AVX512-NEXT: vextracti128 $1, %ymm1, %xmm10<br>
+; AVX512-NEXT: vmovdqa {{.*#+}} xmm3 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u><br>
; AVX512-NEXT: vpshufb %xmm3, %xmm10, %xmm6<br>
; AVX512-NEXT: vpshufb %xmm3, %xmm1, %xmm4<br>
; AVX512-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm4[0],xmm6[0],xmm4[1],xmm6[1]<br>
<br>
<br>
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<br>
-- <br>
Jatin Bhateja<o:p></o:p></p>
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<p>This e-mail and any attachments may contain confidential material for<br>
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