<div dir="ltr">Looks like there are two different issues preventing the folding. If you use the data result from the instruction we emit a And_flag/Or_flag/etc node which we don't match to TBM. If you don't use the result we emit a regular 'and' with a cmp, 0 but we aggressively pattern match the cmp 0 + and to a test instruction.<div><br></div><div>I suppose we can add more patterns to catch these cases. Do we only care about the Z flag when we create an And_flag/Or_flag/etc operation?</div></div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br><div class="gmail_quote">On Sun, Aug 13, 2017 at 5:16 AM, Simon Pilgrim via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rksimon<br>
Date: Sun Aug 13 05:16:00 2017<br>
New Revision: 310790<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=310790&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=310790&view=rev</a><br>
Log:<br>
[X86][TBM] Add tests showing failure to fold RFLAGS result into TBM instructions.<br>
<br>
And fails to select TBM instructions at all.<br>
<br>
Modified:<br>
llvm/trunk/test/CodeGen/X86/<wbr>tbm-intrinsics-x86_64.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>tbm_patterns.ll<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>tbm-intrinsics-x86_64.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm-intrinsics-x86_64.ll?rev=310790&r1=310789&r2=310790&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/tbm-intrinsics-<wbr>x86_64.ll?rev=310790&r1=<wbr>310789&r2=310790&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>tbm-intrinsics-x86_64.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>tbm-intrinsics-x86_64.ll Sun Aug 13 05:16:00 2017<br>
@@ -24,6 +24,20 @@ entry:<br>
ret i32 %0<br>
}<br>
<br>
+define i32 @test_x86_tbm_bextri_u32_z(i32 %a, i32 %b) nounwind readonly {<br>
+; CHECK-LABEL: test_x86_tbm_bextri_u32_z:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: bextr $2814, %edi, %eax # imm = 0xAFE<br>
+; CHECK-NEXT: testl %eax, %eax<br>
+; CHECK-NEXT: cmovel %esi, %eax<br>
+; CHECK-NEXT: retq<br>
+entry:<br>
+ %0 = tail call i32 @llvm.x86.tbm.bextri.u32(i32 %a, i32 2814)<br>
+ %1 = icmp eq i32 %0, 0<br>
+ %2 = select i1 %1, i32 %b, i32 %0<br>
+ ret i32 %2<br>
+}<br>
+<br>
define i64 @test_x86_tbm_bextri_u64(i64 %a) nounwind readnone {<br>
; CHECK-LABEL: test_x86_tbm_bextri_u64:<br>
; CHECK: # BB#0: # %entry<br>
@@ -46,3 +60,17 @@ entry:<br>
%0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %tmp1, i64 2814)<br>
ret i64 %0<br>
}<br>
+<br>
+define i64 @test_x86_tbm_bextri_u64_z(i64 %a, i64 %b) nounwind readnone {<br>
+; CHECK-LABEL: test_x86_tbm_bextri_u64_z:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: bextr $2814, %rdi, %rax # imm = 0xAFE<br>
+; CHECK-NEXT: testq %rax, %rax<br>
+; CHECK-NEXT: cmoveq %rsi, %rax<br>
+; CHECK-NEXT: retq<br>
+entry:<br>
+ %0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %a, i64 2814)<br>
+ %1 = icmp eq i64 %0, 0<br>
+ %2 = select i1 %1, i64 %b, i64 %0<br>
+ ret i64 %2<br>
+}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>tbm_patterns.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm_patterns.ll?rev=310790&r1=310789&r2=310790&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/tbm_patterns.ll?<wbr>rev=310790&r1=310789&r2=<wbr>310790&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>tbm_patterns.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>tbm_patterns.ll Sun Aug 13 05:16:00 2017<br>
@@ -1,6 +1,8 @@<br>
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.<wbr>py<br>
; RUN: llc -mtriple=x86_64-unknown-<wbr>unknown -mattr=+tbm < %s | FileCheck %s<br>
<br>
+; TODO - Patterns fail to fold with ZF flags and prevents TBM instruction selection.<br>
+<br>
define i32 @test_x86_tbm_bextri_u32(i32 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_bextri_u32:<br>
; CHECK: # BB#0:<br>
@@ -22,6 +24,21 @@ define i32 @test_x86_tbm_bextri_u32_m(i3<br>
ret i32 %t2<br>
}<br>
<br>
+define i32 @test_x86_tbm_bextri_u32_z(i32 %a, i32 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_bextri_u32_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: shrl $4, %edi<br>
+; CHECK-NEXT: andl $4095, %edi # imm = 0xFFF<br>
+; CHECK-NEXT: cmovel %esi, %edi<br>
+; CHECK-NEXT: movl %edi, %eax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = lshr i32 %a, 4<br>
+ %t1 = and i32 %t0, 4095<br>
+ %t2 = icmp eq i32 %t1, 0<br>
+ %t3 = select i1 %t2, i32 %b, i32 %t1<br>
+ ret i32 %t3<br>
+}<br>
+<br>
define i64 @test_x86_tbm_bextri_u64(i64 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_bextri_u64:<br>
; CHECK: # BB#0:<br>
@@ -43,6 +60,21 @@ define i64 @test_x86_tbm_bextri_u64_m(i6<br>
ret i64 %t2<br>
}<br>
<br>
+define i64 @test_x86_tbm_bextri_u64_z(i64 %a, i64 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_bextri_u64_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: shrl $4, %edi<br>
+; CHECK-NEXT: andl $4095, %edi # imm = 0xFFF<br>
+; CHECK-NEXT: cmoveq %rsi, %rdi<br>
+; CHECK-NEXT: movq %rdi, %rax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = lshr i64 %a, 4<br>
+ %t1 = and i64 %t0, 4095<br>
+ %t2 = icmp eq i64 %t1, 0<br>
+ %t3 = select i1 %t2, i64 %b, i64 %t1<br>
+ ret i64 %t3<br>
+}<br>
+<br>
define i32 @test_x86_tbm_blcfill_u32(i32 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blcfill_u32:<br>
; CHECK: # BB#0:<br>
@@ -53,6 +85,21 @@ define i32 @test_x86_tbm_blcfill_u32(i32<br>
ret i32 %t1<br>
}<br>
<br>
+define i32 @test_x86_tbm_blcfill_u32_z(<wbr>i32 %a, i32 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blcfill_u32_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
+; CHECK-NEXT: leal 1(%rdi), %eax<br>
+; CHECK-NEXT: andl %edi, %eax<br>
+; CHECK-NEXT: cmovel %esi, %eax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = add i32 %a, 1<br>
+ %t1 = and i32 %t0, %a<br>
+ %t2 = icmp eq i32 %t1, 0<br>
+ %t3 = select i1 %t2, i32 %b, i32 %t1<br>
+ ret i32 %t3<br>
+}<br>
+<br>
define i64 @test_x86_tbm_blcfill_u64(i64 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blcfill_u64:<br>
; CHECK: # BB#0:<br>
@@ -63,6 +110,20 @@ define i64 @test_x86_tbm_blcfill_u64(i64<br>
ret i64 %t1<br>
}<br>
<br>
+define i64 @test_x86_tbm_blcfill_u64_z(<wbr>i64 %a, i64 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blcfill_u64_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: leaq 1(%rdi), %rax<br>
+; CHECK-NEXT: andq %rdi, %rax<br>
+; CHECK-NEXT: cmoveq %rsi, %rax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = add i64 %a, 1<br>
+ %t1 = and i64 %t0, %a<br>
+ %t2 = icmp eq i64 %t1, 0<br>
+ %t3 = select i1 %t2, i64 %b, i64 %t1<br>
+ ret i64 %t3<br>
+}<br>
+<br>
define i32 @test_x86_tbm_blci_u32(i32 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blci_u32:<br>
; CHECK: # BB#0:<br>
@@ -74,6 +135,23 @@ define i32 @test_x86_tbm_blci_u32(i32 %a<br>
ret i32 %t2<br>
}<br>
<br>
+define i32 @test_x86_tbm_blci_u32_z(i32 %a, i32 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blci_u32_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
+; CHECK-NEXT: leal 1(%rdi), %eax<br>
+; CHECK-NEXT: notl %eax<br>
+; CHECK-NEXT: orl %edi, %eax<br>
+; CHECK-NEXT: cmovel %esi, %eax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = add i32 1, %a<br>
+ %t1 = xor i32 %t0, -1<br>
+ %t2 = or i32 %t1, %a<br>
+ %t3 = icmp eq i32 %t2, 0<br>
+ %t4 = select i1 %t3, i32 %b, i32 %t2<br>
+ ret i32 %t4<br>
+}<br>
+<br>
define i64 @test_x86_tbm_blci_u64(i64 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blci_u64:<br>
; CHECK: # BB#0:<br>
@@ -85,6 +163,22 @@ define i64 @test_x86_tbm_blci_u64(i64 %a<br>
ret i64 %t2<br>
}<br>
<br>
+define i64 @test_x86_tbm_blci_u64_z(i64 %a, i64 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blci_u64_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: leaq 1(%rdi), %rax<br>
+; CHECK-NEXT: notq %rax<br>
+; CHECK-NEXT: orq %rdi, %rax<br>
+; CHECK-NEXT: cmoveq %rsi, %rax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = add i64 1, %a<br>
+ %t1 = xor i64 %t0, -1<br>
+ %t2 = or i64 %t1, %a<br>
+ %t3 = icmp eq i64 %t2, 0<br>
+ %t4 = select i1 %t3, i64 %b, i64 %t2<br>
+ ret i64 %t4<br>
+}<br>
+<br>
define i32 @test_x86_tbm_blci_u32_b(i32 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blci_u32_b:<br>
; CHECK: # BB#0:<br>
@@ -116,6 +210,24 @@ define i32 @test_x86_tbm_blcic_u32(i32 %<br>
ret i32 %t2<br>
}<br>
<br>
+define i32 @test_x86_tbm_blcic_u32_z(i32 %a, i32 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blcic_u32_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
+; CHECK-NEXT: leal 1(%rdi), %eax<br>
+; CHECK-NEXT: movl %edi, %ecx<br>
+; CHECK-NEXT: notl %ecx<br>
+; CHECK-NEXT: andl %ecx, %eax<br>
+; CHECK-NEXT: cmovel %esi, %eax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = xor i32 %a, -1<br>
+ %t1 = add i32 %a, 1<br>
+ %t2 = and i32 %t1, %t0<br>
+ %t3 = icmp eq i32 %t2, 0<br>
+ %t4 = select i1 %t3, i32 %b, i32 %t2<br>
+ ret i32 %t4<br>
+}<br>
+<br>
define i64 @test_x86_tbm_blcic_u64(i64 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blcic_u64:<br>
; CHECK: # BB#0:<br>
@@ -127,6 +239,22 @@ define i64 @test_x86_tbm_blcic_u64(i64 %<br>
ret i64 %t2<br>
}<br>
<br>
+define i64 @test_x86_tbm_blcic_u64_z(i64 %a, i64 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blcic_u64_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: leaq 1(%rdi), %rax<br>
+; CHECK-NEXT: notq %rdi<br>
+; CHECK-NEXT: andq %rdi, %rax<br>
+; CHECK-NEXT: cmoveq %rsi, %rax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = xor i64 %a, -1<br>
+ %t1 = add i64 %a, 1<br>
+ %t2 = and i64 %t1, %t0<br>
+ %t3 = icmp eq i64 %t2, 0<br>
+ %t4 = select i1 %t3, i64 %b, i64 %t2<br>
+ ret i64 %t4<br>
+}<br>
+<br>
define i32 @test_x86_tbm_blcmsk_u32(i32 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blcmsk_u32:<br>
; CHECK: # BB#0:<br>
@@ -137,6 +265,21 @@ define i32 @test_x86_tbm_blcmsk_u32(i32<br>
ret i32 %t1<br>
}<br>
<br>
+define i32 @test_x86_tbm_blcmsk_u32_z(i32 %a, i32 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blcmsk_u32_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
+; CHECK-NEXT: leal 1(%rdi), %eax<br>
+; CHECK-NEXT: xorl %edi, %eax<br>
+; CHECK-NEXT: cmovel %esi, %eax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = add i32 %a, 1<br>
+ %t1 = xor i32 %t0, %a<br>
+ %t2 = icmp eq i32 %t1, 0<br>
+ %t3 = select i1 %t2, i32 %b, i32 %t1<br>
+ ret i32 %t3<br>
+}<br>
+<br>
define i64 @test_x86_tbm_blcmsk_u64(i64 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blcmsk_u64:<br>
; CHECK: # BB#0:<br>
@@ -147,6 +290,20 @@ define i64 @test_x86_tbm_blcmsk_u64(i64<br>
ret i64 %t1<br>
}<br>
<br>
+define i64 @test_x86_tbm_blcmsk_u64_z(i64 %a, i64 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blcmsk_u64_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: leaq 1(%rdi), %rax<br>
+; CHECK-NEXT: xorq %rdi, %rax<br>
+; CHECK-NEXT: cmoveq %rsi, %rax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = add i64 %a, 1<br>
+ %t1 = xor i64 %t0, %a<br>
+ %t2 = icmp eq i64 %t1, 0<br>
+ %t3 = select i1 %t2, i64 %b, i64 %t1<br>
+ ret i64 %t3<br>
+}<br>
+<br>
define i32 @test_x86_tbm_blcs_u32(i32 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blcs_u32:<br>
; CHECK: # BB#0:<br>
@@ -157,6 +314,21 @@ define i32 @test_x86_tbm_blcs_u32(i32 %a<br>
ret i32 %t1<br>
}<br>
<br>
+define i32 @test_x86_tbm_blcs_u32_z(i32 %a, i32 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blcs_u32_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
+; CHECK-NEXT: leal 1(%rdi), %eax<br>
+; CHECK-NEXT: orl %edi, %eax<br>
+; CHECK-NEXT: cmovel %esi, %eax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = add i32 %a, 1<br>
+ %t1 = or i32 %t0, %a<br>
+ %t2 = icmp eq i32 %t1, 0<br>
+ %t3 = select i1 %t2, i32 %b, i32 %t1<br>
+ ret i32 %t3<br>
+}<br>
+<br>
define i64 @test_x86_tbm_blcs_u64(i64 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blcs_u64:<br>
; CHECK: # BB#0:<br>
@@ -167,6 +339,20 @@ define i64 @test_x86_tbm_blcs_u64(i64 %a<br>
ret i64 %t1<br>
}<br>
<br>
+define i64 @test_x86_tbm_blcs_u64_z(i64 %a, i64 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blcs_u64_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: leaq 1(%rdi), %rax<br>
+; CHECK-NEXT: orq %rdi, %rax<br>
+; CHECK-NEXT: cmoveq %rsi, %rax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = add i64 %a, 1<br>
+ %t1 = or i64 %t0, %a<br>
+ %t2 = icmp eq i64 %t1, 0<br>
+ %t3 = select i1 %t2, i64 %b, i64 %t1<br>
+ ret i64 %t3<br>
+}<br>
+<br>
define i32 @test_x86_tbm_blsfill_u32(i32 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blsfill_u32:<br>
; CHECK: # BB#0:<br>
@@ -177,6 +363,21 @@ define i32 @test_x86_tbm_blsfill_u32(i32<br>
ret i32 %t1<br>
}<br>
<br>
+define i32 @test_x86_tbm_blsfill_u32_z(<wbr>i32 %a, i32 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blsfill_u32_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
+; CHECK-NEXT: leal -1(%rdi), %eax<br>
+; CHECK-NEXT: orl %edi, %eax<br>
+; CHECK-NEXT: cmovel %esi, %eax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = add i32 %a, -1<br>
+ %t1 = or i32 %t0, %a<br>
+ %t2 = icmp eq i32 %t1, 0<br>
+ %t3 = select i1 %t2, i32 %b, i32 %t1<br>
+ ret i32 %t3<br>
+}<br>
+<br>
define i64 @test_x86_tbm_blsfill_u64(i64 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blsfill_u64:<br>
; CHECK: # BB#0:<br>
@@ -187,6 +388,20 @@ define i64 @test_x86_tbm_blsfill_u64(i64<br>
ret i64 %t1<br>
}<br>
<br>
+define i64 @test_x86_tbm_blsfill_u64_z(<wbr>i64 %a, i64 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blsfill_u64_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: leaq -1(%rdi), %rax<br>
+; CHECK-NEXT: orq %rdi, %rax<br>
+; CHECK-NEXT: cmoveq %rsi, %rax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = add i64 %a, -1<br>
+ %t1 = or i64 %t0, %a<br>
+ %t2 = icmp eq i64 %t1, 0<br>
+ %t3 = select i1 %t2, i64 %b, i64 %t1<br>
+ ret i64 %t3<br>
+}<br>
+<br>
define i32 @test_x86_tbm_blsic_u32(i32 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blsic_u32:<br>
; CHECK: # BB#0:<br>
@@ -198,6 +413,24 @@ define i32 @test_x86_tbm_blsic_u32(i32 %<br>
ret i32 %t2<br>
}<br>
<br>
+define i32 @test_x86_tbm_blsic_u32_z(i32 %a, i32 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blsic_u32_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: movl %edi, %eax<br>
+; CHECK-NEXT: notl %eax<br>
+; CHECK-NEXT: decl %edi<br>
+; CHECK-NEXT: orl %eax, %edi<br>
+; CHECK-NEXT: cmovel %esi, %edi<br>
+; CHECK-NEXT: movl %edi, %eax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = xor i32 %a, -1<br>
+ %t1 = add i32 %a, -1<br>
+ %t2 = or i32 %t0, %t1<br>
+ %t3 = icmp eq i32 %t2, 0<br>
+ %t4 = select i1 %t3, i32 %b, i32 %t2<br>
+ ret i32 %t4<br>
+}<br>
+<br>
define i64 @test_x86_tbm_blsic_u64(i64 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_blsic_u64:<br>
; CHECK: # BB#0:<br>
@@ -209,6 +442,24 @@ define i64 @test_x86_tbm_blsic_u64(i64 %<br>
ret i64 %t2<br>
}<br>
<br>
+define i64 @test_x86_tbm_blsic_u64_z(i64 %a, i64 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_blsic_u64_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: movq %rdi, %rax<br>
+; CHECK-NEXT: notq %rax<br>
+; CHECK-NEXT: decq %rdi<br>
+; CHECK-NEXT: orq %rax, %rdi<br>
+; CHECK-NEXT: cmoveq %rsi, %rdi<br>
+; CHECK-NEXT: movq %rdi, %rax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = xor i64 %a, -1<br>
+ %t1 = add i64 %a, -1<br>
+ %t2 = or i64 %t0, %t1<br>
+ %t3 = icmp eq i64 %t2, 0<br>
+ %t4 = select i1 %t3, i64 %b, i64 %t2<br>
+ ret i64 %t4<br>
+}<br>
+<br>
define i32 @test_x86_tbm_t1mskc_u32(i32 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_t1mskc_u32:<br>
; CHECK: # BB#0:<br>
@@ -220,8 +471,26 @@ define i32 @test_x86_tbm_t1mskc_u32(i32<br>
ret i32 %t2<br>
}<br>
<br>
-define i64 @Ttest_x86_tbm_t1mskc_u64(i64 %a) nounwind {<br>
-; CHECK-LABEL: Ttest_x86_tbm_t1mskc_u64:<br>
+define i32 @test_x86_tbm_t1mskc_u32_z(i32 %a, i32 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_t1mskc_u32_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: movl %edi, %eax<br>
+; CHECK-NEXT: notl %eax<br>
+; CHECK-NEXT: incl %edi<br>
+; CHECK-NEXT: orl %eax, %edi<br>
+; CHECK-NEXT: cmovel %esi, %edi<br>
+; CHECK-NEXT: movl %edi, %eax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = xor i32 %a, -1<br>
+ %t1 = add i32 %a, 1<br>
+ %t2 = or i32 %t0, %t1<br>
+ %t3 = icmp eq i32 %t2, 0<br>
+ %t4 = select i1 %t3, i32 %b, i32 %t2<br>
+ ret i32 %t4<br>
+}<br>
+<br>
+define i64 @test_x86_tbm_t1mskc_u64(i64 %a) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_t1mskc_u64:<br>
; CHECK: # BB#0:<br>
; CHECK-NEXT: t1mskc %rdi, %rax<br>
; CHECK-NEXT: retq<br>
@@ -231,6 +500,24 @@ define i64 @Ttest_x86_tbm_t1mskc_u64(i64<br>
ret i64 %t2<br>
}<br>
<br>
+define i64 @test_x86_tbm_t1mskc_u64_z(i64 %a, i64 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_t1mskc_u64_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: movq %rdi, %rax<br>
+; CHECK-NEXT: notq %rax<br>
+; CHECK-NEXT: incq %rdi<br>
+; CHECK-NEXT: orq %rax, %rdi<br>
+; CHECK-NEXT: cmoveq %rsi, %rdi<br>
+; CHECK-NEXT: movq %rdi, %rax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = xor i64 %a, -1<br>
+ %t1 = add i64 %a, 1<br>
+ %t2 = or i64 %t0, %t1<br>
+ %t3 = icmp eq i64 %t2, 0<br>
+ %t4 = select i1 %t3, i64 %b, i64 %t2<br>
+ ret i64 %t4<br>
+}<br>
+<br>
define i32 @test_x86_tbm_tzmsk_u32(i32 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_tzmsk_u32:<br>
; CHECK: # BB#0:<br>
@@ -242,6 +529,24 @@ define i32 @test_x86_tbm_tzmsk_u32(i32 %<br>
ret i32 %t2<br>
}<br>
<br>
+define i32 @test_x86_tbm_tzmsk_u32_z(i32 %a, i32 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_tzmsk_u32_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: movl %edi, %eax<br>
+; CHECK-NEXT: notl %eax<br>
+; CHECK-NEXT: decl %edi<br>
+; CHECK-NEXT: andl %eax, %edi<br>
+; CHECK-NEXT: cmovel %esi, %edi<br>
+; CHECK-NEXT: movl %edi, %eax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = xor i32 %a, -1<br>
+ %t1 = add i32 %a, -1<br>
+ %t2 = and i32 %t0, %t1<br>
+ %t3 = icmp eq i32 %t2, 0<br>
+ %t4 = select i1 %t3, i32 %b, i32 %t2<br>
+ ret i32 %t4<br>
+}<br>
+<br>
define i64 @test_x86_tbm_tzmsk_u64(i64 %a) nounwind {<br>
; CHECK-LABEL: test_x86_tbm_tzmsk_u64:<br>
; CHECK: # BB#0:<br>
@@ -253,6 +558,24 @@ define i64 @test_x86_tbm_tzmsk_u64(i64 %<br>
ret i64 %t2<br>
}<br>
<br>
+define i64 @test_x86_tbm_tzmsk_u64_z(i64 %a, i64 %b) nounwind {<br>
+; CHECK-LABEL: test_x86_tbm_tzmsk_u64_z:<br>
+; CHECK: # BB#0:<br>
+; CHECK-NEXT: movq %rdi, %rax<br>
+; CHECK-NEXT: notq %rax<br>
+; CHECK-NEXT: decq %rdi<br>
+; CHECK-NEXT: andq %rax, %rdi<br>
+; CHECK-NEXT: cmoveq %rsi, %rdi<br>
+; CHECK-NEXT: movq %rdi, %rax<br>
+; CHECK-NEXT: retq<br>
+ %t0 = xor i64 %a, -1<br>
+ %t1 = add i64 %a, -1<br>
+ %t2 = and i64 %t0, %t1<br>
+ %t3 = icmp eq i64 %t2, 0<br>
+ %t4 = select i1 %t3, i64 %b, i64 %t2<br>
+ ret i64 %t4<br>
+}<br>
+<br>
define i64 @test_and_large_constant_mask(<wbr>i64 %x) {<br>
; CHECK-LABEL: test_and_large_constant_mask:<br>
; CHECK: # BB#0: # %entry<br>
<br>
<br>
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