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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hi Ahmed,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I also didn’t realise this, but now I think the best way to look at this table is as some sensible defaults for the architecture. What I mean is, crypto is
optional, and strictly speaking even FP is optional, but it is of course sensible to have them on by default. What exactly constitutes an architecture is a bit difficult to tell with all the (non)optional extensions. However, I will remove dot product from
this base extensions list as it was a late addition to ARMv8.2a (and also optional). Thanks for checking and reviewing this.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">There are a few more odd things about this table. For example, I am also wondering why LSE is listed there while it is non-optional; it should just be implied
by v8.1a. <o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">It is actually very high on our agenda to do some serious work refactoring here and we will send an RFC to the list first what we plan to do.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Cheers,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Sjoerd.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Sjoerd Meijer
<br>
<b>Sent:</b> 10 August 2017 22:17<br>
<b>To:</b> Ahmed Bougacha<br>
<b>Cc:</b> llvm-commits<br>
<b>Subject:</b> Re: [llvm] r310480 - [AArch64] Assembler support for the ARMv8.2a dot product instructions<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p><span style="font-family:"Calibri","sans-serif";color:black">Hi Ahmed,<o:p></o:p></span></p>
<p><span style="font-family:"Calibri","sans-serif";color:black"><o:p> </o:p></span></p>
<p><span style="font-family:"Calibri","sans-serif";color:black">Just to let you know I will check the armv8.2a arch description my tomorrow morning and will let you know.<o:p></o:p></span></p>
<p><span style="font-family:"Calibri","sans-serif";color:black">And yes, the target parser support was added so that we can expose it to user and do things like -march=armv8.2a+dotprod. I will put the Clang patch up for review soon; I hope to do that tomorrow.
I probably should have mentioned that in this commit.<o:p></o:p></span></p>
<p><span style="font-family:"Calibri","sans-serif";color:black"><o:p> </o:p></span></p>
<p><span style="font-family:"Calibri","sans-serif";color:black">Thanks,<o:p></o:p></span></p>
<p><span style="font-family:"Calibri","sans-serif";color:black">Sjoerd.<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:black">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:black"> Ahmed Bougacha <<a href="mailto:ahmed.bougacha@gmail.com">ahmed.bougacha@gmail.com</a>><br>
<b>Sent:</b> 10 August 2017 21:02:38<br>
<b>To:</b> Sjoerd Meijer<br>
<b>Cc:</b> llvm-commits<br>
<b>Subject:</b> Re: [llvm] r310480 - [AArch64] Assembler support for the ARMv8.2a dot product instructions</span>
<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:10.0pt">Hi Sjoerd,<br>
<br>
On Wed, Aug 9, 2017 at 7:59 AM, Sjoerd Meijer via llvm-commits<br>
<<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br>
> Author: sjoerdmeijer<br>
> Date: Wed Aug 9 07:59:54 2017<br>
> New Revision: 310480<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=310480&view=rev">http://llvm.org/viewvc/llvm-project?rev=310480&view=rev</a><br>
> Log:<br>
> [AArch64] Assembler support for the ARMv8.2a dot product instructions<br>
><br>
> Dot product is an optional ARMv8.2a extension, see also the public architecture<br>
> specification here:<br>
> <a href="https://developer.arm.com/products/architecture/a-profile/exploration-tools">
https://developer.arm.com/products/architecture/a-profile/exploration-tools</a>.<br>
> This patch adds AArch64 assembler support for these dot product instructions.<br>
><br>
> Differential Revision: <a href="https://reviews.llvm.org/D36515">https://reviews.llvm.org/D36515</a><br>
><br>
> Added:<br>
> llvm/trunk/test/MC/AArch64/armv8.2a-dotprod-errors.s<br>
> llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s<br>
> llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt<br>
> Modified:<br>
> llvm/trunk/include/llvm/Support/AArch64TargetParser.def<br>
> llvm/trunk/include/llvm/Support/TargetParser.h<br>
> llvm/trunk/lib/Target/AArch64/AArch64.td<br>
> llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td<br>
> llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td<br>
> llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h<br>
> llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp<br>
> llvm/trunk/test/MC/AArch64/neon-diagnostics.s<br>
><br>
> Modified: llvm/trunk/include/llvm/Support/AArch64TargetParser.def<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.def?rev=310480&r1=310479&r2=310480&view=diff">
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.def?rev=310480&r1=310479&r2=310480&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/include/llvm/Support/AArch64TargetParser.def (original)<br>
> +++ llvm/trunk/include/llvm/Support/AArch64TargetParser.def Wed Aug 9 07:59:54 2017<br>
> @@ -28,7 +28,8 @@ AARCH64_ARCH("armv8.1-a", ARMV8_1A, "8.1<br>
> AARCH64_ARCH("armv8.2-a", ARMV8_2A, "8.2-A", "v8.2a",<br>
> ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,<br>
> (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |<br>
> - AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE))<br>
> + AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |<br>
> + AArch64::AEK_DOTPROD))<br>
<br>
If the feature is optional with v8.2a, why is it here? We use these<br>
"base" extensions as the mandatory extensions constituting the arch,<br>
no?<br>
<br>
Additionally, why do we need the support in TargetParser in the first<br>
place? My understanding is, exposing the feature here is only<br>
necessary to be able to expose it to users in the clang driver (via<br>
preprocessor macros and/or -m flags). Do you plan to add that too?<br>
<br>
Thanks!<br>
-Ahmed<br>
<br>
> #undef AARCH64_ARCH<br>
><br>
> #ifndef AARCH64_ARCH_EXT_NAME<br>
> @@ -40,6 +41,7 @@ AARCH64_ARCH_EXT_NAME("none", AArch6<br>
> AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc")<br>
> AARCH64_ARCH_EXT_NAME("lse", AArch64::AEK_LSE, "+lse", "-lse")<br>
> AARCH64_ARCH_EXT_NAME("crypto", AArch64::AEK_CRYPTO, "+crypto","-crypto")<br>
> +AARCH64_ARCH_EXT_NAME("dotprod", AArch64::AEK_DOTPROD, "+dotprod","-dotprod")<br>
> AARCH64_ARCH_EXT_NAME("fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8")<br>
> AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD, "+neon", "-neon")<br>
> AARCH64_ARCH_EXT_NAME("fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16")<br>
><br>
> Modified: llvm/trunk/include/llvm/Support/TargetParser.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetParser.h?rev=310480&r1=310479&r2=310480&view=diff">
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetParser.h?rev=310480&r1=310479&r2=310480&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/include/llvm/Support/TargetParser.h (original)<br>
> +++ llvm/trunk/include/llvm/Support/TargetParser.h Wed Aug 9 07:59:54 2017<br>
> @@ -166,7 +166,8 @@ enum ArchExtKind : unsigned {<br>
> AEK_PROFILE = 0x40,<br>
> AEK_RAS = 0x80,<br>
> AEK_LSE = 0x100,<br>
> - AEK_SVE = 0x200<br>
> + AEK_SVE = 0x200,<br>
> + AEK_DOTPROD = 0x400<br>
> };<br>
><br>
> StringRef getCanonicalArchName(StringRef Arch);<br>
><br>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=310480&r1=310479&r2=310480&view=diff">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=310480&r1=310479&r2=310480&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/AArch64/AArch64.td (original)<br>
> +++ llvm/trunk/lib/Target/AArch64/AArch64.td Wed Aug 9 07:59:54 2017<br>
> @@ -122,6 +122,10 @@ def FeatureUseRSqrt : SubtargetFeature<<br>
> "use-reciprocal-square-root", "UseRSqrt", "true",<br>
> "Use the reciprocal square root approximation">;<br>
><br>
> +def FeatureDotProd : SubtargetFeature<<br>
> + "dotprod", "HasDotProd", "true",<br>
> + "Enable dot product support">;<br>
> +<br>
> def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",<br>
> "NegativeImmediates", "false",<br>
> "Convert immediates and instructions "<br>
><br>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=310480&r1=310479&r2=310480&view=diff">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=310480&r1=310479&r2=310480&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)<br>
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Wed Aug 9 07:59:54 2017<br>
> @@ -4374,6 +4374,12 @@ class BaseSIMDThreeSameVectorTied<bit Q,<br>
> let Inst{4-0} = Rd;<br>
> }<br>
><br>
> +class BaseSIMDThreeSameVectorDot<bit Q, bit U, string asm, string kind1,<br>
> + string kind2> :<br>
> + BaseSIMDThreeSameVector<Q, U, 0b100, 0b10010, V128, asm, kind1, [] > {<br>
> + let AsmString = !strconcat(asm, "{\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2 # "}");<br>
> +}<br>
> +<br>
> // All operand sizes distinguished in the encoding.<br>
> multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,<br>
> SDPatternOperator OpNode> {<br>
> @@ -6801,6 +6807,16 @@ class BaseSIMDIndexedTied<bit Q, bit U,<br>
> let Inst{4-0} = Rd;<br>
> }<br>
><br>
> +// ARMv8.2 Index Dot product instructions<br>
> +class BaseSIMDThreeSameVectorDotIndex<bit Q, bit U, string asm, string dst_kind,<br>
> + string lhs_kind, string rhs_kind> :<br>
> + BaseSIMDIndexedTied<Q, U, 0b0, 0b10, 0b1110, V128, V128, V128, VectorIndexS,<br>
> + asm, "", dst_kind, lhs_kind, rhs_kind, []> {<br>
> + bits<2> idx;<br>
> + let Inst{21} = idx{0}; // L<br>
> + let Inst{11} = idx{1}; // H<br>
> +}<br>
> +<br>
> multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,<br>
> SDPatternOperator OpNode> {<br>
> let Predicates = [HasNEON, HasFullFP16] in {<br>
> @@ -9596,6 +9612,7 @@ multiclass STOPregister<string asm, stri<br>
><br>
> //----------------------------------------------------------------------------<br>
> // Allow the size specifier tokens to be upper case, not just lower.<br>
> +def : TokenAlias<".4B", ".4b">; // Add dot product<br>
> def : TokenAlias<".8B", ".8b">;<br>
> def : TokenAlias<".4H", ".4h">;<br>
> def : TokenAlias<".2S", ".2s">;<br>
><br>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=310480&r1=310479&r2=310480&view=diff">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=310480&r1=310479&r2=310480&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Wed Aug 9 07:59:54 2017<br>
> @@ -24,6 +24,8 @@ def HasNEON : Predicate<"Subtar<br>
> AssemblerPredicate<"FeatureNEON", "neon">;<br>
> def HasCrypto : Predicate<"Subtarget->hasCrypto()">,<br>
> AssemblerPredicate<"FeatureCrypto", "crypto">;<br>
> +def HasDotProd : Predicate<"Subtarget->hasDotProd()">,<br>
> + AssemblerPredicate<"FeatureDotProd", "dotprod">;<br>
> def HasCRC : Predicate<"Subtarget->hasCRC()">,<br>
> AssemblerPredicate<"FeatureCRC", "crc">;<br>
> def HasLSE : Predicate<"Subtarget->hasLSE()">,<br>
> @@ -432,6 +434,18 @@ def ISB : CRmSystemI<barrier_op, 0b110<br>
> [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;<br>
> }<br>
><br>
> +// ARMv8.2 Dot Product<br>
> +let Predicates = [HasDotProd] in {<br>
> +def UDOT2S : BaseSIMDThreeSameVectorDot<0, 1, "udot", ".2s", ".8b">;<br>
> +def SDOT2S : BaseSIMDThreeSameVectorDot<0, 0, "sdot", ".2s", ".8b">;<br>
> +def UDOT4S : BaseSIMDThreeSameVectorDot<1, 1, "udot", ".4s", ".16b">;<br>
> +def SDOT4S : BaseSIMDThreeSameVectorDot<1, 0, "sdot", ".4s", ".16b">;<br>
> +def UDOTIDX2S : BaseSIMDThreeSameVectorDotIndex<0, 1, "udot", ".2s", ".8b", ".4b">;<br>
> +def SDOTIDX2S : BaseSIMDThreeSameVectorDotIndex<0, 0, "sdot", ".2s", ".8b", ".4b">;<br>
> +def UDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 1, "udot", ".4s", ".16b", ".4b">;<br>
> +def SDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 0, "sdot", ".4s", ".16b", ".4b">;<br>
> +}<br>
> +<br>
> def : InstAlias<"clrex", (CLREX 0xf)>;<br>
> def : InstAlias<"isb", (ISB 0xf)>;<br>
><br>
><br>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=310480&r1=310479&r2=310480&view=diff">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=310480&r1=310479&r2=310480&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)<br>
> +++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Wed Aug 9 07:59:54 2017<br>
> @@ -62,6 +62,7 @@ protected:<br>
> bool HasFPARMv8 = false;<br>
> bool HasNEON = false;<br>
> bool HasCrypto = false;<br>
> + bool HasDotProd = false;<br>
> bool HasCRC = false;<br>
> bool HasLSE = false;<br>
> bool HasRAS = false;<br>
> @@ -201,6 +202,7 @@ public:<br>
> bool hasFPARMv8() const { return HasFPARMv8; }<br>
> bool hasNEON() const { return HasNEON; }<br>
> bool hasCrypto() const { return HasCrypto; }<br>
> + bool hasDotProd() const { return HasDotProd; }<br>
> bool hasCRC() const { return HasCRC; }<br>
> bool hasLSE() const { return HasLSE; }<br>
> bool hasRAS() const { return HasRAS; }<br>
><br>
> Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=310480&r1=310479&r2=310480&view=diff">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=310480&r1=310479&r2=310480&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)<br>
> +++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Wed Aug 9 07:59:54 2017<br>
> @@ -1810,6 +1810,8 @@ static bool isValidVectorKind(StringRef<br>
> .Case(".d", true)<br>
> // Needed for fp16 scalar pairwise reductions<br>
> .Case(".2h", true)<br>
> + // another special case for the ARMv8.2a dot product operand<br>
> + .Case(".4b", true)<br>
> .Default(false);<br>
> }<br>
><br>
><br>
> Added: llvm/trunk/test/MC/AArch64/armv8.2a-dotprod-errors.s<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-dotprod-errors.s?rev=310480&view=auto">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-dotprod-errors.s?rev=310480&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/AArch64/armv8.2a-dotprod-errors.s (added)<br>
> +++ llvm/trunk/test/MC/AArch64/armv8.2a-dotprod-errors.s Wed Aug 9 07:59:54 2017<br>
> @@ -0,0 +1,12 @@<br>
> +// RUN: not llvm-mc -triple aarch64 -mattr=+dotprod -show-encoding < %s 2> %t<br>
> +// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s<br>
> +<br>
> +udot v0.2s, v1.8b, v2.4b[4]<br>
> +sdot v0.2s, v1.8b, v2.4b[4]<br>
> +udot v0.4s, v1.16b, v2.4b[4]<br>
> +sdot v0.4s, v1.16b, v2.4b[4]<br>
> +<br>
> +// CHECK-ERROR: vector lane must be an integer in range [0, 3]<br>
> +// CHECK-ERROR: vector lane must be an integer in range [0, 3]<br>
> +// CHECK-ERROR: vector lane must be an integer in range [0, 3]<br>
> +// CHECK-ERROR: vector lane must be an integer in range [0, 3]<br>
><br>
> Added: llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s?rev=310480&view=auto">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s?rev=310480&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s (added)<br>
> +++ llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s Wed Aug 9 07:59:54 2017<br>
> @@ -0,0 +1,60 @@<br>
> +// RUN: llvm-mc -triple aarch64 -mattr=+dotprod -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD<br>
> +// RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t<br>
> +// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s<br>
> +<br>
> +udot v0.2s, v1.8b, v2.8b<br>
> +sdot v0.2s, v1.8b, v2.8b<br>
> +udot v0.4s, v1.16b, v2.16b<br>
> +sdot v0.4s, v1.16b, v2.16b<br>
> +udot v0.2s, v1.8b, v2.4b[0]<br>
> +sdot v0.2s, v1.8b, v2.4b[1]<br>
> +udot v0.4s, v1.16b, v2.4b[2]<br>
> +sdot v0.4s, v1.16b, v2.4b[3]<br>
> +<br>
> +// Check that the upper case types are aliases<br>
> +udot v0.2S, v1.8B, v2.4B[0]<br>
> +udot v0.4S, v1.16B, v2.4B[2]<br>
> +<br>
> +// CHECK-DOTPROD: udot v0.2s, v1.8b, v2.8b // encoding: [0x20,0x94,0x82,0x2e]<br>
> +// CHECK-DOTPROD: sdot v0.2s, v1.8b, v2.8b // encoding: [0x20,0x94,0x82,0x0e]<br>
> +// CHECK-DOTPROD: udot v0.4s, v1.16b, v2.16b // encoding: [0x20,0x94,0x82,0x6e]<br>
> +// CHECK-DOTPROD: sdot v0.4s, v1.16b, v2.16b // encoding: [0x20,0x94,0x82,0x4e]<br>
> +// CHECK-DOTPROD: udot v0.2s, v1.8b, v2.4b[0] // encoding: [0x20,0xe0,0x82,0x2f]<br>
> +// CHECK-DOTPROD: sdot v0.2s, v1.8b, v2.4b[1] // encoding: [0x20,0xe0,0xa2,0x0f]<br>
> +// CHECK-DOTPROD: udot v0.4s, v1.16b, v2.4b[2] // encoding: [0x20,0xe8,0x82,0x6f]<br>
> +// CHECK-DOTPROD: sdot v0.4s, v1.16b, v2.4b[3] // encoding: [0x20,0xe8,0xa2,0x4f]<br>
> +<br>
> +// CHECK-DOTPROD: udot v0.2s, v1.8b, v2.4b[0] // encoding: [0x20,0xe0,0x82,0x2f]<br>
> +// CHECK-DOTPROD: udot v0.4s, v1.16b, v2.4b[2] // encoding: [0x20,0xe8,0x82,0x6f]<br>
> +<br>
> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod<br>
> +// CHECK-NO-DOTPROD: udot v0.2s, v1.8b, v2.8b<br>
> +// CHECK-NO-DOTPROD: ^<br>
> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod<br>
> +// CHECK-NO-DOTPROD: sdot v0.2s, v1.8b, v2.8b<br>
> +// CHECK-NO-DOTPROD: ^<br>
> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod<br>
> +// CHECK-NO-DOTPROD: udot v0.4s, v1.16b, v2.16b<br>
> +// CHECK-NO-DOTPROD: ^<br>
> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod<br>
> +// CHECK-NO-DOTPROD: sdot v0.4s, v1.16b, v2.16b<br>
> +// CHECK-NO-DOTPROD: ^<br>
> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod<br>
> +// CHECK-NO-DOTPROD: udot v0.2s, v1.8b, v2.4b[0]<br>
> +// CHECK-NO-DOTPROD: ^<br>
> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod<br>
> +// CHECK-NO-DOTPROD: sdot v0.2s, v1.8b, v2.4b[1]<br>
> +// CHECK-NO-DOTPROD: ^<br>
> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod<br>
> +// CHECK-NO-DOTPROD: udot v0.4s, v1.16b, v2.4b[2]<br>
> +// CHECK-NO-DOTPROD: ^<br>
> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod<br>
> +// CHECK-NO-DOTPROD: sdot v0.4s, v1.16b, v2.4b[3]<br>
> +// CHECK-NO-DOTPROD: ^<br>
> +<br>
> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod<br>
> +// CHECK-NO-DOTPROD: udot v0.2S, v1.8B, v2.4B[0]<br>
> +// CHECK-NO-DOTPROD: ^<br>
> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod<br>
> +// CHECK-NO-DOTPROD: udot v0.4S, v1.16B, v2.4B[2]<br>
> +// CHECK-NO-DOTPROD: ^<br>
><br>
> Modified: llvm/trunk/test/MC/AArch64/neon-diagnostics.s<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-diagnostics.s?rev=310480&r1=310479&r2=310480&view=diff">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-diagnostics.s?rev=310480&r1=310479&r2=310480&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/AArch64/neon-diagnostics.s (original)<br>
> +++ llvm/trunk/test/MC/AArch64/neon-diagnostics.s Wed Aug 9 07:59:54 2017<br>
> @@ -6395,8 +6395,7 @@<br>
> uzp1 v0.16b, v1.8b, v2.8b<br>
> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction<br>
> uzp1 v0.8b, v1.4b, v2.4b<br>
> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier<br>
> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier<br>
> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> uzp1 v0.8h, v1.4h, v2.4h<br>
> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> uzp1 v0.4h, v1.2h, v2.2h<br>
> @@ -6416,8 +6415,7 @@<br>
> uzp2 v0.16b, v1.8b, v2.8b<br>
> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction<br>
> uzp2 v0.8b, v1.4b, v2.4b<br>
> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier<br>
> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier<br>
> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> uzp2 v0.8h, v1.4h, v2.4h<br>
> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> uzp2 v0.4h, v1.2h, v2.2h<br>
> @@ -6437,8 +6435,7 @@<br>
> zip1 v0.16b, v1.8b, v2.8b<br>
> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction<br>
> zip1 v0.8b, v1.4b, v2.4b<br>
> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier<br>
> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier<br>
> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> zip1 v0.8h, v1.4h, v2.4h<br>
> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> zip1 v0.4h, v1.2h, v2.2h<br>
> @@ -6454,12 +6451,11 @@<br>
> // CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction<br>
><br>
><br>
> -\<br>
> +<br>
> zip2 v0.16b, v1.8b, v2.8b<br>
> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction<br>
> zip2 v0.8b, v1.4b, v2.4b<br>
> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier<br>
> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier<br>
> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> zip2 v0.8h, v1.4h, v2.4h<br>
> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> zip2 v0.4h, v1.2h, v2.2h<br>
> @@ -6479,8 +6475,7 @@<br>
> trn1 v0.16b, v1.8b, v2.8b<br>
> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction<br>
> trn1 v0.8b, v1.4b, v2.4b<br>
> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier<br>
> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier<br>
> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> trn1 v0.8h, v1.4h, v2.4h<br>
> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> trn1 v0.4h, v1.2h, v2.2h<br>
> @@ -6500,8 +6495,7 @@<br>
> trn2 v0.16b, v1.8b, v2.8b<br>
> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction<br>
> trn2 v0.8b, v1.4b, v2.4b<br>
> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier<br>
> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier<br>
> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> trn2 v0.8h, v1.4h, v2.4h<br>
> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> trn2 v0.4h, v1.2h, v2.2h<br>
> @@ -6523,8 +6517,7 @@<br>
> uzp1 v0.16b, v1.8b, v2.8b<br>
> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction<br>
> uzp1 v0.8b, v1.4b, v2.4b<br>
> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier<br>
> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier<br>
> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> uzp1 v0.8h, v1.4h, v2.4h<br>
> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> uzp1 v0.4h, v1.2h, v2.2h<br>
> @@ -6542,8 +6535,7 @@<br>
> uzp2 v0.16b, v1.8b, v2.8b<br>
> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction<br>
> uzp2 v0.8b, v1.4b, v2.4b<br>
> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier<br>
> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier<br>
> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> uzp2 v0.8h, v1.4h, v2.4h<br>
> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> uzp2 v0.4h, v1.2h, v2.2h<br>
> @@ -6561,8 +6553,7 @@<br>
> zip1 v0.16b, v1.8b, v2.8b<br>
> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction<br>
> zip1 v0.8b, v1.4b, v2.4b<br>
> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier<br>
> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier<br>
> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> zip1 v0.8h, v1.4h, v2.4h<br>
> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> zip1 v0.4h, v1.2h, v2.2h<br>
> @@ -6584,8 +6575,7 @@<br>
> zip2 v0.16b, v1.8b, v2.8b<br>
> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction<br>
> zip2 v0.8b, v1.4b, v2.4b<br>
> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier<br>
> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier<br>
> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> zip2 v0.8h, v1.4h, v2.4h<br>
> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> zip2 v0.4h, v1.2h, v2.2h<br>
> @@ -6606,8 +6596,7 @@<br>
> trn1 v0.16b, v1.8b, v2.8b<br>
> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction<br>
> trn1 v0.8b, v1.4b, v2.4b<br>
> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier<br>
> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier<br>
> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> trn1 v0.8h, v1.4h, v2.4h<br>
> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> trn1 v0.4h, v1.2h, v2.2h<br>
> @@ -6627,8 +6616,7 @@<br>
> trn2 v0.16b, v1.8b, v2.8b<br>
> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction<br>
> trn2 v0.8b, v1.4b, v2.4b<br>
> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier<br>
> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier<br>
> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> trn2 v0.8h, v1.4h, v2.4h<br>
> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction<br>
> trn2 v0.4h, v1.2h, v2.2h<br>
><br>
> Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt?rev=310480&view=auto">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt?rev=310480&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt (added)<br>
> +++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt Wed Aug 9 07:59:54 2017<br>
> @@ -0,0 +1,29 @@<br>
> +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+dotprod --disassemble < %s | FileCheck %s<br>
> +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-dotprod --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR<br>
> +<br>
> +0x20,0x94,0x82,0x2e<br>
> +0x20,0x94,0x82,0x0e<br>
> +0x20,0x94,0x82,0x6e<br>
> +0x20,0x94,0x82,0x4e<br>
> +0x20,0xe0,0x82,0x2f<br>
> +0x20,0xe0,0xa2,0x0f<br>
> +0x20,0xe8,0x82,0x6f<br>
> +0x20,0xe8,0xa2,0x4f<br>
> +<br>
> +#CHECK: udot v0.2s, v1.8b, v2.8b<br>
> +#CHECK: sdot v0.2s, v1.8b, v2.8b<br>
> +#CHECK: udot v0.4s, v1.16b, v2.16b<br>
> +#CHECK: sdot v0.4s, v1.16b, v2.16b<br>
> +#CHECK: udot v0.2s, v1.8b, v2.4b[0]<br>
> +#CHECK: sdot v0.2s, v1.8b, v2.4b[1]<br>
> +#CHECK: udot v0.4s, v1.16b, v2.4b[2]<br>
> +#CHECK: sdot v0.4s, v1.16b, v2.4b[3]<br>
> +<br>
> +# CHECK-ERROR: invalid instruction encoding<br>
> +# CHECK-ERROR: invalid instruction encoding<br>
> +# CHECK-ERROR: invalid instruction encoding<br>
> +# CHECK-ERROR: invalid instruction encoding<br>
> +# CHECK-ERROR: invalid instruction encoding<br>
> +# CHECK-ERROR: invalid instruction encoding<br>
> +# CHECK-ERROR: invalid instruction encoding<br>
> +# CHECK-ERROR: invalid instruction encoding<br>
><br>
><br>
> _______________________________________________<br>
> llvm-commits mailing list<br>
> <a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a><br>
> <a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><o:p></o:p></span></p>
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