<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">Hi Diane,<div class=""><br class=""></div><div class="">Thanks for the feedbacks.</div><div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Aug 4, 2017, at 1:25 AM, Diana Picus <<a href="mailto:diana.picus@linaro.org" class="">diana.picus@linaro.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Just a few nits:</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">On 3 August 2017 at 23:52, Quentin Colombet via llvm-commits</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class=""><</span><a href="mailto:llvm-commits@lists.llvm.org" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px;" class="">llvm-commits@lists.llvm.org</a><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">> wrote:</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px;" class="">Author: qcolombet<br class="">Date: Thu Aug 3 14:52:25 2017<br class="">New Revision: 309990<br class=""><br class="">URL: <a href="http://llvm.org/viewvc/llvm-project?rev=309990&view=rev" class="">http://llvm.org/viewvc/llvm-project?rev=309990&view=rev</a><br class="">Log:<br class="">[GlobalISel] Make GlobalISel a non-optional library.<br class=""><br class="">With this change, the GlobalISel library gets always built. In<br class="">particular, this is not possible to opt GlobalISel out of the build<br class="">using the LLVM_BUILD_GLOBAL_ISEL variable any more.<br class=""><br class="">Modified:<br class=""> llvm/trunk/CMakeLists.txt<br class=""> llvm/trunk/lib/CodeGen/GlobalISel/CMakeLists.txt<br class=""> llvm/trunk/lib/CodeGen/GlobalISel/GlobalISel.cpp<br class=""> llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp<br class=""> llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def<br class=""> llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp<br class=""> llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp<br class=""> llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp<br class=""> llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp<br class=""> llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp<br class=""> llvm/trunk/lib/Target/AArch64/CMakeLists.txt<br class=""> llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp<br class=""> llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def<br class=""> llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp<br class=""> llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp<br class=""> llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp<br class=""> llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp<br class=""> llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt<br class=""> llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp<br class=""> llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp<br class=""> llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp<br class=""> llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp<br class=""> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp<br class=""> llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp<br class=""> llvm/trunk/lib/Target/ARM/CMakeLists.txt<br class=""> llvm/trunk/lib/Target/X86/CMakeLists.txt<br class=""> llvm/trunk/lib/Target/X86/X86CallLowering.cpp<br class=""> llvm/trunk/lib/Target/X86/X86GenRegisterBankInfo.def<br class=""> llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp<br class=""> llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp<br class=""> llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp<br class=""> llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br class=""> llvm/trunk/lib/Target/X86/X86TargetMachine.cpp<br class=""> llvm/trunk/tools/llvm-config/CMakeLists.txt<br class=""> llvm/trunk/unittests/CodeGen/GlobalISel/CMakeLists.txt<br class=""><br class="">Modified: llvm/trunk/CMakeLists.txt<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/CMakeLists.txt (original)<br class="">+++ llvm/trunk/CMakeLists.txt Thu Aug 3 14:52:25 2017<br class="">@@ -176,11 +176,6 @@ if(LLVM_DEPENDENCY_DEBUGGING)<br class=""> endif()<br class="">endif()<br class=""><br class="">-option(LLVM_BUILD_GLOBAL_ISEL "Experimental: Build GlobalISel" ON)<br class="">-if(LLVM_BUILD_GLOBAL_ISEL)<br class="">- add_definitions(-DLLVM_BUILD_GLOBAL_ISEL)<br class="">-endif()<br class="">-<br class="">option(LLVM_ENABLE_DAGISEL_COV "Debug: Prints tablegen patterns that were used for selecting" OFF)<br class=""><br class=""># Add path for custom modules<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/GlobalISel/CMakeLists.txt<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/GlobalISel/CMakeLists.txt (original)<br class="">+++ llvm/trunk/lib/CodeGen/GlobalISel/CMakeLists.txt Thu Aug 3 14:52:25 2017<br class="">@@ -1,34 +1,21 @@<br class="">-# List of all GlobalISel files.<br class="">-set(GLOBAL_ISEL_FILES<br class="">- CallLowering.cpp<br class="">- IRTranslator.cpp<br class="">- InstructionSelect.cpp<br class="">- InstructionSelector.cpp<br class="">- MachineIRBuilder.cpp<br class="">- LegalizerHelper.cpp<br class="">- Legalizer.cpp<br class="">- LegalizerInfo.cpp<br class="">- Localizer.cpp<br class="">- RegBankSelect.cpp<br class="">- RegisterBank.cpp<br class="">- RegisterBankInfo.cpp<br class="">- Utils.cpp<br class="">- )<br class="">-<br class="">-# Add GlobalISel files to the dependencies if the user wants to build it.<br class="">-if(LLVM_BUILD_GLOBAL_ISEL)<br class="">- set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})<br class="">-else()<br class="">- set(GLOBAL_ISEL_BUILD_FILES"")<br class="">- set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})<br class="">-endif()<br class="">-<br class=""># In LLVMBuild.txt files, it is not possible to mark a dependency to a<br class=""># library as optional. So instead, generate an empty library if we did<br class=""># not ask for it.<br class=""></blockquote><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">This comment doesn't seem necessary anymore.</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""></div></blockquote><div><br class=""></div><div><br class=""></div><div>Good point.</div><br class=""><blockquote type="cite" class=""><div class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px;" class="">add_llvm_library(LLVMGlobalISel<br class="">- ${GLOBAL_ISEL_BUILD_FILES}<br class="">+ CallLowering.cpp<br class=""> GlobalISel.cpp<br class="">+ IRTranslator.cpp<br class="">+ InstructionSelect.cpp<br class="">+ InstructionSelector.cpp<br class="">+ LegalizerHelper.cpp<br class="">+ Legalizer.cpp<br class="">+ LegalizerInfo.cpp<br class="">+ Localizer.cpp<br class="">+ MachineIRBuilder.cpp<br class="">+ RegBankSelect.cpp<br class="">+ RegisterBank.cpp<br class="">+ RegisterBankInfo.cpp<br class="">+ Utils.cpp<br class=""><br class=""> DEPENDS<br class=""> intrinsics_gen<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/GlobalISel/GlobalISel.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/GlobalISel.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/GlobalISel.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/GlobalISel/GlobalISel.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/GlobalISel/GlobalISel.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -16,13 +16,6 @@<br class=""><br class="">using namespace llvm;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-<br class="">-void llvm::initializeGlobalISel(PassRegistry &Registry) {<br class="">-}<br class="">-<br class="">-#else<br class="">-<br class="">void llvm::initializeGlobalISel(PassRegistry &Registry) {<br class=""> initializeIRTranslatorPass(Registry);<br class=""> initializeLegalizerPass(Registry);<br class="">@@ -30,4 +23,3 @@ void llvm::initializeGlobalISel(PassRegi<br class=""> initializeRegBankSelectPass(Registry);<br class=""> initializeInstructionSelectPass(Registry);<br class="">}<br class="">-#endif // LLVM_BUILD_GLOBAL_ISEL<br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -47,10 +47,6 @@<br class=""><br class="">using namespace llvm;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "This shouldn't be built without GISel"<br class="">-#endif<br class="">-<br class="">AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI)<br class=""> : CallLowering(&TLI) {}<br class=""><br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def Thu Aug 3 14:52:25 2017<br class="">@@ -11,10 +11,6 @@<br class="">/// \todo This should be generated by TableGen.<br class="">//===----------------------------------------------------------------------===//<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">namespace llvm {<br class="">RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{<br class=""> /* StartIdx, Length, RegBank */<br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -37,10 +37,6 @@<br class=""><br class="">using namespace llvm;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">namespace {<br class=""><br class="">#define GET_GLOBALISEL_PREDICATE_BITSET<br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -23,10 +23,6 @@<br class=""><br class="">using namespace llvm;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">AArch64LegalizerInfo::AArch64LegalizerInfo() {<br class=""> using namespace TargetOpcode;<br class=""> const LLT p0 = LLT::pointer(0, 64);<br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -37,10 +37,6 @@<br class=""><br class="">using namespace llvm;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)<br class=""> : AArch64GenRegisterBankInfo() {<br class=""> static bool AlreadyInit = false;<br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -18,7 +18,6 @@<br class="">#include "AArch64PBQPRegAlloc.h"<br class="">#include "AArch64TargetMachine.h"<br class=""><br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">#include "AArch64CallLowering.h"<br class="">#include "AArch64LegalizerInfo.h"<br class="">#include "AArch64RegisterBankInfo.h"<br class="">@@ -27,7 +26,6 @@<br class="">#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"<br class="">#include "llvm/CodeGen/GlobalISel/Legalizer.h"<br class="">#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"<br class="">-#endif<br class="">#include "llvm/CodeGen/MachineScheduler.h"<br class="">#include "llvm/IR/GlobalValue.h"<br class="">#include "llvm/Support/TargetRegistry.h"<br class=""></blockquote><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Maybe sort the includes?</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""></div></blockquote><div><br class=""></div><div>I’ve run clang-format and didn’t check afterward, I though it was supposed to do this kind of thing.</div><div>That being said, a quick glance at this part of the diff seems to be fine (GlobalISel is before MachineScheduler).</div><div>Am I missing something?</div><br class=""><blockquote type="cite" class=""><div class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px;" class="">@@ -143,7 +141,6 @@ void AArch64Subtarget::initializePropert<br class=""> }<br class="">}<br class=""><br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">namespace {<br class=""><br class="">struct AArch64GISelActualAccessor : public GISelAccessor {<br class=""></blockquote><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">I suppose now we don't need to call it "actual" anymore, right?</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""></div></blockquote><div><br class=""></div><div>Indeed. I suppose we could get rid of the GISelAccessor thing all together.</div><div>What do you think?</div><div><br class=""></div><div>Cheers,</div><div>-Quentin</div><br class=""><blockquote type="cite" class=""><div class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px;" class="">@@ -170,7 +167,6 @@ struct AArch64GISelActualAccessor : publ<br class="">};<br class=""><br class="">} // end anonymous namespace<br class="">-#endif<br class=""><br class="">AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,<br class=""> const std::string &FS,<br class="">@@ -180,9 +176,6 @@ AArch64Subtarget::AArch64Subtarget(const<br class=""> IsLittle(LittleEndian), TargetTriple(TT), FrameLowering(),<br class=""> InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),<br class=""> TLInfo(TM, *this), GISel() {<br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">- GISelAccessor *AArch64GISel = new GISelAccessor();<br class="">-#else<br class=""> AArch64GISelActualAccessor *AArch64GISel = new AArch64GISelActualAccessor();<br class=""> AArch64GISel->CallLoweringInfo.reset(<br class=""> new AArch64CallLowering(*getTargetLowering()));<br class="">@@ -197,7 +190,6 @@ AArch64Subtarget::AArch64Subtarget(const<br class=""> *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));<br class=""><br class=""> AArch64GISel->RegBankInfo.reset(RBI);<br class="">-#endif<br class=""> setGISelAccessor(*AArch64GISel);<br class="">}<br class=""><br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -330,13 +330,11 @@ public:<br class=""> void addIRPasses() override;<br class=""> bool addPreISel() override;<br class=""> bool addInstSelector() override;<br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class=""> bool addIRTranslator() override;<br class=""> bool addLegalizeMachineIR() override;<br class=""> bool addRegBankSelect() override;<br class=""> void addPreGlobalInstructionSelect() override;<br class=""> bool addGlobalInstructionSelect() override;<br class="">-#endif<br class=""> bool addILPOpts() override;<br class=""> void addPreRegAlloc() override;<br class=""> void addPostRegAlloc() override;<br class="">@@ -432,7 +430,6 @@ bool AArch64PassConfig::addInstSelector(<br class=""> return false;<br class="">}<br class=""><br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">bool AArch64PassConfig::addIRTranslator() {<br class=""> addPass(new IRTranslator());<br class=""> return false;<br class="">@@ -458,7 +455,6 @@ bool AArch64PassConfig::addGlobalInstruc<br class=""> addPass(new InstructionSelect());<br class=""> return false;<br class="">}<br class="">-#endif<br class=""><br class="">bool AArch64PassConfig::isGlobalISelEnabled() const {<br class=""> return TM->getOptLevel() <= EnableGlobalISelAtO;<br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/CMakeLists.txt<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AArch64/CMakeLists.txt (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/CMakeLists.txt Thu Aug 3 14:52:25 2017<br class="">@@ -13,34 +13,16 @@ tablegen(LLVM AArch64GenCallingConv.inc<br class="">tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget)<br class="">tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)<br class="">tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables)<br class="">-if(LLVM_BUILD_GLOBAL_ISEL)<br class="">- tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)<br class="">- tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)<br class="">-endif()<br class="">+tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)<br class="">+tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)<br class=""><br class="">add_public_tablegen_target(AArch64CommonTableGen)<br class=""><br class="">-# List of all GlobalISel files.<br class="">-set(GLOBAL_ISEL_FILES<br class="">- AArch64CallLowering.cpp<br class="">- AArch64InstructionSelector.cpp<br class="">- AArch64LegalizerInfo.cpp<br class="">- AArch64RegisterBankInfo.cpp<br class="">- )<br class="">-<br class="">-# Add GlobalISel files to the dependencies if the user wants to build it.<br class="">-if(LLVM_BUILD_GLOBAL_ISEL)<br class="">- set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})<br class="">-else()<br class="">- set(GLOBAL_ISEL_BUILD_FILES"")<br class="">- set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})<br class="">-endif()<br class="">-<br class="">-<br class="">add_llvm_target(AArch64CodeGen<br class=""> AArch64A57FPLoadBalancing.cpp<br class=""> AArch64AdvSIMDScalarPass.cpp<br class=""> AArch64AsmPrinter.cpp<br class="">+ AArch64CallLowering.cpp<br class=""> AArch64CleanupLocalDynamicTLSPass.cpp<br class=""> AArch64CollectLOH.cpp<br class=""> AArch64CondBrTuning.cpp<br class="">@@ -56,11 +38,14 @@ add_llvm_target(AArch64CodeGen<br class=""> AArch64ISelDAGToDAG.cpp<br class=""> AArch64ISelLowering.cpp<br class=""> AArch64InstrInfo.cpp<br class="">+ AArch64InstructionSelector.cpp<br class="">+ AArch64LegalizerInfo.cpp<br class=""> AArch64LoadStoreOptimizer.cpp<br class=""> AArch64MacroFusion.cpp<br class=""> AArch64MCInstLower.cpp<br class=""> AArch64PromoteConstant.cpp<br class=""> AArch64PBQPRegAlloc.cpp<br class="">+ AArch64RegisterBankInfo.cpp<br class=""> AArch64RegisterInfo.cpp<br class=""> AArch64SelectionDAGInfo.cpp<br class=""> AArch64StorePairSuppress.cpp<br class="">@@ -69,7 +54,6 @@ add_llvm_target(AArch64CodeGen<br class=""> AArch64TargetObjectFile.cpp<br class=""> AArch64TargetTransformInfo.cpp<br class=""> AArch64VectorByElementOpt.cpp<br class="">- ${GLOBAL_ISEL_BUILD_FILES}<br class=""><br class=""> DEPENDS<br class=""> intrinsics_gen<br class=""><br class="">Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -26,10 +26,6 @@<br class=""><br class="">using namespace llvm;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "This shouldn't be built without GISel"<br class="">-#endif<br class="">-<br class="">AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)<br class=""> : CallLowering(&TLI), AMDGPUASI(TLI.getAMDGPUAS()) {<br class="">}<br class=""><br class="">Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def (original)<br class="">+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def Thu Aug 3 14:52:25 2017<br class="">@@ -11,10 +11,6 @@<br class="">/// \todo This should be generated by TableGen.<br class="">//===----------------------------------------------------------------------===//<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">namespace llvm {<br class="">namespace AMDGPU {<br class=""><br class=""><br class="">Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -21,10 +21,6 @@<br class=""><br class="">using namespace llvm;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">AMDGPULegalizerInfo::AMDGPULegalizerInfo() {<br class=""> using namespace TargetOpcode;<br class=""><br class=""><br class="">Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -29,10 +29,6 @@<br class=""><br class="">using namespace llvm;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI)<br class=""> : AMDGPUGenRegisterBankInfo(),<br class=""> TRI(static_cast<const SIRegisterInfo*>(&TRI)) {<br class=""><br class="">Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -15,12 +15,10 @@<br class="">#include "AMDGPUSubtarget.h"<br class="">#include "AMDGPU.h"<br class="">#include "AMDGPUTargetMachine.h"<br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">#include "AMDGPUCallLowering.h"<br class="">#include "AMDGPUInstructionSelector.h"<br class="">#include "AMDGPULegalizerInfo.h"<br class="">#include "AMDGPURegisterBankInfo.h"<br class="">-#endif<br class="">#include "SIMachineFunctionInfo.h"<br class="">#include "llvm/ADT/SmallString.h"<br class="">#include "llvm/CodeGen/MachineScheduler.h"<br class="">@@ -80,7 +78,6 @@ AMDGPUSubtarget::initializeSubtargetDepe<br class=""> return *this;<br class="">}<br class=""><br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">namespace {<br class=""><br class="">struct SIGISelActualAccessor : public GISelAccessor {<br class="">@@ -103,7 +100,6 @@ struct SIGISelActualAccessor : public GI<br class="">};<br class=""><br class="">} // end anonymous namespace<br class="">-#endif<br class=""><br class="">AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,<br class=""> const TargetMachine &TM)<br class="">@@ -358,9 +354,6 @@ SISubtarget::SISubtarget(const Triple &T<br class=""> : AMDGPUSubtarget(TT, GPU, FS, TM), InstrInfo(*this),<br class=""> FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0),<br class=""> TLInfo(TM, *this) {<br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">- GISelAccessor *GISel = new GISelAccessor();<br class="">-#else<br class=""> SIGISelActualAccessor *GISel = new SIGISelActualAccessor();<br class=""> GISel->CallLoweringInfo.reset(new AMDGPUCallLowering(*getTargetLowering()));<br class=""> GISel->Legalizer.reset(new AMDGPULegalizerInfo());<br class="">@@ -368,7 +361,6 @@ SISubtarget::SISubtarget(const Triple &T<br class=""> GISel->RegBankInfo.reset(new AMDGPURegisterBankInfo(*getRegisterInfo()));<br class=""> GISel->InstSelector.reset(new AMDGPUInstructionSelector(<br class=""> *this, *static_cast<AMDGPURegisterBankInfo *>(GISel->RegBankInfo.get())));<br class="">-#endif<br class=""> setGISelAccessor(*GISel);<br class="">}<br class=""><br class=""><br class="">Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -516,12 +516,10 @@ public:<br class=""> void addMachineSSAOptimization() override;<br class=""> bool addILPOpts() override;<br class=""> bool addInstSelector() override;<br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class=""> bool addIRTranslator() override;<br class=""> bool addLegalizeMachineIR() override;<br class=""> bool addRegBankSelect() override;<br class=""> bool addGlobalInstructionSelect() override;<br class="">-#endif<br class=""> void addFastRegAlloc(FunctionPass *RegAllocPass) override;<br class=""> void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;<br class=""> void addPreRegAlloc() override;<br class="">@@ -756,7 +754,6 @@ bool GCNPassConfig::addInstSelector() {<br class=""> return false;<br class="">}<br class=""><br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">bool GCNPassConfig::addIRTranslator() {<br class=""> addPass(new IRTranslator());<br class=""> return false;<br class="">@@ -777,8 +774,6 @@ bool GCNPassConfig::addGlobalInstruction<br class=""> return false;<br class="">}<br class=""><br class="">-#endif<br class="">-<br class="">void GCNPassConfig::addPreRegAlloc() {<br class=""> if (LateCFGStructurize) {<br class=""> addPass(createAMDGPUMachineCFGStructurizerPass());<br class=""><br class="">Modified: llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt (original)<br class="">+++ llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt Thu Aug 3 14:52:25 2017<br class="">@@ -12,28 +12,9 @@ tablegen(LLVM AMDGPUGenAsmWriter.inc -ge<br class="">tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)<br class="">tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)<br class="">tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)<br class="">-if(LLVM_BUILD_GLOBAL_ISEL)<br class="">- tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)<br class="">-endif()<br class="">+tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)<br class="">add_public_tablegen_target(AMDGPUCommonTableGen)<br class=""><br class="">-# List of all GlobalISel files.<br class="">-set(GLOBAL_ISEL_FILES<br class="">- AMDGPUCallLowering.cpp<br class="">- AMDGPUInstructionSelector.cpp<br class="">- AMDGPULegalizerInfo.cpp<br class="">- AMDGPURegisterBankInfo.cpp<br class="">- )<br class="">-<br class="">-# Add GlobalISel files to the dependencies if the user wants to build it.<br class="">-if(LLVM_BUILD_GLOBAL_ISEL)<br class="">- set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})<br class="">-else()<br class="">- set(GLOBAL_ISEL_BUILD_FILES"")<br class="">- set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})<br class="">-endif()<br class="">-<br class="">-<br class="">add_llvm_target(AMDGPUCodeGen<br class=""> AMDILCFGStructurizer.cpp<br class=""> AMDGPUAliasAnalysis.cpp<br class="">@@ -41,9 +22,12 @@ add_llvm_target(AMDGPUCodeGen<br class=""> AMDGPUAnnotateKernelFeatures.cpp<br class=""> AMDGPUAnnotateUniformValues.cpp<br class=""> AMDGPUAsmPrinter.cpp<br class="">+ AMDGPUCallLowering.cpp<br class=""> AMDGPUCodeGenPrepare.cpp<br class=""> AMDGPUFrameLowering.cpp<br class="">+ AMDGPULegalizerInfo.cpp<br class=""> AMDGPUTargetObjectFile.cpp<br class="">+ AMDGPUInstructionSelector.cpp<br class=""> AMDGPUIntrinsicInfo.cpp<br class=""> AMDGPUISelDAGToDAG.cpp<br class=""> AMDGPULowerIntrinsics.cpp<br class="">@@ -61,6 +45,7 @@ add_llvm_target(AMDGPUCodeGen<br class=""> AMDGPUInstrInfo.cpp<br class=""> AMDGPUPromoteAlloca.cpp<br class=""> AMDGPURegAsmNames.inc.cpp<br class="">+ AMDGPURegisterBankInfo.cpp<br class=""> AMDGPURegisterInfo.cpp<br class=""> AMDGPURewriteOutArguments.cpp<br class=""> AMDGPUUnifyDivergentExitNodes.cpp<br class="">@@ -105,7 +90,6 @@ add_llvm_target(AMDGPUCodeGen<br class=""> GCNIterativeScheduler.cpp<br class=""> GCNMinRegStrategy.cpp<br class=""> GCNRegPressure.cpp<br class="">- ${GLOBAL_ISEL_BUILD_FILES}<br class=""> )<br class=""><br class="">add_subdirectory(AsmParser)<br class=""><br class="">Modified: llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp (original)<br class="">+++ llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -26,10 +26,6 @@<br class=""><br class="">using namespace llvm;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "This shouldn't be built without GISel"<br class="">-#endif<br class="">-<br class="">ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)<br class=""> : CallLowering(&TLI) {}<br class=""><br class=""><br class="">Modified: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp (original)<br class="">+++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -25,10 +25,6 @@<br class=""><br class="">using namespace llvm;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">namespace {<br class=""><br class="">#define GET_GLOBALISEL_PREDICATE_BITSET<br class=""><br class="">Modified: llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp (original)<br class="">+++ llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -24,10 +24,6 @@<br class=""><br class="">using namespace llvm;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">static bool AEABI(const ARMSubtarget &ST) {<br class=""> return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();<br class="">}<br class=""><br class="">Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)<br class="">+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -24,10 +24,6 @@<br class=""><br class="">using namespace llvm;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">// FIXME: TableGen this.<br class="">// If it grows too much and TableGen still isn't ready to do the job, extract it<br class="">// into an ARMGenRegisterBankInfo.def (similar to AArch64).<br class=""><br class="">Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)<br class="">+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -13,11 +13,9 @@<br class=""><br class="">#include "ARM.h"<br class=""><br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">#include "ARMCallLowering.h"<br class="">#include "ARMLegalizerInfo.h"<br class="">#include "ARMRegisterBankInfo.h"<br class="">-#endif<br class="">#include "ARMSubtarget.h"<br class="">#include "ARMFrameLowering.h"<br class="">#include "ARMInstrInfo.h"<br class="">@@ -30,13 +28,11 @@<br class="">#include "llvm/ADT/StringRef.h"<br class="">#include "llvm/ADT/Triple.h"<br class="">#include "llvm/ADT/Twine.h"<br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">#include "llvm/CodeGen/GlobalISel/GISelAccessor.h"<br class="">#include "llvm/CodeGen/GlobalISel/IRTranslator.h"<br class="">#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"<br class="">#include "llvm/CodeGen/GlobalISel/Legalizer.h"<br class="">#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"<br class="">-#endif<br class="">#include "llvm/CodeGen/MachineFunction.h"<br class="">#include "llvm/IR/Function.h"<br class="">#include "llvm/IR/GlobalValue.h"<br class="">@@ -101,7 +97,6 @@ ARMFrameLowering *ARMSubtarget::initiali<br class=""> return new ARMFrameLowering(STI);<br class="">}<br class=""><br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">namespace {<br class=""><br class="">struct ARMGISelActualAccessor : public GISelAccessor {<br class="">@@ -128,7 +123,6 @@ struct ARMGISelActualAccessor : public G<br class="">};<br class=""><br class="">} // end anonymous namespace<br class="">-#endif<br class=""><br class="">ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,<br class=""> const std::string &FS,<br class="">@@ -147,9 +141,6 @@ ARMSubtarget::ARMSubtarget(const Triple<br class=""> assert((isThumb() || hasARMOps()) &&<br class=""> "Target must either be thumb or support ARM operations!");<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">- GISelAccessor *GISel = new GISelAccessor();<br class="">-#else<br class=""> ARMGISelActualAccessor *GISel = new ARMGISelActualAccessor();<br class=""> GISel->CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));<br class=""> GISel->Legalizer.reset(new ARMLegalizerInfo(*this));<br class="">@@ -163,7 +154,6 @@ ARMSubtarget::ARMSubtarget(const Triple<br class=""> *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));<br class=""><br class=""> GISel->RegBankInfo.reset(RBI);<br class="">-#endif<br class=""> setGISelAccessor(*GISel);<br class="">}<br class=""><br class=""><br class="">Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)<br class="">+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -333,12 +333,10 @@ public:<br class=""> void addIRPasses() override;<br class=""> bool addPreISel() override;<br class=""> bool addInstSelector() override;<br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class=""> bool addIRTranslator() override;<br class=""> bool addLegalizeMachineIR() override;<br class=""> bool addRegBankSelect() override;<br class=""> bool addGlobalInstructionSelect() override;<br class="">-#endif<br class=""> void addPreRegAlloc() override;<br class=""> void addPreSched2() override;<br class=""> void addPreEmitPass() override;<br class="">@@ -413,7 +411,6 @@ bool ARMPassConfig::addInstSelector() {<br class=""> return false;<br class="">}<br class=""><br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">bool ARMPassConfig::addIRTranslator() {<br class=""> addPass(new IRTranslator());<br class=""> return false;<br class="">@@ -433,7 +430,6 @@ bool ARMPassConfig::addGlobalInstruction<br class=""> addPass(new InstructionSelect());<br class=""> return false;<br class="">}<br class="">-#endif<br class=""><br class="">void ARMPassConfig::addPreRegAlloc() {<br class=""> if (getOptLevel() != CodeGenOpt::None) {<br class=""><br class="">Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original)<br class="">+++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Thu Aug 3 14:52:25 2017<br class="">@@ -1,9 +1,7 @@<br class="">set(LLVM_TARGET_DEFINITIONS ARM.td)<br class=""><br class="">-if(LLVM_BUILD_GLOBAL_ISEL)<br class="">- tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)<br class="">- tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)<br class="">-endif()<br class="">+tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)<br class="">+tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)<br class="">tablegen(LLVM ARMGenRegisterInfo.inc -gen-register-info)<br class="">tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)<br class="">tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter)<br class="">@@ -18,41 +16,30 @@ tablegen(LLVM ARMGenDisassemblerTables.i<br class="">tablegen(LLVM ARMGenSystemRegister.inc -gen-searchable-tables)<br class="">add_public_tablegen_target(ARMCommonTableGen)<br class=""><br class="">-# Add GlobalISel files if the user wants to build it.<br class="">-set(GLOBAL_ISEL_FILES<br class="">- ARMCallLowering.cpp<br class="">- ARMInstructionSelector.cpp<br class="">- ARMLegalizerInfo.cpp<br class="">- ARMRegisterBankInfo.cpp<br class="">- )<br class="">-<br class="">-if(LLVM_BUILD_GLOBAL_ISEL)<br class="">- set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})<br class="">-else()<br class="">- set(GLOBAL_ISEL_BUILD_FILES "")<br class="">- set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})<br class="">-endif()<br class="">-<br class="">add_llvm_target(ARMCodeGen<br class=""> A15SDOptimizer.cpp<br class=""> ARMAsmPrinter.cpp<br class=""> ARMBaseInstrInfo.cpp<br class=""> ARMBaseRegisterInfo.cpp<br class="">+ ARMCallLowering.cpp<br class=""> ARMConstantIslandPass.cpp<br class=""> ARMConstantPoolValue.cpp<br class=""> ARMExpandPseudoInsts.cpp<br class=""> ARMFastISel.cpp<br class=""> ARMFrameLowering.cpp<br class=""> ARMHazardRecognizer.cpp<br class="">+ ARMInstructionSelector.cpp<br class=""> ARMISelDAGToDAG.cpp<br class=""> ARMISelLowering.cpp<br class=""> ARMInstrInfo.cpp<br class="">+ ARMLegalizerInfo.cpp<br class=""> ARMLoadStoreOptimizer.cpp<br class=""> ARMMCInstLower.cpp<br class=""> ARMMachineFunctionInfo.cpp<br class=""> ARMMacroFusion.cpp<br class=""> ARMRegisterInfo.cpp<br class=""> ARMOptimizeBarriersPass.cpp<br class="">+ ARMRegisterBankInfo.cpp<br class=""> ARMSelectionDAGInfo.cpp<br class=""> ARMSubtarget.cpp<br class=""> ARMTargetMachine.cpp<br class="">@@ -66,7 +53,6 @@ add_llvm_target(ARMCodeGen<br class=""> Thumb2InstrInfo.cpp<br class=""> Thumb2SizeReduction.cpp<br class=""> ARMComputeBlockSize.cpp<br class="">- ${GLOBAL_ISEL_BUILD_FILES}<br class=""> )<br class=""><br class="">add_subdirectory(TargetInfo)<br class=""><br class="">Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/X86/CMakeLists.txt (original)<br class="">+++ llvm/trunk/lib/Target/X86/CMakeLists.txt Thu Aug 3 14:52:25 2017<br class="">@@ -11,32 +11,15 @@ tablegen(LLVM X86GenFastISel.inc -gen-fa<br class="">tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)<br class="">tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget)<br class="">tablegen(LLVM X86GenEVEX2VEXTables.inc -gen-x86-EVEX2VEX-tables)<br class="">-if(LLVM_BUILD_GLOBAL_ISEL)<br class="">- tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)<br class="">- tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)<br class="">-endif()<br class="">+tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)<br class="">+tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)<br class=""><br class="">add_public_tablegen_target(X86CommonTableGen)<br class=""><br class="">-# Add GlobalISel files if the build option was enabled.<br class="">-set(GLOBAL_ISEL_FILES<br class="">- X86CallLowering.cpp<br class="">- X86LegalizerInfo.cpp<br class="">- X86RegisterBankInfo.cpp<br class="">- X86InstructionSelector.cpp<br class="">- )<br class="">-<br class="">-if(LLVM_BUILD_GLOBAL_ISEL)<br class="">- set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})<br class="">-else()<br class="">- set(GLOBAL_ISEL_BUILD_FILES "")<br class="">- set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})<br class="">-endif()<br class="">-<br class="">-<br class="">set(sources<br class=""> X86AsmPrinter.cpp<br class=""> X86CallFrameOptimization.cpp<br class="">+ X86CallLowering.cpp<br class=""> X86CmovConversion.cpp<br class=""> X86ExpandPseudo.cpp<br class=""> X86FastISel.cpp<br class="">@@ -45,17 +28,20 @@ set(sources<br class=""> X86FixupSetCC.cpp<br class=""> X86FloatingPoint.cpp<br class=""> X86FrameLowering.cpp<br class="">+ X86InstructionSelector.cpp<br class=""> X86ISelDAGToDAG.cpp<br class=""> X86ISelLowering.cpp<br class=""> X86InterleavedAccess.cpp<br class=""> X86InstrFMA3Info.cpp<br class=""> X86InstrInfo.cpp<br class=""> X86EvexToVex.cpp<br class="">+ X86LegalizerInfo.cpp<br class=""> X86MCInstLower.cpp<br class=""> X86MachineFunctionInfo.cpp<br class=""> X86MacroFusion.cpp<br class=""> X86OptimizeLEAs.cpp<br class=""> X86PadShortFunction.cpp<br class="">+ X86RegisterBankInfo.cpp<br class=""> X86RegisterInfo.cpp<br class=""> X86SelectionDAGInfo.cpp<br class=""> X86ShuffleDecodeConstantPool.cpp<br class="">@@ -67,7 +53,6 @@ set(sources<br class=""> X86WinAllocaExpander.cpp<br class=""> X86WinEHState.cpp<br class=""> X86CallingConv.cpp<br class="">- ${GLOBAL_ISEL_BUILD_FILES}<br class=""> )<br class=""><br class="">add_llvm_target(X86CodeGen ${sources})<br class=""><br class="">Modified: llvm/trunk/lib/Target/X86/X86CallLowering.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallLowering.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallLowering.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/X86/X86CallLowering.cpp (original)<br class="">+++ llvm/trunk/lib/Target/X86/X86CallLowering.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -29,10 +29,6 @@ using namespace llvm;<br class=""><br class="">#include "X86GenCallingConv.inc"<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "This shouldn't be built without GISel"<br class="">-#endif<br class="">-<br class="">X86CallLowering::X86CallLowering(const X86TargetLowering &TLI)<br class=""> : CallLowering(&TLI) {}<br class=""><br class=""><br class="">Modified: llvm/trunk/lib/Target/X86/X86GenRegisterBankInfo.def<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86GenRegisterBankInfo.def?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86GenRegisterBankInfo.def?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/X86/X86GenRegisterBankInfo.def (original)<br class="">+++ llvm/trunk/lib/Target/X86/X86GenRegisterBankInfo.def Thu Aug 3 14:52:25 2017<br class="">@@ -11,10 +11,6 @@<br class="">/// \todo This should be generated by TableGen.<br class="">//===----------------------------------------------------------------------===//<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">#ifdef GET_TARGET_REGBANK_INFO_IMPL<br class="">RegisterBankInfo::PartialMapping X86GenRegisterBankInfo::PartMappings[]{<br class=""> /* StartIdx, Length, RegBank */<br class=""><br class="">Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)<br class="">+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -36,10 +36,6 @@<br class=""><br class="">using namespace llvm;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">namespace {<br class=""><br class="">#define GET_GLOBALISEL_PREDICATE_BITSET<br class=""><br class="">Modified: llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp (original)<br class="">+++ llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -22,10 +22,6 @@<br class="">using namespace llvm;<br class="">using namespace TargetOpcode;<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,<br class=""> const X86TargetMachine &TM)<br class=""> : Subtarget(STI), TM(TM) {<br class=""><br class="">Modified: llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp (original)<br class="">+++ llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -26,10 +26,6 @@ using namespace llvm;<br class="">#define GET_TARGET_REGBANK_INFO_IMPL<br class="">#include "X86GenRegisterBankInfo.def"<br class=""><br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">-#error "You shouldn't build this"<br class="">-#endif<br class="">-<br class="">X86RegisterBankInfo::X86RegisterBankInfo(const TargetRegisterInfo &TRI)<br class=""> : X86GenRegisterBankInfo() {<br class=""><br class=""><br class="">Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)<br class="">+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -13,21 +13,17 @@<br class=""><br class="">#include "X86.h"<br class=""><br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">#include "X86CallLowering.h"<br class="">#include "X86LegalizerInfo.h"<br class="">#include "X86RegisterBankInfo.h"<br class="">-#endif<br class="">#include "X86Subtarget.h"<br class="">#include "MCTargetDesc/X86BaseInfo.h"<br class="">#include "X86TargetMachine.h"<br class="">#include "llvm/ADT/Triple.h"<br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">#include "llvm/CodeGen/GlobalISel/CallLowering.h"<br class="">#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"<br class="">#include "llvm/CodeGen/GlobalISel/Legalizer.h"<br class="">#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"<br class="">-#endif<br class="">#include "llvm/IR/Attributes.h"<br class="">#include "llvm/IR/ConstantRange.h"<br class="">#include "llvm/IR/Function.h"<br class="">@@ -352,7 +348,6 @@ X86Subtarget &X86Subtarget::initializeSu<br class=""> return *this;<br class="">}<br class=""><br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">namespace {<br class=""><br class="">struct X86GISelActualAccessor : public GISelAccessor {<br class="">@@ -379,7 +374,6 @@ struct X86GISelActualAccessor : public G<br class="">};<br class=""><br class="">} // end anonymous namespace<br class="">-#endif<br class=""><br class="">X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,<br class=""> const X86TargetMachine &TM,<br class="">@@ -405,9 +399,6 @@ X86Subtarget::X86Subtarget(const Triple<br class=""> setPICStyle(PICStyles::StubPIC);<br class=""> else if (isTargetELF())<br class=""> setPICStyle(PICStyles::GOT);<br class="">-#ifndef LLVM_BUILD_GLOBAL_ISEL<br class="">- GISelAccessor *GISel = new GISelAccessor();<br class="">-#else<br class=""> X86GISelActualAccessor *GISel = new X86GISelActualAccessor();<br class=""><br class=""> GISel->CallLoweringInfo.reset(new X86CallLowering(*getTargetLowering()));<br class="">@@ -416,7 +407,6 @@ X86Subtarget::X86Subtarget(const Triple<br class=""> auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());<br class=""> GISel->RegBankInfo.reset(RBI);<br class=""> GISel->InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));<br class="">-#endif<br class=""> setGISelAccessor(*GISel);<br class="">}<br class=""><br class=""><br class="">Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)<br class="">+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Aug 3 14:52:25 2017<br class="">@@ -306,12 +306,10 @@ public:<br class=""><br class=""> void addIRPasses() override;<br class=""> bool addInstSelector() override;<br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class=""> bool addIRTranslator() override;<br class=""> bool addLegalizeMachineIR() override;<br class=""> bool addRegBankSelect() override;<br class=""> bool addGlobalInstructionSelect() override;<br class="">-#endif<br class=""> bool addILPOpts() override;<br class=""> bool addPreISel() override;<br class=""> void addPreRegAlloc() override;<br class="">@@ -361,7 +359,6 @@ bool X86PassConfig::addInstSelector() {<br class=""> return false;<br class="">}<br class=""><br class="">-#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">bool X86PassConfig::addIRTranslator() {<br class=""> addPass(new IRTranslator());<br class=""> return false;<br class="">@@ -381,7 +378,6 @@ bool X86PassConfig::addGlobalInstruction<br class=""> addPass(new InstructionSelect());<br class=""> return false;<br class="">}<br class="">-#endif<br class=""><br class="">bool X86PassConfig::addILPOpts() {<br class=""> addPass(&EarlyIfConverterID);<br class=""><br class="">Modified: llvm/trunk/tools/llvm-config/CMakeLists.txt<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-config/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-config/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/tools/llvm-config/CMakeLists.txt (original)<br class="">+++ llvm/trunk/tools/llvm-config/CMakeLists.txt Thu Aug 3 14:52:25 2017<br class="">@@ -37,11 +37,7 @@ set(LLVM_CXXFLAGS "${CMAKE_CXX_FLAGS} ${<br class="">set(LLVM_BUILD_SYSTEM cmake)<br class="">set(LLVM_HAS_RTTI ${LLVM_CONFIG_HAS_RTTI})<br class="">set(LLVM_DYLIB_VERSION "${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}${LLVM_VERSION_SUFFIX}")<br class="">-if(LLVM_BUILD_GLOBAL_ISEL)<br class="">- set(LLVM_HAS_GLOBAL_ISEL "ON")<br class="">-else()<br class="">- set(LLVM_HAS_GLOBAL_ISEL "OFF")<br class="">-endif()<br class="">+set(LLVM_HAS_GLOBAL_ISEL "ON")<br class=""><br class=""># Use the C++ link flags, since they should be a superset of C link flags.<br class="">set(LLVM_LDFLAGS "${CMAKE_CXX_LINK_FLAGS}")<br class=""><br class="">Modified: llvm/trunk/unittests/CodeGen/GlobalISel/CMakeLists.txt<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CodeGen/GlobalISel/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CodeGen/GlobalISel/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/unittests/CodeGen/GlobalISel/CMakeLists.txt (original)<br class="">+++ llvm/trunk/unittests/CodeGen/GlobalISel/CMakeLists.txt Thu Aug 3 14:52:25 2017<br class="">@@ -3,8 +3,6 @@ set(LLVM_LINK_COMPONENTS<br class=""> CodeGen<br class=""> )<br class=""><br class="">-if(LLVM_BUILD_GLOBAL_ISEL)<br class="">- add_llvm_unittest(GlobalISelTests<br class="">- LegalizerInfoTest.cpp<br class="">- )<br class="">-endif()<br class="">+add_llvm_unittest(GlobalISelTests<br class="">+ LegalizerInfoTest.cpp<br class="">+ )<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</blockquote></div></blockquote></div><br class=""></div></body></html>