<html><head><meta http-equiv="Content-Type" content="text/html; charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On 2 Aug 2017, at 12:11, Daniel Sanders via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px;" class=""><br class="Apple-interchange-newline">On 2 Aug 2017, at 12:07, Diana Picus <<a href="mailto:diana.picus@linaro.org" class="">diana.picus@linaro.org</a>> wrote:<br class=""><br class="">On 2 August 2017 at 13:03, Daniel Sanders via llvm-commits<br class=""><<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class=""><blockquote type="cite" class="">Author: dsanders<br class="">Date: Wed Aug 2 04:03:36 2017<br class="">New Revision: 309804<br class=""><br class="">URL: <a href="http://llvm.org/viewvc/llvm-project?rev=309804&view=rev" class="">http://llvm.org/viewvc/llvm-project?rev=309804&view=rev</a><br class="">Log:<br class="">[globalisel][tablegen] Do not merge memoperands from instructions that weren't in the match.<br class=""><br class="">Summary:<br class="">Fix a bug discovered in an out-of-tree target where memoperands from<br class="">pseudo-instructions that weren't part of the match were being merged into the<br class="">result instructions as part of GIR_MergeMemOperands.<br class=""><br class="">This bug was caused by a change to the handling of State.MIs between rules when<br class="">the state machine tables were fused into a single table. Previously, each rule<br class="">would reset State.MIs using State.MIs.resize(1) but this is no longer done, as a<br class="">result stale data is occasionally left in some elements of State.MIs. Most<br class="">opcodes aren't affected by this but GIR_MergeMemOperands merges all memoperands<br class="">from the intructions recorded in State.MIs into the result instruction.<br class=""><br class="">Suppose for example, we processed but rejected the following pattern:<br class="">(signextend (load x))<br class="">at this point, State.MIs contains the signextend and the load. Now suppose we<br class="">process and accept this pattern:<br class="">(add x, y)<br class="">at this point, State.MIs contains the add as well as the (now irrelevant) load.<br class="">When GIR_MergeMemOperands is processed, the memoperands from that irrelevant<br class="">load will be merged into the result instruction even though it was not part of<br class="">the match.<br class=""><br class="">Bringing back the State.MIs.resize(1) would fix the problem but it would limit<br class="">our ability to optimize the table in the future. Instead, this patch fixes the<br class="">problem by explicitly stating which instructions should be merged into the result.<br class=""><br class="">There's no direct test case in this commit because a test case would be very brittle.<br class="">However, at the time of writing this should fix the failures in<br class=""><a href="http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/" class="">http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/</a> as well as a<br class="">failure in test/CodeGen/ARM/GlobalISel/arm-isel.ll when expensive checks are enabled.<br class=""><br class="">Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar<br class=""><br class="">Subscribers: fhahn, kristof.beyls, igorb, llvm-commits<br class=""><br class="">Differential Revision: <a href="https://reviews.llvm.org/D36094" class="">https://reviews.llvm.org/D36094</a><br class=""><br class=""><br class="">Modified:<br class=""> llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h<br class=""> llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h<br class=""> llvm/trunk/test/TableGen/GlobalISelEmitter.td<br class=""> llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp<br class=""><br class="">Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h?rev=309804&r1=309803&r2=309804&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h?rev=309804&r1=309803&r2=309804&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h (original)<br class="">+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h Wed Aug 2 04:03:36 2017<br class="">@@ -195,6 +195,8 @@ enum {<br class=""> GIR_ConstrainSelectedInstOperands,<br class=""> /// Merge all memory operands into instruction.<br class=""> /// - InsnID - Instruction ID to modify<br class="">+ /// - MergeInsnID... - One or more Instruction ID to merge into the result.<br class="">+ /// - -1 - Terminates the list of instructions to merge.<br class=""></blockquote><br class="">This comment should say GIU_MergeMemOperands_EndOfList instead of -1.<br class=""></blockquote><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Thanks. I'll fix this once the commit has gone through the green dragon bot that was failing.</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""></div></blockquote><div><br class=""></div>Fixed in r<span style="color: rgba(0, 0, 0, 0.85098); font-family: "Helvetica Neue";" class="">309924</span><br class=""><br class=""><blockquote type="cite" class=""><div class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" class=""> GIR_MergeMemOperands,<br class=""> /// Erase from parent.<br class=""> /// - InsnID - Instruction ID to erase<br class="">@@ -204,6 +206,12 @@ enum {<br class=""> GIR_Done,<br class="">};<br class=""><br class="">+enum {<br class="">+ /// Indicates the end of the variable-length MergeInsnID list in a<br class="">+ /// GIR_MergeMemOperands opcode.<br class="">+ GIU_MergeMemOperands_EndOfList = -1,<br class="">+};<br class="">+<br class="">/// Provides the logic to select generic machine instructions.<br class="">class InstructionSelector {<br class="">public:<br class=""><br class="">Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h?rev=309804&r1=309803&r2=309804&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h?rev=309804&r1=309803&r2=309804&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h (original)<br class="">+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h Wed Aug 2 04:03:36 2017<br class="">@@ -370,11 +370,17 @@ bool InstructionSelector::executeMatchTa<br class=""> case GIR_MergeMemOperands: {<br class=""> int64_t InsnID = MatchTable[CurrentIdx++];<br class=""> assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");<br class="">- for (const auto *FromMI : State.MIs)<br class="">- for (const auto &MMO : FromMI->memoperands())<br class="">- OutMIs[InsnID].addMemOperand(MMO);<br class="">+<br class=""> DEBUG(dbgs() << CurrentIdx << ": GIR_MergeMemOperands(OutMIs[" << InsnID<br class="">- << "])\n");<br class="">+ << "]");<br class="">+ int64_t MergeInsnID = GIU_MergeMemOperands_EndOfList;<br class="">+ while ((MergeInsnID = MatchTable[CurrentIdx++]) !=<br class="">+ GIU_MergeMemOperands_EndOfList) {<br class="">+ DEBUG(dbgs() << ", MIs[" << MergeInsnID << "]");<br class="">+ for (const auto &MMO : State.MIs[MergeInsnID]->memoperands())<br class="">+ OutMIs[InsnID].addMemOperand(MMO);<br class="">+ }<br class="">+ DEBUG(dbgs() << ")\n");<br class=""> break;<br class=""> }<br class=""> case GIR_EraseFromParent: {<br class=""><br class="">Modified: llvm/trunk/test/TableGen/GlobalISelEmitter.td<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/GlobalISelEmitter.td?rev=309804&r1=309803&r2=309804&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/GlobalISelEmitter.td?rev=309804&r1=309803&r2=309804&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/TableGen/GlobalISelEmitter.td (original)<br class="">+++ llvm/trunk/test/TableGen/GlobalISelEmitter.td Wed Aug 2 04:03:36 2017<br class="">@@ -117,7 +117,7 @@ def HasC : Predicate<"Subtarget->hasC()"<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1<br class="">// CHECK-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/1,<br class="">// CHECK-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0,<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class="">@@ -168,7 +168,7 @@ def : Pat<(select GPR32:$src1, complex:$<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src3<br class="">// CHECK-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/1,<br class="">// CHECK-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/2,<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class="">@@ -221,7 +221,7 @@ def ADD : I<(outs GPR32:$dst), (ins GPR3<br class="">// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOV,<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class="">@@ -262,7 +262,7 @@ def MOV : I<(outs GPR32:$dst), (ins GPR3<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class="">@@ -299,7 +299,7 @@ def MOV : I<(outs GPR32:$dst), (ins GPR3<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class="">@@ -330,7 +330,7 @@ def MULADD : I<(outs GPR32:$dst), (ins G<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class="">@@ -384,7 +384,7 @@ def MUL : I<(outs GPR32:$dst), (ins GPR3<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src3<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src4<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class="">@@ -415,7 +415,7 @@ def INSNBOB : I<(outs GPR32:$dst), (ins<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1<br class="">// CHECK-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0,<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class="">@@ -444,7 +444,7 @@ def : Pat<(sub GPR32:$src1, complex:$src<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst<br class="">// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/-1,<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class="">@@ -474,7 +474,7 @@ def XORI : I<(outs GPR32:$dst), (ins m1:<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst<br class="">// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::R0,<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class="">@@ -505,7 +505,7 @@ def XOR : I<(outs GPR32:$dst), (ins Z:$s<br class="">// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/-1,<br class="">// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::R0,<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class="">@@ -537,7 +537,7 @@ def XORlike : I<(outs GPR32:$dst), (ins<br class="">// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::R0,<br class="">// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::R0,<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class="">@@ -569,7 +569,7 @@ def XORManyDefaults : I<(outs GPR32:$dst<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst<br class="">// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::R0,<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Wm<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class="">@@ -612,7 +612,7 @@ def : Pat<(i32 (bitconvert FPR32:$src1))<br class="">// CHECK-NEXT: // 1:i32 => (MOV1:i32)<br class="">// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOV1,<br class="">// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst<br class="">-// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0,<br class="">+// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,<br class="">// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,<br class="">// CHECK-NEXT: GIR_Done,<br class=""><br class="">Modified: llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp?rev=309804&r1=309803&r2=309804&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp?rev=309804&r1=309803&r2=309804&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp (original)<br class="">+++ llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp Wed Aug 2 04:03:36 2017<br class="">@@ -460,9 +460,11 @@ class RuleMatcher {<br class=""> /// have succeeded.<br class=""> std::vector<std::unique_ptr<MatchAction>> Actions;<br class=""><br class="">+ typedef std::map<const InstructionMatcher *, unsigned><br class="">+ DefinedInsnVariablesMap;<br class=""> /// A map of instruction matchers to the local variables created by<br class=""> /// emitCaptureOpcodes().<br class="">- std::map<const InstructionMatcher *, unsigned> InsnVariableIDs;<br class="">+ DefinedInsnVariablesMap InsnVariableIDs;<br class=""><br class=""> /// ID for the next instruction variable defined with defineInsnVar()<br class=""> unsigned NextInsnVarID;<br class="">@@ -488,6 +490,16 @@ public:<br class=""> unsigned defineInsnVar(MatchTable &Table, const InstructionMatcher &Matcher,<br class=""> unsigned InsnVarID, unsigned OpIdx);<br class=""> unsigned getInsnVarID(const InstructionMatcher &InsnMatcher) const;<br class="">+ DefinedInsnVariablesMap::const_iterator defined_insn_vars_begin() const {<br class="">+ return InsnVariableIDs.begin();<br class="">+ }<br class="">+ DefinedInsnVariablesMap::const_iterator defined_insn_vars_end() const {<br class="">+ return InsnVariableIDs.end();<br class="">+ }<br class="">+ iterator_range<typename DefinedInsnVariablesMap::const_iterator><br class="">+ defined_insn_vars() const {<br class="">+ return make_range(defined_insn_vars_begin(), defined_insn_vars_end());<br class="">+ }<br class=""><br class=""> void emitCaptureOpcodes(MatchTable &Table);<br class=""><br class="">@@ -1452,6 +1464,21 @@ public:<br class=""><br class=""> Table << MatchTable::Opcode("GIR_MergeMemOperands")<br class=""> << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID)<br class="">+ << MatchTable::Comment("MergeInsnID's");<br class="">+ // Emit the ID's for all the instructions that are matched by this rule.<br class="">+ // TODO: Limit this to matched instructions that mayLoad/mayStore or have<br class="">+ // some other means of having a memoperand. Also limit this to emitted<br class="">+ // instructions that expect to have a memoperand too. For example,<br class="">+ // (G_SEXT (G_LOAD x)) that results in separate load and sign-extend<br class="">+ // instructions shouldn't put the memoperand on the sign-extend since<br class="">+ // it has no effect there.<br class="">+ std::vector<unsigned> MergeInsnIDs;<br class="">+ for (const auto &IDMatcherPair : Rule.defined_insn_vars())<br class="">+ MergeInsnIDs.push_back(IDMatcherPair.second);<br class="">+ std::sort(MergeInsnIDs.begin(), MergeInsnIDs.end());<br class="">+ for (const auto &MergeInsnID : MergeInsnIDs)<br class="">+ Table << MatchTable::IntValue(MergeInsnID);<br class="">+ Table << MatchTable::NamedValue("GIU_MergeMemOperands_EndOfList")<br class=""> << MatchTable::LineBreak << MatchTable::Opcode("GIR_EraseFromParent")<br class=""> << MatchTable::Comment("InsnID")<br class=""> << MatchTable::IntValue(RecycleInsnID) << MatchTable::LineBreak;<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits<br class=""></blockquote></blockquote><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">_______________________________________________</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">llvm-commits mailing list</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><a href="mailto:llvm-commits@lists.llvm.org" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px;" class="">llvm-commits@lists.llvm.org</a><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px;" class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a></div></blockquote></div><br class=""></body></html>